1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-access-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-access-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s
4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -mattr=+unaligned-access-mode -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
5
6; Unaligned DS access in available from GFX9 onwards.
7; LDS alignment enforcement is controlled by a configuration register:
8; SH_MEM_CONFIG.alignment_mode
9
10define <4 x i32> @load_lds_v4i32_align1(<4 x i32> addrspace(3)* %ptr) {
11; GFX9-LABEL: load_lds_v4i32_align1:
12; GFX9:       ; %bb.0:
13; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
14; GFX9-NEXT:    ds_read2_b64 v[0:3], v0 offset1:1
15; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
16; GFX9-NEXT:    s_setpc_b64 s[30:31]
17;
18; GFX7-LABEL: load_lds_v4i32_align1:
19; GFX7:       ; %bb.0:
20; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21; GFX7-NEXT:    s_mov_b32 m0, -1
22; GFX7-NEXT:    s_movk_i32 s4, 0xff
23; GFX7-NEXT:    ds_read_u8 v1, v0
24; GFX7-NEXT:    ds_read_u8 v2, v0 offset:1
25; GFX7-NEXT:    ds_read_u8 v4, v0 offset:2
26; GFX7-NEXT:    ds_read_u8 v5, v0 offset:3
27; GFX7-NEXT:    ds_read_u8 v6, v0 offset:4
28; GFX7-NEXT:    ds_read_u8 v7, v0 offset:5
29; GFX7-NEXT:    ds_read_u8 v8, v0 offset:6
30; GFX7-NEXT:    ds_read_u8 v9, v0 offset:7
31; GFX7-NEXT:    s_waitcnt lgkmcnt(6)
32; GFX7-NEXT:    v_and_b32_e32 v2, s4, v2
33; GFX7-NEXT:    v_and_b32_e32 v1, s4, v1
34; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
35; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
36; GFX7-NEXT:    s_waitcnt lgkmcnt(5)
37; GFX7-NEXT:    v_and_b32_e32 v2, s4, v4
38; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
39; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
40; GFX7-NEXT:    s_waitcnt lgkmcnt(4)
41; GFX7-NEXT:    v_and_b32_e32 v2, s4, v5
42; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
43; GFX7-NEXT:    v_mov_b32_e32 v3, 0xff
44; GFX7-NEXT:    v_or_b32_e32 v4, v1, v2
45; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
46; GFX7-NEXT:    v_and_b32_e32 v2, v7, v3
47; GFX7-NEXT:    v_and_b32_e32 v1, s4, v6
48; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
49; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
50; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
51; GFX7-NEXT:    v_and_b32_e32 v2, v8, v3
52; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
53; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
54; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
55; GFX7-NEXT:    v_and_b32_e32 v2, v9, v3
56; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
57; GFX7-NEXT:    v_or_b32_e32 v1, v1, v2
58; GFX7-NEXT:    ds_read_u8 v2, v0 offset:8
59; GFX7-NEXT:    ds_read_u8 v5, v0 offset:9
60; GFX7-NEXT:    ds_read_u8 v6, v0 offset:10
61; GFX7-NEXT:    ds_read_u8 v7, v0 offset:11
62; GFX7-NEXT:    ds_read_u8 v8, v0 offset:12
63; GFX7-NEXT:    ds_read_u8 v9, v0 offset:13
64; GFX7-NEXT:    ds_read_u8 v10, v0 offset:14
65; GFX7-NEXT:    ds_read_u8 v0, v0 offset:15
66; GFX7-NEXT:    s_waitcnt lgkmcnt(6)
67; GFX7-NEXT:    v_and_b32_e32 v5, v5, v3
68; GFX7-NEXT:    v_and_b32_e32 v2, v2, v3
69; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 8, v5
70; GFX7-NEXT:    v_or_b32_e32 v2, v2, v5
71; GFX7-NEXT:    s_waitcnt lgkmcnt(5)
72; GFX7-NEXT:    v_and_b32_e32 v5, v6, v3
73; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
74; GFX7-NEXT:    v_or_b32_e32 v2, v2, v5
75; GFX7-NEXT:    s_waitcnt lgkmcnt(4)
76; GFX7-NEXT:    v_and_b32_e32 v5, v7, v3
77; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
78; GFX7-NEXT:    v_and_b32_e32 v6, v9, v3
79; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 24, v5
80; GFX7-NEXT:    v_or_b32_e32 v2, v2, v5
81; GFX7-NEXT:    v_and_b32_e32 v5, v8, v3
82; GFX7-NEXT:    v_lshlrev_b32_e32 v6, 8, v6
83; GFX7-NEXT:    v_or_b32_e32 v5, v5, v6
84; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
85; GFX7-NEXT:    v_and_b32_e32 v6, v10, v3
86; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
87; GFX7-NEXT:    v_and_b32_e32 v0, v0, v3
88; GFX7-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
89; GFX7-NEXT:    v_or_b32_e32 v5, v5, v6
90; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
91; GFX7-NEXT:    v_or_b32_e32 v3, v5, v0
92; GFX7-NEXT:    v_mov_b32_e32 v0, v4
93; GFX7-NEXT:    s_setpc_b64 s[30:31]
94;
95; GFX10-LABEL: load_lds_v4i32_align1:
96; GFX10:       ; %bb.0:
97; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
98; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
99; GFX10-NEXT:    ds_read_u8 v1, v0 offset:1
100; GFX10-NEXT:    ds_read_u8 v2, v0 offset:2
101; GFX10-NEXT:    ds_read_u8 v3, v0 offset:3
102; GFX10-NEXT:    ds_read_u8 v4, v0 offset:5
103; GFX10-NEXT:    ds_read_u8 v5, v0 offset:6
104; GFX10-NEXT:    ds_read_u8 v6, v0 offset:7
105; GFX10-NEXT:    ds_read_u8 v7, v0 offset:9
106; GFX10-NEXT:    ds_read_u8 v8, v0
107; GFX10-NEXT:    ds_read_u8 v9, v0 offset:4
108; GFX10-NEXT:    ds_read_u8 v10, v0 offset:8
109; GFX10-NEXT:    ds_read_u8 v12, v0 offset:10
110; GFX10-NEXT:    ds_read_u8 v13, v0 offset:11
111; GFX10-NEXT:    ds_read_u8 v14, v0 offset:12
112; GFX10-NEXT:    ds_read_u8 v15, v0 offset:13
113; GFX10-NEXT:    ds_read_u8 v16, v0 offset:14
114; GFX10-NEXT:    ds_read_u8 v0, v0 offset:15
115; GFX10-NEXT:    v_mov_b32_e32 v17, 8
116; GFX10-NEXT:    s_mov_b32 s5, 8
117; GFX10-NEXT:    v_mov_b32_e32 v11, 0xff
118; GFX10-NEXT:    s_movk_i32 s4, 0xff
119; GFX10-NEXT:    s_waitcnt lgkmcnt(15)
120; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
121; GFX10-NEXT:    s_waitcnt lgkmcnt(14)
122; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
123; GFX10-NEXT:    s_waitcnt lgkmcnt(13)
124; GFX10-NEXT:    v_and_b32_e32 v3, s4, v3
125; GFX10-NEXT:    s_waitcnt lgkmcnt(12)
126; GFX10-NEXT:    v_lshlrev_b32_sdwa v4, s5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
127; GFX10-NEXT:    s_waitcnt lgkmcnt(11)
128; GFX10-NEXT:    v_and_b32_e32 v5, v5, v11
129; GFX10-NEXT:    s_waitcnt lgkmcnt(10)
130; GFX10-NEXT:    v_and_b32_e32 v6, v6, v11
131; GFX10-NEXT:    s_waitcnt lgkmcnt(9)
132; GFX10-NEXT:    v_lshlrev_b32_sdwa v7, v17, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
133; GFX10-NEXT:    s_waitcnt lgkmcnt(8)
134; GFX10-NEXT:    v_and_or_b32 v1, v8, s4, v1
135; GFX10-NEXT:    s_waitcnt lgkmcnt(5)
136; GFX10-NEXT:    v_and_b32_e32 v8, v12, v11
137; GFX10-NEXT:    v_and_or_b32 v4, v9, s4, v4
138; GFX10-NEXT:    s_waitcnt lgkmcnt(4)
139; GFX10-NEXT:    v_and_b32_e32 v9, v13, v11
140; GFX10-NEXT:    v_and_or_b32 v7, v10, v11, v7
141; GFX10-NEXT:    s_waitcnt lgkmcnt(2)
142; GFX10-NEXT:    v_lshlrev_b32_sdwa v10, v17, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
143; GFX10-NEXT:    s_waitcnt lgkmcnt(1)
144; GFX10-NEXT:    v_and_b32_e32 v12, v16, v11
145; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
146; GFX10-NEXT:    v_and_b32_e32 v0, v0, v11
147; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
148; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
149; GFX10-NEXT:    v_and_or_b32 v10, v14, v11, v10
150; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v12
151; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 24, v0
152; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
153; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 24, v6
154; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
155; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 24, v9
156; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v3
157; GFX10-NEXT:    v_or3_b32 v3, v10, v11, v12
158; GFX10-NEXT:    v_or3_b32 v1, v4, v5, v6
159; GFX10-NEXT:    v_or3_b32 v2, v7, v8, v9
160; GFX10-NEXT:    s_setpc_b64 s[30:31]
161  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 1
162  ret <4 x i32> %load
163}
164
165define <3 x i32> @load_lds_v3i32_align1(<3 x i32> addrspace(3)* %ptr) {
166; GFX9-LABEL: load_lds_v3i32_align1:
167; GFX9:       ; %bb.0:
168; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
169; GFX9-NEXT:    ds_read_b96 v[0:2], v0
170; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
171; GFX9-NEXT:    s_setpc_b64 s[30:31]
172;
173; GFX7-LABEL: load_lds_v3i32_align1:
174; GFX7:       ; %bb.0:
175; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
176; GFX7-NEXT:    s_mov_b32 m0, -1
177; GFX7-NEXT:    v_mov_b32_e32 v2, v0
178; GFX7-NEXT:    s_movk_i32 s4, 0xff
179; GFX7-NEXT:    ds_read_u8 v0, v0
180; GFX7-NEXT:    ds_read_u8 v1, v2 offset:1
181; GFX7-NEXT:    ds_read_u8 v4, v2 offset:2
182; GFX7-NEXT:    ds_read_u8 v5, v2 offset:3
183; GFX7-NEXT:    ds_read_u8 v6, v2 offset:4
184; GFX7-NEXT:    ds_read_u8 v7, v2 offset:5
185; GFX7-NEXT:    ds_read_u8 v8, v2 offset:6
186; GFX7-NEXT:    ds_read_u8 v9, v2 offset:7
187; GFX7-NEXT:    s_waitcnt lgkmcnt(6)
188; GFX7-NEXT:    v_and_b32_e32 v1, s4, v1
189; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
190; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
191; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
192; GFX7-NEXT:    s_waitcnt lgkmcnt(5)
193; GFX7-NEXT:    v_and_b32_e32 v1, s4, v4
194; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
195; GFX7-NEXT:    v_mov_b32_e32 v3, 0xff
196; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
197; GFX7-NEXT:    s_waitcnt lgkmcnt(4)
198; GFX7-NEXT:    v_and_b32_e32 v1, s4, v5
199; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
200; GFX7-NEXT:    v_and_b32_e32 v4, v7, v3
201; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
202; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
203; GFX7-NEXT:    v_and_b32_e32 v1, s4, v6
204; GFX7-NEXT:    v_lshlrev_b32_e32 v4, 8, v4
205; GFX7-NEXT:    v_or_b32_e32 v1, v1, v4
206; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
207; GFX7-NEXT:    v_and_b32_e32 v4, v8, v3
208; GFX7-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
209; GFX7-NEXT:    v_or_b32_e32 v1, v1, v4
210; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
211; GFX7-NEXT:    v_and_b32_e32 v4, v9, v3
212; GFX7-NEXT:    v_lshlrev_b32_e32 v4, 24, v4
213; GFX7-NEXT:    v_or_b32_e32 v1, v1, v4
214; GFX7-NEXT:    ds_read_u8 v4, v2 offset:8
215; GFX7-NEXT:    ds_read_u8 v5, v2 offset:9
216; GFX7-NEXT:    ds_read_u8 v6, v2 offset:10
217; GFX7-NEXT:    ds_read_u8 v2, v2 offset:11
218; GFX7-NEXT:    s_waitcnt lgkmcnt(3)
219; GFX7-NEXT:    v_and_b32_e32 v4, v4, v3
220; GFX7-NEXT:    s_waitcnt lgkmcnt(2)
221; GFX7-NEXT:    v_and_b32_e32 v5, v5, v3
222; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 8, v5
223; GFX7-NEXT:    v_or_b32_e32 v4, v4, v5
224; GFX7-NEXT:    s_waitcnt lgkmcnt(1)
225; GFX7-NEXT:    v_and_b32_e32 v5, v6, v3
226; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
227; GFX7-NEXT:    v_and_b32_e32 v2, v2, v3
228; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
229; GFX7-NEXT:    v_or_b32_e32 v4, v4, v5
230; GFX7-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
231; GFX7-NEXT:    v_or_b32_e32 v2, v4, v2
232; GFX7-NEXT:    s_setpc_b64 s[30:31]
233;
234; GFX10-LABEL: load_lds_v3i32_align1:
235; GFX10:       ; %bb.0:
236; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
237; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
238; GFX10-NEXT:    ds_read_u8 v1, v0 offset:1
239; GFX10-NEXT:    ds_read_u8 v2, v0 offset:2
240; GFX10-NEXT:    ds_read_u8 v3, v0 offset:3
241; GFX10-NEXT:    ds_read_u8 v4, v0 offset:5
242; GFX10-NEXT:    ds_read_u8 v5, v0 offset:6
243; GFX10-NEXT:    ds_read_u8 v6, v0 offset:7
244; GFX10-NEXT:    ds_read_u8 v7, v0 offset:9
245; GFX10-NEXT:    ds_read_u8 v8, v0 offset:10
246; GFX10-NEXT:    ds_read_u8 v9, v0 offset:11
247; GFX10-NEXT:    ds_read_u8 v10, v0
248; GFX10-NEXT:    ds_read_u8 v11, v0 offset:4
249; GFX10-NEXT:    ds_read_u8 v0, v0 offset:8
250; GFX10-NEXT:    v_mov_b32_e32 v12, 0xff
251; GFX10-NEXT:    v_mov_b32_e32 v13, 8
252; GFX10-NEXT:    s_movk_i32 s4, 0xff
253; GFX10-NEXT:    s_mov_b32 s5, 8
254; GFX10-NEXT:    s_waitcnt lgkmcnt(11)
255; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
256; GFX10-NEXT:    s_waitcnt lgkmcnt(10)
257; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
258; GFX10-NEXT:    s_waitcnt lgkmcnt(9)
259; GFX10-NEXT:    v_and_b32_e32 v3, s4, v3
260; GFX10-NEXT:    s_waitcnt lgkmcnt(8)
261; GFX10-NEXT:    v_lshlrev_b32_sdwa v4, s5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
262; GFX10-NEXT:    s_waitcnt lgkmcnt(7)
263; GFX10-NEXT:    v_and_b32_e32 v5, v5, v12
264; GFX10-NEXT:    s_waitcnt lgkmcnt(6)
265; GFX10-NEXT:    v_and_b32_e32 v6, v6, v12
266; GFX10-NEXT:    s_waitcnt lgkmcnt(5)
267; GFX10-NEXT:    v_lshlrev_b32_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
268; GFX10-NEXT:    s_waitcnt lgkmcnt(4)
269; GFX10-NEXT:    v_and_b32_e32 v8, v8, v12
270; GFX10-NEXT:    s_waitcnt lgkmcnt(3)
271; GFX10-NEXT:    v_and_b32_e32 v9, v9, v12
272; GFX10-NEXT:    s_waitcnt lgkmcnt(2)
273; GFX10-NEXT:    v_and_or_b32 v1, v10, s4, v1
274; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
275; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
276; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
277; GFX10-NEXT:    v_and_or_b32 v7, v0, v12, v7
278; GFX10-NEXT:    v_and_or_b32 v4, v11, s4, v4
279; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
280; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 24, v6
281; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
282; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 24, v9
283; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v3
284; GFX10-NEXT:    v_or3_b32 v1, v4, v5, v6
285; GFX10-NEXT:    v_or3_b32 v2, v7, v8, v9
286; GFX10-NEXT:    s_setpc_b64 s[30:31]
287  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 1
288  ret <3 x i32> %load
289}
290
291define void @store_lds_v4i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
292; GFX9-LABEL: store_lds_v4i32_align1:
293; GFX9:       ; %bb.0:
294; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
295; GFX9-NEXT:    ds_write2_b64 v0, v[1:2], v[3:4] offset1:1
296; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
297; GFX9-NEXT:    s_setpc_b64 s[30:31]
298;
299; GFX7-LABEL: store_lds_v4i32_align1:
300; GFX7:       ; %bb.0:
301; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
302; GFX7-NEXT:    s_mov_b32 m0, -1
303; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
304; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
305; GFX7-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
306; GFX7-NEXT:    ds_write_b8 v0, v1
307; GFX7-NEXT:    ds_write_b8 v0, v5 offset:1
308; GFX7-NEXT:    ds_write_b8 v0, v6 offset:2
309; GFX7-NEXT:    ds_write_b8 v0, v7 offset:3
310; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
311; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
312; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 24, v2
313; GFX7-NEXT:    ds_write_b8 v0, v2 offset:4
314; GFX7-NEXT:    ds_write_b8 v0, v1 offset:5
315; GFX7-NEXT:    ds_write_b8 v0, v5 offset:6
316; GFX7-NEXT:    ds_write_b8 v0, v6 offset:7
317; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
318; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
319; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 24, v3
320; GFX7-NEXT:    ds_write_b8 v0, v3 offset:8
321; GFX7-NEXT:    ds_write_b8 v0, v1 offset:9
322; GFX7-NEXT:    ds_write_b8 v0, v2 offset:10
323; GFX7-NEXT:    ds_write_b8 v0, v5 offset:11
324; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
325; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
326; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
327; GFX7-NEXT:    ds_write_b8 v0, v4 offset:12
328; GFX7-NEXT:    ds_write_b8 v0, v1 offset:13
329; GFX7-NEXT:    ds_write_b8 v0, v2 offset:14
330; GFX7-NEXT:    ds_write_b8 v0, v3 offset:15
331; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
332; GFX7-NEXT:    s_setpc_b64 s[30:31]
333;
334; GFX10-LABEL: store_lds_v4i32_align1:
335; GFX10:       ; %bb.0:
336; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
337; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
338; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
339; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
340; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
341; GFX10-NEXT:    ds_write_b8 v0, v1
342; GFX10-NEXT:    ds_write_b8 v0, v5 offset:1
343; GFX10-NEXT:    ds_write_b8 v0, v6 offset:2
344; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
345; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
346; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 24, v2
347; GFX10-NEXT:    ds_write_b8 v0, v7 offset:3
348; GFX10-NEXT:    ds_write_b8 v0, v2 offset:4
349; GFX10-NEXT:    ds_write_b8 v0, v1 offset:5
350; GFX10-NEXT:    ds_write_b8 v0, v5 offset:6
351; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
352; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
353; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v3
354; GFX10-NEXT:    ds_write_b8 v0, v6 offset:7
355; GFX10-NEXT:    ds_write_b8 v0, v3 offset:8
356; GFX10-NEXT:    ds_write_b8 v0, v1 offset:9
357; GFX10-NEXT:    ds_write_b8 v0, v2 offset:10
358; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
359; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
360; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
361; GFX10-NEXT:    ds_write_b8 v0, v5 offset:11
362; GFX10-NEXT:    ds_write_b8 v0, v4 offset:12
363; GFX10-NEXT:    ds_write_b8 v0, v1 offset:13
364; GFX10-NEXT:    ds_write_b8 v0, v2 offset:14
365; GFX10-NEXT:    ds_write_b8 v0, v3 offset:15
366; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
367; GFX10-NEXT:    s_setpc_b64 s[30:31]
368  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 1
369  ret void
370}
371
372define void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
373; GFX9-LABEL: store_lds_v3i32_align1:
374; GFX9:       ; %bb.0:
375; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
376; GFX9-NEXT:    ds_write_b96 v0, v[1:3]
377; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
378; GFX9-NEXT:    s_setpc_b64 s[30:31]
379;
380; GFX7-LABEL: store_lds_v3i32_align1:
381; GFX7:       ; %bb.0:
382; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
383; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
384; GFX7-NEXT:    s_mov_b32 m0, -1
385; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
386; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
387; GFX7-NEXT:    ds_write_b8 v0, v1
388; GFX7-NEXT:    ds_write_b8 v0, v4 offset:1
389; GFX7-NEXT:    ds_write_b8 v0, v5 offset:2
390; GFX7-NEXT:    ds_write_b8 v0, v6 offset:3
391; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
392; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
393; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 24, v2
394; GFX7-NEXT:    ds_write_b8 v0, v2 offset:4
395; GFX7-NEXT:    ds_write_b8 v0, v1 offset:5
396; GFX7-NEXT:    ds_write_b8 v0, v4 offset:6
397; GFX7-NEXT:    ds_write_b8 v0, v5 offset:7
398; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
399; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
400; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 24, v3
401; GFX7-NEXT:    ds_write_b8 v0, v3 offset:8
402; GFX7-NEXT:    ds_write_b8 v0, v1 offset:9
403; GFX7-NEXT:    ds_write_b8 v0, v2 offset:10
404; GFX7-NEXT:    ds_write_b8 v0, v4 offset:11
405; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
406; GFX7-NEXT:    s_setpc_b64 s[30:31]
407;
408; GFX10-LABEL: store_lds_v3i32_align1:
409; GFX10:       ; %bb.0:
410; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
411; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
412; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
413; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
414; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
415; GFX10-NEXT:    ds_write_b8 v0, v1
416; GFX10-NEXT:    ds_write_b8 v0, v4 offset:1
417; GFX10-NEXT:    ds_write_b8 v0, v5 offset:2
418; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
419; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
420; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v2
421; GFX10-NEXT:    ds_write_b8 v0, v6 offset:3
422; GFX10-NEXT:    ds_write_b8 v0, v2 offset:4
423; GFX10-NEXT:    ds_write_b8 v0, v1 offset:5
424; GFX10-NEXT:    ds_write_b8 v0, v4 offset:6
425; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
426; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
427; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 24, v3
428; GFX10-NEXT:    ds_write_b8 v0, v5 offset:7
429; GFX10-NEXT:    ds_write_b8 v0, v3 offset:8
430; GFX10-NEXT:    ds_write_b8 v0, v1 offset:9
431; GFX10-NEXT:    ds_write_b8 v0, v2 offset:10
432; GFX10-NEXT:    ds_write_b8 v0, v4 offset:11
433; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
434; GFX10-NEXT:    s_setpc_b64 s[30:31]
435  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1
436  ret void
437}
438