1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
4
5; Natural mapping
6define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
7  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
8  ; CHECK: bb.1 (%ir-block.0):
9  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
10  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
11  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
12  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
13  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
14  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
15  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
16  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
17  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
18  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
19  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
20  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
21  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
22  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
23  ret float %val
24}
25
26; Natural mapping
27define amdgpu_ps <2 x float> @struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
28  ; CHECK-LABEL: name: struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
29  ; CHECK: bb.1 (%ir-block.0):
30  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
31  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
32  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
33  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
34  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
35  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
36  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
37  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
38  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
39  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
40  ; CHECK:   [[BUFFER_LOAD_DWORDX2_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "TargetCustom7", align 1, addrspace 4)
41  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub0
42  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub1
43  ; CHECK:   $vgpr0 = COPY [[COPY7]]
44  ; CHECK:   $vgpr1 = COPY [[COPY8]]
45  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
46  %val = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
47  ret <2 x float> %val
48}
49
50; Natural mapping
51define amdgpu_ps <3 x float> @struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
52  ; CHECK-LABEL: name: struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
53  ; CHECK: bb.1 (%ir-block.0):
54  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
55  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
56  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
57  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
58  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
59  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
60  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
61  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
62  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
63  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
64  ; CHECK:   [[BUFFER_LOAD_DWORDX3_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "TargetCustom7", align 1, addrspace 4)
65  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub0
66  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub1
67  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_BOTHEN]].sub2
68  ; CHECK:   $vgpr0 = COPY [[COPY7]]
69  ; CHECK:   $vgpr1 = COPY [[COPY8]]
70  ; CHECK:   $vgpr2 = COPY [[COPY9]]
71  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
72  %val = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
73  ret <3 x float> %val
74}
75
76; Natural mapping
77define amdgpu_ps <4 x float> @struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
78  ; CHECK-LABEL: name: struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
79  ; CHECK: bb.1 (%ir-block.0):
80  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
81  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
82  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
83  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
84  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
85  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
86  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
87  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
88  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
89  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
90  ; CHECK:   [[BUFFER_LOAD_DWORDX4_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "TargetCustom7", align 1, addrspace 4)
91  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub0
92  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub1
93  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub2
94  ; CHECK:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_BOTHEN]].sub3
95  ; CHECK:   $vgpr0 = COPY [[COPY7]]
96  ; CHECK:   $vgpr1 = COPY [[COPY8]]
97  ; CHECK:   $vgpr2 = COPY [[COPY9]]
98  ; CHECK:   $vgpr3 = COPY [[COPY10]]
99  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
100  %val = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
101  ret <4 x float> %val
102}
103
104; Natural mapping
105define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
106  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0
107  ; CHECK: bb.1 (%ir-block.0):
108  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
109  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
110  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
111  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
112  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
113  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
114  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
115  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
116  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
117  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
118  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1
119  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
120  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
121  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
122  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 0)
123  ret float %val
124}
125
126; Natural mapping
127define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset.base, i32 inreg %soffset) {
128  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095
129  ; CHECK: bb.1 (%ir-block.0):
130  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
131  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
132  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
133  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
134  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
135  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
136  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
137  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
138  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
139  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
140  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 4095, align 1, addrspace 4)
141  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
142  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
143  %voffset = add i32 %voffset.base, 4095
144  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
145  ret float %val
146}
147
148define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset) {
149  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64
150  ; CHECK: bb.1 (%ir-block.0):
151  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1
152  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
153  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
154  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
155  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
156  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
157  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
158  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
159  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 64
160  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
161  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
162  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
163  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
164  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 64, i32 0)
165  ret float %val
166}
167
168; Need to legalize all reg operands
169define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %vindex, i32 inreg %voffset, i32 %soffset) {
170  ; CHECK-LABEL: name: struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset
171  ; CHECK: bb.1 (%ir-block.0):
172  ; CHECK:   successors: %bb.2(0x80000000)
173  ; CHECK:   liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
174  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
175  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
176  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
177  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
178  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
179  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3
180  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4
181  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
182  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
183  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
184  ; CHECK:   [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
185  ; CHECK:   [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
186  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
187  ; CHECK: bb.2:
188  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
189  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
190  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub1, implicit $exec
191  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
192  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY9]], implicit $exec
193  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]].sub0, implicit $exec
194  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]].sub1, implicit $exec
195  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
196  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY10]], implicit $exec
197  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
198  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
199  ; CHECK:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
200  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
201  ; CHECK:   [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc
202  ; CHECK:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1
203  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
204  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
205  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
206  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
207  ; CHECK: bb.3:
208  ; CHECK:   successors: %bb.4(0x80000000)
209  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
210  ; CHECK: bb.4:
211  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
212  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
213  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
214  ret float %val
215}
216
217define amdgpu_ps float @struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
218  ; CHECK-LABEL: name: struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
219  ; CHECK: bb.1 (%ir-block.0):
220  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
221  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
222  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
223  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
224  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
225  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
226  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
227  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
228  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
229  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
230  ; CHECK:   [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "TargetCustom7", addrspace 4)
231  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255
232  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
233  ; CHECK:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[BUFFER_LOAD_UBYTE_BOTHEN]], [[COPY7]], implicit $exec
234  ; CHECK:   $vgpr0 = COPY [[V_AND_B32_e64_]]
235  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
236  %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
237  %ext = zext i8 %val to i32
238  %cast = bitcast i32 %ext to float
239  ret float %cast
240}
241
242define amdgpu_ps float @struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
243  ; CHECK-LABEL: name: struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
244  ; CHECK: bb.1 (%ir-block.0):
245  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
246  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
247  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
248  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
249  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
250  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
251  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
252  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
253  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
254  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
255  ; CHECK:   [[BUFFER_LOAD_UBYTE_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "TargetCustom7", addrspace 4)
256  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 24
257  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
258  ; CHECK:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY7]], [[BUFFER_LOAD_UBYTE_BOTHEN]], implicit $exec
259  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
260  ; CHECK:   [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY8]], [[V_LSHLREV_B32_e64_]], implicit $exec
261  ; CHECK:   $vgpr0 = COPY [[V_ASHRREV_I32_e64_]]
262  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
263  %val = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
264  %ext = sext i8 %val to i32
265  %cast = bitcast i32 %ext to float
266  ret float %cast
267}
268
269define amdgpu_ps float @struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
270  ; CHECK-LABEL: name: struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
271  ; CHECK: bb.1 (%ir-block.0):
272  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
273  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
274  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
275  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
276  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
277  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
278  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
279  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
280  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
281  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
282  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "TargetCustom7", align 1, addrspace 4)
283  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
284  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
285  ; CHECK:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[BUFFER_LOAD_USHORT_BOTHEN]], [[COPY7]], implicit $exec
286  ; CHECK:   $vgpr0 = COPY [[V_AND_B32_e64_]]
287  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
288  %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
289  %ext = zext i16 %val to i32
290  %cast = bitcast i32 %ext to float
291  ret float %cast
292}
293
294define amdgpu_ps float @struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
295  ; CHECK-LABEL: name: struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
296  ; CHECK: bb.1 (%ir-block.0):
297  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
298  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
299  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
300  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
301  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
302  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
303  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
304  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
305  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
306  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
307  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "TargetCustom7", align 1, addrspace 4)
308  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
309  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
310  ; CHECK:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY7]], [[BUFFER_LOAD_USHORT_BOTHEN]], implicit $exec
311  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
312  ; CHECK:   [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY8]], [[V_LSHLREV_B32_e64_]], implicit $exec
313  ; CHECK:   $vgpr0 = COPY [[V_ASHRREV_I32_e64_]]
314  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
315  %val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
316  %ext = sext i16 %val to i32
317  %cast = bitcast i32 %ext to float
318  ret float %cast
319}
320
321; Natural mapping
322define amdgpu_ps half @struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
323  ; CHECK-LABEL: name: struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
324  ; CHECK: bb.1 (%ir-block.0):
325  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
326  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
327  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
328  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
329  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
330  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
331  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
332  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
333  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
334  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
335  ; CHECK:   [[BUFFER_LOAD_USHORT_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "TargetCustom7", align 1, addrspace 4)
336  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_BOTHEN]]
337  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
338  %val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
339  ret half %val
340}
341
342; Natural mapping
343define amdgpu_ps <2 x half> @struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
344  ; CHECK-LABEL: name: struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
345  ; CHECK: bb.1 (%ir-block.0):
346  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
347  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
348  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
349  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
350  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
351  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
352  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
353  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
354  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
355  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
356  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
357  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
358  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
359  %val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
360  ret <2 x half> %val
361}
362
363; FIXME: Crashes
364; define amdgpu_ps <3 x half> @struct_buffer_load_v3f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
365;   %val = call <3 x half> @llvm.amdgcn.struct.buffer.load.v3f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
366;   ret <3 x half> %val
367; }
368
369; Natural mapping
370define amdgpu_ps <4 x half> @struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
371  ; CHECK-LABEL: name: struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset
372  ; CHECK: bb.1 (%ir-block.0):
373  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
374  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
375  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
376  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
377  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
378  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
379  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
380  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
381  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
382  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
383  ; CHECK:   [[BUFFER_LOAD_DWORDX2_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "TargetCustom7", align 1, addrspace 4)
384  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub0
385  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_BOTHEN]].sub1
386  ; CHECK:   $vgpr0 = COPY [[COPY7]]
387  ; CHECK:   $vgpr1 = COPY [[COPY8]]
388  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
389  %val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
390  ret <4 x half> %val
391}
392
393; Natural mapping + glc
394define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
395  ; CHECK-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc
396  ; CHECK: bb.1 (%ir-block.0):
397  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
398  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
399  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
400  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
401  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
402  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
403  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
404  ; CHECK:   [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
405  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
406  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
407  ; CHECK:   [[BUFFER_LOAD_DWORD_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
408  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
409  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
410  %val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 1)
411  ret float %val
412}
413
414declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32 immarg) #0
415declare i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32>, i32, i32, i32, i32 immarg) #0
416declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
417declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
418declare <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
419declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #0
420declare half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
421declare <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
422declare <3 x half> @llvm.amdgcn.struct.buffer.load.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
423declare <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32>, i32, i32, i32, i32 immarg) #0
424
425attributes #0 = { nounwind readonly }
426