1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX6 %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX7 %s
4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -simplify-mir -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
5
6; FIXME: Merge with regbankselect, which mostly overlaps when all types supported.
7
8; Natural mapping
9define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
10  ; GFX6-LABEL: name: s_buffer_load_i32
11  ; GFX6: bb.1 (%ir-block.0):
12  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
13  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
14  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
15  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
16  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
17  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
18  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
19  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)
20  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
21  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
22  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
23  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
24  ; GFX7-LABEL: name: s_buffer_load_i32
25  ; GFX7: bb.1 (%ir-block.0):
26  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
27  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
28  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
29  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
30  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
31  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
32  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
33  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)
34  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
35  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
36  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
37  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
38  ; GFX8-LABEL: name: s_buffer_load_i32
39  ; GFX8: bb.1 (%ir-block.0):
40  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
41  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
42  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
43  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
44  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
45  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
46  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
47  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 4)
48  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
49  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
50  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
51  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
52  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
53  ret i32 %val
54}
55
56define amdgpu_ps i32 @s_buffer_load_i32_glc(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
57  ; GFX6-LABEL: name: s_buffer_load_i32_glc
58  ; GFX6: bb.1 (%ir-block.0):
59  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
60  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
61  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
62  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
63  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
64  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
65  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
66  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)
67  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
68  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
69  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
70  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
71  ; GFX7-LABEL: name: s_buffer_load_i32_glc
72  ; GFX7: bb.1 (%ir-block.0):
73  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
74  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
75  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
76  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
77  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
78  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
79  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
80  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)
81  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
82  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
83  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
84  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
85  ; GFX8-LABEL: name: s_buffer_load_i32_glc
86  ; GFX8: bb.1 (%ir-block.0):
87  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
88  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
89  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
90  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
91  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
92  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
93  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
94  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[COPY4]], 1, 0 :: (dereferenceable invariant load 4)
95  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
96  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
97  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
98  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
99  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %soffset, i32 1)
100  ret i32 %val
101}
102
103define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
104  ; GFX6-LABEL: name: s_buffer_load_v2i32
105  ; GFX6: bb.1 (%ir-block.0):
106  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
107  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
108  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
109  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
110  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
111  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
112  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
113  ; GFX6:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)
114  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
115  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
116  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
117  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
118  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
119  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
120  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
121  ; GFX6:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
122  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
123  ; GFX7-LABEL: name: s_buffer_load_v2i32
124  ; GFX7: bb.1 (%ir-block.0):
125  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
126  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
127  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
128  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
129  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
130  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
131  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
132  ; GFX7:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)
133  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
134  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
135  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
136  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
137  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
138  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
139  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
140  ; GFX7:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
141  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
142  ; GFX8-LABEL: name: s_buffer_load_v2i32
143  ; GFX8: bb.1 (%ir-block.0):
144  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
145  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
146  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
147  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
148  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
149  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
150  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
151  ; GFX8:   [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 8, align 4)
152  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
153  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
154  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
155  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
156  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
157  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
158  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
159  ; GFX8:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
160  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
161  %val = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
162  ret <2 x i32> %val
163}
164
165define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
166  ; GFX6-LABEL: name: s_buffer_load_v3i32
167  ; GFX6: bb.1 (%ir-block.0):
168  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
169  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
170  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
171  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
172  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
173  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
174  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
175  ; GFX6:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
176  ; GFX6:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
177  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
178  ; GFX6:   [[COPY5:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
179  ; GFX6:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
180  ; GFX6:   [[COPY7:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
181  ; GFX6:   [[COPY8:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
182  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub0
183  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub1
184  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub2
185  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
186  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
187  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
188  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
189  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
190  ; GFX6:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
191  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
192  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
193  ; GFX6:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
194  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
195  ; GFX7-LABEL: name: s_buffer_load_v3i32
196  ; GFX7: bb.1 (%ir-block.0):
197  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
198  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
199  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
200  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
201  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
202  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
203  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
204  ; GFX7:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
205  ; GFX7:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
206  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
207  ; GFX7:   [[COPY5:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
208  ; GFX7:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
209  ; GFX7:   [[COPY7:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
210  ; GFX7:   [[COPY8:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
211  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub0
212  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub1
213  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub2
214  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
215  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
216  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
217  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
218  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
219  ; GFX7:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
220  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
221  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
222  ; GFX7:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
223  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
224  ; GFX8-LABEL: name: s_buffer_load_v3i32
225  ; GFX8: bb.1 (%ir-block.0):
226  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
227  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
228  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
229  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
230  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
231  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
232  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
233  ; GFX8:   [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
234  ; GFX8:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
235  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
236  ; GFX8:   [[COPY5:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
237  ; GFX8:   [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
238  ; GFX8:   [[COPY7:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
239  ; GFX8:   [[COPY8:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
240  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub0
241  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub1
242  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub2
243  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
244  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
245  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
246  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
247  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
248  ; GFX8:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
249  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
250  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
251  ; GFX8:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
252  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
253  %val = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
254  ret <3 x i32> %val
255}
256
257define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
258  ; GFX6-LABEL: name: s_buffer_load_v8i32
259  ; GFX6: bb.1 (%ir-block.0):
260  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
261  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
262  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
263  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
264  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
265  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
266  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
267  ; GFX6:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)
268  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
269  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
270  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
271  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
272  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
273  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
274  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
275  ; GFX6:   [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
276  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
277  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
278  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
279  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
280  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
281  ; GFX6:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
282  ; GFX6:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
283  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
284  ; GFX6:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
285  ; GFX6:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
286  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
287  ; GFX6:   $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
288  ; GFX6:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
289  ; GFX6:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
290  ; GFX6:   $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
291  ; GFX6:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
292  ; GFX6:   [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
293  ; GFX6:   $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
294  ; GFX6:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
295  ; GFX6:   [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
296  ; GFX6:   $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
297  ; GFX6:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
298  ; GFX6:   [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
299  ; GFX6:   $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
300  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
301  ; GFX7-LABEL: name: s_buffer_load_v8i32
302  ; GFX7: bb.1 (%ir-block.0):
303  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
304  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
305  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
306  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
307  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
308  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
309  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
310  ; GFX7:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)
311  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
312  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
313  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
314  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
315  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
316  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
317  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
318  ; GFX7:   [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
319  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
320  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
321  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
322  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
323  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
324  ; GFX7:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
325  ; GFX7:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
326  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
327  ; GFX7:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
328  ; GFX7:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
329  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
330  ; GFX7:   $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
331  ; GFX7:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
332  ; GFX7:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
333  ; GFX7:   $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
334  ; GFX7:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
335  ; GFX7:   [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
336  ; GFX7:   $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
337  ; GFX7:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
338  ; GFX7:   [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
339  ; GFX7:   $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
340  ; GFX7:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
341  ; GFX7:   [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
342  ; GFX7:   $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
343  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
344  ; GFX8-LABEL: name: s_buffer_load_v8i32
345  ; GFX8: bb.1 (%ir-block.0):
346  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
347  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
348  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
349  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
350  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
351  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
352  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
353  ; GFX8:   [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 32, align 4)
354  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
355  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
356  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
357  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
358  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
359  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
360  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
361  ; GFX8:   [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
362  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
363  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
364  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
365  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
366  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
367  ; GFX8:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
368  ; GFX8:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
369  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
370  ; GFX8:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
371  ; GFX8:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
372  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
373  ; GFX8:   $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
374  ; GFX8:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
375  ; GFX8:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
376  ; GFX8:   $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
377  ; GFX8:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
378  ; GFX8:   [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
379  ; GFX8:   $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
380  ; GFX8:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
381  ; GFX8:   [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
382  ; GFX8:   $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
383  ; GFX8:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
384  ; GFX8:   [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
385  ; GFX8:   $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
386  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
387  %val = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
388  ret <8 x i32> %val
389}
390
391define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
392  ; GFX6-LABEL: name: s_buffer_load_v16i32
393  ; GFX6: bb.1 (%ir-block.0):
394  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
395  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
396  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
397  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
398  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
399  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
400  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
401  ; GFX6:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)
402  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
403  ; GFX6:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
404  ; GFX6:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
405  ; GFX6:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
406  ; GFX6:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
407  ; GFX6:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
408  ; GFX6:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
409  ; GFX6:   [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
410  ; GFX6:   [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
411  ; GFX6:   [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
412  ; GFX6:   [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
413  ; GFX6:   [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
414  ; GFX6:   [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
415  ; GFX6:   [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
416  ; GFX6:   [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
417  ; GFX6:   [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
418  ; GFX6:   [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
419  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
420  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
421  ; GFX6:   [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
422  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
423  ; GFX6:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
424  ; GFX6:   [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
425  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
426  ; GFX6:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
427  ; GFX6:   [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
428  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
429  ; GFX6:   $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
430  ; GFX6:   [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
431  ; GFX6:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
432  ; GFX6:   $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
433  ; GFX6:   [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
434  ; GFX6:   [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
435  ; GFX6:   $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
436  ; GFX6:   [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
437  ; GFX6:   [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
438  ; GFX6:   $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
439  ; GFX6:   [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
440  ; GFX6:   [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
441  ; GFX6:   $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
442  ; GFX6:   [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
443  ; GFX6:   [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
444  ; GFX6:   $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
445  ; GFX6:   [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
446  ; GFX6:   [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
447  ; GFX6:   $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
448  ; GFX6:   [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
449  ; GFX6:   [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
450  ; GFX6:   $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
451  ; GFX6:   [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
452  ; GFX6:   [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
453  ; GFX6:   $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
454  ; GFX6:   [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
455  ; GFX6:   [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
456  ; GFX6:   $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
457  ; GFX6:   [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
458  ; GFX6:   [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
459  ; GFX6:   $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
460  ; GFX6:   [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
461  ; GFX6:   [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
462  ; GFX6:   $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
463  ; GFX6:   [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
464  ; GFX6:   [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
465  ; GFX6:   $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
466  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
467  ; GFX7-LABEL: name: s_buffer_load_v16i32
468  ; GFX7: bb.1 (%ir-block.0):
469  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
470  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
471  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
472  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
473  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
474  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
475  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
476  ; GFX7:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)
477  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
478  ; GFX7:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
479  ; GFX7:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
480  ; GFX7:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
481  ; GFX7:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
482  ; GFX7:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
483  ; GFX7:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
484  ; GFX7:   [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
485  ; GFX7:   [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
486  ; GFX7:   [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
487  ; GFX7:   [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
488  ; GFX7:   [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
489  ; GFX7:   [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
490  ; GFX7:   [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
491  ; GFX7:   [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
492  ; GFX7:   [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
493  ; GFX7:   [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
494  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
495  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
496  ; GFX7:   [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
497  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
498  ; GFX7:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
499  ; GFX7:   [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
500  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
501  ; GFX7:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
502  ; GFX7:   [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
503  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
504  ; GFX7:   $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
505  ; GFX7:   [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
506  ; GFX7:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
507  ; GFX7:   $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
508  ; GFX7:   [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
509  ; GFX7:   [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
510  ; GFX7:   $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
511  ; GFX7:   [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
512  ; GFX7:   [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
513  ; GFX7:   $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
514  ; GFX7:   [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
515  ; GFX7:   [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
516  ; GFX7:   $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
517  ; GFX7:   [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
518  ; GFX7:   [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
519  ; GFX7:   $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
520  ; GFX7:   [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
521  ; GFX7:   [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
522  ; GFX7:   $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
523  ; GFX7:   [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
524  ; GFX7:   [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
525  ; GFX7:   $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
526  ; GFX7:   [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
527  ; GFX7:   [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
528  ; GFX7:   $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
529  ; GFX7:   [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
530  ; GFX7:   [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
531  ; GFX7:   $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
532  ; GFX7:   [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
533  ; GFX7:   [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
534  ; GFX7:   $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
535  ; GFX7:   [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
536  ; GFX7:   [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
537  ; GFX7:   $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
538  ; GFX7:   [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
539  ; GFX7:   [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
540  ; GFX7:   $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
541  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
542  ; GFX8-LABEL: name: s_buffer_load_v16i32
543  ; GFX8: bb.1 (%ir-block.0):
544  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
545  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
546  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
547  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
548  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
549  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
550  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
551  ; GFX8:   [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 64, align 4)
552  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
553  ; GFX8:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
554  ; GFX8:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
555  ; GFX8:   [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
556  ; GFX8:   [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
557  ; GFX8:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
558  ; GFX8:   [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
559  ; GFX8:   [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
560  ; GFX8:   [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
561  ; GFX8:   [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
562  ; GFX8:   [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
563  ; GFX8:   [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
564  ; GFX8:   [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
565  ; GFX8:   [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
566  ; GFX8:   [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
567  ; GFX8:   [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
568  ; GFX8:   [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
569  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
570  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
571  ; GFX8:   [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
572  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
573  ; GFX8:   $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
574  ; GFX8:   [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
575  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
576  ; GFX8:   $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
577  ; GFX8:   [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
578  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
579  ; GFX8:   $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
580  ; GFX8:   [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
581  ; GFX8:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
582  ; GFX8:   $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
583  ; GFX8:   [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
584  ; GFX8:   [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
585  ; GFX8:   $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
586  ; GFX8:   [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
587  ; GFX8:   [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
588  ; GFX8:   $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
589  ; GFX8:   [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
590  ; GFX8:   [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
591  ; GFX8:   $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
592  ; GFX8:   [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
593  ; GFX8:   [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
594  ; GFX8:   $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
595  ; GFX8:   [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
596  ; GFX8:   [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
597  ; GFX8:   $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
598  ; GFX8:   [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
599  ; GFX8:   [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
600  ; GFX8:   $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
601  ; GFX8:   [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
602  ; GFX8:   [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
603  ; GFX8:   $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
604  ; GFX8:   [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
605  ; GFX8:   [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
606  ; GFX8:   $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
607  ; GFX8:   [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
608  ; GFX8:   [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
609  ; GFX8:   $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
610  ; GFX8:   [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
611  ; GFX8:   [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
612  ; GFX8:   $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
613  ; GFX8:   [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
614  ; GFX8:   [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
615  ; GFX8:   $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
616  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
617  %val = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
618  ret <16 x i32> %val
619}
620
621define amdgpu_ps i32 @s_buffer_load_i32_offset_1(<4 x i32> inreg %rsrc) {
622  ; GFX6-LABEL: name: s_buffer_load_i32_offset_1
623  ; GFX6: bb.1 (%ir-block.0):
624  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
625  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
626  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
627  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
628  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
629  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
630  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
631  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
632  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
633  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
634  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
635  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
636  ; GFX7-LABEL: name: s_buffer_load_i32_offset_1
637  ; GFX7: bb.1 (%ir-block.0):
638  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
639  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
640  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
641  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
642  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
643  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
644  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
645  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
646  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
647  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
648  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
649  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
650  ; GFX8-LABEL: name: s_buffer_load_i32_offset_1
651  ; GFX8: bb.1 (%ir-block.0):
652  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
653  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
654  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
655  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
656  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
657  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
658  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0, 0 :: (dereferenceable invariant load 4)
659  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
660  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
661  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
662  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
663  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 1, i32 0)
664  ret i32 %val
665}
666
667define amdgpu_ps i32 @s_buffer_load_i32_offset_glc_4(<4 x i32> inreg %rsrc) {
668  ; GFX6-LABEL: name: s_buffer_load_i32_offset_glc_4
669  ; GFX6: bb.1 (%ir-block.0):
670  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
671  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
672  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
673  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
674  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
675  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
676  ; GFX6:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 1, 0 :: (dereferenceable invariant load 4)
677  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
678  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
679  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
680  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
681  ; GFX7-LABEL: name: s_buffer_load_i32_offset_glc_4
682  ; GFX7: bb.1 (%ir-block.0):
683  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
684  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
685  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
686  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
687  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
688  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
689  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 1, 0 :: (dereferenceable invariant load 4)
690  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
691  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
692  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
693  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
694  ; GFX8-LABEL: name: s_buffer_load_i32_offset_glc_4
695  ; GFX8: bb.1 (%ir-block.0):
696  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
697  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
698  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
699  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
700  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
701  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
702  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1, 0 :: (dereferenceable invariant load 4)
703  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
704  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
705  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
706  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
707  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 4, i32 1)
708  ret i32 %val
709}
710
711define amdgpu_ps i32 @s_buffer_load_i32_offset_255(<4 x i32> inreg %rsrc) {
712  ; GFX6-LABEL: name: s_buffer_load_i32_offset_255
713  ; GFX6: bb.1 (%ir-block.0):
714  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
715  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
716  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
717  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
718  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
719  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
720  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255
721  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
722  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
723  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
724  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
725  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
726  ; GFX7-LABEL: name: s_buffer_load_i32_offset_255
727  ; GFX7: bb.1 (%ir-block.0):
728  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
729  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
730  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
731  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
732  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
733  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
734  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255
735  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
736  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
737  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
738  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
739  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
740  ; GFX8-LABEL: name: s_buffer_load_i32_offset_255
741  ; GFX8: bb.1 (%ir-block.0):
742  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
743  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
744  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
745  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
746  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
747  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
748  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0, 0 :: (dereferenceable invariant load 4)
749  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
750  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
751  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
752  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
753  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 255, i32 0)
754  ret i32 %val
755}
756
757define amdgpu_ps i32 @s_buffer_load_i32_offset_256(<4 x i32> inreg %rsrc) {
758  ; GFX6-LABEL: name: s_buffer_load_i32_offset_256
759  ; GFX6: bb.1 (%ir-block.0):
760  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
761  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
762  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
763  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
764  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
765  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
766  ; GFX6:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 64, 0, 0 :: (dereferenceable invariant load 4)
767  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
768  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
769  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
770  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
771  ; GFX7-LABEL: name: s_buffer_load_i32_offset_256
772  ; GFX7: bb.1 (%ir-block.0):
773  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
774  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
775  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
776  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
777  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
778  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
779  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 64, 0, 0 :: (dereferenceable invariant load 4)
780  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
781  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
782  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
783  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
784  ; GFX8-LABEL: name: s_buffer_load_i32_offset_256
785  ; GFX8: bb.1 (%ir-block.0):
786  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
787  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
788  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
789  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
790  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
791  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
792  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0, 0 :: (dereferenceable invariant load 4)
793  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
794  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
795  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
796  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
797  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 256, i32 0)
798  ret i32 %val
799}
800
801define amdgpu_ps i32 @s_buffer_load_i32_offset_1020(<4 x i32> inreg %rsrc) {
802  ; GFX6-LABEL: name: s_buffer_load_i32_offset_1020
803  ; GFX6: bb.1 (%ir-block.0):
804  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
805  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
806  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
807  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
808  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
809  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
810  ; GFX6:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0, 0 :: (dereferenceable invariant load 4)
811  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
812  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
813  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
814  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
815  ; GFX7-LABEL: name: s_buffer_load_i32_offset_1020
816  ; GFX7: bb.1 (%ir-block.0):
817  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
818  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
819  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
820  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
821  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
822  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
823  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0, 0 :: (dereferenceable invariant load 4)
824  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
825  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
826  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
827  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
828  ; GFX8-LABEL: name: s_buffer_load_i32_offset_1020
829  ; GFX8: bb.1 (%ir-block.0):
830  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
831  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
832  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
833  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
834  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
835  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
836  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0, 0 :: (dereferenceable invariant load 4)
837  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
838  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
839  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
840  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
841  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 1020, i32 0)
842  ret i32 %val
843}
844
845define amdgpu_ps i32 @s_buffer_load_i32_offset_1023(<4 x i32> inreg %rsrc) {
846  ; GFX6-LABEL: name: s_buffer_load_i32_offset_1023
847  ; GFX6: bb.1 (%ir-block.0):
848  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
849  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
850  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
851  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
852  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
853  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
854  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
855  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
856  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
857  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
858  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
859  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
860  ; GFX7-LABEL: name: s_buffer_load_i32_offset_1023
861  ; GFX7: bb.1 (%ir-block.0):
862  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
863  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
864  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
865  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
866  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
867  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
868  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1023
869  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
870  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
871  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
872  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
873  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
874  ; GFX8-LABEL: name: s_buffer_load_i32_offset_1023
875  ; GFX8: bb.1 (%ir-block.0):
876  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
877  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
878  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
879  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
880  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
881  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
882  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0, 0 :: (dereferenceable invariant load 4)
883  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
884  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
885  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
886  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
887  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 1023, i32 0)
888  ret i32 %val
889}
890
891define amdgpu_ps i32 @s_buffer_load_i32_offset_1024(<4 x i32> inreg %rsrc) {
892  ; GFX6-LABEL: name: s_buffer_load_i32_offset_1024
893  ; GFX6: bb.1 (%ir-block.0):
894  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
895  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
896  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
897  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
898  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
899  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
900  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
901  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
902  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
903  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
904  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
905  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
906  ; GFX7-LABEL: name: s_buffer_load_i32_offset_1024
907  ; GFX7: bb.1 (%ir-block.0):
908  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
909  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
910  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
911  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
912  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
913  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
914  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 256, 0, 0 :: (dereferenceable invariant load 4)
915  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
916  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
917  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
918  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
919  ; GFX8-LABEL: name: s_buffer_load_i32_offset_1024
920  ; GFX8: bb.1 (%ir-block.0):
921  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
922  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
923  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
924  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
925  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
926  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
927  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0, 0 :: (dereferenceable invariant load 4)
928  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
929  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
930  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
931  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
932  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 1024, i32 0)
933  ret i32 %val
934}
935
936define amdgpu_ps i32 @s_buffer_load_i32_offset_1025(<4 x i32> inreg %rsrc) {
937  ; GFX6-LABEL: name: s_buffer_load_i32_offset_1025
938  ; GFX6: bb.1 (%ir-block.0):
939  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
940  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
941  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
942  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
943  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
944  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
945  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1025
946  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
947  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
948  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
949  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
950  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
951  ; GFX7-LABEL: name: s_buffer_load_i32_offset_1025
952  ; GFX7: bb.1 (%ir-block.0):
953  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
954  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
955  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
956  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
957  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
958  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
959  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1025
960  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
961  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
962  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
963  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
964  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
965  ; GFX8-LABEL: name: s_buffer_load_i32_offset_1025
966  ; GFX8: bb.1 (%ir-block.0):
967  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
968  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
969  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
970  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
971  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
972  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
973  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0, 0 :: (dereferenceable invariant load 4)
974  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
975  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
976  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
977  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
978  %val = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 1025, i32 0)
979  ret i32 %val
980}
981
982define amdgpu_ps i32 @s_buffer_load_i32_offset_neg1(<4 x i32> inreg %desc) {
983  ; GFX6-LABEL: name: s_buffer_load_i32_offset_neg1
984  ; GFX6: bb.1 (%ir-block.0):
985  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
986  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
987  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
988  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
989  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
990  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
991  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
992  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
993  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
994  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
995  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
996  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
997  ; GFX7-LABEL: name: s_buffer_load_i32_offset_neg1
998  ; GFX7: bb.1 (%ir-block.0):
999  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1000  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1001  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1002  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1003  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1004  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1005  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
1006  ; GFX7:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1007  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1008  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1009  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1010  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1011  ; GFX8-LABEL: name: s_buffer_load_i32_offset_neg1
1012  ; GFX8: bb.1 (%ir-block.0):
1013  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1014  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1015  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1016  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1017  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1018  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1019  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
1020  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1021  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1022  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1023  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1024  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1025  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -1, i32 0)
1026  ret i32 %load
1027}
1028
1029define amdgpu_ps i32 @s_buffer_load_i32_offset_neg4(<4 x i32> inreg %desc) {
1030  ; GFX6-LABEL: name: s_buffer_load_i32_offset_neg4
1031  ; GFX6: bb.1 (%ir-block.0):
1032  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1033  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1034  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1035  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1036  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1037  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1038  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
1039  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1040  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1041  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1042  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1043  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1044  ; GFX7-LABEL: name: s_buffer_load_i32_offset_neg4
1045  ; GFX7: bb.1 (%ir-block.0):
1046  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1047  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1048  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1049  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1050  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1051  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1052  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073741823, 0, 0 :: (dereferenceable invariant load 4)
1053  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1054  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1055  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1056  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1057  ; GFX8-LABEL: name: s_buffer_load_i32_offset_neg4
1058  ; GFX8: bb.1 (%ir-block.0):
1059  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1060  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1061  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1062  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1063  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1064  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1065  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
1066  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1067  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1068  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1069  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1070  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1071  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -4, i32 0)
1072  ret i32 %load
1073}
1074
1075define amdgpu_ps i32 @s_buffer_load_i32_offset_neg8(<4 x i32> inreg %desc) {
1076  ; GFX6-LABEL: name: s_buffer_load_i32_offset_neg8
1077  ; GFX6: bb.1 (%ir-block.0):
1078  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1079  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1080  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1081  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1082  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1083  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1084  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
1085  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1086  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1087  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1088  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1089  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1090  ; GFX7-LABEL: name: s_buffer_load_i32_offset_neg8
1091  ; GFX7: bb.1 (%ir-block.0):
1092  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1093  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1094  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1095  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1096  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1097  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1098  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073741822, 0, 0 :: (dereferenceable invariant load 4)
1099  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1100  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1101  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1102  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1103  ; GFX8-LABEL: name: s_buffer_load_i32_offset_neg8
1104  ; GFX8: bb.1 (%ir-block.0):
1105  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1106  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1107  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1108  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1109  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1110  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1111  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
1112  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1113  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1114  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1115  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1116  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1117  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -8, i32 0)
1118  ret i32 %load
1119}
1120
1121define amdgpu_ps i32 @s_buffer_load_i32_offset_bit31(<4 x i32> inreg %desc) {
1122  ; GFX6-LABEL: name: s_buffer_load_i32_offset_bit31
1123  ; GFX6: bb.1 (%ir-block.0):
1124  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1125  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1126  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1127  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1128  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1129  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1130  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
1131  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1132  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1133  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1134  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1135  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1136  ; GFX7-LABEL: name: s_buffer_load_i32_offset_bit31
1137  ; GFX7: bb.1 (%ir-block.0):
1138  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1139  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1140  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1141  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1142  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1143  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1144  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 536870912, 0, 0 :: (dereferenceable invariant load 4)
1145  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1146  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1147  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1148  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1149  ; GFX8-LABEL: name: s_buffer_load_i32_offset_bit31
1150  ; GFX8: bb.1 (%ir-block.0):
1151  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1152  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1153  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1154  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1155  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1156  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1157  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
1158  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1159  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1160  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1161  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1162  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1163  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -2147483648, i32 0)
1164  ret i32 %load
1165}
1166
1167define amdgpu_ps i32 @s_buffer_load_i32_offset_glc_bit30(<4 x i32> inreg %desc) {
1168  ; GFX6-LABEL: name: s_buffer_load_i32_offset_glc_bit30
1169  ; GFX6: bb.1 (%ir-block.0):
1170  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1171  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1172  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1173  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1174  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1175  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1176  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824
1177  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 1, 0 :: (dereferenceable invariant load 4)
1178  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1179  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1180  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1181  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1182  ; GFX7-LABEL: name: s_buffer_load_i32_offset_glc_bit30
1183  ; GFX7: bb.1 (%ir-block.0):
1184  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1185  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1186  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1187  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1188  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1189  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1190  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 268435456, 1, 0 :: (dereferenceable invariant load 4)
1191  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1192  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1193  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1194  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1195  ; GFX8-LABEL: name: s_buffer_load_i32_offset_glc_bit30
1196  ; GFX8: bb.1 (%ir-block.0):
1197  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1198  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1199  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1200  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1201  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1202  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1203  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824
1204  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 1, 0 :: (dereferenceable invariant load 4)
1205  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1206  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1207  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1208  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1209  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1073741824, i32 1)
1210  ret i32 %load
1211}
1212
1213define amdgpu_ps i32 @s_buffer_load_i32_offset_bit29(<4 x i32> inreg %desc) {
1214  ; GFX6-LABEL: name: s_buffer_load_i32_offset_bit29
1215  ; GFX6: bb.1 (%ir-block.0):
1216  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1217  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1218  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1219  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1220  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1221  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1222  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912
1223  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1224  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1225  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1226  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1227  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1228  ; GFX7-LABEL: name: s_buffer_load_i32_offset_bit29
1229  ; GFX7: bb.1 (%ir-block.0):
1230  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1231  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1232  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1233  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1234  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1235  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1236  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 134217728, 0, 0 :: (dereferenceable invariant load 4)
1237  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1238  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1239  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1240  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1241  ; GFX8-LABEL: name: s_buffer_load_i32_offset_bit29
1242  ; GFX8: bb.1 (%ir-block.0):
1243  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1244  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1245  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1246  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1247  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1248  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1249  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912
1250  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1251  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1252  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1253  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1254  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1255  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 536870912, i32 0)
1256  ret i32 %load
1257}
1258
1259define amdgpu_ps i32 @s_buffer_load_i32_offset_bit21(<4 x i32> inreg %desc) {
1260  ; GFX6-LABEL: name: s_buffer_load_i32_offset_bit21
1261  ; GFX6: bb.1 (%ir-block.0):
1262  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1263  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1264  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1265  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1266  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1267  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1268  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2097152
1269  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1270  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1271  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1272  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1273  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1274  ; GFX7-LABEL: name: s_buffer_load_i32_offset_bit21
1275  ; GFX7: bb.1 (%ir-block.0):
1276  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1277  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1278  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1279  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1280  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1281  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1282  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 524288, 0, 0 :: (dereferenceable invariant load 4)
1283  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1284  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1285  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1286  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1287  ; GFX8-LABEL: name: s_buffer_load_i32_offset_bit21
1288  ; GFX8: bb.1 (%ir-block.0):
1289  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1290  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1291  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1292  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1293  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1294  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1295  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2097152
1296  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1297  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1298  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1299  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1300  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1301  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 2097152, i32 0)
1302  ret i32 %load
1303}
1304
1305define amdgpu_ps i32 @s_buffer_load_i32_offset_bit20(<4 x i32> inreg %desc) {
1306  ; GFX6-LABEL: name: s_buffer_load_i32_offset_bit20
1307  ; GFX6: bb.1 (%ir-block.0):
1308  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1309  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1310  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1311  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1312  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1313  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1314  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
1315  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1316  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1317  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1318  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1319  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1320  ; GFX7-LABEL: name: s_buffer_load_i32_offset_bit20
1321  ; GFX7: bb.1 (%ir-block.0):
1322  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1323  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1324  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1325  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1326  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1327  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1328  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 262144, 0, 0 :: (dereferenceable invariant load 4)
1329  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1330  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1331  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1332  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1333  ; GFX8-LABEL: name: s_buffer_load_i32_offset_bit20
1334  ; GFX8: bb.1 (%ir-block.0):
1335  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1336  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1337  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1338  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1339  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1340  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1341  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
1342  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1343  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1344  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1345  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1346  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1347  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1048576, i32 0)
1348  ret i32 %load
1349}
1350
1351define amdgpu_ps i32 @s_buffer_load_i32_offset_neg_bit20(<4 x i32> inreg %desc) {
1352  ; GFX6-LABEL: name: s_buffer_load_i32_offset_neg_bit20
1353  ; GFX6: bb.1 (%ir-block.0):
1354  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1355  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1356  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1357  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1358  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1359  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1360  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576
1361  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1362  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1363  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1364  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1365  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1366  ; GFX7-LABEL: name: s_buffer_load_i32_offset_neg_bit20
1367  ; GFX7: bb.1 (%ir-block.0):
1368  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1369  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1370  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1371  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1372  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1373  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1374  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073479680, 0, 0 :: (dereferenceable invariant load 4)
1375  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1376  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1377  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1378  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1379  ; GFX8-LABEL: name: s_buffer_load_i32_offset_neg_bit20
1380  ; GFX8: bb.1 (%ir-block.0):
1381  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1382  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1383  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1384  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1385  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1386  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1387  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576
1388  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1389  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1390  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1391  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1392  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1393  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32  -1048576, i32 0)
1394  ret i32 %load
1395}
1396
1397define amdgpu_ps i32 @s_buffer_load_i32_offset_bit19(<4 x i32> inreg %desc) {
1398  ; GFX6-LABEL: name: s_buffer_load_i32_offset_bit19
1399  ; GFX6: bb.1 (%ir-block.0):
1400  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1401  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1402  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1403  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1404  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1405  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1406  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 524288
1407  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1408  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1409  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1410  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1411  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1412  ; GFX7-LABEL: name: s_buffer_load_i32_offset_bit19
1413  ; GFX7: bb.1 (%ir-block.0):
1414  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1415  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1416  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1417  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1418  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1419  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1420  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 131072, 0, 0 :: (dereferenceable invariant load 4)
1421  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1422  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1423  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1424  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1425  ; GFX8-LABEL: name: s_buffer_load_i32_offset_bit19
1426  ; GFX8: bb.1 (%ir-block.0):
1427  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1428  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1429  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1430  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1431  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1432  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1433  ; GFX8:   [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0, 0 :: (dereferenceable invariant load 4)
1434  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]]
1435  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1436  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1437  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1438  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 524288, i32 0)
1439  ret i32 %load
1440}
1441
1442define amdgpu_ps i32 @s_buffer_load_i32_offset_neg_bit19(<4 x i32> inreg %desc) {
1443  ; GFX6-LABEL: name: s_buffer_load_i32_offset_neg_bit19
1444  ; GFX6: bb.1 (%ir-block.0):
1445  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1446  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1447  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1448  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1449  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1450  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1451  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288
1452  ; GFX6:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1453  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1454  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1455  ; GFX6:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1456  ; GFX6:   SI_RETURN_TO_EPILOG implicit $sgpr0
1457  ; GFX7-LABEL: name: s_buffer_load_i32_offset_neg_bit19
1458  ; GFX7: bb.1 (%ir-block.0):
1459  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1460  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1461  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1462  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1463  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1464  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1465  ; GFX7:   [[S_BUFFER_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM_ci [[REG_SEQUENCE]], 1073610752, 0, 0 :: (dereferenceable invariant load 4)
1466  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM_ci]]
1467  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1468  ; GFX7:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1469  ; GFX7:   SI_RETURN_TO_EPILOG implicit $sgpr0
1470  ; GFX8-LABEL: name: s_buffer_load_i32_offset_neg_bit19
1471  ; GFX8: bb.1 (%ir-block.0):
1472  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5
1473  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1474  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1475  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1476  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1477  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1478  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288
1479  ; GFX8:   [[S_BUFFER_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load 4)
1480  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR]]
1481  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
1482  ; GFX8:   $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
1483  ; GFX8:   SI_RETURN_TO_EPILOG implicit $sgpr0
1484  %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -524288, i32 0)
1485  ret i32 %load
1486}
1487
1488; Check cases that need to be converted to MUBUF due to the offset being a VGPR.
1489define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
1490  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset
1491  ; GFX6: bb.1 (%ir-block.0):
1492  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1493  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1494  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1495  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1496  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1497  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1498  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1499  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1500  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
1501  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
1502  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
1503  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset
1504  ; GFX7: bb.1 (%ir-block.0):
1505  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1506  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1507  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1508  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1509  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1510  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1511  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1512  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1513  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
1514  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
1515  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
1516  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset
1517  ; GFX8: bb.1 (%ir-block.0):
1518  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1519  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1520  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1521  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1522  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1523  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1524  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1525  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1526  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
1527  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
1528  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
1529  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
1530  ret float %val
1531}
1532
1533define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
1534  ; GFX6-LABEL: name: s_buffer_load_v2f32_vgpr_offset
1535  ; GFX6: bb.1 (%ir-block.0):
1536  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1537  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1538  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1539  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1540  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1541  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1542  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1543  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1544  ; GFX6:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)
1545  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
1546  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
1547  ; GFX6:   $vgpr0 = COPY [[COPY5]]
1548  ; GFX6:   $vgpr1 = COPY [[COPY6]]
1549  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
1550  ; GFX7-LABEL: name: s_buffer_load_v2f32_vgpr_offset
1551  ; GFX7: bb.1 (%ir-block.0):
1552  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1553  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1554  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1555  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1556  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1557  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1558  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1559  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1560  ; GFX7:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)
1561  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
1562  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
1563  ; GFX7:   $vgpr0 = COPY [[COPY5]]
1564  ; GFX7:   $vgpr1 = COPY [[COPY6]]
1565  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
1566  ; GFX8-LABEL: name: s_buffer_load_v2f32_vgpr_offset
1567  ; GFX8: bb.1 (%ir-block.0):
1568  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1569  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1570  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1571  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1572  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1573  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1574  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1575  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1576  ; GFX8:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 8, align 4)
1577  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
1578  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
1579  ; GFX8:   $vgpr0 = COPY [[COPY5]]
1580  ; GFX8:   $vgpr1 = COPY [[COPY6]]
1581  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
1582  %val = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
1583  ret <2 x float> %val
1584}
1585
1586define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
1587  ; GFX6-LABEL: name: s_buffer_load_v3f32_vgpr_offset
1588  ; GFX6: bb.1 (%ir-block.0):
1589  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1590  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1591  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1592  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1593  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1594  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1595  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1596  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1597  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1598  ; GFX6:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
1599  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]
1600  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
1601  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
1602  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
1603  ; GFX6:   [[COPY8:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
1604  ; GFX6:   [[COPY9:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
1605  ; GFX6:   [[COPY10:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
1606  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
1607  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
1608  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
1609  ; GFX6:   $vgpr0 = COPY [[COPY11]]
1610  ; GFX6:   $vgpr1 = COPY [[COPY12]]
1611  ; GFX6:   $vgpr2 = COPY [[COPY13]]
1612  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
1613  ; GFX7-LABEL: name: s_buffer_load_v3f32_vgpr_offset
1614  ; GFX7: bb.1 (%ir-block.0):
1615  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1616  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1617  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1618  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1619  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1620  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1621  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1622  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1623  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1624  ; GFX7:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
1625  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]
1626  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
1627  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
1628  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
1629  ; GFX7:   [[COPY8:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
1630  ; GFX7:   [[COPY9:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
1631  ; GFX7:   [[COPY10:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
1632  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
1633  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
1634  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
1635  ; GFX7:   $vgpr0 = COPY [[COPY11]]
1636  ; GFX7:   $vgpr1 = COPY [[COPY12]]
1637  ; GFX7:   $vgpr2 = COPY [[COPY13]]
1638  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
1639  ; GFX8-LABEL: name: s_buffer_load_v3f32_vgpr_offset
1640  ; GFX8: bb.1 (%ir-block.0):
1641  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1642  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1643  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1644  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1645  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1646  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1647  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1648  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1649  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1650  ; GFX8:   [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
1651  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_128 = COPY [[DEF]]
1652  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
1653  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
1654  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
1655  ; GFX8:   [[COPY8:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
1656  ; GFX8:   [[COPY9:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
1657  ; GFX8:   [[COPY10:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
1658  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
1659  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
1660  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
1661  ; GFX8:   $vgpr0 = COPY [[COPY11]]
1662  ; GFX8:   $vgpr1 = COPY [[COPY12]]
1663  ; GFX8:   $vgpr2 = COPY [[COPY13]]
1664  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
1665  %val = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
1666  ret <3 x float> %val
1667}
1668
1669define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
1670  ; GFX6-LABEL: name: s_buffer_load_v4f32_vgpr_offset
1671  ; GFX6: bb.1 (%ir-block.0):
1672  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1673  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1674  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1675  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1676  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1677  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1678  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1679  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1680  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1681  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
1682  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
1683  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
1684  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
1685  ; GFX6:   $vgpr0 = COPY [[COPY5]]
1686  ; GFX6:   $vgpr1 = COPY [[COPY6]]
1687  ; GFX6:   $vgpr2 = COPY [[COPY7]]
1688  ; GFX6:   $vgpr3 = COPY [[COPY8]]
1689  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
1690  ; GFX7-LABEL: name: s_buffer_load_v4f32_vgpr_offset
1691  ; GFX7: bb.1 (%ir-block.0):
1692  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1693  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1694  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1695  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1696  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1697  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1698  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1699  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1700  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1701  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
1702  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
1703  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
1704  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
1705  ; GFX7:   $vgpr0 = COPY [[COPY5]]
1706  ; GFX7:   $vgpr1 = COPY [[COPY6]]
1707  ; GFX7:   $vgpr2 = COPY [[COPY7]]
1708  ; GFX7:   $vgpr3 = COPY [[COPY8]]
1709  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
1710  ; GFX8-LABEL: name: s_buffer_load_v4f32_vgpr_offset
1711  ; GFX8: bb.1 (%ir-block.0):
1712  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1713  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1714  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1715  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1716  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1717  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1718  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1719  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1720  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1721  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
1722  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
1723  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
1724  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
1725  ; GFX8:   $vgpr0 = COPY [[COPY5]]
1726  ; GFX8:   $vgpr1 = COPY [[COPY6]]
1727  ; GFX8:   $vgpr2 = COPY [[COPY7]]
1728  ; GFX8:   $vgpr3 = COPY [[COPY8]]
1729  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
1730  %val = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
1731  ret <4 x float> %val
1732}
1733
1734define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
1735  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset
1736  ; GFX6: bb.1 (%ir-block.0):
1737  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1738  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1739  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1740  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1741  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1742  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1743  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1744  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1745  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1746  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1747  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
1748  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
1749  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
1750  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
1751  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
1752  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
1753  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
1754  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
1755  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
1756  ; GFX6:   $vgpr0 = COPY [[COPY5]]
1757  ; GFX6:   $vgpr1 = COPY [[COPY6]]
1758  ; GFX6:   $vgpr2 = COPY [[COPY7]]
1759  ; GFX6:   $vgpr3 = COPY [[COPY8]]
1760  ; GFX6:   $vgpr4 = COPY [[COPY9]]
1761  ; GFX6:   $vgpr5 = COPY [[COPY10]]
1762  ; GFX6:   $vgpr6 = COPY [[COPY11]]
1763  ; GFX6:   $vgpr7 = COPY [[COPY12]]
1764  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
1765  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset
1766  ; GFX7: bb.1 (%ir-block.0):
1767  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1768  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1769  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1770  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1771  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1772  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1773  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1774  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1775  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1776  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1777  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
1778  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
1779  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
1780  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
1781  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
1782  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
1783  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
1784  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
1785  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
1786  ; GFX7:   $vgpr0 = COPY [[COPY5]]
1787  ; GFX7:   $vgpr1 = COPY [[COPY6]]
1788  ; GFX7:   $vgpr2 = COPY [[COPY7]]
1789  ; GFX7:   $vgpr3 = COPY [[COPY8]]
1790  ; GFX7:   $vgpr4 = COPY [[COPY9]]
1791  ; GFX7:   $vgpr5 = COPY [[COPY10]]
1792  ; GFX7:   $vgpr6 = COPY [[COPY11]]
1793  ; GFX7:   $vgpr7 = COPY [[COPY12]]
1794  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
1795  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset
1796  ; GFX8: bb.1 (%ir-block.0):
1797  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1798  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1799  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1800  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1801  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1802  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1803  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1804  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1805  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1806  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1807  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
1808  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
1809  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
1810  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
1811  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
1812  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
1813  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
1814  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
1815  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
1816  ; GFX8:   $vgpr0 = COPY [[COPY5]]
1817  ; GFX8:   $vgpr1 = COPY [[COPY6]]
1818  ; GFX8:   $vgpr2 = COPY [[COPY7]]
1819  ; GFX8:   $vgpr3 = COPY [[COPY8]]
1820  ; GFX8:   $vgpr4 = COPY [[COPY9]]
1821  ; GFX8:   $vgpr5 = COPY [[COPY10]]
1822  ; GFX8:   $vgpr6 = COPY [[COPY11]]
1823  ; GFX8:   $vgpr7 = COPY [[COPY12]]
1824  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
1825  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
1826  ret <8 x float> %val
1827}
1828
1829define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %soffset) {
1830  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset
1831  ; GFX6: bb.1 (%ir-block.0):
1832  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1833  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1834  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1835  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1836  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1837  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1838  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1839  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1840  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1841  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1842  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
1843  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
1844  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
1845  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
1846  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
1847  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
1848  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
1849  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
1850  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
1851  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
1852  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
1853  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
1854  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
1855  ; GFX6:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
1856  ; GFX6:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
1857  ; GFX6:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
1858  ; GFX6:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
1859  ; GFX6:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
1860  ; GFX6:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
1861  ; GFX6:   $vgpr0 = COPY [[COPY5]]
1862  ; GFX6:   $vgpr1 = COPY [[COPY6]]
1863  ; GFX6:   $vgpr2 = COPY [[COPY7]]
1864  ; GFX6:   $vgpr3 = COPY [[COPY8]]
1865  ; GFX6:   $vgpr4 = COPY [[COPY9]]
1866  ; GFX6:   $vgpr5 = COPY [[COPY10]]
1867  ; GFX6:   $vgpr6 = COPY [[COPY11]]
1868  ; GFX6:   $vgpr7 = COPY [[COPY12]]
1869  ; GFX6:   $vgpr8 = COPY [[COPY13]]
1870  ; GFX6:   $vgpr9 = COPY [[COPY14]]
1871  ; GFX6:   $vgpr10 = COPY [[COPY15]]
1872  ; GFX6:   $vgpr11 = COPY [[COPY16]]
1873  ; GFX6:   $vgpr12 = COPY [[COPY17]]
1874  ; GFX6:   $vgpr13 = COPY [[COPY18]]
1875  ; GFX6:   $vgpr14 = COPY [[COPY19]]
1876  ; GFX6:   $vgpr15 = COPY [[COPY20]]
1877  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
1878  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset
1879  ; GFX7: bb.1 (%ir-block.0):
1880  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1881  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1882  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1883  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1884  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1885  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1886  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1887  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1888  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1889  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1890  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
1891  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
1892  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
1893  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
1894  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
1895  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
1896  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
1897  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
1898  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
1899  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
1900  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
1901  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
1902  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
1903  ; GFX7:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
1904  ; GFX7:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
1905  ; GFX7:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
1906  ; GFX7:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
1907  ; GFX7:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
1908  ; GFX7:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
1909  ; GFX7:   $vgpr0 = COPY [[COPY5]]
1910  ; GFX7:   $vgpr1 = COPY [[COPY6]]
1911  ; GFX7:   $vgpr2 = COPY [[COPY7]]
1912  ; GFX7:   $vgpr3 = COPY [[COPY8]]
1913  ; GFX7:   $vgpr4 = COPY [[COPY9]]
1914  ; GFX7:   $vgpr5 = COPY [[COPY10]]
1915  ; GFX7:   $vgpr6 = COPY [[COPY11]]
1916  ; GFX7:   $vgpr7 = COPY [[COPY12]]
1917  ; GFX7:   $vgpr8 = COPY [[COPY13]]
1918  ; GFX7:   $vgpr9 = COPY [[COPY14]]
1919  ; GFX7:   $vgpr10 = COPY [[COPY15]]
1920  ; GFX7:   $vgpr11 = COPY [[COPY16]]
1921  ; GFX7:   $vgpr12 = COPY [[COPY17]]
1922  ; GFX7:   $vgpr13 = COPY [[COPY18]]
1923  ; GFX7:   $vgpr14 = COPY [[COPY19]]
1924  ; GFX7:   $vgpr15 = COPY [[COPY20]]
1925  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
1926  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset
1927  ; GFX8: bb.1 (%ir-block.0):
1928  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1929  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1930  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1931  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1932  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1933  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1934  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1935  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1936  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1937  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
1938  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
1939  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
1940  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
1941  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
1942  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
1943  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
1944  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
1945  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
1946  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
1947  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
1948  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
1949  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
1950  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
1951  ; GFX8:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
1952  ; GFX8:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
1953  ; GFX8:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
1954  ; GFX8:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
1955  ; GFX8:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
1956  ; GFX8:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
1957  ; GFX8:   $vgpr0 = COPY [[COPY5]]
1958  ; GFX8:   $vgpr1 = COPY [[COPY6]]
1959  ; GFX8:   $vgpr2 = COPY [[COPY7]]
1960  ; GFX8:   $vgpr3 = COPY [[COPY8]]
1961  ; GFX8:   $vgpr4 = COPY [[COPY9]]
1962  ; GFX8:   $vgpr5 = COPY [[COPY10]]
1963  ; GFX8:   $vgpr6 = COPY [[COPY11]]
1964  ; GFX8:   $vgpr7 = COPY [[COPY12]]
1965  ; GFX8:   $vgpr8 = COPY [[COPY13]]
1966  ; GFX8:   $vgpr9 = COPY [[COPY14]]
1967  ; GFX8:   $vgpr10 = COPY [[COPY15]]
1968  ; GFX8:   $vgpr11 = COPY [[COPY16]]
1969  ; GFX8:   $vgpr12 = COPY [[COPY17]]
1970  ; GFX8:   $vgpr13 = COPY [[COPY18]]
1971  ; GFX8:   $vgpr14 = COPY [[COPY19]]
1972  ; GFX8:   $vgpr15 = COPY [[COPY20]]
1973  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
1974  %val = call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
1975  ret <16 x float> %val
1976}
1977
1978define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg %rsrc, i32 %soffset.base) {
1979  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
1980  ; GFX6: bb.1 (%ir-block.0):
1981  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1982  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1983  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1984  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1985  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1986  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1987  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
1988  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
1989  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
1990  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
1991  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
1992  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
1993  ; GFX7: bb.1 (%ir-block.0):
1994  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
1995  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
1996  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
1997  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
1998  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
1999  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2000  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2001  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2002  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2003  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2004  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
2005  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092
2006  ; GFX8: bb.1 (%ir-block.0):
2007  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2008  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2009  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2010  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2011  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2012  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2013  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2014  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2015  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2016  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2017  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
2018  %soffset = add i32 %soffset.base, 4092
2019  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2020  ret float %val
2021}
2022
2023define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg %rsrc, i32 %soffset.base) {
2024  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
2025  ; GFX6: bb.1 (%ir-block.0):
2026  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2027  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2028  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2029  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2030  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2031  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2032  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2033  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2034  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2035  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2036  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
2037  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
2038  ; GFX7: bb.1 (%ir-block.0):
2039  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2040  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2041  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2042  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2043  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2044  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2045  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2046  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2047  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2048  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2049  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
2050  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095
2051  ; GFX8: bb.1 (%ir-block.0):
2052  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2053  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2054  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2055  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2056  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2057  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2058  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2059  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2060  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2061  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2062  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
2063  %soffset = add i32 %soffset.base, 4095
2064  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2065  ret float %val
2066}
2067
2068define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg %rsrc, i32 %soffset.base) {
2069  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
2070  ; GFX6: bb.1 (%ir-block.0):
2071  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2072  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2073  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2074  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2075  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2076  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2077  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2078  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
2079  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2080  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2081  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
2082  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
2083  ; GFX7: bb.1 (%ir-block.0):
2084  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2085  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2086  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2087  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2088  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2089  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2090  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2091  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
2092  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2093  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2094  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
2095  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096
2096  ; GFX8: bb.1 (%ir-block.0):
2097  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2098  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2099  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2100  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2101  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2102  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2103  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2104  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
2105  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2106  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2107  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
2108  %soffset = add i32 %soffset.base, 4096
2109  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2110  ret float %val
2111}
2112
2113; Make sure the base offset is added to each split load.
2114define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> inreg %rsrc, i32 %soffset.base) {
2115  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
2116  ; GFX6: bb.1 (%ir-block.0):
2117  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2118  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2119  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2120  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2121  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2122  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2123  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2124  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2125  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2126  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2127  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
2128  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2129  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2130  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2131  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2132  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2133  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2134  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2135  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2136  ; GFX6:   $vgpr0 = COPY [[COPY5]]
2137  ; GFX6:   $vgpr1 = COPY [[COPY6]]
2138  ; GFX6:   $vgpr2 = COPY [[COPY7]]
2139  ; GFX6:   $vgpr3 = COPY [[COPY8]]
2140  ; GFX6:   $vgpr4 = COPY [[COPY9]]
2141  ; GFX6:   $vgpr5 = COPY [[COPY10]]
2142  ; GFX6:   $vgpr6 = COPY [[COPY11]]
2143  ; GFX6:   $vgpr7 = COPY [[COPY12]]
2144  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
2145  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
2146  ; GFX7: bb.1 (%ir-block.0):
2147  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2148  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2149  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2150  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2151  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2152  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2153  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2154  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2155  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2156  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2157  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
2158  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2159  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2160  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2161  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2162  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2163  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2164  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2165  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2166  ; GFX7:   $vgpr0 = COPY [[COPY5]]
2167  ; GFX7:   $vgpr1 = COPY [[COPY6]]
2168  ; GFX7:   $vgpr2 = COPY [[COPY7]]
2169  ; GFX7:   $vgpr3 = COPY [[COPY8]]
2170  ; GFX7:   $vgpr4 = COPY [[COPY9]]
2171  ; GFX7:   $vgpr5 = COPY [[COPY10]]
2172  ; GFX7:   $vgpr6 = COPY [[COPY11]]
2173  ; GFX7:   $vgpr7 = COPY [[COPY12]]
2174  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
2175  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064
2176  ; GFX8: bb.1 (%ir-block.0):
2177  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2178  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2179  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2180  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2181  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2182  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2183  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2184  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2185  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2186  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2187  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
2188  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2189  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2190  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2191  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2192  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2193  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2194  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2195  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2196  ; GFX8:   $vgpr0 = COPY [[COPY5]]
2197  ; GFX8:   $vgpr1 = COPY [[COPY6]]
2198  ; GFX8:   $vgpr2 = COPY [[COPY7]]
2199  ; GFX8:   $vgpr3 = COPY [[COPY8]]
2200  ; GFX8:   $vgpr4 = COPY [[COPY9]]
2201  ; GFX8:   $vgpr5 = COPY [[COPY10]]
2202  ; GFX8:   $vgpr6 = COPY [[COPY11]]
2203  ; GFX8:   $vgpr7 = COPY [[COPY12]]
2204  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
2205  %soffset = add i32 %soffset.base, 4064
2206  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2207  ret <8 x float> %val
2208}
2209
2210; Make sure the maximum offset isn't exeeded when splitting this
2211define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> inreg %rsrc, i32 %soffset.base) {
2212  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
2213  ; GFX6: bb.1 (%ir-block.0):
2214  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2215  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2216  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2217  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2218  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2219  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2220  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2221  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
2222  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2223  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2224  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
2225  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2226  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2227  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2228  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2229  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2230  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2231  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2232  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2233  ; GFX6:   $vgpr0 = COPY [[COPY5]]
2234  ; GFX6:   $vgpr1 = COPY [[COPY6]]
2235  ; GFX6:   $vgpr2 = COPY [[COPY7]]
2236  ; GFX6:   $vgpr3 = COPY [[COPY8]]
2237  ; GFX6:   $vgpr4 = COPY [[COPY9]]
2238  ; GFX6:   $vgpr5 = COPY [[COPY10]]
2239  ; GFX6:   $vgpr6 = COPY [[COPY11]]
2240  ; GFX6:   $vgpr7 = COPY [[COPY12]]
2241  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
2242  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
2243  ; GFX7: bb.1 (%ir-block.0):
2244  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2245  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2246  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2247  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2248  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2249  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2250  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2251  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
2252  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2253  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2254  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
2255  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2256  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2257  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2258  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2259  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2260  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2261  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2262  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2263  ; GFX7:   $vgpr0 = COPY [[COPY5]]
2264  ; GFX7:   $vgpr1 = COPY [[COPY6]]
2265  ; GFX7:   $vgpr2 = COPY [[COPY7]]
2266  ; GFX7:   $vgpr3 = COPY [[COPY8]]
2267  ; GFX7:   $vgpr4 = COPY [[COPY9]]
2268  ; GFX7:   $vgpr5 = COPY [[COPY10]]
2269  ; GFX7:   $vgpr6 = COPY [[COPY11]]
2270  ; GFX7:   $vgpr7 = COPY [[COPY12]]
2271  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
2272  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068
2273  ; GFX8: bb.1 (%ir-block.0):
2274  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2275  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2276  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2277  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2278  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2279  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2280  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2281  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4
2282  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2283  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2284  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
2285  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2286  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2287  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2288  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2289  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2290  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2291  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2292  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2293  ; GFX8:   $vgpr0 = COPY [[COPY5]]
2294  ; GFX8:   $vgpr1 = COPY [[COPY6]]
2295  ; GFX8:   $vgpr2 = COPY [[COPY7]]
2296  ; GFX8:   $vgpr3 = COPY [[COPY8]]
2297  ; GFX8:   $vgpr4 = COPY [[COPY9]]
2298  ; GFX8:   $vgpr5 = COPY [[COPY10]]
2299  ; GFX8:   $vgpr6 = COPY [[COPY11]]
2300  ; GFX8:   $vgpr7 = COPY [[COPY12]]
2301  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
2302  %soffset = add i32 %soffset.base, 4068
2303  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2304  ret <8 x float> %val
2305}
2306
2307define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i32> inreg %rsrc, i32 %soffset.base) {
2308  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
2309  ; GFX6: bb.1 (%ir-block.0):
2310  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2311  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2312  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2313  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2314  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2315  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2316  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2317  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2318  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2319  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2320  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
2321  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
2322  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
2323  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2324  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2325  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2326  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2327  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2328  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2329  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2330  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2331  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
2332  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
2333  ; GFX6:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
2334  ; GFX6:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
2335  ; GFX6:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
2336  ; GFX6:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
2337  ; GFX6:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
2338  ; GFX6:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
2339  ; GFX6:   $vgpr0 = COPY [[COPY5]]
2340  ; GFX6:   $vgpr1 = COPY [[COPY6]]
2341  ; GFX6:   $vgpr2 = COPY [[COPY7]]
2342  ; GFX6:   $vgpr3 = COPY [[COPY8]]
2343  ; GFX6:   $vgpr4 = COPY [[COPY9]]
2344  ; GFX6:   $vgpr5 = COPY [[COPY10]]
2345  ; GFX6:   $vgpr6 = COPY [[COPY11]]
2346  ; GFX6:   $vgpr7 = COPY [[COPY12]]
2347  ; GFX6:   $vgpr8 = COPY [[COPY13]]
2348  ; GFX6:   $vgpr9 = COPY [[COPY14]]
2349  ; GFX6:   $vgpr10 = COPY [[COPY15]]
2350  ; GFX6:   $vgpr11 = COPY [[COPY16]]
2351  ; GFX6:   $vgpr12 = COPY [[COPY17]]
2352  ; GFX6:   $vgpr13 = COPY [[COPY18]]
2353  ; GFX6:   $vgpr14 = COPY [[COPY19]]
2354  ; GFX6:   $vgpr15 = COPY [[COPY20]]
2355  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
2356  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
2357  ; GFX7: bb.1 (%ir-block.0):
2358  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2359  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2360  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2361  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2362  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2363  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2364  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2365  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2366  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2367  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2368  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
2369  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
2370  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
2371  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2372  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2373  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2374  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2375  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2376  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2377  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2378  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2379  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
2380  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
2381  ; GFX7:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
2382  ; GFX7:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
2383  ; GFX7:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
2384  ; GFX7:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
2385  ; GFX7:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
2386  ; GFX7:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
2387  ; GFX7:   $vgpr0 = COPY [[COPY5]]
2388  ; GFX7:   $vgpr1 = COPY [[COPY6]]
2389  ; GFX7:   $vgpr2 = COPY [[COPY7]]
2390  ; GFX7:   $vgpr3 = COPY [[COPY8]]
2391  ; GFX7:   $vgpr4 = COPY [[COPY9]]
2392  ; GFX7:   $vgpr5 = COPY [[COPY10]]
2393  ; GFX7:   $vgpr6 = COPY [[COPY11]]
2394  ; GFX7:   $vgpr7 = COPY [[COPY12]]
2395  ; GFX7:   $vgpr8 = COPY [[COPY13]]
2396  ; GFX7:   $vgpr9 = COPY [[COPY14]]
2397  ; GFX7:   $vgpr10 = COPY [[COPY15]]
2398  ; GFX7:   $vgpr11 = COPY [[COPY16]]
2399  ; GFX7:   $vgpr12 = COPY [[COPY17]]
2400  ; GFX7:   $vgpr13 = COPY [[COPY18]]
2401  ; GFX7:   $vgpr14 = COPY [[COPY19]]
2402  ; GFX7:   $vgpr15 = COPY [[COPY20]]
2403  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
2404  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032
2405  ; GFX8: bb.1 (%ir-block.0):
2406  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2407  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2408  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2409  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2410  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2411  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2412  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2413  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2414  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2415  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2416  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
2417  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
2418  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
2419  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2420  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2421  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2422  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2423  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2424  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2425  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2426  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2427  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
2428  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
2429  ; GFX8:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
2430  ; GFX8:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
2431  ; GFX8:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
2432  ; GFX8:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
2433  ; GFX8:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
2434  ; GFX8:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
2435  ; GFX8:   $vgpr0 = COPY [[COPY5]]
2436  ; GFX8:   $vgpr1 = COPY [[COPY6]]
2437  ; GFX8:   $vgpr2 = COPY [[COPY7]]
2438  ; GFX8:   $vgpr3 = COPY [[COPY8]]
2439  ; GFX8:   $vgpr4 = COPY [[COPY9]]
2440  ; GFX8:   $vgpr5 = COPY [[COPY10]]
2441  ; GFX8:   $vgpr6 = COPY [[COPY11]]
2442  ; GFX8:   $vgpr7 = COPY [[COPY12]]
2443  ; GFX8:   $vgpr8 = COPY [[COPY13]]
2444  ; GFX8:   $vgpr9 = COPY [[COPY14]]
2445  ; GFX8:   $vgpr10 = COPY [[COPY15]]
2446  ; GFX8:   $vgpr11 = COPY [[COPY16]]
2447  ; GFX8:   $vgpr12 = COPY [[COPY17]]
2448  ; GFX8:   $vgpr13 = COPY [[COPY18]]
2449  ; GFX8:   $vgpr14 = COPY [[COPY19]]
2450  ; GFX8:   $vgpr15 = COPY [[COPY20]]
2451  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
2452  %soffset = add i32 %soffset.base, 4032
2453  %val = call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2454  ret <16 x float> %val
2455}
2456
2457define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i32> inreg %rsrc, i32 %soffset.base) {
2458  ; GFX6-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
2459  ; GFX6: bb.1 (%ir-block.0):
2460  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2461  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2462  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2463  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2464  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2465  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2466  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2467  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036
2468  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2469  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2470  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
2471  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
2472  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
2473  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2474  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2475  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2476  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2477  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2478  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2479  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2480  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2481  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
2482  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
2483  ; GFX6:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
2484  ; GFX6:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
2485  ; GFX6:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
2486  ; GFX6:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
2487  ; GFX6:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
2488  ; GFX6:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
2489  ; GFX6:   $vgpr0 = COPY [[COPY5]]
2490  ; GFX6:   $vgpr1 = COPY [[COPY6]]
2491  ; GFX6:   $vgpr2 = COPY [[COPY7]]
2492  ; GFX6:   $vgpr3 = COPY [[COPY8]]
2493  ; GFX6:   $vgpr4 = COPY [[COPY9]]
2494  ; GFX6:   $vgpr5 = COPY [[COPY10]]
2495  ; GFX6:   $vgpr6 = COPY [[COPY11]]
2496  ; GFX6:   $vgpr7 = COPY [[COPY12]]
2497  ; GFX6:   $vgpr8 = COPY [[COPY13]]
2498  ; GFX6:   $vgpr9 = COPY [[COPY14]]
2499  ; GFX6:   $vgpr10 = COPY [[COPY15]]
2500  ; GFX6:   $vgpr11 = COPY [[COPY16]]
2501  ; GFX6:   $vgpr12 = COPY [[COPY17]]
2502  ; GFX6:   $vgpr13 = COPY [[COPY18]]
2503  ; GFX6:   $vgpr14 = COPY [[COPY19]]
2504  ; GFX6:   $vgpr15 = COPY [[COPY20]]
2505  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
2506  ; GFX7-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
2507  ; GFX7: bb.1 (%ir-block.0):
2508  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2509  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2510  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2511  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2512  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2513  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2514  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2515  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036
2516  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2517  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2518  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 32, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
2519  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 48, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
2520  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
2521  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2522  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2523  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2524  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2525  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2526  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2527  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2528  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2529  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
2530  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
2531  ; GFX7:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
2532  ; GFX7:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
2533  ; GFX7:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
2534  ; GFX7:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
2535  ; GFX7:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
2536  ; GFX7:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
2537  ; GFX7:   $vgpr0 = COPY [[COPY5]]
2538  ; GFX7:   $vgpr1 = COPY [[COPY6]]
2539  ; GFX7:   $vgpr2 = COPY [[COPY7]]
2540  ; GFX7:   $vgpr3 = COPY [[COPY8]]
2541  ; GFX7:   $vgpr4 = COPY [[COPY9]]
2542  ; GFX7:   $vgpr5 = COPY [[COPY10]]
2543  ; GFX7:   $vgpr6 = COPY [[COPY11]]
2544  ; GFX7:   $vgpr7 = COPY [[COPY12]]
2545  ; GFX7:   $vgpr8 = COPY [[COPY13]]
2546  ; GFX7:   $vgpr9 = COPY [[COPY14]]
2547  ; GFX7:   $vgpr10 = COPY [[COPY15]]
2548  ; GFX7:   $vgpr11 = COPY [[COPY16]]
2549  ; GFX7:   $vgpr12 = COPY [[COPY17]]
2550  ; GFX7:   $vgpr13 = COPY [[COPY18]]
2551  ; GFX7:   $vgpr14 = COPY [[COPY19]]
2552  ; GFX7:   $vgpr15 = COPY [[COPY20]]
2553  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
2554  ; GFX8-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036
2555  ; GFX8: bb.1 (%ir-block.0):
2556  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
2557  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
2558  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
2559  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
2560  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
2561  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2562  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2563  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4
2564  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4032, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2565  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4048, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
2566  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 16, align 4)
2567  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 48, align 4)
2568  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7, [[BUFFER_LOAD_DWORDX4_OFFEN2]], %subreg.sub8_sub9_sub10_sub11, [[BUFFER_LOAD_DWORDX4_OFFEN3]], %subreg.sub12_sub13_sub14_sub15
2569  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0
2570  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub1
2571  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub2
2572  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub3
2573  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub4
2574  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub5
2575  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub6
2576  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub7
2577  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub8
2578  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub9
2579  ; GFX8:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub10
2580  ; GFX8:   [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub11
2581  ; GFX8:   [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub12
2582  ; GFX8:   [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub13
2583  ; GFX8:   [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub14
2584  ; GFX8:   [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub15
2585  ; GFX8:   $vgpr0 = COPY [[COPY5]]
2586  ; GFX8:   $vgpr1 = COPY [[COPY6]]
2587  ; GFX8:   $vgpr2 = COPY [[COPY7]]
2588  ; GFX8:   $vgpr3 = COPY [[COPY8]]
2589  ; GFX8:   $vgpr4 = COPY [[COPY9]]
2590  ; GFX8:   $vgpr5 = COPY [[COPY10]]
2591  ; GFX8:   $vgpr6 = COPY [[COPY11]]
2592  ; GFX8:   $vgpr7 = COPY [[COPY12]]
2593  ; GFX8:   $vgpr8 = COPY [[COPY13]]
2594  ; GFX8:   $vgpr9 = COPY [[COPY14]]
2595  ; GFX8:   $vgpr10 = COPY [[COPY15]]
2596  ; GFX8:   $vgpr11 = COPY [[COPY16]]
2597  ; GFX8:   $vgpr12 = COPY [[COPY17]]
2598  ; GFX8:   $vgpr13 = COPY [[COPY18]]
2599  ; GFX8:   $vgpr14 = COPY [[COPY19]]
2600  ; GFX8:   $vgpr15 = COPY [[COPY20]]
2601  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15
2602  %soffset = add i32 %soffset.base, 4036
2603  %val = call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2604  ret <16 x float> %val
2605}
2606
2607; Waterfall loop due to resource being VGPR
2608define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %soffset) {
2609  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc
2610  ; GFX6: bb.1 (%ir-block.0):
2611  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2612  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2613  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2614  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2615  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2616  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2617  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2618  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
2619  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2620  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2621  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2622  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2623  ; GFX6: bb.2:
2624  ; GFX6:   successors: %bb.3, %bb.2
2625  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2626  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2627  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2628  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
2629  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
2630  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
2631  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2632  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
2633  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2634  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2635  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2636  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2637  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2638  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2639  ; GFX6: bb.3:
2640  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2641  ; GFX6: bb.4:
2642  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2643  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
2644  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc
2645  ; GFX7: bb.1 (%ir-block.0):
2646  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2647  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2648  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2649  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2650  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2651  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2652  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2653  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
2654  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2655  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2656  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2657  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2658  ; GFX7: bb.2:
2659  ; GFX7:   successors: %bb.3, %bb.2
2660  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2661  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2662  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2663  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
2664  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
2665  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
2666  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2667  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
2668  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2669  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2670  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2671  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2672  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2673  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2674  ; GFX7: bb.3:
2675  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2676  ; GFX7: bb.4:
2677  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2678  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
2679  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc
2680  ; GFX8: bb.1 (%ir-block.0):
2681  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2682  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2683  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2684  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2685  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2686  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2687  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2688  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
2689  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2690  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2691  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2692  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2693  ; GFX8: bb.2:
2694  ; GFX8:   successors: %bb.3, %bb.2
2695  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2696  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2697  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2698  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
2699  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
2700  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
2701  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2702  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
2703  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2704  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2705  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2706  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2707  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2708  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2709  ; GFX8: bb.3:
2710  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2711  ; GFX8: bb.4:
2712  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2713  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
2714  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2715  ret float %val
2716}
2717
2718; Use the offset inside the waterfall loop
2719define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %rsrc, i32 inreg %soffset.base) {
2720  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
2721  ; GFX6: bb.1 (%ir-block.0):
2722  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2723  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2724  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2725  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2726  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2727  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2728  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2729  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2730  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2731  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2732  ; GFX6: bb.2:
2733  ; GFX6:   successors: %bb.3, %bb.2
2734  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
2735  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
2736  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2737  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
2738  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2739  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2740  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2741  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
2742  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2743  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2744  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2745  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2746  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2747  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2748  ; GFX6: bb.3:
2749  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2750  ; GFX6: bb.4:
2751  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
2752  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
2753  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
2754  ; GFX7: bb.1 (%ir-block.0):
2755  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2756  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2757  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2758  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2759  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2760  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2761  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2762  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2763  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2764  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2765  ; GFX7: bb.2:
2766  ; GFX7:   successors: %bb.3, %bb.2
2767  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
2768  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
2769  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2770  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
2771  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2772  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2773  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2774  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
2775  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2776  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2777  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2778  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2779  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2780  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2781  ; GFX7: bb.3:
2782  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2783  ; GFX7: bb.4:
2784  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
2785  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
2786  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092
2787  ; GFX8: bb.1 (%ir-block.0):
2788  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2789  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2790  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2791  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2792  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2793  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2794  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2795  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2796  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2797  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2798  ; GFX8: bb.2:
2799  ; GFX8:   successors: %bb.3, %bb.2
2800  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
2801  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
2802  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2803  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
2804  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2805  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2806  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2807  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
2808  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2809  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2810  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4092, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2811  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2812  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2813  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2814  ; GFX8: bb.3:
2815  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2816  ; GFX8: bb.4:
2817  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
2818  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
2819  %soffset = add i32 %soffset.base, 4092
2820  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2821  ret float %val
2822}
2823
2824; Scalar offset exceeds MUBUF limit, keep add out of the loop
2825define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {
2826  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
2827  ; GFX6: bb.1 (%ir-block.0):
2828  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2829  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2830  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2831  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2832  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2833  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2834  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2835  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
2836  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
2837  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
2838  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2839  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2840  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2841  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2842  ; GFX6: bb.2:
2843  ; GFX6:   successors: %bb.3, %bb.2
2844  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2845  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2846  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2847  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
2848  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
2849  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
2850  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2851  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
2852  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2853  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2854  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2855  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2856  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2857  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2858  ; GFX6: bb.3:
2859  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2860  ; GFX6: bb.4:
2861  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2862  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
2863  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
2864  ; GFX7: bb.1 (%ir-block.0):
2865  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2866  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2867  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2868  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2869  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2870  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2871  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2872  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
2873  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
2874  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
2875  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2876  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2877  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2878  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2879  ; GFX7: bb.2:
2880  ; GFX7:   successors: %bb.3, %bb.2
2881  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2882  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2883  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2884  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
2885  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
2886  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
2887  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2888  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
2889  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2890  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2891  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2892  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2893  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2894  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2895  ; GFX7: bb.3:
2896  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2897  ; GFX7: bb.4:
2898  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2899  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
2900  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096
2901  ; GFX8: bb.1 (%ir-block.0):
2902  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
2903  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2904  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2905  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2906  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2907  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
2908  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2909  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
2910  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
2911  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
2912  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2913  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2914  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2915  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2916  ; GFX8: bb.2:
2917  ; GFX8:   successors: %bb.3, %bb.2
2918  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
2919  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
2920  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2921  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
2922  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
2923  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
2924  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2925  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
2926  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2927  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2928  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
2929  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2930  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2931  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2932  ; GFX8: bb.3:
2933  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2934  ; GFX8: bb.4:
2935  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
2936  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
2937  %soffset = add i32 %soffset.base, 4096
2938  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
2939  ret float %val
2940}
2941
2942; Waterfall loop, but constant offset
2943define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc) {
2944  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4095
2945  ; GFX6: bb.1 (%ir-block.0):
2946  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
2947  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2948  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2949  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2950  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2951  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2952  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2953  ; GFX6:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2954  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2955  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2956  ; GFX6: bb.2:
2957  ; GFX6:   successors: %bb.3, %bb.2
2958  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
2959  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
2960  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2961  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
2962  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
2963  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
2964  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2965  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
2966  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
2967  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
2968  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4 + 4095, align 1)
2969  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
2970  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
2971  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
2972  ; GFX6: bb.3:
2973  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
2974  ; GFX6: bb.4:
2975  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
2976  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
2977  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4095
2978  ; GFX7: bb.1 (%ir-block.0):
2979  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
2980  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2981  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
2982  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
2983  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
2984  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
2985  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
2986  ; GFX7:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
2987  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
2988  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
2989  ; GFX7: bb.2:
2990  ; GFX7:   successors: %bb.3, %bb.2
2991  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
2992  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
2993  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
2994  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
2995  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
2996  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
2997  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
2998  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
2999  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3000  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3001  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4 + 4095, align 1)
3002  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3003  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3004  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3005  ; GFX7: bb.3:
3006  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3007  ; GFX7: bb.4:
3008  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
3009  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
3010  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4095
3011  ; GFX8: bb.1 (%ir-block.0):
3012  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
3013  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3014  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3015  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3016  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3017  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3018  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3019  ; GFX8:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3020  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3021  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3022  ; GFX8: bb.2:
3023  ; GFX8:   successors: %bb.3, %bb.2
3024  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
3025  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
3026  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3027  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
3028  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3029  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3030  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3031  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
3032  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3033  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3034  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4 + 4095, align 1)
3035  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3036  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3037  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3038  ; GFX8: bb.3:
3039  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3040  ; GFX8: bb.4:
3041  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
3042  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
3043  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 4095, i32 0)
3044  ret float %val
3045}
3046
3047; Waterfall loop, but constant offset
3048define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc) {
3049  ; GFX6-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4096
3050  ; GFX6: bb.1 (%ir-block.0):
3051  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
3052  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3053  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3054  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3055  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3056  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3057  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
3058  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
3059  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3060  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3061  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3062  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3063  ; GFX6: bb.2:
3064  ; GFX6:   successors: %bb.3, %bb.2
3065  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3066  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3067  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3068  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3069  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3070  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3071  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3072  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3073  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3074  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3075  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
3076  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3077  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3078  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3079  ; GFX6: bb.3:
3080  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3081  ; GFX6: bb.4:
3082  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
3083  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
3084  ; GFX7-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4096
3085  ; GFX7: bb.1 (%ir-block.0):
3086  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
3087  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3088  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3089  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3090  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3091  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3092  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
3093  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
3094  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3095  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3096  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3097  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3098  ; GFX7: bb.2:
3099  ; GFX7:   successors: %bb.3, %bb.2
3100  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3101  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3102  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3103  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3104  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3105  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3106  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3107  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3108  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3109  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3110  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
3111  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3112  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3113  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3114  ; GFX7: bb.3:
3115  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3116  ; GFX7: bb.4:
3117  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
3118  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
3119  ; GFX8-LABEL: name: s_buffer_load_f32_vgpr_rsrc_offset_4096
3120  ; GFX8: bb.1 (%ir-block.0):
3121  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
3122  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3123  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3124  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3125  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3126  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3127  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
3128  ; GFX8:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3129  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3130  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3131  ; GFX8: bb.2:
3132  ; GFX8:   successors: %bb.3, %bb.2
3133  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
3134  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
3135  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3136  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
3137  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3138  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3139  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3140  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
3141  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3142  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3143  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4 + 4096)
3144  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3145  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3146  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3147  ; GFX8: bb.3:
3148  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3149  ; GFX8: bb.4:
3150  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
3151  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
3152  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 4096, i32 0)
3153  ret float %val
3154}
3155
3156; Need a waterfall loop, but the offset is scalar.
3157; Make sure the base offset is added to each split load.
3158define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %rsrc, i32 inreg %soffset.base) {
3159  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
3160  ; GFX6: bb.1 (%ir-block.0):
3161  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3162  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3163  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3164  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3165  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3166  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3167  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3168  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3169  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3170  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3171  ; GFX6: bb.2:
3172  ; GFX6:   successors: %bb.3, %bb.2
3173  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3174  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3175  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3176  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3177  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3178  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3179  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3180  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3181  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3182  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3183  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3184  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3185  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3186  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3187  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3188  ; GFX6: bb.3:
3189  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3190  ; GFX6: bb.4:
3191  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
3192  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3193  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3194  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3195  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3196  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3197  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3198  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3199  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3200  ; GFX6:   $vgpr0 = COPY [[COPY7]]
3201  ; GFX6:   $vgpr1 = COPY [[COPY8]]
3202  ; GFX6:   $vgpr2 = COPY [[COPY9]]
3203  ; GFX6:   $vgpr3 = COPY [[COPY10]]
3204  ; GFX6:   $vgpr4 = COPY [[COPY11]]
3205  ; GFX6:   $vgpr5 = COPY [[COPY12]]
3206  ; GFX6:   $vgpr6 = COPY [[COPY13]]
3207  ; GFX6:   $vgpr7 = COPY [[COPY14]]
3208  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3209  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
3210  ; GFX7: bb.1 (%ir-block.0):
3211  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3212  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3213  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3214  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3215  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3216  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3217  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3218  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3219  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3220  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3221  ; GFX7: bb.2:
3222  ; GFX7:   successors: %bb.3, %bb.2
3223  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3224  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3225  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3226  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3227  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3228  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3229  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3230  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3231  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3232  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3233  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3234  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3235  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3236  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3237  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3238  ; GFX7: bb.3:
3239  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3240  ; GFX7: bb.4:
3241  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
3242  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3243  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3244  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3245  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3246  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3247  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3248  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3249  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3250  ; GFX7:   $vgpr0 = COPY [[COPY7]]
3251  ; GFX7:   $vgpr1 = COPY [[COPY8]]
3252  ; GFX7:   $vgpr2 = COPY [[COPY9]]
3253  ; GFX7:   $vgpr3 = COPY [[COPY10]]
3254  ; GFX7:   $vgpr4 = COPY [[COPY11]]
3255  ; GFX7:   $vgpr5 = COPY [[COPY12]]
3256  ; GFX7:   $vgpr6 = COPY [[COPY13]]
3257  ; GFX7:   $vgpr7 = COPY [[COPY14]]
3258  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3259  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064
3260  ; GFX8: bb.1 (%ir-block.0):
3261  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3262  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3263  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3264  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3265  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3266  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3267  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3268  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3269  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3270  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3271  ; GFX8: bb.2:
3272  ; GFX8:   successors: %bb.3, %bb.2
3273  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3274  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3275  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3276  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3277  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3278  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3279  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3280  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3281  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3282  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3283  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3284  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[COPY4]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3285  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3286  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3287  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3288  ; GFX8: bb.3:
3289  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3290  ; GFX8: bb.4:
3291  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
3292  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3293  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3294  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3295  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3296  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3297  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3298  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3299  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3300  ; GFX8:   $vgpr0 = COPY [[COPY7]]
3301  ; GFX8:   $vgpr1 = COPY [[COPY8]]
3302  ; GFX8:   $vgpr2 = COPY [[COPY9]]
3303  ; GFX8:   $vgpr3 = COPY [[COPY10]]
3304  ; GFX8:   $vgpr4 = COPY [[COPY11]]
3305  ; GFX8:   $vgpr5 = COPY [[COPY12]]
3306  ; GFX8:   $vgpr6 = COPY [[COPY13]]
3307  ; GFX8:   $vgpr7 = COPY [[COPY14]]
3308  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3309  %soffset = add i32 %soffset.base, 4064
3310  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
3311  ret <8 x float> %val
3312}
3313
3314; Need a waterfall loop, but the offset is scalar.
3315; Make sure the maximum offset isn't exeeded when splitting this
3316define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %rsrc, i32 inreg %soffset.base) {
3317  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
3318  ; GFX6: bb.1 (%ir-block.0):
3319  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3320  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3321  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3322  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3323  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3324  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3325  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3326  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
3327  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
3328  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
3329  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3330  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3331  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3332  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3333  ; GFX6: bb.2:
3334  ; GFX6:   successors: %bb.3, %bb.2
3335  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3336  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3337  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3338  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
3339  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
3340  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
3341  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3342  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
3343  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3344  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3345  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3346  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3347  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3348  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3349  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3350  ; GFX6: bb.3:
3351  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3352  ; GFX6: bb.4:
3353  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3354  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3355  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3356  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3357  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3358  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3359  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3360  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3361  ; GFX6:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3362  ; GFX6:   $vgpr0 = COPY [[COPY8]]
3363  ; GFX6:   $vgpr1 = COPY [[COPY9]]
3364  ; GFX6:   $vgpr2 = COPY [[COPY10]]
3365  ; GFX6:   $vgpr3 = COPY [[COPY11]]
3366  ; GFX6:   $vgpr4 = COPY [[COPY12]]
3367  ; GFX6:   $vgpr5 = COPY [[COPY13]]
3368  ; GFX6:   $vgpr6 = COPY [[COPY14]]
3369  ; GFX6:   $vgpr7 = COPY [[COPY15]]
3370  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3371  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
3372  ; GFX7: bb.1 (%ir-block.0):
3373  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3374  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3375  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3376  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3377  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3378  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3379  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3380  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
3381  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
3382  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
3383  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3384  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3385  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3386  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3387  ; GFX7: bb.2:
3388  ; GFX7:   successors: %bb.3, %bb.2
3389  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3390  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3391  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3392  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
3393  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
3394  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
3395  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3396  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
3397  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3398  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3399  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3400  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3401  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3402  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3403  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3404  ; GFX7: bb.3:
3405  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3406  ; GFX7: bb.4:
3407  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3408  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3409  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3410  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3411  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3412  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3413  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3414  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3415  ; GFX7:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3416  ; GFX7:   $vgpr0 = COPY [[COPY8]]
3417  ; GFX7:   $vgpr1 = COPY [[COPY9]]
3418  ; GFX7:   $vgpr2 = COPY [[COPY10]]
3419  ; GFX7:   $vgpr3 = COPY [[COPY11]]
3420  ; GFX7:   $vgpr4 = COPY [[COPY12]]
3421  ; GFX7:   $vgpr5 = COPY [[COPY13]]
3422  ; GFX7:   $vgpr6 = COPY [[COPY14]]
3423  ; GFX7:   $vgpr7 = COPY [[COPY15]]
3424  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3425  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068
3426  ; GFX8: bb.1 (%ir-block.0):
3427  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3428  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3429  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3430  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3431  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3432  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3433  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3434  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068
3435  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
3436  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
3437  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3438  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3439  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3440  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3441  ; GFX8: bb.2:
3442  ; GFX8:   successors: %bb.3, %bb.2
3443  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3444  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3445  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3446  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
3447  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
3448  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
3449  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3450  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
3451  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3452  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3453  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3454  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3455  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3456  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3457  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3458  ; GFX8: bb.3:
3459  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3460  ; GFX8: bb.4:
3461  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3462  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3463  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3464  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3465  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3466  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3467  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3468  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3469  ; GFX8:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3470  ; GFX8:   $vgpr0 = COPY [[COPY8]]
3471  ; GFX8:   $vgpr1 = COPY [[COPY9]]
3472  ; GFX8:   $vgpr2 = COPY [[COPY10]]
3473  ; GFX8:   $vgpr3 = COPY [[COPY11]]
3474  ; GFX8:   $vgpr4 = COPY [[COPY12]]
3475  ; GFX8:   $vgpr5 = COPY [[COPY13]]
3476  ; GFX8:   $vgpr6 = COPY [[COPY14]]
3477  ; GFX8:   $vgpr7 = COPY [[COPY15]]
3478  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3479  %soffset = add i32 %soffset.base, 4068
3480  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
3481  ret <8 x float> %val
3482}
3483
3484define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %rsrc, i32 inreg %soffset.base) {
3485  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
3486  ; GFX6: bb.1 (%ir-block.0):
3487  ; GFX6:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3488  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3489  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3490  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3491  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3492  ; GFX6:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3493  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3494  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
3495  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
3496  ; GFX6:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
3497  ; GFX6:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3498  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3499  ; GFX6:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3500  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3501  ; GFX6: bb.2:
3502  ; GFX6:   successors: %bb.3, %bb.2
3503  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3504  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3505  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3506  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
3507  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
3508  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
3509  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3510  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
3511  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3512  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3513  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3514  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3515  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3516  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3517  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3518  ; GFX6: bb.3:
3519  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3520  ; GFX6: bb.4:
3521  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3522  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3523  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3524  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3525  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3526  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3527  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3528  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3529  ; GFX6:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3530  ; GFX6:   $vgpr0 = COPY [[COPY8]]
3531  ; GFX6:   $vgpr1 = COPY [[COPY9]]
3532  ; GFX6:   $vgpr2 = COPY [[COPY10]]
3533  ; GFX6:   $vgpr3 = COPY [[COPY11]]
3534  ; GFX6:   $vgpr4 = COPY [[COPY12]]
3535  ; GFX6:   $vgpr5 = COPY [[COPY13]]
3536  ; GFX6:   $vgpr6 = COPY [[COPY14]]
3537  ; GFX6:   $vgpr7 = COPY [[COPY15]]
3538  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3539  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
3540  ; GFX7: bb.1 (%ir-block.0):
3541  ; GFX7:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3542  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3543  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3544  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3545  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3546  ; GFX7:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3547  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3548  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
3549  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
3550  ; GFX7:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
3551  ; GFX7:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3552  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3553  ; GFX7:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3554  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3555  ; GFX7: bb.2:
3556  ; GFX7:   successors: %bb.3, %bb.2
3557  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3558  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3559  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3560  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
3561  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
3562  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
3563  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3564  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
3565  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3566  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3567  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3568  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3569  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3570  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3571  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3572  ; GFX7: bb.3:
3573  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3574  ; GFX7: bb.4:
3575  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3576  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3577  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3578  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3579  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3580  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3581  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3582  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3583  ; GFX7:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3584  ; GFX7:   $vgpr0 = COPY [[COPY8]]
3585  ; GFX7:   $vgpr1 = COPY [[COPY9]]
3586  ; GFX7:   $vgpr2 = COPY [[COPY10]]
3587  ; GFX7:   $vgpr3 = COPY [[COPY11]]
3588  ; GFX7:   $vgpr4 = COPY [[COPY12]]
3589  ; GFX7:   $vgpr5 = COPY [[COPY13]]
3590  ; GFX7:   $vgpr6 = COPY [[COPY14]]
3591  ; GFX7:   $vgpr7 = COPY [[COPY15]]
3592  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3593  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096
3594  ; GFX8: bb.1 (%ir-block.0):
3595  ; GFX8:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3
3596  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3597  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3598  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3599  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3600  ; GFX8:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
3601  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3602  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
3603  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def $scc
3604  ; GFX8:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
3605  ; GFX8:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
3606  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3607  ; GFX8:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3608  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3609  ; GFX8: bb.2:
3610  ; GFX8:   successors: %bb.3, %bb.2
3611  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3612  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3613  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3614  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
3615  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
3616  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
3617  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3618  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
3619  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3620  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3621  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3622  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY5]], [[REG_SEQUENCE3]], [[S_MOV_B32_1]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3623  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3624  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3625  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3626  ; GFX8: bb.3:
3627  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3628  ; GFX8: bb.4:
3629  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3630  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3631  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3632  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3633  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3634  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3635  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3636  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3637  ; GFX8:   [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3638  ; GFX8:   $vgpr0 = COPY [[COPY8]]
3639  ; GFX8:   $vgpr1 = COPY [[COPY9]]
3640  ; GFX8:   $vgpr2 = COPY [[COPY10]]
3641  ; GFX8:   $vgpr3 = COPY [[COPY11]]
3642  ; GFX8:   $vgpr4 = COPY [[COPY12]]
3643  ; GFX8:   $vgpr5 = COPY [[COPY13]]
3644  ; GFX8:   $vgpr6 = COPY [[COPY14]]
3645  ; GFX8:   $vgpr7 = COPY [[COPY15]]
3646  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3647  %soffset = add i32 %soffset.base, 4096
3648  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
3649  ret <8 x float> %val
3650}
3651
3652define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000(<4 x i32> %rsrc, i32 %offset.base) {
3653  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
3654  ; GFX6: bb.1 (%ir-block.0):
3655  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3656  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3657  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3658  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3659  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3660  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3661  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3662  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
3663  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3664  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3665  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3666  ; GFX6: bb.2:
3667  ; GFX6:   successors: %bb.3, %bb.2
3668  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3669  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3670  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3671  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3672  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3673  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3674  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3675  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3676  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3677  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3678  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3679  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3680  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3681  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3682  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3683  ; GFX6: bb.3:
3684  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3685  ; GFX6: bb.4:
3686  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3687  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3688  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3689  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3690  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3691  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3692  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3693  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3694  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3695  ; GFX6:   $vgpr0 = COPY [[COPY7]]
3696  ; GFX6:   $vgpr1 = COPY [[COPY8]]
3697  ; GFX6:   $vgpr2 = COPY [[COPY9]]
3698  ; GFX6:   $vgpr3 = COPY [[COPY10]]
3699  ; GFX6:   $vgpr4 = COPY [[COPY11]]
3700  ; GFX6:   $vgpr5 = COPY [[COPY12]]
3701  ; GFX6:   $vgpr6 = COPY [[COPY13]]
3702  ; GFX6:   $vgpr7 = COPY [[COPY14]]
3703  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3704  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
3705  ; GFX7: bb.1 (%ir-block.0):
3706  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3707  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3708  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3709  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3710  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3711  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3712  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3713  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
3714  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3715  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3716  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3717  ; GFX7: bb.2:
3718  ; GFX7:   successors: %bb.3, %bb.2
3719  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3720  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3721  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3722  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3723  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3724  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3725  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3726  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3727  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3728  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3729  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3730  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3731  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3732  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3733  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3734  ; GFX7: bb.3:
3735  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3736  ; GFX7: bb.4:
3737  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3738  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3739  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3740  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3741  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3742  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3743  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3744  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3745  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3746  ; GFX7:   $vgpr0 = COPY [[COPY7]]
3747  ; GFX7:   $vgpr1 = COPY [[COPY8]]
3748  ; GFX7:   $vgpr2 = COPY [[COPY9]]
3749  ; GFX7:   $vgpr3 = COPY [[COPY10]]
3750  ; GFX7:   $vgpr4 = COPY [[COPY11]]
3751  ; GFX7:   $vgpr5 = COPY [[COPY12]]
3752  ; GFX7:   $vgpr6 = COPY [[COPY13]]
3753  ; GFX7:   $vgpr7 = COPY [[COPY14]]
3754  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3755  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
3756  ; GFX8: bb.1 (%ir-block.0):
3757  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3758  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3759  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3760  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3761  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3762  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3763  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3764  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064
3765  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3766  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3767  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3768  ; GFX8: bb.2:
3769  ; GFX8:   successors: %bb.3, %bb.2
3770  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3771  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3772  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3773  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3774  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3775  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3776  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3777  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3778  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3779  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3780  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 936, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3781  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 952, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3782  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3783  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3784  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3785  ; GFX8: bb.3:
3786  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3787  ; GFX8: bb.4:
3788  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3789  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3790  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3791  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3792  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3793  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3794  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3795  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3796  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3797  ; GFX8:   $vgpr0 = COPY [[COPY7]]
3798  ; GFX8:   $vgpr1 = COPY [[COPY8]]
3799  ; GFX8:   $vgpr2 = COPY [[COPY9]]
3800  ; GFX8:   $vgpr3 = COPY [[COPY10]]
3801  ; GFX8:   $vgpr4 = COPY [[COPY11]]
3802  ; GFX8:   $vgpr5 = COPY [[COPY12]]
3803  ; GFX8:   $vgpr6 = COPY [[COPY13]]
3804  ; GFX8:   $vgpr7 = COPY [[COPY14]]
3805  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3806  %soffset = add i32 %offset.base, 5000
3807  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
3808  ret <8 x float> %val
3809}
3810
3811define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076(<4 x i32> %rsrc, i32 %offset.base) {
3812  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
3813  ; GFX6: bb.1 (%ir-block.0):
3814  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3815  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3816  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3817  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3818  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3819  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3820  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3821  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076
3822  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3823  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3824  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3825  ; GFX6: bb.2:
3826  ; GFX6:   successors: %bb.3, %bb.2
3827  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3828  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3829  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3830  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3831  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3832  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3833  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3834  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3835  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3836  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3837  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3838  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3839  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3840  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3841  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3842  ; GFX6: bb.3:
3843  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3844  ; GFX6: bb.4:
3845  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3846  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3847  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3848  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3849  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3850  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3851  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3852  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3853  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3854  ; GFX6:   $vgpr0 = COPY [[COPY7]]
3855  ; GFX6:   $vgpr1 = COPY [[COPY8]]
3856  ; GFX6:   $vgpr2 = COPY [[COPY9]]
3857  ; GFX6:   $vgpr3 = COPY [[COPY10]]
3858  ; GFX6:   $vgpr4 = COPY [[COPY11]]
3859  ; GFX6:   $vgpr5 = COPY [[COPY12]]
3860  ; GFX6:   $vgpr6 = COPY [[COPY13]]
3861  ; GFX6:   $vgpr7 = COPY [[COPY14]]
3862  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3863  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
3864  ; GFX7: bb.1 (%ir-block.0):
3865  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3866  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3867  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3868  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3869  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3870  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3871  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3872  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076
3873  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3874  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3875  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3876  ; GFX7: bb.2:
3877  ; GFX7:   successors: %bb.3, %bb.2
3878  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3879  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3880  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3881  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3882  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3883  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3884  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3885  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3886  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3887  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3888  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3889  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3890  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3891  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3892  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3893  ; GFX7: bb.3:
3894  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3895  ; GFX7: bb.4:
3896  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3897  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3898  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3899  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3900  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3901  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3902  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3903  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3904  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3905  ; GFX7:   $vgpr0 = COPY [[COPY7]]
3906  ; GFX7:   $vgpr1 = COPY [[COPY8]]
3907  ; GFX7:   $vgpr2 = COPY [[COPY9]]
3908  ; GFX7:   $vgpr3 = COPY [[COPY10]]
3909  ; GFX7:   $vgpr4 = COPY [[COPY11]]
3910  ; GFX7:   $vgpr5 = COPY [[COPY12]]
3911  ; GFX7:   $vgpr6 = COPY [[COPY13]]
3912  ; GFX7:   $vgpr7 = COPY [[COPY14]]
3913  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3914  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
3915  ; GFX8: bb.1 (%ir-block.0):
3916  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3917  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3918  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3919  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3920  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3921  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3922  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3923  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 12
3924  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3925  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3926  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3927  ; GFX8: bb.2:
3928  ; GFX8:   successors: %bb.3, %bb.2
3929  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3930  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3931  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3932  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3933  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3934  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3935  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3936  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3937  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3938  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3939  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3940  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3941  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3942  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
3943  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
3944  ; GFX8: bb.3:
3945  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
3946  ; GFX8: bb.4:
3947  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
3948  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
3949  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
3950  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
3951  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
3952  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
3953  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
3954  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
3955  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
3956  ; GFX8:   $vgpr0 = COPY [[COPY7]]
3957  ; GFX8:   $vgpr1 = COPY [[COPY8]]
3958  ; GFX8:   $vgpr2 = COPY [[COPY9]]
3959  ; GFX8:   $vgpr3 = COPY [[COPY10]]
3960  ; GFX8:   $vgpr4 = COPY [[COPY11]]
3961  ; GFX8:   $vgpr5 = COPY [[COPY12]]
3962  ; GFX8:   $vgpr6 = COPY [[COPY13]]
3963  ; GFX8:   $vgpr7 = COPY [[COPY14]]
3964  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
3965  %soffset = add i32 %offset.base, 4076
3966  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
3967  ret <8 x float> %val
3968}
3969
3970define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080(<4 x i32> %rsrc, i32 %offset.base) {
3971  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
3972  ; GFX6: bb.1 (%ir-block.0):
3973  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
3974  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
3975  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
3976  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
3977  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
3978  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
3979  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
3980  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080
3981  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
3982  ; GFX6:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
3983  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
3984  ; GFX6: bb.2:
3985  ; GFX6:   successors: %bb.3, %bb.2
3986  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
3987  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
3988  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
3989  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
3990  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
3991  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
3992  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
3993  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
3994  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
3995  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
3996  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3997  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
3998  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
3999  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
4000  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
4001  ; GFX6: bb.3:
4002  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
4003  ; GFX6: bb.4:
4004  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
4005  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
4006  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
4007  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
4008  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
4009  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
4010  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
4011  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
4012  ; GFX6:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
4013  ; GFX6:   $vgpr0 = COPY [[COPY7]]
4014  ; GFX6:   $vgpr1 = COPY [[COPY8]]
4015  ; GFX6:   $vgpr2 = COPY [[COPY9]]
4016  ; GFX6:   $vgpr3 = COPY [[COPY10]]
4017  ; GFX6:   $vgpr4 = COPY [[COPY11]]
4018  ; GFX6:   $vgpr5 = COPY [[COPY12]]
4019  ; GFX6:   $vgpr6 = COPY [[COPY13]]
4020  ; GFX6:   $vgpr7 = COPY [[COPY14]]
4021  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
4022  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
4023  ; GFX7: bb.1 (%ir-block.0):
4024  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
4025  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4026  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
4027  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
4028  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
4029  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
4030  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4031  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080
4032  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
4033  ; GFX7:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
4034  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
4035  ; GFX7: bb.2:
4036  ; GFX7:   successors: %bb.3, %bb.2
4037  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
4038  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
4039  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
4040  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
4041  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
4042  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
4043  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
4044  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
4045  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
4046  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
4047  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
4048  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
4049  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
4050  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
4051  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
4052  ; GFX7: bb.3:
4053  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
4054  ; GFX7: bb.4:
4055  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
4056  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
4057  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
4058  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
4059  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
4060  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
4061  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
4062  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
4063  ; GFX7:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
4064  ; GFX7:   $vgpr0 = COPY [[COPY7]]
4065  ; GFX7:   $vgpr1 = COPY [[COPY8]]
4066  ; GFX7:   $vgpr2 = COPY [[COPY9]]
4067  ; GFX7:   $vgpr3 = COPY [[COPY10]]
4068  ; GFX7:   $vgpr4 = COPY [[COPY11]]
4069  ; GFX7:   $vgpr5 = COPY [[COPY12]]
4070  ; GFX7:   $vgpr6 = COPY [[COPY13]]
4071  ; GFX7:   $vgpr7 = COPY [[COPY14]]
4072  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
4073  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
4074  ; GFX8: bb.1 (%ir-block.0):
4075  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
4076  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4077  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
4078  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
4079  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
4080  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
4081  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4082  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
4083  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
4084  ; GFX8:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
4085  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
4086  ; GFX8: bb.2:
4087  ; GFX8:   successors: %bb.3, %bb.2
4088  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
4089  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
4090  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
4091  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY5]], implicit $exec
4092  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
4093  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
4094  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
4095  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY6]], implicit $exec
4096  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
4097  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
4098  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
4099  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16, align 4)
4100  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
4101  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
4102  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
4103  ; GFX8: bb.3:
4104  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
4105  ; GFX8: bb.4:
4106  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
4107  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
4108  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
4109  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
4110  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
4111  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
4112  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
4113  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
4114  ; GFX8:   [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
4115  ; GFX8:   $vgpr0 = COPY [[COPY7]]
4116  ; GFX8:   $vgpr1 = COPY [[COPY8]]
4117  ; GFX8:   $vgpr2 = COPY [[COPY9]]
4118  ; GFX8:   $vgpr3 = COPY [[COPY10]]
4119  ; GFX8:   $vgpr4 = COPY [[COPY11]]
4120  ; GFX8:   $vgpr5 = COPY [[COPY12]]
4121  ; GFX8:   $vgpr6 = COPY [[COPY13]]
4122  ; GFX8:   $vgpr7 = COPY [[COPY14]]
4123  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
4124  %soffset = add i32 %offset.base, 4080
4125  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
4126  ret <8 x float> %val
4127}
4128
4129define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064(<4 x i32> %rsrc, i32 %offset.base) {
4130  ; GFX6-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064
4131  ; GFX6: bb.1 (%ir-block.0):
4132  ; GFX6:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
4133  ; GFX6:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4134  ; GFX6:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
4135  ; GFX6:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
4136  ; GFX6:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
4137  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4138  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4139  ; GFX6:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
4140  ; GFX6:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
4141  ; GFX6:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
4142  ; GFX6: bb.2:
4143  ; GFX6:   successors: %bb.3, %bb.2
4144  ; GFX6:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
4145  ; GFX6:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
4146  ; GFX6:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
4147  ; GFX6:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
4148  ; GFX6:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
4149  ; GFX6:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
4150  ; GFX6:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
4151  ; GFX6:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
4152  ; GFX6:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
4153  ; GFX6:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
4154  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 4064, align 4)
4155  ; GFX6:   [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 4064, align 4)
4156  ; GFX6:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
4157  ; GFX6:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
4158  ; GFX6:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
4159  ; GFX6: bb.3:
4160  ; GFX6:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
4161  ; GFX6: bb.4:
4162  ; GFX6:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
4163  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
4164  ; GFX6:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
4165  ; GFX6:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
4166  ; GFX6:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
4167  ; GFX6:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
4168  ; GFX6:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
4169  ; GFX6:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
4170  ; GFX6:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
4171  ; GFX6:   $vgpr0 = COPY [[COPY6]]
4172  ; GFX6:   $vgpr1 = COPY [[COPY7]]
4173  ; GFX6:   $vgpr2 = COPY [[COPY8]]
4174  ; GFX6:   $vgpr3 = COPY [[COPY9]]
4175  ; GFX6:   $vgpr4 = COPY [[COPY10]]
4176  ; GFX6:   $vgpr5 = COPY [[COPY11]]
4177  ; GFX6:   $vgpr6 = COPY [[COPY12]]
4178  ; GFX6:   $vgpr7 = COPY [[COPY13]]
4179  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
4180  ; GFX7-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064
4181  ; GFX7: bb.1 (%ir-block.0):
4182  ; GFX7:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
4183  ; GFX7:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4184  ; GFX7:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
4185  ; GFX7:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
4186  ; GFX7:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
4187  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4188  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4189  ; GFX7:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
4190  ; GFX7:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
4191  ; GFX7:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
4192  ; GFX7: bb.2:
4193  ; GFX7:   successors: %bb.3, %bb.2
4194  ; GFX7:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
4195  ; GFX7:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
4196  ; GFX7:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
4197  ; GFX7:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
4198  ; GFX7:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
4199  ; GFX7:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
4200  ; GFX7:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
4201  ; GFX7:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
4202  ; GFX7:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
4203  ; GFX7:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
4204  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 4064, align 4)
4205  ; GFX7:   [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 4064, align 4)
4206  ; GFX7:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
4207  ; GFX7:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
4208  ; GFX7:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
4209  ; GFX7: bb.3:
4210  ; GFX7:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
4211  ; GFX7: bb.4:
4212  ; GFX7:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
4213  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
4214  ; GFX7:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
4215  ; GFX7:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
4216  ; GFX7:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
4217  ; GFX7:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
4218  ; GFX7:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
4219  ; GFX7:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
4220  ; GFX7:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
4221  ; GFX7:   $vgpr0 = COPY [[COPY6]]
4222  ; GFX7:   $vgpr1 = COPY [[COPY7]]
4223  ; GFX7:   $vgpr2 = COPY [[COPY8]]
4224  ; GFX7:   $vgpr3 = COPY [[COPY9]]
4225  ; GFX7:   $vgpr4 = COPY [[COPY10]]
4226  ; GFX7:   $vgpr5 = COPY [[COPY11]]
4227  ; GFX7:   $vgpr6 = COPY [[COPY12]]
4228  ; GFX7:   $vgpr7 = COPY [[COPY13]]
4229  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
4230  ; GFX8-LABEL: name: s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4064
4231  ; GFX8: bb.1 (%ir-block.0):
4232  ; GFX8:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
4233  ; GFX8:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4234  ; GFX8:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
4235  ; GFX8:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
4236  ; GFX8:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
4237  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4238  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4239  ; GFX8:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
4240  ; GFX8:   [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
4241  ; GFX8:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
4242  ; GFX8: bb.2:
4243  ; GFX8:   successors: %bb.3, %bb.2
4244  ; GFX8:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub0, implicit $exec
4245  ; GFX8:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]].sub1, implicit $exec
4246  ; GFX8:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
4247  ; GFX8:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY4]], implicit $exec
4248  ; GFX8:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub0, implicit $exec
4249  ; GFX8:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]].sub1, implicit $exec
4250  ; GFX8:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
4251  ; GFX8:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY5]], implicit $exec
4252  ; GFX8:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
4253  ; GFX8:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
4254  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4064, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 4064, align 4)
4255  ; GFX8:   [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE3]], [[S_MOV_B32_]], 4080, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 16 + 4064, align 4)
4256  ; GFX8:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
4257  ; GFX8:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
4258  ; GFX8:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
4259  ; GFX8: bb.3:
4260  ; GFX8:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
4261  ; GFX8: bb.4:
4262  ; GFX8:   [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
4263  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub0
4264  ; GFX8:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub1
4265  ; GFX8:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub2
4266  ; GFX8:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub3
4267  ; GFX8:   [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub4
4268  ; GFX8:   [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub5
4269  ; GFX8:   [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub6
4270  ; GFX8:   [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE4]].sub7
4271  ; GFX8:   $vgpr0 = COPY [[COPY6]]
4272  ; GFX8:   $vgpr1 = COPY [[COPY7]]
4273  ; GFX8:   $vgpr2 = COPY [[COPY8]]
4274  ; GFX8:   $vgpr3 = COPY [[COPY9]]
4275  ; GFX8:   $vgpr4 = COPY [[COPY10]]
4276  ; GFX8:   $vgpr5 = COPY [[COPY11]]
4277  ; GFX8:   $vgpr6 = COPY [[COPY12]]
4278  ; GFX8:   $vgpr7 = COPY [[COPY13]]
4279  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7
4280  %val = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 4064, i32 0)
4281  ret <8 x float> %val
4282}
4283
4284define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
4285  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
4286  ; GFX6: bb.1 (%ir-block.0):
4287  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4288  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4289  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4290  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4291  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4292  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4293  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4294  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4295  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4296  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4297  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
4298  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
4299  ; GFX7: bb.1 (%ir-block.0):
4300  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4301  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4302  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4303  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4304  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4305  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4306  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4307  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4308  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4309  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4310  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
4311  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr
4312  ; GFX8: bb.1 (%ir-block.0):
4313  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4314  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4315  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4316  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4317  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4318  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4319  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4320  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4321  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4322  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4323  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
4324  %offset = add i32 %offset.v, %offset.s
4325  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
4326  ret float %val
4327}
4328
4329define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
4330  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
4331  ; GFX6: bb.1 (%ir-block.0):
4332  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4333  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4334  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4335  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4336  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4337  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4338  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4339  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4340  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4341  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4342  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
4343  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
4344  ; GFX7: bb.1 (%ir-block.0):
4345  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4346  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4347  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4348  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4349  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4350  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4351  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4352  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4353  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4354  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4355  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
4356  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr
4357  ; GFX8: bb.1 (%ir-block.0):
4358  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4359  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4360  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4361  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4362  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4363  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4364  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4365  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4366  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4367  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4368  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
4369  %offset = add i32 %offset.s, %offset.v
4370  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
4371  ret float %val
4372}
4373
4374define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
4375  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
4376  ; GFX6: bb.1 (%ir-block.0):
4377  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4378  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4379  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4380  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4381  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4382  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4383  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4384  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4385  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
4386  ; GFX6:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
4387  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4388  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4389  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4390  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
4391  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
4392  ; GFX7: bb.1 (%ir-block.0):
4393  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4394  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4395  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4396  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4397  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4398  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4399  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4400  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4401  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
4402  ; GFX7:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
4403  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4404  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4405  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4406  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
4407  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm
4408  ; GFX8: bb.1 (%ir-block.0):
4409  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4410  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4411  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4412  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4413  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4414  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4415  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4416  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4417  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
4418  ; GFX8:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
4419  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4420  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4421  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4422  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
4423  %offset.base = add i32 %offset.v, %offset.s
4424  %offset = add i32 %offset.base, 1024
4425  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
4426  ret float %val
4427}
4428
4429define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
4430  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
4431  ; GFX6: bb.1 (%ir-block.0):
4432  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4433  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4434  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4435  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4436  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4437  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4438  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4439  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4440  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
4441  ; GFX6:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec
4442  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4443  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4444  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4445  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
4446  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
4447  ; GFX7: bb.1 (%ir-block.0):
4448  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4449  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4450  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4451  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4452  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4453  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4454  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4455  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4456  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
4457  ; GFX7:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec
4458  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4459  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4460  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4461  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
4462  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm
4463  ; GFX8: bb.1 (%ir-block.0):
4464  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4465  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4466  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4467  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4468  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4469  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4470  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4471  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4472  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
4473  ; GFX8:   %9:vgpr_32, dead %17:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec
4474  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4475  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %9, [[REG_SEQUENCE]], [[S_MOV_B32_]], 1024, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4476  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4477  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
4478  %offset.base = add i32 %offset.s, %offset.v
4479  %offset = add i32 %offset.base, 1024
4480  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
4481  ret float %val
4482}
4483
4484; TODO: Ideally this would be reassociated to fold.
4485define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
4486  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
4487  ; GFX6: bb.1 (%ir-block.0):
4488  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4489  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4490  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4491  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4492  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4493  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4494  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4495  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4496  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4497  ; GFX6:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
4498  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4499  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4500  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
4501  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
4502  ; GFX7: bb.1 (%ir-block.0):
4503  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4504  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4505  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4506  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4507  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4508  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4509  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4510  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4511  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4512  ; GFX7:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
4513  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4514  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4515  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
4516  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr
4517  ; GFX8: bb.1 (%ir-block.0):
4518  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4519  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4520  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4521  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4522  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4523  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4524  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4525  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4526  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4527  ; GFX8:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
4528  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4529  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4530  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
4531  %offset.base = add i32 %offset.s, 1024
4532  %offset = add i32 %offset.base, %offset.v
4533  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
4534  ret float %val
4535}
4536
4537define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inreg %rsrc, i32 %offset.v, i32 inreg %offset.s) {
4538  ; GFX6-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
4539  ; GFX6: bb.1 (%ir-block.0):
4540  ; GFX6:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4541  ; GFX6:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4542  ; GFX6:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4543  ; GFX6:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4544  ; GFX6:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4545  ; GFX6:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4546  ; GFX6:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4547  ; GFX6:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4548  ; GFX6:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4549  ; GFX6:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
4550  ; GFX6:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
4551  ; GFX6:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4552  ; GFX6:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4553  ; GFX6:   SI_RETURN_TO_EPILOG implicit $vgpr0
4554  ; GFX7-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
4555  ; GFX7: bb.1 (%ir-block.0):
4556  ; GFX7:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4557  ; GFX7:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4558  ; GFX7:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4559  ; GFX7:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4560  ; GFX7:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4561  ; GFX7:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4562  ; GFX7:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4563  ; GFX7:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4564  ; GFX7:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4565  ; GFX7:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
4566  ; GFX7:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
4567  ; GFX7:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4568  ; GFX7:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4569  ; GFX7:   SI_RETURN_TO_EPILOG implicit $vgpr0
4570  ; GFX8-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr
4571  ; GFX8: bb.1 (%ir-block.0):
4572  ; GFX8:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
4573  ; GFX8:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
4574  ; GFX8:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
4575  ; GFX8:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
4576  ; GFX8:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
4577  ; GFX8:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4578  ; GFX8:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
4579  ; GFX8:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
4580  ; GFX8:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
4581  ; GFX8:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
4582  ; GFX8:   %10:vgpr_32, dead %16:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
4583  ; GFX8:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
4584  ; GFX8:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
4585  ; GFX8:   SI_RETURN_TO_EPILOG implicit $vgpr0
4586  %offset.base = add i32 %offset.v, 1024
4587  %offset = add i32 %offset.base, %offset.s
4588  %val = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
4589  ret float %val
4590}
4591
4592declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg)
4593declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32 immarg)
4594declare <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32>, i32, i32 immarg)
4595declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32 immarg)
4596declare <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32>, i32, i32 immarg)
4597declare <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32>, i32, i32 immarg)
4598
4599declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32      immarg)
4600declare <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32>, i32, i32 immarg)
4601declare <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32>, i32, i32 immarg)
4602declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32 immarg)
4603declare <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32>, i32, i32 immarg)
4604declare <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32>, i32, i32 immarg)
4605
4606declare i96 @llvm.amdgcn.s.buffer.load.i96(<4 x i32>, i32, i32 immarg)
4607declare i256 @llvm.amdgcn.s.buffer.load.i256(<4 x i32>, i32, i32 immarg)
4608declare i512 @llvm.amdgcn.s.buffer.load.i512(<4 x i32>, i32, i32 immarg)
4609
4610declare <16 x i16> @llvm.amdgcn.s.buffer.load.v16i16(<4 x i32>, i32, i32 immarg)
4611declare <32 x i16> @llvm.amdgcn.s.buffer.load.v32i16(<4 x i32>, i32, i32 immarg)
4612
4613declare <4 x i64> @llvm.amdgcn.s.buffer.load.v4i64(<4 x i32>, i32, i32 immarg)
4614declare <8 x i64> @llvm.amdgcn.s.buffer.load.v8i64(<4 x i32>, i32, i32 immarg)
4615
4616declare <4 x i8 addrspace(1)*> @llvm.amdgcn.s.buffer.load.v4p1i8(<4 x i32>, i32, i32 immarg)
4617declare <8 x i8 addrspace(1)*> @llvm.amdgcn.s.buffer.load.v8p1i8(<4 x i32>, i32, i32 immarg)
4618