1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
3
4define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
5  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
6  ; CHECK: bb.1 (%ir-block.0):
7  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
8  ; CHECK:   $vcc_hi = IMPLICIT_DEF
9  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
10  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
11  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
12  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
13  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
14  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
15  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
16  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
17  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
18  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
19  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
20  ret float %val
21}
22
23define amdgpu_ps <2 x float> @raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
24  ; CHECK-LABEL: name: raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
25  ; CHECK: bb.1 (%ir-block.0):
26  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
27  ; CHECK:   $vcc_hi = IMPLICIT_DEF
28  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
29  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
30  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
31  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
32  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
33  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
34  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
35  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "TargetCustom7", align 1, addrspace 4)
36  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub0
37  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub1
38  ; CHECK:   $vgpr0 = COPY [[COPY6]]
39  ; CHECK:   $vgpr1 = COPY [[COPY7]]
40  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
41  %val = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
42  ret <2 x float> %val
43}
44
45define amdgpu_ps <3 x float> @raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
46  ; CHECK-LABEL: name: raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
47  ; CHECK: bb.1 (%ir-block.0):
48  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
49  ; CHECK:   $vcc_hi = IMPLICIT_DEF
50  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
51  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
52  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
53  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
54  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
55  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
56  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
57  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "TargetCustom7", align 1, addrspace 4)
58  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0
59  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1
60  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2
61  ; CHECK:   $vgpr0 = COPY [[COPY6]]
62  ; CHECK:   $vgpr1 = COPY [[COPY7]]
63  ; CHECK:   $vgpr2 = COPY [[COPY8]]
64  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
65  %val = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
66  ret <3 x float> %val
67}
68
69define amdgpu_ps <4 x float> @raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
70  ; CHECK-LABEL: name: raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
71  ; CHECK: bb.1 (%ir-block.0):
72  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
73  ; CHECK:   $vcc_hi = IMPLICIT_DEF
74  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
75  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
76  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
77  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
78  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
79  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
80  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
81  ; CHECK:   [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "TargetCustom7", align 1, addrspace 4)
82  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0
83  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1
84  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2
85  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3
86  ; CHECK:   $vgpr0 = COPY [[COPY6]]
87  ; CHECK:   $vgpr1 = COPY [[COPY7]]
88  ; CHECK:   $vgpr2 = COPY [[COPY8]]
89  ; CHECK:   $vgpr3 = COPY [[COPY9]]
90  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
91  %val = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
92  ret <4 x float> %val
93}
94
95define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 inreg %voffset, i32 %soffset) {
96  ; CHECK-LABEL: name: raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset
97  ; CHECK: bb.1 (%ir-block.0):
98  ; CHECK:   successors: %bb.2(0x80000000)
99  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
100  ; CHECK:   $vcc_hi = IMPLICIT_DEF
101  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
102  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
103  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
104  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
105  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
106  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4
107  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
108  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
109  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
110  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
111  ; CHECK:   [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
112  ; CHECK: bb.2:
113  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
114  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
115  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
116  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
117  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY7]], implicit $exec
118  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
119  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
120  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
121  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec
122  ; CHECK:   [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
123  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
124  ; CHECK:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
125  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY5]], implicit $exec
126  ; CHECK:   [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[S_AND_B32_]], implicit-def $scc
127  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY6]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
128  ; CHECK:   [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_1]], implicit-def $exec, implicit-def $scc, implicit $exec
129  ; CHECK:   $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
130  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
131  ; CHECK: bb.3:
132  ; CHECK:   successors: %bb.4(0x80000000)
133  ; CHECK:   $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
134  ; CHECK: bb.4:
135  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
136  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
137  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
138  ret float %val
139}
140
141define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
142  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
143  ; CHECK: bb.1 (%ir-block.0):
144  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
145  ; CHECK:   $vcc_hi = IMPLICIT_DEF
146  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
147  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
148  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
149  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
150  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
151  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
152  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
153  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
154  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
155  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
156  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
157  ret float %val
158}
159
160define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
161  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
162  ; CHECK: bb.1 (%ir-block.0):
163  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
164  ; CHECK:   $vcc_hi = IMPLICIT_DEF
165  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
166  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
167  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
168  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
169  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
170  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
171  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
172  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
173  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
174  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
175  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
176  ret float %val
177}
178
179define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
180  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc
181  ; CHECK: bb.1 (%ir-block.0):
182  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
183  ; CHECK:   $vcc_hi = IMPLICIT_DEF
184  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
185  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
186  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
187  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
188  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
189  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
190  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
191  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
192  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
193  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
194  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
195  ret float %val
196}
197
198define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
199  ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
200  ; CHECK: bb.1 (%ir-block.0):
201  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
202  ; CHECK:   $vcc_hi = IMPLICIT_DEF
203  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
204  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
205  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
206  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
207  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
208  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
209  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
210  ; CHECK:   [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
211  ; CHECK:   $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
212  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
213  %val = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
214  ret float %val
215}
216
217declare float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
218declare <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
219declare <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
220declare <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0
221
222attributes #0 = { nounwind readonly }
223