1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
3; FIXME: Test with SI when argument lowering not broken for f16
4
5; Natural mapping
6define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
7  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
8  ; CHECK: bb.1 (%ir-block.0):
9  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
10  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
11  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
12  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
13  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
14  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
15  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
16  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
17  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
18  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
19  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
20  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
21  ret float %val
22}
23
24; Copies for VGPR arguments
25define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) {
26  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset
27  ; CHECK: bb.1 (%ir-block.0):
28  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
29  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
30  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
31  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
32  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
33  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
34  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7
35  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
36  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
37  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
38  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
39  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
40  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
41  ret float %val
42}
43
44; Waterfall for rsrc
45define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
46  ; CHECK-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset
47  ; CHECK: bb.1 (%ir-block.0):
48  ; CHECK:   successors: %bb.2(0x80000000)
49  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
50  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
51  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
52  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
53  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
54  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
55  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
56  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
57  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
58  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
59  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
60  ; CHECK: bb.2:
61  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
62  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
63  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
64  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
65  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
66  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
67  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
68  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
69  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
70  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
71  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
72  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
73  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
74  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
75  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
76  ; CHECK: bb.3:
77  ; CHECK:   successors: %bb.4(0x80000000)
78  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
79  ; CHECK: bb.4:
80  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
81  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
82  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
83  ret float %val
84}
85
86; Waterfall for rsrc and soffset
87define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 %soffset) {
88  ; CHECK-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset
89  ; CHECK: bb.1 (%ir-block.0):
90  ; CHECK:   successors: %bb.2(0x80000000)
91  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
92  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
93  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
94  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
95  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
96  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
97  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
98  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
99  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
100  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
101  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
102  ; CHECK: bb.2:
103  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
104  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
105  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
106  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
107  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
108  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
109  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
110  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
111  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
112  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
113  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
114  ; CHECK:   [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
115  ; CHECK:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY5]], implicit $exec
116  ; CHECK:   [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc
117  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
118  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec
119  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
120  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
121  ; CHECK: bb.3:
122  ; CHECK:   successors: %bb.4(0x80000000)
123  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
124  ; CHECK: bb.4:
125  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
126  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
127  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
128  ret float %val
129}
130
131; Natural mapping + glc
132define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
133  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc
134  ; CHECK: bb.1 (%ir-block.0):
135  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
136  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
137  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
138  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
139  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
140  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
141  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
142  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
143  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
144  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
145  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
146  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)
147  ret float %val
148}
149
150; Natural mapping + slc
151define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
152  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc
153  ; CHECK: bb.1 (%ir-block.0):
154  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
155  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
156  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
157  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
158  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
159  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
160  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
161  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
162  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
163  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
164  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
165  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
166  ret float %val
167}
168
169; Natural mapping + dlc
170define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
171  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc
172  ; CHECK: bb.1 (%ir-block.0):
173  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
174  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
175  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
176  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
177  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
178  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
179  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
180  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
181  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
182  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
183  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
184  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)
185  ret float %val
186}
187
188; Natural mapping + slc + dlc
189define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
190  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc
191  ; CHECK: bb.1 (%ir-block.0):
192  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
193  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
194  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
195  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
196  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
197  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
198  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
199  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
200  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
201  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
202  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
203  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)
204  ret float %val
205}
206
207; Natural mapping + glc + dlc
208define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
209  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc
210  ; CHECK: bb.1 (%ir-block.0):
211  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
212  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
213  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
214  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
215  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
216  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
217  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
218  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
219  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
220  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
221  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
222  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)
223  ret float %val
224}
225
226; Natural mapping + glc + slc + dlc
227define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
228  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc
229  ; CHECK: bb.1 (%ir-block.0):
230  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
231  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
232  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
233  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
234  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
235  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
236  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
237  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
238  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
239  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
240  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
241  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)
242  ret float %val
243}
244
245; Natural mapping
246define amdgpu_ps <2 x float> @raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
247  ; CHECK-LABEL: name: raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
248  ; CHECK: bb.1 (%ir-block.0):
249  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
250  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
251  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
252  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
253  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
254  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
255  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
256  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
257  ; CHECK:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "TargetCustom7", align 1, addrspace 4)
258  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
259  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
260  ; CHECK:   $vgpr0 = COPY [[COPY6]]
261  ; CHECK:   $vgpr1 = COPY [[COPY7]]
262  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
263  %val = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
264  ret <2 x float> %val
265}
266
267define amdgpu_ps <3 x float> @raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
268  ; CHECK-LABEL: name: raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
269  ; CHECK: bb.1 (%ir-block.0):
270  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
271  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
272  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
273  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
274  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
275  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
276  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
277  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
278  ; CHECK:   [[BUFFER_LOAD_DWORDX3_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 12 from custom "TargetCustom7", align 1, addrspace 4)
279  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub0
280  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub1
281  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFEN]].sub2
282  ; CHECK:   $vgpr0 = COPY [[COPY6]]
283  ; CHECK:   $vgpr1 = COPY [[COPY7]]
284  ; CHECK:   $vgpr2 = COPY [[COPY8]]
285  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
286  %val = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
287  ret <3 x float> %val
288}
289
290define amdgpu_ps <4 x float> @raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
291  ; CHECK-LABEL: name: raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset
292  ; CHECK: bb.1 (%ir-block.0):
293  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
294  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
295  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
296  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
297  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
298  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
299  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
300  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
301  ; CHECK:   [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "TargetCustom7", align 1, addrspace 4)
302  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
303  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
304  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
305  ; CHECK:   [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
306  ; CHECK:   $vgpr0 = COPY [[COPY6]]
307  ; CHECK:   $vgpr1 = COPY [[COPY7]]
308  ; CHECK:   $vgpr2 = COPY [[COPY8]]
309  ; CHECK:   $vgpr3 = COPY [[COPY9]]
310  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
311  %val = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
312  ret <4 x float> %val
313}
314
315define amdgpu_ps half @raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
316  ; CHECK-LABEL: name: raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
317  ; CHECK: bb.1 (%ir-block.0):
318  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
319  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
320  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
321  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
322  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
323  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
324  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
325  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
326  ; CHECK:   [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "TargetCustom7", align 1, addrspace 4)
327  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]
328  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
329  %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
330  ret half %val
331}
332
333define amdgpu_ps <2 x half> @raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
334  ; CHECK-LABEL: name: raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
335  ; CHECK: bb.1 (%ir-block.0):
336  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
337  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
338  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
339  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
340  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
341  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
342  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
343  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
344  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
345  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
346  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
347  %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
348  ret <2 x half> %val
349}
350
351; FIXME: Crashes
352; define amdgpu_ps <3 x half> @raw_buffer_load_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
353;   %val = call <3 x half> @llvm.amdgcn.raw.buffer.load.v3f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
354;   ret <3 x half> %val
355; }
356
357define amdgpu_ps <4 x half> @raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
358  ; CHECK-LABEL: name: raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset
359  ; CHECK: bb.1 (%ir-block.0):
360  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
361  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
362  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
363  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
364  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
365  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
366  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
367  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
368  ; CHECK:   [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from custom "TargetCustom7", align 1, addrspace 4)
369  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0
370  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1
371  ; CHECK:   $vgpr0 = COPY [[COPY6]]
372  ; CHECK:   $vgpr1 = COPY [[COPY7]]
373  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
374  %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
375  ret <4 x half> %val
376}
377
378define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
379  ; CHECK-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext
380  ; CHECK: bb.1 (%ir-block.0):
381  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
382  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
383  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
384  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
385  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
386  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
387  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
388  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
389  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "TargetCustom7", addrspace 4)
390  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255
391  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
392  ; CHECK:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[BUFFER_LOAD_UBYTE_OFFEN]], [[COPY6]], implicit $exec
393  ; CHECK:   $vgpr0 = COPY [[V_AND_B32_e64_]]
394  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
395  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
396  %zext = zext i8 %val to i32
397  %cast = bitcast i32 %zext to float
398  ret float %cast
399}
400
401define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
402  ; CHECK-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext
403  ; CHECK: bb.1 (%ir-block.0):
404  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
405  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
406  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
407  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
408  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
409  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
410  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
411  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
412  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "TargetCustom7", addrspace 4)
413  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 24
414  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
415  ; CHECK:   [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY6]], [[BUFFER_LOAD_UBYTE_OFFEN]], implicit $exec
416  ; CHECK:   [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
417  ; CHECK:   [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY7]], [[V_LSHLREV_B32_e64_]], implicit $exec
418  ; CHECK:   $vgpr0 = COPY [[V_ASHRREV_I32_e64_]]
419  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
420  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
421  %zext = sext i8 %val to i32
422  %cast = bitcast i32 %zext to float
423  ret float %cast
424}
425
426; Waterfall for rsrc
427define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
428  ; CHECK-LABEL: name: raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset
429  ; CHECK: bb.1 (%ir-block.0):
430  ; CHECK:   successors: %bb.2(0x80000000)
431  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
432  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
433  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
434  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
435  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
436  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
437  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
438  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
439  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
440  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
441  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
442  ; CHECK: bb.2:
443  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
444  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
445  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
446  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
447  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
448  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
449  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
450  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
451  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
452  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
453  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
454  ; CHECK:   [[BUFFER_LOAD_USHORT_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 2 from custom "TargetCustom7", align 1, addrspace 4)
455  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
456  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
457  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
458  ; CHECK: bb.3:
459  ; CHECK:   successors: %bb.4(0x80000000)
460  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
461  ; CHECK: bb.4:
462  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]
463  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
464  %val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
465  ret half %val
466}
467
468; Waterfall for rsrc
469define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset) {
470  ; CHECK-LABEL: name: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset
471  ; CHECK: bb.1 (%ir-block.0):
472  ; CHECK:   successors: %bb.2(0x80000000)
473  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
474  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
475  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
476  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
477  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
478  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
479  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
480  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
481  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
482  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
483  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
484  ; CHECK: bb.2:
485  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
486  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
487  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
488  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
489  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
490  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
491  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
492  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
493  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
494  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
495  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
496  ; CHECK:   [[BUFFER_LOAD_UBYTE_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 1 from custom "TargetCustom7", addrspace 4)
497  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
498  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
499  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
500  ; CHECK: bb.3:
501  ; CHECK:   successors: %bb.4(0x80000000)
502  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
503  ; CHECK: bb.4:
504  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 255
505  ; CHECK:   [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
506  ; CHECK:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[BUFFER_LOAD_UBYTE_OFFEN]], [[COPY8]], implicit $exec
507  ; CHECK:   $vgpr0 = COPY [[V_AND_B32_e64_]]
508  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
509  %val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
510  %zext = zext i8 %val to i32
511  %cast = bitcast i32 %zext to float
512  ret float %cast
513}
514
515define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
516  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0
517  ; CHECK: bb.1 (%ir-block.0):
518  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
519  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
520  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
521  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
522  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
523  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
524  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
525  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
526  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
527  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
528  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
529  ret float %val
530}
531
532define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
533  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095
534  ; CHECK: bb.1 (%ir-block.0):
535  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
536  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
537  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
538  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
539  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
540  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
541  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
542  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 4095, align 1, addrspace 4)
543  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
544  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
545  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
546  ret float %val
547}
548
549define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
550  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096
551  ; CHECK: bb.1 (%ir-block.0):
552  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
553  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
554  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
555  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
556  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
557  ; CHECK:   [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
558  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
559  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
560  ; CHECK:   [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
561  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY5]], [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 4096, align 1, addrspace 4)
562  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
563  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
564  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)
565  ret float %val
566}
567
568define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
569  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16
570  ; CHECK: bb.1 (%ir-block.0):
571  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
572  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
573  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
574  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
575  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
576  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
577  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
578  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
579  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 16, align 1, addrspace 4)
580  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
581  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
582  %voffset = add i32 %voffset.base, 16
583  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
584  ret float %val
585}
586
587define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
588  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095
589  ; CHECK: bb.1 (%ir-block.0):
590  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
591  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
592  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
593  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
594  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
595  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
596  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
597  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
598  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 4095, align 1, addrspace 4)
599  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
600  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
601  %voffset = add i32 %voffset.base, 4095
602  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
603  ret float %val
604}
605
606define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096(<4 x i32> inreg %rsrc, i32 %voffset.base, i32 inreg %soffset) {
607  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096
608  ; CHECK: bb.1 (%ir-block.0):
609  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
610  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
611  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
612  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
613  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
614  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
615  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
616  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
617  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
618  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
619  ; CHECK:   %10:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
620  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %10, [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 4096, align 1, addrspace 4)
621  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
622  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
623  %voffset = add i32 %voffset.base, 4096
624  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
625  ret float %val
626}
627
628define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095(<4 x i32> inreg %rsrc, i32 %voffset) {
629  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095
630  ; CHECK: bb.1 (%ir-block.0):
631  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
632  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
633  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
634  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
635  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
636  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
637  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
638  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
639  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
640  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
641  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
642  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
643  ret float %val
644}
645
646define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096(<4 x i32> inreg %rsrc, i32 %voffset) {
647  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096
648  ; CHECK: bb.1 (%ir-block.0):
649  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0
650  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
651  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
652  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
653  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
654  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
655  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
656  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
657  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
658  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
659  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
660  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
661  ret float %val
662}
663
664define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
665  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16
666  ; CHECK: bb.1 (%ir-block.0):
667  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
668  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
669  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
670  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
671  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
672  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
673  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
674  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
675  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
676  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
677  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
678  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
679  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
680  %soffset = add i32 %soffset.base, 16
681  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
682  ret float %val
683}
684
685define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
686  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095
687  ; CHECK: bb.1 (%ir-block.0):
688  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
689  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
690  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
691  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
692  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
693  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
694  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
695  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
696  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
697  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
698  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
699  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
700  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
701  %soffset = add i32 %soffset.base, 4095
702  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
703  ret float %val
704}
705
706define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset.base) {
707  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096
708  ; CHECK: bb.1 (%ir-block.0):
709  ; CHECK:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
710  ; CHECK:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
711  ; CHECK:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
712  ; CHECK:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
713  ; CHECK:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
714  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
715  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
716  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
717  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
718  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
719  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
720  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
721  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
722  %soffset = add i32 %soffset.base, 4096
723  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
724  ret float %val
725}
726
727; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.
728define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset.base) {
729  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000
730  ; CHECK: bb.1 (%ir-block.0):
731  ; CHECK:   successors: %bb.2(0x80000000)
732  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
733  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
734  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
735  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
736  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
737  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
738  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
739  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
740  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
741  ; CHECK:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
742  ; CHECK:   [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
743  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
744  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
745  ; CHECK: bb.2:
746  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
747  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec
748  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec
749  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
750  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec
751  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
752  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
753  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
754  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
755  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
756  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
757  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY4]], [[REG_SEQUENCE3]], [[S_ADD_I32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7", align 1, addrspace 4)
758  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
759  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
760  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
761  ; CHECK: bb.3:
762  ; CHECK:   successors: %bb.4(0x80000000)
763  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
764  ; CHECK: bb.4:
765  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
766  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
767  %soffset = add i32 %soffset.base, 5000
768  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
769  ret float %val
770}
771
772; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.
773define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000(<4 x i32> %rsrc, i32 %voffset.base, i32 inreg %soffset) {
774  ; CHECK-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000
775  ; CHECK: bb.1 (%ir-block.0):
776  ; CHECK:   successors: %bb.2(0x80000000)
777  ; CHECK:   liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
778  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
779  ; CHECK:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
780  ; CHECK:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
781  ; CHECK:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
782  ; CHECK:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
783  ; CHECK:   [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
784  ; CHECK:   [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
785  ; CHECK:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
786  ; CHECK:   [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
787  ; CHECK:   %13:vgpr_32, dead %35:sreg_64_xexec = V_ADD_I32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
788  ; CHECK:   [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
789  ; CHECK:   [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
790  ; CHECK:   [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
791  ; CHECK: bb.2:
792  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
793  ; CHECK:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec
794  ; CHECK:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec
795  ; CHECK:   [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
796  ; CHECK:   [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY7]], implicit $exec
797  ; CHECK:   [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
798  ; CHECK:   [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec
799  ; CHECK:   [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
800  ; CHECK:   [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec
801  ; CHECK:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
802  ; CHECK:   [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
803  ; CHECK:   [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %13, [[REG_SEQUENCE3]], [[COPY5]], 904, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "TargetCustom7" + 5000, align 1, addrspace 4)
804  ; CHECK:   [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
805  ; CHECK:   $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
806  ; CHECK:   S_CBRANCH_EXECNZ %bb.2, implicit $exec
807  ; CHECK: bb.3:
808  ; CHECK:   successors: %bb.4(0x80000000)
809  ; CHECK:   $exec = S_MOV_B64_term [[S_MOV_B64_term]]
810  ; CHECK: bb.4:
811  ; CHECK:   $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
812  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
813  %voffset = add i32 %voffset.base, 5000
814  %val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
815  ret float %val
816}
817
818declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32 immarg)
819declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32 immarg)
820declare <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32>, i32, i32, i32 immarg)
821declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32 immarg)
822
823declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32 immarg)
824declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32 immarg)
825declare <3 x half> @llvm.amdgcn.raw.buffer.load.v3f16(<4 x i32>, i32, i32, i32 immarg)
826declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32 immarg)
827
828declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32 immarg)
829