1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s 6 7; TODO: Merge with DAG test 8 9define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { 10; CI-LABEL: is_local_vgpr: 11; CI: ; %bb.0: 12; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 13; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 14; CI-NEXT: s_waitcnt lgkmcnt(0) 15; CI-NEXT: v_mov_b32_e32 v0, s0 16; CI-NEXT: v_mov_b32_e32 v1, s1 17; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2 18; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 19; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc 20; CI-NEXT: s_waitcnt vmcnt(0) 21; CI-NEXT: s_load_dword s0, s[4:5], 0x10 22; CI-NEXT: s_waitcnt lgkmcnt(0) 23; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 24; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc 25; CI-NEXT: flat_store_dword v[0:1], v0 26; CI-NEXT: s_endpgm 27; 28; GFX9-LABEL: is_local_vgpr: 29; GFX9: ; %bb.0: 30; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 31; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 32; GFX9-NEXT: s_waitcnt lgkmcnt(0) 33; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc 34; GFX9-NEXT: s_waitcnt vmcnt(0) 35; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 36; GFX9-NEXT: s_lshl_b32 s0, s0, 16 37; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 38; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc 39; GFX9-NEXT: global_store_dword v[0:1], v0, off 40; GFX9-NEXT: s_endpgm 41; 42; GFX10-LABEL: is_local_vgpr: 43; GFX10: ; %bb.0: 44; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 45; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 46; GFX10-NEXT: s_waitcnt lgkmcnt(0) 47; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc dlc 48; GFX10-NEXT: s_waitcnt vmcnt(0) 49; GFX10-NEXT: s_waitcnt_depctr 0xffe3 50; GFX10-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 51; GFX10-NEXT: s_lshl_b32 s0, s0, 16 52; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s0, v1 53; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo 54; GFX10-NEXT: global_store_dword v[0:1], v0, off 55; GFX10-NEXT: s_endpgm 56; 57; GFX11-LABEL: is_local_vgpr: 58; GFX11: ; %bb.0: 59; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 60; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 61; GFX11-NEXT: s_waitcnt lgkmcnt(0) 62; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] glc dlc 63; GFX11-NEXT: s_waitcnt vmcnt(0) 64; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 65; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) 66; GFX11-NEXT: s_lshl_b32 s0, s0, 16 67; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, s0, v1 68; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo 69; GFX11-NEXT: global_store_b32 v[0:1], v0, off 70; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 71; GFX11-NEXT: s_endpgm 72 %id = call i32 @llvm.amdgcn.workitem.id.x() 73 %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id 74 %ptr = load volatile i8*, i8* addrspace(1)* %gep 75 %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) 76 %ext = zext i1 %val to i32 77 store i32 %ext, i32 addrspace(1)* undef 78 ret void 79} 80 81define amdgpu_kernel void @is_local_sgpr(i8* %ptr) { 82; CI-LABEL: is_local_sgpr: 83; CI: ; %bb.0: 84; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 85; CI-NEXT: s_waitcnt lgkmcnt(0) 86; CI-NEXT: s_load_dword s0, s[4:5], 0x10 87; CI-NEXT: s_waitcnt lgkmcnt(0) 88; CI-NEXT: s_cmp_lg_u32 s1, s0 89; CI-NEXT: s_cbranch_scc1 .LBB1_2 90; CI-NEXT: ; %bb.1: ; %bb0 91; CI-NEXT: v_mov_b32_e32 v0, 0 92; CI-NEXT: flat_store_dword v[0:1], v0 93; CI-NEXT: s_waitcnt vmcnt(0) 94; CI-NEXT: .LBB1_2: ; %bb1 95; CI-NEXT: s_endpgm 96; 97; GFX9-LABEL: is_local_sgpr: 98; GFX9: ; %bb.0: 99; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 100; GFX9-NEXT: s_waitcnt lgkmcnt(0) 101; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 102; GFX9-NEXT: s_lshl_b32 s0, s0, 16 103; GFX9-NEXT: s_cmp_lg_u32 s1, s0 104; GFX9-NEXT: s_cbranch_scc1 .LBB1_2 105; GFX9-NEXT: ; %bb.1: ; %bb0 106; GFX9-NEXT: v_mov_b32_e32 v0, 0 107; GFX9-NEXT: global_store_dword v[0:1], v0, off 108; GFX9-NEXT: s_waitcnt vmcnt(0) 109; GFX9-NEXT: .LBB1_2: ; %bb1 110; GFX9-NEXT: s_endpgm 111; 112; GFX10-LABEL: is_local_sgpr: 113; GFX10: ; %bb.0: 114; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 115; GFX10-NEXT: s_waitcnt lgkmcnt(0) 116; GFX10-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 117; GFX10-NEXT: s_lshl_b32 s0, s0, 16 118; GFX10-NEXT: s_cmp_lg_u32 s1, s0 119; GFX10-NEXT: s_cbranch_scc1 .LBB1_2 120; GFX10-NEXT: ; %bb.1: ; %bb0 121; GFX10-NEXT: v_mov_b32_e32 v0, 0 122; GFX10-NEXT: global_store_dword v[0:1], v0, off 123; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 124; GFX10-NEXT: .LBB1_2: ; %bb1 125; GFX10-NEXT: s_endpgm 126; 127; GFX11-LABEL: is_local_sgpr: 128; GFX11: ; %bb.0: 129; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 130; GFX11-NEXT: s_waitcnt lgkmcnt(0) 131; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 132; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) 133; GFX11-NEXT: s_lshl_b32 s0, s0, 16 134; GFX11-NEXT: s_cmp_lg_u32 s1, s0 135; GFX11-NEXT: s_cbranch_scc1 .LBB1_2 136; GFX11-NEXT: ; %bb.1: ; %bb0 137; GFX11-NEXT: v_mov_b32_e32 v0, 0 138; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc 139; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 140; GFX11-NEXT: .LBB1_2: ; %bb1 141; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 142; GFX11-NEXT: s_endpgm 143 %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) 144 br i1 %val, label %bb0, label %bb1 145 146bb0: 147 store volatile i32 0, i32 addrspace(1)* undef 148 br label %bb1 149 150bb1: 151 ret void 152} 153 154declare i32 @llvm.amdgcn.workitem.id.x() #0 155declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0 156 157attributes #0 = { nounwind readnone speculatable } 158