1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
4
5define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
6; GFX9-LABEL: load_2darraymsaa_v4f32_xyzw:
7; GFX9:       ; %bb.0:
8; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
9; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
10; GFX9-NEXT:    v_and_or_b32 v0, v0, v4, v1
11; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v3
12; GFX9-NEXT:    s_mov_b32 s0, s2
13; GFX9-NEXT:    s_mov_b32 s1, s3
14; GFX9-NEXT:    s_mov_b32 s2, s4
15; GFX9-NEXT:    s_mov_b32 s3, s5
16; GFX9-NEXT:    s_mov_b32 s4, s6
17; GFX9-NEXT:    s_mov_b32 s5, s7
18; GFX9-NEXT:    s_mov_b32 s6, s8
19; GFX9-NEXT:    s_mov_b32 s7, s9
20; GFX9-NEXT:    v_and_or_b32 v1, v2, v4, v1
21; GFX9-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da
22; GFX9-NEXT:    s_waitcnt vmcnt(0)
23; GFX9-NEXT:    ; return to shader part epilog
24;
25; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw:
26; GFX10:       ; %bb.0:
27; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
28; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
29; GFX10-NEXT:    s_mov_b32 s0, s2
30; GFX10-NEXT:    s_mov_b32 s1, s3
31; GFX10-NEXT:    s_mov_b32 s2, s4
32; GFX10-NEXT:    v_and_or_b32 v0, 0xffff, v0, v1
33; GFX10-NEXT:    v_and_or_b32 v1, 0xffff, v2, v3
34; GFX10-NEXT:    s_mov_b32 s3, s5
35; GFX10-NEXT:    s_mov_b32 s4, s6
36; GFX10-NEXT:    s_mov_b32 s5, s7
37; GFX10-NEXT:    s_mov_b32 s6, s8
38; GFX10-NEXT:    s_mov_b32 s7, s9
39; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
40; GFX10-NEXT:    s_waitcnt vmcnt(0)
41; GFX10-NEXT:    ; return to shader part epilog
42  %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
43  ret <4 x float> %v
44}
45
46define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
47; GFX9-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
48; GFX9:       ; %bb.0:
49; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
50; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
51; GFX9-NEXT:    v_and_or_b32 v10, v0, v4, v1
52; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 16, v3
53; GFX9-NEXT:    v_mov_b32_e32 v5, 0
54; GFX9-NEXT:    v_and_or_b32 v11, v2, v4, v0
55; GFX9-NEXT:    v_mov_b32_e32 v6, v5
56; GFX9-NEXT:    v_mov_b32_e32 v7, v5
57; GFX9-NEXT:    v_mov_b32_e32 v8, v5
58; GFX9-NEXT:    v_mov_b32_e32 v9, v5
59; GFX9-NEXT:    v_mov_b32_e32 v0, v5
60; GFX9-NEXT:    s_mov_b32 s0, s2
61; GFX9-NEXT:    s_mov_b32 s1, s3
62; GFX9-NEXT:    s_mov_b32 s2, s4
63; GFX9-NEXT:    s_mov_b32 s3, s5
64; GFX9-NEXT:    s_mov_b32 s4, s6
65; GFX9-NEXT:    s_mov_b32 s5, s7
66; GFX9-NEXT:    s_mov_b32 s6, s8
67; GFX9-NEXT:    s_mov_b32 s7, s9
68; GFX9-NEXT:    v_mov_b32_e32 v1, v6
69; GFX9-NEXT:    v_mov_b32_e32 v2, v7
70; GFX9-NEXT:    v_mov_b32_e32 v3, v8
71; GFX9-NEXT:    v_mov_b32_e32 v4, v9
72; GFX9-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf unorm a16 tfe da
73; GFX9-NEXT:    s_waitcnt vmcnt(0)
74; GFX9-NEXT:    global_store_dword v5, v4, s[10:11]
75; GFX9-NEXT:    s_waitcnt vmcnt(0)
76; GFX9-NEXT:    ; return to shader part epilog
77;
78; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw_tfe:
79; GFX10:       ; %bb.0:
80; GFX10-NEXT:    v_mov_b32_e32 v5, 0
81; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
82; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
83; GFX10-NEXT:    s_mov_b32 s0, s2
84; GFX10-NEXT:    s_mov_b32 s1, s3
85; GFX10-NEXT:    v_mov_b32_e32 v6, v5
86; GFX10-NEXT:    v_mov_b32_e32 v7, v5
87; GFX10-NEXT:    v_mov_b32_e32 v8, v5
88; GFX10-NEXT:    v_mov_b32_e32 v9, v5
89; GFX10-NEXT:    v_and_or_b32 v10, 0xffff, v0, v1
90; GFX10-NEXT:    v_and_or_b32 v11, 0xffff, v2, v3
91; GFX10-NEXT:    s_mov_b32 s2, s4
92; GFX10-NEXT:    s_mov_b32 s3, s5
93; GFX10-NEXT:    s_mov_b32 s4, s6
94; GFX10-NEXT:    s_mov_b32 s5, s7
95; GFX10-NEXT:    s_mov_b32 s6, s8
96; GFX10-NEXT:    s_mov_b32 s7, s9
97; GFX10-NEXT:    v_mov_b32_e32 v0, v5
98; GFX10-NEXT:    v_mov_b32_e32 v1, v6
99; GFX10-NEXT:    v_mov_b32_e32 v2, v7
100; GFX10-NEXT:    v_mov_b32_e32 v3, v8
101; GFX10-NEXT:    v_mov_b32_e32 v4, v9
102; GFX10-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
103; GFX10-NEXT:    s_waitcnt vmcnt(0)
104; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
105; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
106; GFX10-NEXT:    ; return to shader part epilog
107  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 1, i32 0)
108  %v.vec = extractvalue { <4 x float>, i32 } %v, 0
109  %v.err = extractvalue { <4 x float>, i32 } %v, 1
110  store i32 %v.err, i32 addrspace(1)* %out, align 4
111  ret <4 x float> %v.vec
112}
113
114define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
115; GFX9-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
116; GFX9:       ; %bb.0:
117; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
118; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
119; GFX9-NEXT:    v_and_or_b32 v10, v0, v4, v1
120; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 16, v3
121; GFX9-NEXT:    v_mov_b32_e32 v5, 0
122; GFX9-NEXT:    v_and_or_b32 v11, v2, v4, v0
123; GFX9-NEXT:    v_mov_b32_e32 v6, v5
124; GFX9-NEXT:    v_mov_b32_e32 v7, v5
125; GFX9-NEXT:    v_mov_b32_e32 v8, v5
126; GFX9-NEXT:    v_mov_b32_e32 v9, v5
127; GFX9-NEXT:    v_mov_b32_e32 v0, v5
128; GFX9-NEXT:    s_mov_b32 s0, s2
129; GFX9-NEXT:    s_mov_b32 s1, s3
130; GFX9-NEXT:    s_mov_b32 s2, s4
131; GFX9-NEXT:    s_mov_b32 s3, s5
132; GFX9-NEXT:    s_mov_b32 s4, s6
133; GFX9-NEXT:    s_mov_b32 s5, s7
134; GFX9-NEXT:    s_mov_b32 s6, s8
135; GFX9-NEXT:    s_mov_b32 s7, s9
136; GFX9-NEXT:    v_mov_b32_e32 v1, v6
137; GFX9-NEXT:    v_mov_b32_e32 v2, v7
138; GFX9-NEXT:    v_mov_b32_e32 v3, v8
139; GFX9-NEXT:    v_mov_b32_e32 v4, v9
140; GFX9-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf unorm a16 tfe lwe da
141; GFX9-NEXT:    s_waitcnt vmcnt(0)
142; GFX9-NEXT:    global_store_dword v5, v4, s[10:11]
143; GFX9-NEXT:    s_waitcnt vmcnt(0)
144; GFX9-NEXT:    ; return to shader part epilog
145;
146; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe:
147; GFX10:       ; %bb.0:
148; GFX10-NEXT:    v_mov_b32_e32 v5, 0
149; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
150; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
151; GFX10-NEXT:    s_mov_b32 s0, s2
152; GFX10-NEXT:    s_mov_b32 s1, s3
153; GFX10-NEXT:    v_mov_b32_e32 v6, v5
154; GFX10-NEXT:    v_mov_b32_e32 v7, v5
155; GFX10-NEXT:    v_mov_b32_e32 v8, v5
156; GFX10-NEXT:    v_mov_b32_e32 v9, v5
157; GFX10-NEXT:    v_and_or_b32 v10, 0xffff, v0, v1
158; GFX10-NEXT:    v_and_or_b32 v11, 0xffff, v2, v3
159; GFX10-NEXT:    s_mov_b32 s2, s4
160; GFX10-NEXT:    s_mov_b32 s3, s5
161; GFX10-NEXT:    s_mov_b32 s4, s6
162; GFX10-NEXT:    s_mov_b32 s5, s7
163; GFX10-NEXT:    s_mov_b32 s6, s8
164; GFX10-NEXT:    s_mov_b32 s7, s9
165; GFX10-NEXT:    v_mov_b32_e32 v0, v5
166; GFX10-NEXT:    v_mov_b32_e32 v1, v6
167; GFX10-NEXT:    v_mov_b32_e32 v2, v7
168; GFX10-NEXT:    v_mov_b32_e32 v3, v8
169; GFX10-NEXT:    v_mov_b32_e32 v4, v9
170; GFX10-NEXT:    image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
171; GFX10-NEXT:    s_waitcnt vmcnt(0)
172; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
173; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
174; GFX10-NEXT:    ; return to shader part epilog
175  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 3, i32 0)
176  %v.vec = extractvalue { <4 x float>, i32 } %v, 0
177  %v.err = extractvalue { <4 x float>, i32 } %v, 1
178  store i32 %v.err, i32 addrspace(1)* %out, align 4
179  ret <4 x float> %v.vec
180}
181
182declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
183declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
184
185attributes #0 = { nounwind readonly }
186