1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s 4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s 5 6define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) { 7 ; GFX6-LABEL: name: load_2darraymsaa 8 ; GFX6: bb.1 (%ir-block.0): 9 ; GFX6: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 10 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 11 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 12 ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 13 ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 14 ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 15 ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 16 ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 17 ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 18 ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 19 ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 20 ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 21 ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2 22 ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3 23 ; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32) 24 ; GFX6: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<4 x s32>) from custom "ImageResource") 25 ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>) 26 ; GFX6: $vgpr0 = COPY [[UV]](s32) 27 ; GFX6: $vgpr1 = COPY [[UV1]](s32) 28 ; GFX6: $vgpr2 = COPY [[UV2]](s32) 29 ; GFX6: $vgpr3 = COPY [[UV3]](s32) 30 ; GFX6: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 31 ; GFX10NSA-LABEL: name: load_2darraymsaa 32 ; GFX10NSA: bb.1 (%ir-block.0): 33 ; GFX10NSA: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 34 ; GFX10NSA: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 35 ; GFX10NSA: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 36 ; GFX10NSA: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 37 ; GFX10NSA: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 38 ; GFX10NSA: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 39 ; GFX10NSA: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 40 ; GFX10NSA: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 41 ; GFX10NSA: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 42 ; GFX10NSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 43 ; GFX10NSA: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 44 ; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 45 ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2 46 ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3 47 ; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<4 x s32>) from custom "ImageResource") 48 ; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>) 49 ; GFX10NSA: $vgpr0 = COPY [[UV]](s32) 50 ; GFX10NSA: $vgpr1 = COPY [[UV1]](s32) 51 ; GFX10NSA: $vgpr2 = COPY [[UV2]](s32) 52 ; GFX10NSA: $vgpr3 = COPY [[UV3]](s32) 53 ; GFX10NSA: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 54 %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 55 ret <4 x float> %v 56} 57 58define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) { 59 ; GFX6-LABEL: name: load_2darraymsaa_tfe 60 ; GFX6: bb.1 (%ir-block.0): 61 ; GFX6: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 62 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 63 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 64 ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 65 ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 66 ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 67 ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 68 ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 69 ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 70 ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 71 ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 72 ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 73 ; GFX6: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32) 74 ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0 75 ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1 76 ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2 77 ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3 78 ; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32) 79 ; GFX6: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<4 x s32>) from custom "ImageResource") 80 ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>) 81 ; GFX6: G_STORE [[UV4]](s32), [[MV]](p1) :: (store (s32) into %ir.out, addrspace 1) 82 ; GFX6: $vgpr0 = COPY [[UV]](s32) 83 ; GFX6: $vgpr1 = COPY [[UV1]](s32) 84 ; GFX6: $vgpr2 = COPY [[UV2]](s32) 85 ; GFX6: $vgpr3 = COPY [[UV3]](s32) 86 ; GFX6: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 87 ; GFX10NSA-LABEL: name: load_2darraymsaa_tfe 88 ; GFX10NSA: bb.1 (%ir-block.0): 89 ; GFX10NSA: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 90 ; GFX10NSA: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 91 ; GFX10NSA: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 92 ; GFX10NSA: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 93 ; GFX10NSA: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 94 ; GFX10NSA: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 95 ; GFX10NSA: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 96 ; GFX10NSA: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 97 ; GFX10NSA: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 98 ; GFX10NSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 99 ; GFX10NSA: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 100 ; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 101 ; GFX10NSA: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32) 102 ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr0 103 ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr1 104 ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr2 105 ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr3 106 ; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<4 x s32>) from custom "ImageResource") 107 ; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>) 108 ; GFX10NSA: G_STORE [[UV4]](s32), [[MV]](p1) :: (store (s32) into %ir.out, addrspace 1) 109 ; GFX10NSA: $vgpr0 = COPY [[UV]](s32) 110 ; GFX10NSA: $vgpr1 = COPY [[UV1]](s32) 111 ; GFX10NSA: $vgpr2 = COPY [[UV2]](s32) 112 ; GFX10NSA: $vgpr3 = COPY [[UV3]](s32) 113 ; GFX10NSA: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 114 %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0) 115 %v.vec = extractvalue { <4 x float>, i32 } %v, 0 116 %v.err = extractvalue { <4 x float>, i32 } %v, 1 117 store i32 %v.err, i32 addrspace(1)* %out, align 4 118 ret <4 x float> %v.vec 119} 120 121declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 122declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 123 124attributes #0 = { nounwind readonly } 125