1; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED %s
2; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED %s
3; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED %s
4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED %s
5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s
6
7; GCN-LABEL: test_local_misaligned_v2:
8; GCN-DAG: ds_read2_b32
9; GCN-DAG: ds_write2_b32
10define amdgpu_kernel void @test_local_misaligned_v2(i32 addrspace(3)* %arg) {
11bb:
12  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
13  %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
14  %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)*
15  %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 4
16  %v1 = extractelement <2 x i32> %load, i32 0
17  %v2 = extractelement <2 x i32> %load, i32 1
18  %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
19  %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
20  store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 4
21  ret void
22}
23
24; GCN-LABEL: test_local_misaligned_v4:
25; ALIGNED-DAG: ds_read2_b32
26; ALIGNED-DAG: ds_read2_b32
27; ALIGNED-DAG: ds_write2_b32
28; ALIGNED-DAG: ds_write2_b32
29; UNALIGNED-DAG: ds_read2_b64
30; UNALIGNED-DAG: ds_write2_b64
31define amdgpu_kernel void @test_local_misaligned_v4(i32 addrspace(3)* %arg) {
32bb:
33  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
34  %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
35  %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)*
36  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4
37  %v1 = extractelement <4 x i32> %load, i32 0
38  %v2 = extractelement <4 x i32> %load, i32 1
39  %v3 = extractelement <4 x i32> %load, i32 2
40  %v4 = extractelement <4 x i32> %load, i32 3
41  %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
42  %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
43  %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
44  %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
45  store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 4
46  ret void
47}
48
49; GCN-LABEL: test_local_misaligned_v3:
50; ALIGNED-DAG: ds_read2_b32
51; ALIGNED-DAG: ds_read_b32
52; ALIGNED-DAG: ds_write2_b32
53; ALIGNED-DAG: ds_write_b32
54; UNALIGNED-DAG: ds_read_b96
55; UNALIGNED-DAG: ds_write_b96
56define amdgpu_kernel void @test_local_misaligned_v3(i32 addrspace(3)* %arg) {
57bb:
58  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
59  %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
60  %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)*
61  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4
62  %v1 = extractelement <3 x i32> %load, i32 0
63  %v2 = extractelement <3 x i32> %load, i32 1
64  %v3 = extractelement <3 x i32> %load, i32 2
65  %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
66  %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
67  %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
68  store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 4
69  ret void
70}
71
72; GCN-LABEL: test_local_aligned_v2:
73; GCN-DAG: ds_read_b64
74; GCN-DAG: ds_write_b64
75define amdgpu_kernel void @test_local_aligned_v2(i32 addrspace(3)* %arg) {
76bb:
77  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
78  %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
79  %ptr = bitcast i32 addrspace(3)* %gep to <2 x i32> addrspace(3)*
80  %load = load <2 x i32>, <2 x i32> addrspace(3)* %ptr, align 8
81  %v1 = extractelement <2 x i32> %load, i32 0
82  %v2 = extractelement <2 x i32> %load, i32 1
83  %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
84  %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
85  store <2 x i32> %v4, <2 x i32> addrspace(3)* %ptr, align 8
86  ret void
87}
88
89; GCN-LABEL: test_local_aligned_v3:
90; GCN-DAG: ds_read_b96
91; GCN-DAG: ds_write_b96
92define amdgpu_kernel void @test_local_aligned_v3(i32 addrspace(3)* %arg) {
93bb:
94  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
95  %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
96  %ptr = bitcast i32 addrspace(3)* %gep to <3 x i32> addrspace(3)*
97  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16
98  %v1 = extractelement <3 x i32> %load, i32 0
99  %v2 = extractelement <3 x i32> %load, i32 1
100  %v3 = extractelement <3 x i32> %load, i32 2
101  %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
102  %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
103  %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
104  store <3 x i32> %v7, <3 x i32> addrspace(3)* %ptr, align 16
105  ret void
106}
107
108; GCN-LABEL: test_local_v4_aligned8:
109; ALIGNED-DAG: ds_read2_b64
110; ALIGNED-DAG: ds_write2_b64
111; UNALIGNED-DAG: ds_read2_b64
112; UNALIGNED-DAG: ds_write2_b64
113define amdgpu_kernel void @test_local_v4_aligned8(i32 addrspace(3)* %arg) {
114bb:
115  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
116  %gep = getelementptr inbounds i32, i32 addrspace(3)* %arg, i32 %lid
117  %ptr = bitcast i32 addrspace(3)* %gep to <4 x i32> addrspace(3)*
118  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8
119  %v1 = extractelement <4 x i32> %load, i32 0
120  %v2 = extractelement <4 x i32> %load, i32 1
121  %v3 = extractelement <4 x i32> %load, i32 2
122  %v4 = extractelement <4 x i32> %load, i32 3
123  %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
124  %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
125  %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
126  %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
127  store <4 x i32> %v8, <4 x i32> addrspace(3)* %ptr, align 8
128  ret void
129}
130
131declare i32 @llvm.amdgcn.workitem.id.x()
132