1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; REQUIRES: global-isel 3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -O0 -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator -global-isel %s -o - | FileCheck -check-prefix=HSA-VI %s 4 5define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { 6 ; HSA-VI-LABEL: name: i8_arg 7 ; HSA-VI: bb.1 (%ir-block.0): 8 ; HSA-VI: liveins: $sgpr4_sgpr5 9 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 10 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 11 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 12 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 13 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 14 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 15 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 8, addrspace 4) 16 ; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8) 17 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 18 ; HSA-VI: S_ENDPGM 19 %ext = zext i8 %in to i32 20 store i32 %ext, i32 addrspace(1)* %out, align 4 21 ret void 22} 23 24define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { 25 ; HSA-VI-LABEL: name: i8_zext_arg 26 ; HSA-VI: bb.1 (%ir-block.0): 27 ; HSA-VI: liveins: $sgpr4_sgpr5 28 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 29 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 30 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 31 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 32 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 33 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 34 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 8, addrspace 4) 35 ; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8) 36 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 37 ; HSA-VI: S_ENDPGM 38 %ext = zext i8 %in to i32 39 store i32 %ext, i32 addrspace(1)* %out, align 4 40 ret void 41} 42 43define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { 44 ; HSA-VI-LABEL: name: i8_sext_arg 45 ; HSA-VI: bb.1 (%ir-block.0): 46 ; HSA-VI: liveins: $sgpr4_sgpr5 47 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 48 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 49 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 50 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 51 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 52 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 53 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 8, addrspace 4) 54 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8) 55 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 56 ; HSA-VI: S_ENDPGM 57 %ext = sext i8 %in to i32 58 store i32 %ext, i32 addrspace(1)* %out, align 4 59 ret void 60} 61 62define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { 63 ; HSA-VI-LABEL: name: i16_arg 64 ; HSA-VI: bb.1 (%ir-block.0): 65 ; HSA-VI: liveins: $sgpr4_sgpr5 66 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 67 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 68 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 69 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 70 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 71 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 72 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 2 from `i16 addrspace(4)* undef`, align 8, addrspace 4) 73 ; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16) 74 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 75 ; HSA-VI: S_ENDPGM 76 %ext = zext i16 %in to i32 77 store i32 %ext, i32 addrspace(1)* %out, align 4 78 ret void 79} 80 81define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { 82 ; HSA-VI-LABEL: name: i16_zext_arg 83 ; HSA-VI: bb.1 (%ir-block.0): 84 ; HSA-VI: liveins: $sgpr4_sgpr5 85 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 86 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 87 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 88 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 89 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 90 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 91 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 2 from `i16 addrspace(4)* undef`, align 8, addrspace 4) 92 ; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16) 93 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 94 ; HSA-VI: S_ENDPGM 95 %ext = zext i16 %in to i32 96 store i32 %ext, i32 addrspace(1)* %out, align 4 97 ret void 98} 99 100define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { 101 ; HSA-VI-LABEL: name: i16_sext_arg 102 ; HSA-VI: bb.1 (%ir-block.0): 103 ; HSA-VI: liveins: $sgpr4_sgpr5 104 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 105 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 106 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 107 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 108 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 109 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 110 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 2 from `i16 addrspace(4)* undef`, align 8, addrspace 4) 111 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s16) 112 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 113 ; HSA-VI: S_ENDPGM 114 %ext = sext i16 %in to i32 115 store i32 %ext, i32 addrspace(1)* %out, align 4 116 ret void 117} 118 119define amdgpu_kernel void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind { 120 ; HSA-VI-LABEL: name: i32_arg 121 ; HSA-VI: bb.1.entry: 122 ; HSA-VI: liveins: $sgpr4_sgpr5 123 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 124 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 125 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 126 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 127 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 128 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 129 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 4 from `i32 addrspace(4)* undef`, align 8, addrspace 4) 130 ; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 131 ; HSA-VI: S_ENDPGM 132entry: 133 store i32 %in, i32 addrspace(1)* %out, align 4 134 ret void 135} 136 137define amdgpu_kernel void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind { 138 ; HSA-VI-LABEL: name: f32_arg 139 ; HSA-VI: bb.1.entry: 140 ; HSA-VI: liveins: $sgpr4_sgpr5 141 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 142 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 143 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 144 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `float addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 145 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 146 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 147 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 4 from `float addrspace(4)* undef`, align 8, addrspace 4) 148 ; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 149 ; HSA-VI: S_ENDPGM 150entry: 151 store float %in, float addrspace(1)* %out, align 4 152 ret void 153} 154 155define amdgpu_kernel void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) { 156 ; HSA-VI-LABEL: name: v2i8_arg 157 ; HSA-VI: bb.1.entry: 158 ; HSA-VI: liveins: $sgpr4_sgpr5 159 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 160 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 161 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 162 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<2 x i8> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 163 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 164 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 165 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 2 from `<2 x i8> addrspace(4)* undef`, align 8, addrspace 4) 166 ; HSA-VI: G_STORE [[LOAD1]](<2 x s8>), [[LOAD]](p1) :: (store 2 into %ir.out, addrspace 1) 167 ; HSA-VI: S_ENDPGM 168entry: 169 store <2 x i8> %in, <2 x i8> addrspace(1)* %out 170 ret void 171} 172 173define amdgpu_kernel void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) { 174 ; HSA-VI-LABEL: name: v2i16_arg 175 ; HSA-VI: bb.1.entry: 176 ; HSA-VI: liveins: $sgpr4_sgpr5 177 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 178 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 179 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 180 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<2 x i16> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 181 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 182 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 183 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 4 from `<2 x i16> addrspace(4)* undef`, align 8, addrspace 4) 184 ; HSA-VI: G_STORE [[LOAD1]](<2 x s16>), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 185 ; HSA-VI: S_ENDPGM 186entry: 187 store <2 x i16> %in, <2 x i16> addrspace(1)* %out 188 ret void 189} 190 191define amdgpu_kernel void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind { 192 ; HSA-VI-LABEL: name: v2i32_arg 193 ; HSA-VI: bb.1.entry: 194 ; HSA-VI: liveins: $sgpr4_sgpr5 195 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 196 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 197 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 198 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<2 x i32> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 199 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 200 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 201 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 8 from `<2 x i32> addrspace(4)* undef`, addrspace 4) 202 ; HSA-VI: G_STORE [[LOAD1]](<2 x s32>), [[LOAD]](p1) :: (store 8 into %ir.out, align 4, addrspace 1) 203 ; HSA-VI: S_ENDPGM 204entry: 205 store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4 206 ret void 207} 208 209define amdgpu_kernel void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind { 210 ; HSA-VI-LABEL: name: v2f32_arg 211 ; HSA-VI: bb.1.entry: 212 ; HSA-VI: liveins: $sgpr4_sgpr5 213 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 214 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 215 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 216 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<2 x float> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 217 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 218 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 219 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 8 from `<2 x float> addrspace(4)* undef`, addrspace 4) 220 ; HSA-VI: G_STORE [[LOAD1]](<2 x s32>), [[LOAD]](p1) :: (store 8 into %ir.out, align 4, addrspace 1) 221 ; HSA-VI: S_ENDPGM 222entry: 223 store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4 224 ret void 225} 226 227define amdgpu_kernel void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind { 228 ; HSA-VI-LABEL: name: v3i8_arg 229 ; HSA-VI: bb.1.entry: 230 ; HSA-VI: liveins: $sgpr4_sgpr5 231 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 232 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 233 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 234 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<3 x i8> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 235 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 236 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 237 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s8>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 3 from `<3 x i8> addrspace(4)* undef`, align 8, addrspace 4) 238 ; HSA-VI: G_STORE [[LOAD1]](<3 x s8>), [[LOAD]](p1) :: (store 3 into %ir.out, align 4, addrspace 1) 239 ; HSA-VI: S_ENDPGM 240entry: 241 store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4 242 ret void 243} 244 245define amdgpu_kernel void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind { 246 ; HSA-VI-LABEL: name: v3i16_arg 247 ; HSA-VI: bb.1.entry: 248 ; HSA-VI: liveins: $sgpr4_sgpr5 249 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 250 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 251 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 252 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<3 x i16> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 253 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 254 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 255 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 6 from `<3 x i16> addrspace(4)* undef`, align 8, addrspace 4) 256 ; HSA-VI: G_STORE [[LOAD1]](<3 x s16>), [[LOAD]](p1) :: (store 6 into %ir.out, align 4, addrspace 1) 257 ; HSA-VI: S_ENDPGM 258entry: 259 store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4 260 ret void 261} 262 263define amdgpu_kernel void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind { 264 ; HSA-VI-LABEL: name: v3i32_arg 265 ; HSA-VI: bb.1.entry: 266 ; HSA-VI: liveins: $sgpr4_sgpr5 267 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 268 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 269 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 270 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<3 x i32> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 271 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 272 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 273 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 12 from `<3 x i32> addrspace(4)* undef`, align 16, addrspace 4) 274 ; HSA-VI: G_STORE [[LOAD1]](<3 x s32>), [[LOAD]](p1) :: (store 12 into %ir.out, align 4, addrspace 1) 275 ; HSA-VI: S_ENDPGM 276entry: 277 store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4 278 ret void 279} 280 281define amdgpu_kernel void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind { 282 ; HSA-VI-LABEL: name: v3f32_arg 283 ; HSA-VI: bb.1.entry: 284 ; HSA-VI: liveins: $sgpr4_sgpr5 285 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 286 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 287 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 288 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<3 x float> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 289 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 290 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 291 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 12 from `<3 x float> addrspace(4)* undef`, align 16, addrspace 4) 292 ; HSA-VI: G_STORE [[LOAD1]](<3 x s32>), [[LOAD]](p1) :: (store 12 into %ir.out, align 4, addrspace 1) 293 ; HSA-VI: S_ENDPGM 294entry: 295 store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4 296 ret void 297} 298 299define amdgpu_kernel void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) { 300 ; HSA-VI-LABEL: name: v4i8_arg 301 ; HSA-VI: bb.1.entry: 302 ; HSA-VI: liveins: $sgpr4_sgpr5 303 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 304 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 305 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 306 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<4 x i8> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 307 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 308 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 309 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 4 from `<4 x i8> addrspace(4)* undef`, align 8, addrspace 4) 310 ; HSA-VI: G_STORE [[LOAD1]](<4 x s8>), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 311 ; HSA-VI: S_ENDPGM 312entry: 313 store <4 x i8> %in, <4 x i8> addrspace(1)* %out 314 ret void 315} 316 317define amdgpu_kernel void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) { 318 ; HSA-VI-LABEL: name: v4i16_arg 319 ; HSA-VI: bb.1.entry: 320 ; HSA-VI: liveins: $sgpr4_sgpr5 321 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 322 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 323 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 324 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<4 x i16> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 325 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 326 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 327 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 8 from `<4 x i16> addrspace(4)* undef`, addrspace 4) 328 ; HSA-VI: G_STORE [[LOAD1]](<4 x s16>), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1) 329 ; HSA-VI: S_ENDPGM 330entry: 331 store <4 x i16> %in, <4 x i16> addrspace(1)* %out 332 ret void 333} 334 335define amdgpu_kernel void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind { 336 ; HSA-VI-LABEL: name: v4i32_arg 337 ; HSA-VI: bb.1.entry: 338 ; HSA-VI: liveins: $sgpr4_sgpr5 339 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 340 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 341 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 342 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<4 x i32> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 343 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 344 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 345 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 16 from `<4 x i32> addrspace(4)* undef`, addrspace 4) 346 ; HSA-VI: G_STORE [[LOAD1]](<4 x s32>), [[LOAD]](p1) :: (store 16 into %ir.out, align 4, addrspace 1) 347 ; HSA-VI: S_ENDPGM 348entry: 349 store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 350 ret void 351} 352 353define amdgpu_kernel void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind { 354 ; HSA-VI-LABEL: name: v4f32_arg 355 ; HSA-VI: bb.1.entry: 356 ; HSA-VI: liveins: $sgpr4_sgpr5 357 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 358 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 359 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 360 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<4 x float> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 361 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 362 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 363 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 16 from `<4 x float> addrspace(4)* undef`, addrspace 4) 364 ; HSA-VI: G_STORE [[LOAD1]](<4 x s32>), [[LOAD]](p1) :: (store 16 into %ir.out, align 4, addrspace 1) 365 ; HSA-VI: S_ENDPGM 366entry: 367 store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4 368 ret void 369} 370 371define amdgpu_kernel void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) { 372 ; HSA-VI-LABEL: name: v8i8_arg 373 ; HSA-VI: bb.1.entry: 374 ; HSA-VI: liveins: $sgpr4_sgpr5 375 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 376 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 377 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 378 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<8 x i8> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 379 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 380 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 381 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 8 from `<8 x i8> addrspace(4)* undef`, addrspace 4) 382 ; HSA-VI: G_STORE [[LOAD1]](<8 x s8>), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1) 383 ; HSA-VI: S_ENDPGM 384entry: 385 store <8 x i8> %in, <8 x i8> addrspace(1)* %out 386 ret void 387} 388 389define amdgpu_kernel void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) { 390 ; HSA-VI-LABEL: name: v8i16_arg 391 ; HSA-VI: bb.1.entry: 392 ; HSA-VI: liveins: $sgpr4_sgpr5 393 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 394 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 395 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 396 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<8 x i16> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 397 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 398 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 399 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 16 from `<8 x i16> addrspace(4)* undef`, addrspace 4) 400 ; HSA-VI: G_STORE [[LOAD1]](<8 x s16>), [[LOAD]](p1) :: (store 16 into %ir.out, addrspace 1) 401 ; HSA-VI: S_ENDPGM 402entry: 403 store <8 x i16> %in, <8 x i16> addrspace(1)* %out 404 ret void 405} 406 407define amdgpu_kernel void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind { 408 ; HSA-VI-LABEL: name: v8i32_arg 409 ; HSA-VI: bb.1.entry: 410 ; HSA-VI: liveins: $sgpr4_sgpr5 411 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 412 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 413 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 414 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<8 x i32> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 415 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 416 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 417 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 32 from `<8 x i32> addrspace(4)* undef`, align 16, addrspace 4) 418 ; HSA-VI: G_STORE [[LOAD1]](<8 x s32>), [[LOAD]](p1) :: (store 32 into %ir.out, align 4, addrspace 1) 419 ; HSA-VI: S_ENDPGM 420entry: 421 store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4 422 ret void 423} 424 425define amdgpu_kernel void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { 426 ; HSA-VI-LABEL: name: v8f32_arg 427 ; HSA-VI: bb.1.entry: 428 ; HSA-VI: liveins: $sgpr4_sgpr5 429 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 430 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 431 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 432 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<8 x float> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 433 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 434 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 435 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 32 from `<8 x float> addrspace(4)* undef`, align 16, addrspace 4) 436 ; HSA-VI: G_STORE [[LOAD1]](<8 x s32>), [[LOAD]](p1) :: (store 32 into %ir.out, align 4, addrspace 1) 437 ; HSA-VI: S_ENDPGM 438entry: 439 store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4 440 ret void 441} 442 443define amdgpu_kernel void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) { 444 ; HSA-VI-LABEL: name: v16i8_arg 445 ; HSA-VI: bb.1.entry: 446 ; HSA-VI: liveins: $sgpr4_sgpr5 447 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 448 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 449 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 450 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<16 x i8> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 451 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 452 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 453 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 16 from `<16 x i8> addrspace(4)* undef`, addrspace 4) 454 ; HSA-VI: G_STORE [[LOAD1]](<16 x s8>), [[LOAD]](p1) :: (store 16 into %ir.out, addrspace 1) 455 ; HSA-VI: S_ENDPGM 456entry: 457 store <16 x i8> %in, <16 x i8> addrspace(1)* %out 458 ret void 459} 460 461define amdgpu_kernel void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) { 462 ; HSA-VI-LABEL: name: v16i16_arg 463 ; HSA-VI: bb.1.entry: 464 ; HSA-VI: liveins: $sgpr4_sgpr5 465 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 466 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 467 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 468 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<16 x i16> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 469 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 470 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 471 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s16>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 32 from `<16 x i16> addrspace(4)* undef`, align 16, addrspace 4) 472 ; HSA-VI: G_STORE [[LOAD1]](<16 x s16>), [[LOAD]](p1) :: (store 32 into %ir.out, addrspace 1) 473 ; HSA-VI: S_ENDPGM 474entry: 475 store <16 x i16> %in, <16 x i16> addrspace(1)* %out 476 ret void 477} 478 479define amdgpu_kernel void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind { 480 ; HSA-VI-LABEL: name: v16i32_arg 481 ; HSA-VI: bb.1.entry: 482 ; HSA-VI: liveins: $sgpr4_sgpr5 483 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 484 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 485 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 486 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<16 x i32> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 487 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 488 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 489 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 64 from `<16 x i32> addrspace(4)* undef`, align 16, addrspace 4) 490 ; HSA-VI: G_STORE [[LOAD1]](<16 x s32>), [[LOAD]](p1) :: (store 64 into %ir.out, align 4, addrspace 1) 491 ; HSA-VI: S_ENDPGM 492entry: 493 store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4 494 ret void 495} 496 497define amdgpu_kernel void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind { 498 ; HSA-VI-LABEL: name: v16f32_arg 499 ; HSA-VI: bb.1.entry: 500 ; HSA-VI: liveins: $sgpr4_sgpr5 501 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 502 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 503 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 504 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `<16 x float> addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 505 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 506 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 507 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 64 from `<16 x float> addrspace(4)* undef`, align 16, addrspace 4) 508 ; HSA-VI: G_STORE [[LOAD1]](<16 x s32>), [[LOAD]](p1) :: (store 64 into %ir.out, align 4, addrspace 1) 509 ; HSA-VI: S_ENDPGM 510entry: 511 store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4 512 ret void 513} 514 515define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind { 516 ; HSA-VI-LABEL: name: kernel_arg_i64 517 ; HSA-VI: bb.1 (%ir-block.0): 518 ; HSA-VI: liveins: $sgpr4_sgpr5 519 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 520 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 521 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 522 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i64 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 523 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 524 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 525 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 8 from `i64 addrspace(4)* undef`, addrspace 4) 526 ; HSA-VI: G_STORE [[LOAD1]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1) 527 ; HSA-VI: S_ENDPGM 528 store i64 %a, i64 addrspace(1)* %out, align 8 529 ret void 530} 531 532define amdgpu_kernel void @f64_kernel_arg(double addrspace(1)* %out, double %in) { 533 ; HSA-VI-LABEL: name: f64_kernel_arg 534 ; HSA-VI: bb.1.entry: 535 ; HSA-VI: liveins: $sgpr4_sgpr5 536 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 537 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 538 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 539 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `double addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 540 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 541 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 542 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 8 from `double addrspace(4)* undef`, addrspace 4) 543 ; HSA-VI: G_STORE [[LOAD1]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1) 544 ; HSA-VI: S_ENDPGM 545entry: 546 store double %in, double addrspace(1)* %out 547 ret void 548} 549 550define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { 551 ; HSA-VI-LABEL: name: i1_arg 552 ; HSA-VI: bb.1 (%ir-block.0): 553 ; HSA-VI: liveins: $sgpr4_sgpr5 554 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 555 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 556 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 557 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i1 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 558 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 559 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 560 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i1 addrspace(4)* undef`, align 8, addrspace 4) 561 ; HSA-VI: G_STORE [[LOAD1]](s1), [[LOAD]](p1) :: (store 1 into %ir.out, addrspace 1) 562 ; HSA-VI: S_ENDPGM 563 store i1 %x, i1 addrspace(1)* %out, align 1 564 ret void 565} 566 567define amdgpu_kernel void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { 568 ; HSA-VI-LABEL: name: i1_arg_zext_i32 569 ; HSA-VI: bb.1 (%ir-block.0): 570 ; HSA-VI: liveins: $sgpr4_sgpr5 571 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 572 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 573 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 574 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 575 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 576 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 577 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i1 addrspace(4)* undef`, align 8, addrspace 4) 578 ; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s1) 579 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 580 ; HSA-VI: S_ENDPGM 581 %ext = zext i1 %x to i32 582 store i32 %ext, i32 addrspace(1)* %out, align 4 583 ret void 584} 585 586define amdgpu_kernel void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { 587 ; HSA-VI-LABEL: name: i1_arg_zext_i64 588 ; HSA-VI: bb.1 (%ir-block.0): 589 ; HSA-VI: liveins: $sgpr4_sgpr5 590 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 591 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 592 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 593 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i64 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 594 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 595 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 596 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i1 addrspace(4)* undef`, align 8, addrspace 4) 597 ; HSA-VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD1]](s1) 598 ; HSA-VI: G_STORE [[ZEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1) 599 ; HSA-VI: S_ENDPGM 600 %ext = zext i1 %x to i64 601 store i64 %ext, i64 addrspace(1)* %out, align 8 602 ret void 603} 604 605define amdgpu_kernel void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { 606 ; HSA-VI-LABEL: name: i1_arg_sext_i32 607 ; HSA-VI: bb.1 (%ir-block.0): 608 ; HSA-VI: liveins: $sgpr4_sgpr5 609 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 610 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 611 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 612 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i32 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 613 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 614 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 615 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i1 addrspace(4)* undef`, align 8, addrspace 4) 616 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s1) 617 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1) 618 ; HSA-VI: S_ENDPGM 619 %ext = sext i1 %x to i32 620 store i32 %ext, i32addrspace(1)* %out, align 4 621 ret void 622} 623 624define amdgpu_kernel void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { 625 ; HSA-VI-LABEL: name: i1_arg_sext_i64 626 ; HSA-VI: bb.1 (%ir-block.0): 627 ; HSA-VI: liveins: $sgpr4_sgpr5 628 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 629 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 630 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 631 ; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i64 addrspace(1)* addrspace(4)* undef`, align 16, addrspace 4) 632 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 633 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 634 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i1 addrspace(4)* undef`, align 8, addrspace 4) 635 ; HSA-VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD1]](s1) 636 ; HSA-VI: G_STORE [[SEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1) 637 ; HSA-VI: S_ENDPGM 638 %ext = sext i1 %x to i64 639 store i64 %ext, i64 addrspace(1)* %out, align 8 640 ret void 641} 642 643define amdgpu_kernel void @empty_struct_arg({} %in) nounwind { 644 ; HSA-VI-LABEL: name: empty_struct_arg 645 ; HSA-VI: bb.1 (%ir-block.0): 646 ; HSA-VI: liveins: $sgpr4_sgpr5 647 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 648 ; HSA-VI: S_ENDPGM 649 ret void 650} 651 652; The correct load offsets for these: 653; load 4 from 0, 654; load 8 from 8 655; load 4 from 24 656; load 8 from 32 657 658; With the SelectionDAG argument lowering, the alignments for the 659; struct members is not properly considered, making these wrong. 660 661; FIXME: GlobalISel extractvalue emission broken 662 663define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) { 664 ; %val0 = extractvalue {i32, i64} %arg0, 0 665 ; %val1 = extractvalue {i32, i64} %arg0, 1 666 ; %val2 = extractvalue {i32, i64} %arg1, 0 667 ; %val3 = extractvalue {i32, i64} %arg1, 1 668 ; store volatile i32 %val0, i32 addrspace(1)* null 669 ; store volatile i64 %val1, i64 addrspace(1)* null 670 ; store volatile i32 %val2, i32 addrspace(1)* null 671 ; store volatile i64 %val3, i64 addrspace(1)* null 672 ; HSA-VI-LABEL: name: struct_argument_alignment 673 ; HSA-VI: bb.1 (%ir-block.1): 674 ; HSA-VI: liveins: $sgpr4_sgpr5 675 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 676 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 677 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 678 ; HSA-VI: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 16 from `{ i32, i64 } addrspace(4)* undef`, addrspace 4) 679 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 680 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 681 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 16, addrspace 4) 682 ; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 683 ; HSA-VI: [[GEP2:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C2]](s64) 684 ; HSA-VI: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[GEP2]](p4) :: (non-temporal invariant load 16 from `{ i32, i64 } addrspace(4)* undef`, align 8, addrspace 4) 685 ; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s128), 0 686 ; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s128), 64 687 ; HSA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD2]](s128), 0 688 ; HSA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD2]](s128), 64 689 ; HSA-VI: S_ENDPGM 690 ret void 691} 692 693; No padding between i8 and next struct, but round up at end to 4 byte 694; multiple. 695define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) { 696 ; %val0 = extractvalue <{i32, i64}> %arg0, 0 697 ; %val1 = extractvalue <{i32, i64}> %arg0, 1 698 ; %val2 = extractvalue <{i32, i64}> %arg1, 0 699 ; %val3 = extractvalue <{i32, i64}> %arg1, 1 700 ; store volatile i32 %val0, i32 addrspace(1)* null 701 ; store volatile i64 %val1, i64 addrspace(1)* null 702 ; store volatile i32 %val2, i32 addrspace(1)* null 703 ; store volatile i64 %val3, i64 addrspace(1)* null 704 ; HSA-VI-LABEL: name: packed_struct_argument_alignment 705 ; HSA-VI: bb.1 (%ir-block.1): 706 ; HSA-VI: liveins: $sgpr4_sgpr5 707 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 708 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 709 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64) 710 ; HSA-VI: [[LOAD:%[0-9]+]]:_(s96) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 12 from `<{ i32, i64 }> addrspace(4)* undef`, align 16, addrspace 4) 711 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 712 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64) 713 ; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p4) :: (non-temporal invariant load 1 from `i8 addrspace(4)* undef`, align 4, addrspace 4) 714 ; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 13 715 ; HSA-VI: [[GEP2:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C2]](s64) 716 ; HSA-VI: [[LOAD2:%[0-9]+]]:_(s96) = G_LOAD [[GEP2]](p4) :: (non-temporal invariant load 12 from `<{ i32, i64 }> addrspace(4)* undef`, align 1, addrspace 4) 717 ; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s96), 0 718 ; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s96), 32 719 ; HSA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD2]](s96), 0 720 ; HSA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD2]](s96), 32 721 ; HSA-VI: S_ENDPGM 722 ret void 723} 724