1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck %s
3
4---
5name:  ptrmask_p3_s32_sgpr_sgpr_sgpr
6legalized:       true
7regBankSelected: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12
13    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_sgpr
14    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
15    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
16    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
17    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
18    %0:sgpr(p3) = COPY $sgpr0
19    %1:sgpr(s32) = COPY $sgpr1
20    %2:sgpr(p3) = G_PTRMASK %0, %1
21    S_ENDPGM 0, implicit %2
22
23...
24
25---
26name:  ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
27legalized:       true
28regBankSelected: true
29
30body: |
31  bb.0:
32    liveins: $sgpr0
33
34    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
35    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
36    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -252645136
37    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
38    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
39    %0:sgpr(p3) = COPY $sgpr0
40    %const:sgpr(s32) = G_CONSTANT i32 -252645136
41    %1:sgpr(p3) = G_PTRMASK %0, %const
42    S_ENDPGM 0, implicit %1
43
44...
45
46---
47name:  ptrmask_p3_s32_sgpr_sgpr_0xffffffff
48legalized:       true
49regBankSelected: true
50
51body: |
52  bb.0:
53    liveins: $sgpr0
54
55    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xffffffff
56    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
57    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -1
58    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
59    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
60    %0:sgpr(p3) = COPY $sgpr0
61    %const:sgpr(s32) = G_CONSTANT i32 -1
62    %1:sgpr(p3) = G_PTRMASK %0, %const
63    S_ENDPGM 0, implicit %1
64
65...
66
67---
68name:  ptrmask_p3_s32_sgpr_sgpr_0x00000000
69legalized:       true
70regBankSelected: true
71
72body: |
73  bb.0:
74    liveins: $sgpr0
75
76    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0x00000000
77    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
78    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 0
79    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
80    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
81    %0:sgpr(p3) = COPY $sgpr0
82    %const:sgpr(s32) = G_CONSTANT i32 0
83    %1:sgpr(p3) = G_PTRMASK %0, %const
84    S_ENDPGM 0, implicit %1
85
86...
87
88---
89name:  ptrmask_p3_s32_sgpr_sgpr_clearhi1
90legalized:       true
91regBankSelected: true
92
93body: |
94  bb.0:
95    liveins: $sgpr0
96
97    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi1
98    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
99    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -2147483648
100    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
101    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
102    %0:sgpr(p3) = COPY $sgpr0
103    %const:sgpr(s32) = G_CONSTANT i32  -2147483648
104    %1:sgpr(p3) = G_PTRMASK %0, %const
105    S_ENDPGM 0, implicit %1
106
107...
108
109---
110name:  ptrmask_p3_s32_sgpr_sgpr_clearhi2
111legalized:       true
112regBankSelected: true
113
114body: |
115  bb.0:
116    liveins: $sgpr0
117
118    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi2
119    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
120    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -1073741824
121    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
122    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
123    %0:sgpr(p3) = COPY $sgpr0
124    %const:sgpr(s32) = G_CONSTANT i32  -1073741824
125    %1:sgpr(p3) = G_PTRMASK %0, %const
126    S_ENDPGM 0, implicit %1
127
128...
129
130---
131name:  ptrmask_p3_s32_sgpr_sgpr_clearlo1
132legalized:       true
133regBankSelected: true
134
135body: |
136  bb.0:
137    liveins: $sgpr0
138
139    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo1
140    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
141    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -2
142    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
143    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
144    %0:sgpr(p3) = COPY $sgpr0
145    %const:sgpr(s32) = G_CONSTANT i32 -2
146    %1:sgpr(p3) = G_PTRMASK %0, %const
147    S_ENDPGM 0, implicit %1
148
149...
150
151---
152name:  ptrmask_p3_s32_sgpr_sgpr_clearlo2
153legalized:       true
154regBankSelected: true
155
156body: |
157  bb.0:
158    liveins: $sgpr0
159
160    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo2
161    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
162    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -4
163    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
164    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
165    %0:sgpr(p3) = COPY $sgpr0
166    %const:sgpr(s32) = G_CONSTANT i32 -4
167    %1:sgpr(p3) = G_PTRMASK %0, %const
168    S_ENDPGM 0, implicit %1
169
170...
171
172---
173name:  ptrmask_p3_s32_sgpr_sgpr_clearlo3
174legalized:       true
175regBankSelected: true
176
177body: |
178  bb.0:
179    liveins: $sgpr0
180
181    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo3
182    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
183    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -8
184    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
185    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
186    %0:sgpr(p3) = COPY $sgpr0
187    %const:sgpr(s32) = G_CONSTANT i32 -8
188    %1:sgpr(p3) = G_PTRMASK %0, %const
189    S_ENDPGM 0, implicit %1
190
191...
192
193---
194name:  ptrmask_p3_s32_sgpr_sgpr_clearlo4
195legalized:       true
196regBankSelected: true
197
198body: |
199  bb.0:
200    liveins: $sgpr0
201
202    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo4
203    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
204    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -16
205    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
206    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
207    %0:sgpr(p3) = COPY $sgpr0
208    %const:sgpr(s32) = G_CONSTANT i32 -16
209    %1:sgpr(p3) = G_PTRMASK %0, %const
210    S_ENDPGM 0, implicit %1
211
212...
213
214---
215name:  ptrmask_p3_s32_sgpr_sgpr_clearlo29
216legalized:       true
217regBankSelected: true
218
219body: |
220  bb.0:
221    liveins: $sgpr0
222
223    ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo29
224    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
225    ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -536870912
226    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
227    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
228    %0:sgpr(p3) = COPY $sgpr0
229    %const:sgpr(s32) = G_CONSTANT i32 -536870912
230    %1:sgpr(p3) = G_PTRMASK %0, %const
231    S_ENDPGM 0, implicit %1
232
233...
234
235---
236name:  ptrmask_p0_s64_sgpr_sgpr_sgpr
237legalized:       true
238regBankSelected: true
239
240body: |
241  bb.0:
242    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
243
244    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr
245    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
246    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
247    ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def $scc
248    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
249    %0:sgpr(p0) = COPY $sgpr0_sgpr1
250    %1:sgpr(s64) = COPY $sgpr2_sgpr3
251    %2:sgpr(p0) = G_PTRMASK %0, %1
252    S_ENDPGM 0, implicit %2
253
254...
255
256---
257name:  ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff
258legalized:       true
259regBankSelected: true
260
261body: |
262  bb.0:
263    liveins: $sgpr0_sgpr1
264
265    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff
266    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
267    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
268    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
269    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
270    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
271    %0:sgpr(p0) = COPY $sgpr0_sgpr1
272    %1:sgpr(s64) = G_CONSTANT i64 -1
273    %2:sgpr(p0) = G_PTRMASK %0, %1
274    S_ENDPGM 0, implicit %2
275
276...
277
278---
279name:  ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000
280legalized:       true
281regBankSelected: true
282
283body: |
284  bb.0:
285    liveins: $sgpr0_sgpr1
286
287    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000
288    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
289    ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
290    ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[S_MOV_B64_]], implicit-def $scc
291    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
292    %0:sgpr(p0) = COPY $sgpr0_sgpr1
293    %1:sgpr(s64) = G_CONSTANT i64 0
294    %2:sgpr(p0) = G_PTRMASK %0, %1
295    S_ENDPGM 0, implicit %2
296
297...
298
299---
300name:  ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
301legalized:       true
302regBankSelected: true
303
304body: |
305  bb.0:
306    liveins: $sgpr0_sgpr1
307
308    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
309    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
310    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4042322160
311    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -252645136
312    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
313    ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[REG_SEQUENCE]], implicit-def $scc
314    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
315    %0:sgpr(p0) = COPY $sgpr0_sgpr1
316    %1:sgpr(s64) = G_CONSTANT i64 -1085102592571150096
317    %2:sgpr(p0) = G_PTRMASK %0, %1
318    S_ENDPGM 0, implicit %2
319
320...
321
322---
323name:  ptrmask_p0_s64_sgpr_sgpr_clearhi1
324legalized:       true
325regBankSelected: true
326
327body: |
328  bb.0:
329    liveins: $sgpr0_sgpr1
330
331    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi1
332    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
333    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
334    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
335    ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
336    ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], %const, implicit-def $scc
337    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
338    %0:sgpr(p0) = COPY $sgpr0_sgpr1
339    %const:sgpr(s64) = G_CONSTANT i64 -9223372036854775808
340    %1:sgpr(p0) = G_PTRMASK %0, %const
341    S_ENDPGM 0, implicit %1
342
343...
344
345---
346name:  ptrmask_p0_s64_sgpr_sgpr_clearhi32
347legalized:       true
348regBankSelected: true
349
350body: |
351  bb.0:
352    liveins: $sgpr0_sgpr1
353
354    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi32
355    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
356    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
357    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
358    ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
359    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
360    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
361    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
362    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
363    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
364    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
365    %0:sgpr(p0) = COPY $sgpr0_sgpr1
366    %const:sgpr(s64) = G_CONSTANT i64 -4294967296
367    %1:sgpr(p0) = G_PTRMASK %0, %const
368    S_ENDPGM 0, implicit %1
369
370...
371
372---
373name:  ptrmask_p0_s64_sgpr_sgpr_clear_32
374legalized:       true
375regBankSelected: true
376
377body: |
378  bb.0:
379    liveins: $sgpr0_sgpr1
380
381    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clear_32
382    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
383    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
384    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
385    ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
386    ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], %const, implicit-def $scc
387    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
388    %0:sgpr(p0) = COPY $sgpr0_sgpr1
389    %const:sgpr(s64) = G_CONSTANT i64 4294967296
390    %1:sgpr(p0) = G_PTRMASK %0, %const
391    S_ENDPGM 0, implicit %1
392
393...
394
395---
396name:  ptrmask_p0_s64_sgpr_sgpr_clearlo1
397legalized:       true
398regBankSelected: true
399
400body: |
401  bb.0:
402    liveins: $sgpr0_sgpr1
403
404    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo1
405    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
406    ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64 -2
407    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
408    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
409    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
410    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
411    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
412    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
413    %0:sgpr(p0) = COPY $sgpr0_sgpr1
414    %const:sgpr(s64) = G_CONSTANT i64 -2
415    %1:sgpr(p0) = G_PTRMASK %0, %const
416    S_ENDPGM 0, implicit %1
417
418...
419
420---
421name:  ptrmask_p0_s64_sgpr_sgpr_clearlo2
422legalized:       true
423regBankSelected: true
424
425body: |
426  bb.0:
427    liveins: $sgpr0_sgpr1
428
429    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo2
430    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
431    ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64 -4
432    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
433    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
434    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
435    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
436    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
437    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
438    %0:sgpr(p0) = COPY $sgpr0_sgpr1
439    %const:sgpr(s64) = G_CONSTANT i64 -4
440    %1:sgpr(p0) = G_PTRMASK %0, %const
441    S_ENDPGM 0, implicit %1
442
443...
444
445---
446name:  ptrmask_p0_s64_sgpr_sgpr_clearlo3
447legalized:       true
448regBankSelected: true
449
450body: |
451  bb.0:
452    liveins: $sgpr0_sgpr1
453
454    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo3
455    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
456    ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64 -8
457    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
458    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
459    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
460    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
461    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
462    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
463    %0:sgpr(p0) = COPY $sgpr0_sgpr1
464    %const:sgpr(s64) = G_CONSTANT i64 -8
465    %1:sgpr(p0) = G_PTRMASK %0, %const
466    S_ENDPGM 0, implicit %1
467
468...
469
470---
471name:  ptrmask_p0_s64_sgpr_sgpr_clearlo4
472legalized:       true
473regBankSelected: true
474
475body: |
476  bb.0:
477    liveins: $sgpr0_sgpr1
478
479    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo4
480    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
481    ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64 -16
482    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
483    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
484    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
485    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
486    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
487    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
488    %0:sgpr(p0) = COPY $sgpr0_sgpr1
489    %const:sgpr(s64) = G_CONSTANT i64 -16
490    %1:sgpr(p0) = G_PTRMASK %0, %const
491    S_ENDPGM 0, implicit %1
492
493...
494
495---
496name:  ptrmask_p0_s64_sgpr_sgpr_clearlo29
497legalized:       true
498regBankSelected: true
499
500body: |
501  bb.0:
502    liveins: $sgpr0_sgpr1
503
504    ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo29
505    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
506    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3758096384
507    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
508    ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
509    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
510    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
511    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
512    ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
513    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
514    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
515    %0:sgpr(p0) = COPY $sgpr0_sgpr1
516    %const:sgpr(s64) = G_CONSTANT i64 -536870912
517    %1:sgpr(p0) = G_PTRMASK %0, %const
518    S_ENDPGM 0, implicit %1
519
520...
521
522---
523name:  ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
524legalized:       true
525regBankSelected: true
526
527body: |
528  bb.0:
529    liveins: $vgpr0
530
531    ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
532    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
533    ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec
534    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
535    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
536    %0:vgpr(p3) = COPY $vgpr0
537    %const:vgpr(s32) = G_CONSTANT i32 -252645136
538    %1:vgpr(p3) = G_PTRMASK %0, %const
539    S_ENDPGM 0, implicit %1
540
541...
542
543---
544name:  ptrmask_p3_vgpr_vgpr_clearlo1
545legalized:       true
546regBankSelected: true
547
548body: |
549  bb.0:
550    liveins: $vgpr0
551
552    ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo1
553    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
554    ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
555    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
556    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
557    %0:vgpr(p3) = COPY $vgpr0
558    %const:vgpr(s32) = G_CONSTANT i32 -2
559    %1:vgpr(p3) = G_PTRMASK %0, %const
560    S_ENDPGM 0, implicit %1
561
562...
563
564---
565name:  ptrmask_p3_vgpr_vgpr_clearlo2
566legalized:       true
567regBankSelected: true
568
569body: |
570  bb.0:
571    liveins: $vgpr0
572
573    ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo2
574    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
575    ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
576    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
577    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
578    %0:vgpr(p3) = COPY $vgpr0
579    %const:vgpr(s32) = G_CONSTANT i32 -4
580    %1:vgpr(p3) = G_PTRMASK %0, %const
581    S_ENDPGM 0, implicit %1
582
583...
584
585---
586name:  ptrmask_p3_vgpr_vgpr_clearlo3
587legalized:       true
588regBankSelected: true
589
590body: |
591  bb.0:
592    liveins: $vgpr0
593
594    ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo3
595    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
596    ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec
597    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
598    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
599    %0:vgpr(p3) = COPY $vgpr0
600    %const:vgpr(s32) = G_CONSTANT i32 -8
601    %1:vgpr(p3) = G_PTRMASK %0, %const
602    S_ENDPGM 0, implicit %1
603
604...
605
606---
607name:  ptrmask_p3_vgpr_vgpr_clearlo4
608legalized:       true
609regBankSelected: true
610
611body: |
612  bb.0:
613    liveins: $vgpr0
614
615    ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo4
616    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
617    ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
618    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
619    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
620    %0:vgpr(p3) = COPY $vgpr0
621    %const:vgpr(s32) = G_CONSTANT i32 -16
622    %1:vgpr(p3) = G_PTRMASK %0, %const
623    S_ENDPGM 0, implicit %1
624
625...
626
627---
628name:  ptrmask_p3_vgpr_vgpr_clearlo29
629legalized:       true
630regBankSelected: true
631
632body: |
633  bb.0:
634    liveins: $vgpr0
635
636    ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo29
637    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
638    ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec
639    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
640    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
641    %0:vgpr(p3) = COPY $vgpr0
642    %const:vgpr(s32) = G_CONSTANT i32 -536870912
643    %1:vgpr(p3) = G_PTRMASK %0, %const
644    S_ENDPGM 0, implicit %1
645
646...
647
648---
649name:  ptrmask_p0_s64_vgpr_vgpr_vgpr
650legalized:       true
651regBankSelected: true
652
653body: |
654  bb.0:
655    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
656
657    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr
658    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
659    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
660    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
661    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
662    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
663    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec
664    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
665    ; CHECK-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[COPY5]], implicit $exec
666    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
667    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
668    %0:vgpr(p0) = COPY $vgpr0_vgpr1
669    %1:vgpr(s64) = COPY $vgpr2_vgpr3
670    %2:vgpr(p0) = G_PTRMASK %0, %1
671    S_ENDPGM 0, implicit %2
672
673...
674
675---
676name:  ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
677legalized:       true
678regBankSelected: true
679
680body: |
681  bb.0:
682    liveins: $vgpr0_vgpr1
683
684    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
685    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
686    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4042322160, implicit $exec
687    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec
688    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
689    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
690    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
691    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
692    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
693    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
694    ; CHECK-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec
695    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
696    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
697    %0:vgpr(p0) = COPY $vgpr0_vgpr1
698    %1:vgpr(s64) = G_CONSTANT i64 -1085102592571150096
699    %2:vgpr(p0) = G_PTRMASK %0, %1
700    S_ENDPGM 0, implicit %2
701
702...
703
704---
705name:  ptrmask_p0_s64_vgpr_vgpr_clearlo1
706legalized:       true
707regBankSelected: true
708
709body: |
710  bb.0:
711    liveins: $vgpr0_vgpr1
712
713    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo1
714    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
715    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967294, implicit $exec
716    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
717    ; CHECK-NEXT: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
718    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
719    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
720    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
721    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
722    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
723    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
724    %0:vgpr(p0) = COPY $vgpr0_vgpr1
725    %const:vgpr(s64) = G_CONSTANT i64 -2
726    %1:vgpr(p0) = G_PTRMASK %0, %const
727    S_ENDPGM 0, implicit %1
728
729...
730
731---
732name:  ptrmask_p0_s64_vgpr_vgpr_clearlo2
733legalized:       true
734regBankSelected: true
735
736body: |
737  bb.0:
738    liveins: $vgpr0_vgpr1
739
740    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo2
741    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
742    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
743    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
744    ; CHECK-NEXT: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
745    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
746    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
747    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
748    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
749    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
750    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
751    %0:vgpr(p0) = COPY $vgpr0_vgpr1
752    %const:vgpr(s64) = G_CONSTANT i64 -4
753    %1:vgpr(p0) = G_PTRMASK %0, %const
754    S_ENDPGM 0, implicit %1
755
756...
757
758---
759name:  ptrmask_p0_s64_vgpr_vgpr_clearlo3
760legalized:       true
761regBankSelected: true
762
763body: |
764  bb.0:
765    liveins: $vgpr0_vgpr1
766
767    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo3
768    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
769    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
770    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
771    ; CHECK-NEXT: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
772    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
773    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
774    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
775    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
776    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
777    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
778    %0:vgpr(p0) = COPY $vgpr0_vgpr1
779    %const:vgpr(s64) = G_CONSTANT i64 -4
780    %1:vgpr(p0) = G_PTRMASK %0, %const
781    S_ENDPGM 0, implicit %1
782
783...
784
785---
786name:  ptrmask_p0_s64_vgpr_vgpr_clearlo4
787legalized:       true
788regBankSelected: true
789
790body: |
791  bb.0:
792    liveins: $vgpr0_vgpr1
793
794    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo4
795    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
796    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967280, implicit $exec
797    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
798    ; CHECK-NEXT: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
799    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
800    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
801    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
802    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
803    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
804    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
805    %0:vgpr(p0) = COPY $vgpr0_vgpr1
806    %const:vgpr(s64) = G_CONSTANT i64 -16
807    %1:vgpr(p0) = G_PTRMASK %0, %const
808    S_ENDPGM 0, implicit %1
809
810...
811
812---
813name:  ptrmask_p0_s64_vgpr_vgpr_clearlo29
814legalized:       true
815regBankSelected: true
816
817body: |
818  bb.0:
819    liveins: $vgpr0_vgpr1
820
821    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo29
822    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
823    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3758096384, implicit $exec
824    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
825    ; CHECK-NEXT: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
826    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
827    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
828    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
829    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
830    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
831    ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
832    %0:vgpr(p0) = COPY $vgpr0_vgpr1
833    %const:vgpr(s64) = G_CONSTANT i64 -536870912
834    %1:vgpr(p0) = G_PTRMASK %0, %const
835    S_ENDPGM 0, implicit %1
836
837...
838
839---
840name:  ptrmask_p3_vgpr_sgpr_clearlo2
841legalized:       true
842regBankSelected: true
843
844body: |
845  bb.0:
846    liveins: $sgpr0
847
848    ; CHECK-LABEL: name: ptrmask_p3_vgpr_sgpr_clearlo2
849    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
850    ; CHECK-NEXT: %const:sgpr(s32) = G_CONSTANT i32 -4
851    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:vgpr(p3) = G_PTRMASK [[COPY]], %const(s32)
852    ; CHECK-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p3)
853    %0:sgpr(p3) = COPY $sgpr0
854    %const:sgpr(s32) = G_CONSTANT i32 -4
855    %1:vgpr(p3) = G_PTRMASK %0, %const
856    S_ENDPGM 0, implicit %1
857
858...
859
860---
861name:  ptrmask_p0_s64_vgpr_sgpr_clearlo2
862legalized:       true
863regBankSelected: true
864
865body: |
866  bb.0:
867    liveins: $sgpr0_sgpr1
868
869    ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_sgpr_clearlo2
870    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
871    ; CHECK-NEXT: %const:sgpr(s32) = G_CONSTANT i32 -4
872    ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], %const(s32)
873    ; CHECK-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p0)
874    %0:sgpr(p0) = COPY $sgpr0_sgpr1
875    %const:sgpr(s32) = G_CONSTANT i32 -4
876    %1:vgpr(p0) = G_PTRMASK %0, %const
877    S_ENDPGM 0, implicit %1
878
879...
880