1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -amdgpu-global-isel-risky-select -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN
3
4---
5name:            g_phi_s32_ss_sbranch
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9machineFunctionInfo: {}
10body:             |
11  ; GCN-LABEL: name: g_phi_s32_ss_sbranch
12  ; GCN: bb.0:
13  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
14  ; GCN:   liveins: $sgpr0, $sgpr1, $sgpr2
15  ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
16  ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
17  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
18  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
19  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
20  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
21  ; GCN:   $scc = COPY [[COPY3]]
22  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
23  ; GCN:   S_BRANCH %bb.2
24  ; GCN: bb.1:
25  ; GCN:   successors: %bb.2(0x80000000)
26  ; GCN:   S_BRANCH %bb.2
27  ; GCN: bb.2:
28  ; GCN:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
29  ; GCN:   $sgpr0 = COPY [[PHI]]
30  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
31  bb.0:
32    liveins: $sgpr0, $sgpr1, $sgpr2
33
34    %0:sgpr(s32) = COPY $sgpr0
35    %1:sgpr(s32) = COPY $sgpr1
36    %2:sgpr(s32) = COPY $sgpr2
37    %3:sgpr(s32) = G_CONSTANT i32 0
38    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
39    G_BRCOND %4, %bb.1
40    G_BR %bb.2
41
42  bb.1:
43    %5:sgpr(s32) = COPY %1
44    G_BR %bb.2
45
46  bb.2:
47    %6:sgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
48    $sgpr0 = COPY %6
49    S_SETPC_B64 undef $sgpr30_sgpr31
50
51...
52
53---
54name:            g_phi_s32_vv_sbranch
55legalized:       true
56regBankSelected: true
57tracksRegLiveness: true
58machineFunctionInfo: {}
59body:             |
60  ; GCN-LABEL: name: g_phi_s32_vv_sbranch
61  ; GCN: bb.0:
62  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
63  ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
64  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
65  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
66  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
67  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
68  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
69  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
70  ; GCN:   $scc = COPY [[COPY3]]
71  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
72  ; GCN:   S_BRANCH %bb.2
73  ; GCN: bb.1:
74  ; GCN:   successors: %bb.2(0x80000000)
75  ; GCN:   [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
76  ; GCN:   S_BRANCH %bb.2
77  ; GCN: bb.2:
78  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
79  ; GCN:   $vgpr0 = COPY [[PHI]]
80  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
81  bb.0:
82    liveins: $vgpr0, $vgpr1, $sgpr2
83
84    %0:vgpr(s32) = COPY $vgpr0
85    %1:vgpr(s32) = COPY $vgpr1
86    %2:sgpr(s32) = COPY $sgpr2
87    %3:sgpr(s32) = G_CONSTANT i32 0
88    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
89    G_BRCOND %4, %bb.1
90    G_BR %bb.2
91
92  bb.1:
93    %5:sgpr(s32) = COPY %1
94    G_BR %bb.2
95
96  bb.2:
97    %6:vgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
98    $vgpr0 = COPY %6(s32)
99    S_SETPC_B64 undef $sgpr30_sgpr31
100
101...
102
103---
104name:            g_phi_s32_sv_sbranch
105legalized:       true
106regBankSelected: true
107tracksRegLiveness: true
108machineFunctionInfo: {}
109body:             |
110  ; GCN-LABEL: name: g_phi_s32_sv_sbranch
111  ; GCN: bb.0:
112  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
113  ; GCN:   liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2
114  ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
115  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
116  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
117  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
118  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
119  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
120  ; GCN:   $scc = COPY [[COPY3]]
121  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
122  ; GCN:   S_BRANCH %bb.2
123  ; GCN: bb.1:
124  ; GCN:   successors: %bb.2(0x80000000)
125  ; GCN:   S_BRANCH %bb.2
126  ; GCN: bb.2:
127  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
128  ; GCN:   $vgpr0 = COPY [[PHI]]
129  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
130  bb.0:
131    liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2
132
133    %0:sgpr(s32) = COPY $sgpr0
134    %1:vgpr(s32) = COPY $vgpr0
135    %2:sgpr(s32) = COPY $sgpr2
136    %3:sgpr(s32) = G_CONSTANT i32 0
137    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
138    G_BRCOND %4, %bb.1
139    G_BR %bb.2
140
141  bb.1:
142    %5:vgpr(s32) = COPY %1
143    G_BR %bb.2
144
145  bb.2:
146    %6:vgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
147    $vgpr0 = COPY %6
148    S_SETPC_B64 undef $sgpr30_sgpr31
149
150...
151
152---
153name:            g_phi_s32_vs_sbranch
154legalized:       true
155regBankSelected: true
156tracksRegLiveness: true
157machineFunctionInfo: {}
158body:             |
159  ; GCN-LABEL: name: g_phi_s32_vs_sbranch
160  ; GCN: bb.0:
161  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
162  ; GCN:   liveins: $sgpr0, $vgpr0, $sgpr1
163  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
164  ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
165  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1
166  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
167  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
168  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
169  ; GCN:   $scc = COPY [[COPY3]]
170  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
171  ; GCN:   S_BRANCH %bb.2
172  ; GCN: bb.1:
173  ; GCN:   successors: %bb.2(0x80000000)
174  ; GCN:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
175  ; GCN:   S_BRANCH %bb.2
176  ; GCN: bb.2:
177  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
178  ; GCN:   $vgpr0 = COPY [[PHI]]
179  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
180  bb.0:
181    liveins: $sgpr0, $vgpr0, $sgpr1
182
183    %0:vgpr(s32) = COPY $vgpr0
184    %1:sgpr(s32) = COPY $sgpr0
185    %2:sgpr(s32) = COPY $sgpr1
186    %3:sgpr(s32) = G_CONSTANT i32 0
187    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
188    G_BRCOND %4, %bb.1
189    G_BR %bb.2
190
191  bb.1:
192    %5:vgpr(s32) = COPY %1
193    G_BR %bb.2
194
195  bb.2:
196    %6:vgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
197    $vgpr0 = COPY %6
198    S_SETPC_B64 undef $sgpr30_sgpr31
199
200...
201
202---
203name:            g_phi_s64_ss_sbranch
204legalized:       true
205regBankSelected: true
206tracksRegLiveness: true
207machineFunctionInfo: {}
208body:             |
209  ; GCN-LABEL: name: g_phi_s64_ss_sbranch
210  ; GCN: bb.0:
211  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
212  ; GCN:   liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4
213  ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
214  ; GCN:   [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
215  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
216  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
217  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
218  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
219  ; GCN:   $scc = COPY [[COPY3]]
220  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
221  ; GCN:   S_BRANCH %bb.2
222  ; GCN: bb.1:
223  ; GCN:   successors: %bb.2(0x80000000)
224  ; GCN:   S_BRANCH %bb.2
225  ; GCN: bb.2:
226  ; GCN:   [[PHI:%[0-9]+]]:sreg_64 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
227  ; GCN:   $sgpr0_sgpr1 = COPY [[PHI]]
228  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
229  bb.0:
230    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4
231
232    %0:sgpr(s64) = COPY $sgpr0_sgpr1
233    %1:sgpr(s64) = COPY $sgpr2_sgpr3
234    %2:sgpr(s32) = COPY $sgpr4
235    %3:sgpr(s32) = G_CONSTANT i32 0
236    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
237    G_BRCOND %4, %bb.1
238    G_BR %bb.2
239
240  bb.1:
241    %5:sgpr(s64) = COPY %1
242    G_BR %bb.2
243
244  bb.2:
245    %6:sgpr(s64) = G_PHI %0(s64), %bb.0, %5(s64), %bb.1
246    $sgpr0_sgpr1 = COPY %6
247    S_SETPC_B64 undef $sgpr30_sgpr31
248
249...
250---
251name:            g_phi_v2s16_vv_sbranch
252legalized:       true
253regBankSelected: true
254tracksRegLiveness: true
255machineFunctionInfo: {}
256body:             |
257  ; GCN-LABEL: name: g_phi_v2s16_vv_sbranch
258  ; GCN: bb.0:
259  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
260  ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
261  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
262  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
263  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
264  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
265  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
266  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
267  ; GCN:   $scc = COPY [[COPY3]]
268  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
269  ; GCN:   S_BRANCH %bb.2
270  ; GCN: bb.1:
271  ; GCN:   successors: %bb.2(0x80000000)
272  ; GCN:   [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
273  ; GCN:   S_BRANCH %bb.2
274  ; GCN: bb.2:
275  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
276  ; GCN:   $vgpr0 = COPY [[PHI]]
277  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
278  bb.0:
279    liveins: $vgpr0, $vgpr1, $sgpr2
280
281    %0:vgpr(<2 x s16>) = COPY $vgpr0
282    %1:vgpr(<2 x s16>) = COPY $vgpr1
283    %2:sgpr(s32) = COPY $sgpr2
284    %3:sgpr(s32) = G_CONSTANT i32 0
285    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
286    G_BRCOND %4, %bb.1
287    G_BR %bb.2
288
289  bb.1:
290    %5:sgpr(<2 x s16>) = COPY %1
291    G_BR %bb.2
292
293  bb.2:
294    %6:vgpr(<2 x s16>) = G_PHI %0(<2 x s16>), %bb.0, %5(<2 x s16>), %bb.1
295    $vgpr0 = COPY %6
296    S_SETPC_B64 undef $sgpr30_sgpr31
297
298...
299
300---
301name:            g_phi_vcc_s1_sbranch
302legalized:       true
303regBankSelected: true
304tracksRegLiveness: true
305machineFunctionInfo: {}
306body:             |
307  ; GCN-LABEL: name: g_phi_vcc_s1_sbranch
308  ; GCN: bb.0:
309  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
310  ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
311  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
312  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
313  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
314  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
315  ; GCN:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
316  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
317  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
318  ; GCN:   $scc = COPY [[COPY3]]
319  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
320  ; GCN:   S_BRANCH %bb.2
321  ; GCN: bb.1:
322  ; GCN:   successors: %bb.2(0x80000000)
323  ; GCN:   [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
324  ; GCN:   S_BRANCH %bb.2
325  ; GCN: bb.2:
326  ; GCN:   [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[V_CMP_EQ_U32_e64_]], %bb.0, [[V_CMP_EQ_U32_e64_1]], %bb.1
327  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]]
328  bb.0:
329    liveins: $vgpr0, $vgpr1, $sgpr2
330
331    %0:vgpr(s32) = COPY $vgpr0
332    %1:vgpr(s32) = COPY $vgpr1
333    %2:sgpr(s32) = COPY $sgpr2
334    %3:sgpr(s32) = G_CONSTANT i32 0
335    %4:vcc(s1) = G_ICMP intpred(eq), %0, %3
336    %5:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
337    G_BRCOND %5, %bb.1
338    G_BR %bb.2
339
340  bb.1:
341    %6:vcc(s1) = G_ICMP intpred(eq), %1, %3
342    G_BR %bb.2
343
344  bb.2:
345    %7:vcc(s1) = G_PHI %4, %bb.0, %6, %bb.1
346    S_SETPC_B64 undef $sgpr30_sgpr31, implicit %7
347
348...
349
350---
351name:            phi_s32_ss_sbranch
352legalized:       true
353regBankSelected: true
354tracksRegLiveness: true
355machineFunctionInfo: {}
356body:             |
357  ; GCN-LABEL: name: phi_s32_ss_sbranch
358  ; GCN: bb.0:
359  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
360  ; GCN:   liveins: $sgpr0, $sgpr1, $sgpr2
361  ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
362  ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
363  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
364  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
365  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
366  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
367  ; GCN:   $scc = COPY [[COPY3]]
368  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
369  ; GCN:   S_BRANCH %bb.2
370  ; GCN: bb.1:
371  ; GCN:   successors: %bb.2(0x80000000)
372  ; GCN:   S_BRANCH %bb.2
373  ; GCN: bb.2:
374  ; GCN:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
375  ; GCN:   $sgpr0 = COPY [[PHI]]
376  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
377  bb.0:
378    liveins: $sgpr0, $sgpr1, $sgpr2
379
380    %0:sgpr(s32) = COPY $sgpr0
381    %1:sgpr(s32) = COPY $sgpr1
382    %2:sgpr(s32) = COPY $sgpr2
383    %3:sgpr(s32) = G_CONSTANT i32 0
384    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
385    G_BRCOND %4, %bb.1
386    G_BR %bb.2
387
388  bb.1:
389    %5:sgpr(s32) = COPY %1
390    G_BR %bb.2
391
392  bb.2:
393    %6:sgpr(s32) = PHI %0(s32), %bb.0, %5(s32), %bb.1
394    $sgpr0 = COPY %6(s32)
395    S_SETPC_B64 undef $sgpr30_sgpr31
396
397...
398
399---
400name:            phi_s32_vv_sbranch
401legalized:       true
402regBankSelected: true
403tracksRegLiveness: true
404machineFunctionInfo: {}
405body:             |
406  ; GCN-LABEL: name: phi_s32_vv_sbranch
407  ; GCN: bb.0:
408  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
409  ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
410  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
411  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
412  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
413  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
414  ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
415  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
416  ; GCN:   $scc = COPY [[COPY3]]
417  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
418  ; GCN:   S_BRANCH %bb.2
419  ; GCN: bb.1:
420  ; GCN:   successors: %bb.2(0x80000000)
421  ; GCN:   [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
422  ; GCN:   S_BRANCH %bb.2
423  ; GCN: bb.2:
424  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
425  ; GCN:   $vgpr0 = COPY [[PHI]]
426  ; GCN:   S_SETPC_B64 undef $sgpr30_sgpr31
427  bb.0:
428    liveins: $vgpr0, $vgpr1, $sgpr2
429
430    %0:vgpr(s32) = COPY $vgpr0
431    %1:vgpr(s32) = COPY $vgpr1
432    %2:sgpr(s32) = COPY $sgpr2
433    %3:sgpr(s32) = G_CONSTANT i32 0
434    %4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
435    G_BRCOND %4, %bb.1
436    G_BR %bb.2
437
438  bb.1:
439    %5:sgpr(s32) = COPY %1
440    G_BR %bb.2
441
442  bb.2:
443    %6:vgpr(s32) = PHI %0(s32), %bb.0, %5(s32), %bb.1
444    $vgpr0 = COPY %6
445    S_SETPC_B64 undef $sgpr30_sgpr31
446
447...
448