1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5 6name: insert_s512_s32 7legalized: true 8regBankSelected: true 9 10body: | 11 bb.0: 12 ; CHECK-LABEL: name: insert_s512_s32 13 ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF 14 ; CHECK: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 15 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0 16 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1 17 ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2 18 ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3 19 ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4 20 ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5 21 ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6 22 ; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7 23 ; CHECK: [[INSERT_SUBREG8:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG7]], [[DEF1]], %subreg.sub8 24 ; CHECK: [[INSERT_SUBREG9:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG8]], [[DEF1]], %subreg.sub9 25 ; CHECK: [[INSERT_SUBREG10:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG9]], [[DEF1]], %subreg.sub10 26 ; CHECK: [[INSERT_SUBREG11:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG10]], [[DEF1]], %subreg.sub11 27 ; CHECK: [[INSERT_SUBREG12:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG11]], [[DEF1]], %subreg.sub12 28 ; CHECK: [[INSERT_SUBREG13:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG12]], [[DEF1]], %subreg.sub13 29 ; CHECK: [[INSERT_SUBREG14:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG13]], [[DEF1]], %subreg.sub14 30 ; CHECK: [[INSERT_SUBREG15:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG14]], [[DEF1]], %subreg.sub15 31 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[INSERT_SUBREG15]] 32 ; CHECK: SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 33 %0:sgpr(s512) = G_IMPLICIT_DEF 34 %1:sgpr(s32) = G_IMPLICIT_DEF 35 %2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0 36 %3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32 37 %4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64 38 %5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96 39 %6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128 40 %7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160 41 %8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192 42 %9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224 43 %10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256 44 %11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288 45 %12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320 46 %13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352 47 %14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384 48 %15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416 49 %16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448 50 %17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480 51 $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512) 52 SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 53... 54 55--- 56 57name: insert_v_s64_v_s32_0 58legalized: true 59regBankSelected: true 60 61body: | 62 bb.0: 63 liveins: $vgpr0_vgpr1, $vgpr2 64 ; CHECK-LABEL: name: insert_v_s64_v_s32_0 65 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 66 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 67 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0 68 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 69 %0:vgpr(s64) = COPY $vgpr0_vgpr1 70 %1:vgpr(s32) = COPY $vgpr2 71 %2:vgpr(s64) = G_INSERT %0, %1, 0 72 S_ENDPGM 0, implicit %2 73... 74 75--- 76 77name: insert_v_s64_v_s32_32 78legalized: true 79regBankSelected: true 80 81body: | 82 bb.0: 83 liveins: $vgpr0_vgpr1, $vgpr2 84 ; CHECK-LABEL: name: insert_v_s64_v_s32_32 85 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 86 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1 88 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 89 %0:vgpr(s64) = COPY $vgpr0_vgpr1 90 %1:vgpr(s32) = COPY $vgpr2 91 %2:vgpr(s64) = G_INSERT %0, %1, 32 92 S_ENDPGM 0, implicit %2 93... 94 95--- 96 97name: insert_s_s64_s_s32_0 98legalized: true 99regBankSelected: true 100 101body: | 102 bb.0: 103 liveins: $sgpr0_sgpr1, $sgpr2 104 ; CHECK-LABEL: name: insert_s_s64_s_s32_0 105 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 106 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 107 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0 108 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 109 %0:sgpr(s64) = COPY $sgpr0_sgpr1 110 %1:sgpr(s32) = COPY $sgpr2 111 %2:sgpr(s64) = G_INSERT %0, %1, 0 112 S_ENDPGM 0, implicit %2 113... 114 115--- 116 117name: insert_s_s64_s_s32_32 118legalized: true 119regBankSelected: true 120 121body: | 122 bb.0: 123 liveins: $sgpr0_sgpr1, $sgpr2 124 ; CHECK-LABEL: name: insert_s_s64_s_s32_32 125 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 126 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 127 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1 128 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 129 %0:sgpr(s64) = COPY $sgpr0_sgpr1 130 %1:sgpr(s32) = COPY $sgpr2 131 %2:sgpr(s64) = G_INSERT %0, %1, 32 132 S_ENDPGM 0, implicit %2 133... 134 135--- 136 137name: insert_s_s64_v_s32_32 138legalized: true 139regBankSelected: true 140 141body: | 142 bb.0: 143 liveins: $sgpr0_sgpr1, $vgpr0 144 ; CHECK-LABEL: name: insert_s_s64_v_s32_32 145 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 146 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 147 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1 148 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 149 %0:sgpr(s64) = COPY $sgpr0_sgpr1 150 %1:vgpr(s32) = COPY $vgpr2 151 %2:vgpr(s64) = G_INSERT %0, %1, 32 152 S_ENDPGM 0, implicit %2 153... 154 155--- 156 157name: insert_v_s64_s_s32_32 158legalized: true 159regBankSelected: true 160 161body: | 162 bb.0: 163 liveins: $vgpr0_vgpr1, $sgpr0 164 ; CHECK-LABEL: name: insert_v_s64_s_s32_32 165 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 166 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 167 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1 168 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 169 %0:vgpr(s64) = COPY $vgpr0_vgpr1 170 %1:sgpr(s32) = COPY $sgpr0 171 %2:vgpr(s64) = G_INSERT %0, %1, 32 172 S_ENDPGM 0, implicit %2 173... 174 175--- 176 177name: insert_v_s96_v_s64_0 178legalized: true 179regBankSelected: true 180 181body: | 182 bb.0: 183 liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4 184 ; CHECK-LABEL: name: insert_v_s96_v_s64_0 185 ; CHECK: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2 186 ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 187 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1 188 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 189 %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2 190 %1:vgpr(s64) = COPY $vgpr3_vgpr4 191 %2:vgpr(s96) = G_INSERT %0, %1, 0 192 S_ENDPGM 0, implicit %2 193... 194 195--- 196 197name: insert_v_s96_v_s64_32 198legalized: true 199regBankSelected: true 200 201body: | 202 bb.0: 203 liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4 204 ; CHECK-LABEL: name: insert_v_s96_v_s64_32 205 ; CHECK: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2 206 ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 207 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2 208 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 209 %0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2 210 %1:vgpr(s64) = COPY $vgpr3_vgpr4 211 %2:vgpr(s96) = G_INSERT %0, %1, 32 212 S_ENDPGM 0, implicit %2 213... 214 215--- 216 217name: insert_s_s96_s_s64_0 218legalized: true 219regBankSelected: true 220 221body: | 222 bb.0: 223 liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5 224 ; CHECK-LABEL: name: insert_s_s96_s_s64_0 225 ; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub0_sub1 = COPY $sgpr0_sgpr1_sgpr2 226 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 227 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1 228 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 229 %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2 230 %1:sgpr(s64) = COPY $sgpr4_sgpr5 231 %2:sgpr(s96) = G_INSERT %0, %1, 0 232 S_ENDPGM 0, implicit %2 233... 234 235--- 236 237name: insert_s_s96_s_s64_32 238legalized: true 239regBankSelected: true 240 241body: | 242 bb.0: 243 liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5 244 ; CHECK-LABEL: name: insert_s_s96_s_s64_32 245 ; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2 246 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 247 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2 248 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 249 %0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2 250 %1:sgpr(s64) = COPY $sgpr4_sgpr5 251 %2:sgpr(s96) = G_INSERT %0, %1, 32 252 S_ENDPGM 0, implicit %2 253... 254 255--- 256 257name: insert_s_s128_s_s64_0 258legalized: true 259regBankSelected: true 260 261body: | 262 bb.0: 263 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5 264 ; CHECK-LABEL: name: insert_s_s128_s_s64_0 265 ; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 266 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 267 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1 268 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 269 %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 270 %1:sgpr(s64) = COPY $sgpr4_sgpr5 271 %2:sgpr(s128) = G_INSERT %0, %1, 0 272 S_ENDPGM 0, implicit %2 273... 274 275# --- 276 277# name: insert_s_s128_s_s64_32 278# legalized: true 279# regBankSelected: true 280 281# body: | 282# bb.0: 283# liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5 284# %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 285# %1:sgpr(s64) = COPY $sgpr4_sgpr5 286# %2:sgpr(s128) = G_INSERT %0, %1, 32 287# S_ENDPGM 0, implicit %2 288# ... 289 290--- 291 292name: insert_s_s128_s_s64_64 293legalized: true 294regBankSelected: true 295 296body: | 297 bb.0: 298 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5 299 ; CHECK-LABEL: name: insert_s_s128_s_s64_64 300 ; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 301 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 302 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3 303 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 304 %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 305 %1:sgpr(s64) = COPY $sgpr4_sgpr5 306 %2:sgpr(s128) = G_INSERT %0, %1, 64 307 S_ENDPGM 0, implicit %2 308... 309 310--- 311 312name: insert_s_v256_v_s64_96 313legalized: true 314regBankSelected: true 315 316body: | 317 bb.0: 318 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9 319 ; CHECK-LABEL: name: insert_s_v256_v_s64_96 320 ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 321 ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9 322 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4 323 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 324 %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 325 %1:vgpr(s64) = COPY $vgpr8_vgpr9 326 %2:vgpr(s256) = G_INSERT %0, %1, 96 327 S_ENDPGM 0, implicit %2 328... 329 330--- 331 332name: insert_s_s256_s_s64_128 333legalized: true 334regBankSelected: true 335 336body: | 337 bb.0: 338 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9 339 ; CHECK-LABEL: name: insert_s_s256_s_s64_128 340 ; CHECK: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 341 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 342 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5 343 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 344 %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 345 %1:sgpr(s64) = COPY $sgpr4_sgpr5 346 %2:sgpr(s256) = G_INSERT %0, %1, 128 347 S_ENDPGM 0, implicit %2 348... 349 350# --- 351 352# name: insert_s_s256_s_s64_160 353# legalized: true 354# regBankSelected: true 355 356# body: | 357# bb.0: 358# liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9 359# %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 360# %1:sgpr(s64) = COPY $sgpr4_sgpr5 361# %2:sgpr(s256) = G_INSERT %0, %1, 160 362# S_ENDPGM 0, implicit %2 363# ... 364 365--- 366 367name: insert_s_s128_s_s96_0 368legalized: true 369regBankSelected: true 370 371body: | 372 bb.0: 373 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr6_sgpr7_sgpr8 374 ; CHECK-LABEL: name: insert_s_s128_s_s96_0 375 ; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 376 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8 377 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2 378 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 379 %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 380 %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8 381 %2:sgpr(s128) = G_INSERT %0, %1, 0 382 S_ENDPGM 0, implicit %2 383... 384 385--- 386 387name: insert_s_s128_s_s96_32 388legalized: true 389regBankSelected: true 390 391body: | 392 bb.0: 393 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr6_sgpr7_sgpr8 394 ; CHECK-LABEL: name: insert_s_s128_s_s96_32 395 ; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 396 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8 397 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3 398 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 399 %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 400 %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8 401 %2:sgpr(s128) = G_INSERT %0, %1, 32 402 S_ENDPGM 0, implicit %2 403... 404 405--- 406 407name: insert_s_s160_s_s96_0 408legalized: true 409regBankSelected: true 410 411body: | 412 bb.0: 413 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8 414 ; CHECK-LABEL: name: insert_s_s160_s_s96_0 415 ; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 416 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8 417 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2 418 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 419 %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 420 %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8 421 %2:sgpr(s160) = G_INSERT %0, %1, 0 422 S_ENDPGM 0, implicit %2 423... 424 425--- 426 427name: insert_s_s160_s_s96_32 428legalized: true 429regBankSelected: true 430 431body: | 432 bb.0: 433 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8 434 ; CHECK-LABEL: name: insert_s_s160_s_s96_32 435 ; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 436 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8 437 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3 438 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 439 %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 440 %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8 441 %2:sgpr(s160) = G_INSERT %0, %1, 32 442 S_ENDPGM 0, implicit %2 443... 444 445--- 446 447name: insert_s_s160_s_s96_64 448legalized: true 449regBankSelected: true 450 451body: | 452 bb.0: 453 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8 454 ; CHECK-LABEL: name: insert_s_s160_s_s96_64 455 ; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub2_sub3_sub4 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 456 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8 457 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4 458 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 459 %0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 460 %1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8 461 %2:sgpr(s160) = G_INSERT %0, %1, 64 462 S_ENDPGM 0, implicit %2 463... 464 465--- 466 467name: insert_s_s256_s_s128_0 468legalized: true 469regBankSelected: true 470 471body: | 472 bb.0: 473 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11 474 475 ; CHECK-LABEL: name: insert_s_s256_s_s128_0 476 ; CHECK: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 477 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11 478 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3 479 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 480 %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 481 %1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11 482 %2:sgpr(s256) = G_INSERT %0, %1, 0 483 S_ENDPGM 0, implicit %2 484... 485 486--- 487 488name: insert_v_s256_v_s128_32 489legalized: true 490regBankSelected: true 491 492body: | 493 bb.0: 494 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11 495 496 ; CHECK-LABEL: name: insert_v_s256_v_s128_32 497 ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 498 ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11 499 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4 500 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 501 %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 502 %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11 503 %2:vgpr(s256) = G_INSERT %0, %1, 32 504 S_ENDPGM 0, implicit %2 505... 506 507--- 508 509name: insert_v_s256_v_s128_64 510legalized: true 511regBankSelected: true 512 513body: | 514 bb.0: 515 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11 516 517 ; CHECK-LABEL: name: insert_v_s256_v_s128_64 518 ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 519 ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11 520 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5 521 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 522 %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 523 %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11 524 %2:vgpr(s256) = G_INSERT %0, %1, 64 525 S_ENDPGM 0, implicit %2 526... 527 528--- 529 530name: insert_v_s256_v_s128_96 531legalized: true 532regBankSelected: true 533 534body: | 535 bb.0: 536 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11 537 538 ; CHECK-LABEL: name: insert_v_s256_v_s128_96 539 ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 540 ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11 541 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6 542 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 543 %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 544 %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11 545 %2:vgpr(s256) = G_INSERT %0, %1, 96 546 S_ENDPGM 0, implicit %2 547... 548 549--- 550 551name: insert_v_s256_v_s128_128 552legalized: true 553regBankSelected: true 554 555body: | 556 bb.0: 557 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11 558 559 ; CHECK-LABEL: name: insert_v_s256_v_s128_128 560 ; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 561 ; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11 562 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7 563 ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]] 564 %0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 565 %1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11 566 %2:vgpr(s256) = G_INSERT %0, %1, 128 567 S_ENDPGM 0, implicit %2 568... 569