1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s
4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
5# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
6
7---
8name: insert_vector_elt_s_s32_v2s32
9legalized: true
10regBankSelected: true
11
12body: |
13  bb.0:
14    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
15
16    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v2s32
17    ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
18    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
19    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
20    ; MOVREL: $m0 = COPY [[COPY2]]
21    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0
22    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
23    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v2s32
24    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
25    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
26    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
27    ; GPRIDX: $m0 = COPY [[COPY2]]
28    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0
29    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
30    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
31    %1:sgpr(s32) = COPY $sgpr2
32    %2:sgpr(s32) = COPY $sgpr3
33    %3:sgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
34    S_ENDPGM 0, implicit %3
35...
36
37---
38name: insert_vector_elt_s_s32_v3s32
39legalized: true
40regBankSelected: true
41
42body: |
43  bb.0:
44    liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4
45
46    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v3s32
47    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
48    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
49    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
50    ; MOVREL: $m0 = COPY [[COPY2]]
51    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0
52    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
53    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v3s32
54    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_96 = COPY $sgpr0_sgpr1_sgpr2
55    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
56    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
57    ; GPRIDX: $m0 = COPY [[COPY2]]
58    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:sgpr_96 = S_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0
59    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
60    %0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
61    %1:sgpr(s32) = COPY $sgpr3
62    %2:sgpr(s32) = COPY $sgpr4
63    %3:sgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
64    S_ENDPGM 0, implicit %3
65...
66
67---
68name: insert_vector_elt_s_s32_v4s32
69legalized: true
70regBankSelected: true
71
72body: |
73  bb.0:
74    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
75
76    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32
77    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
78    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
79    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
80    ; MOVREL: $m0 = COPY [[COPY2]]
81    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
82    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
83    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32
84    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
85    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
86    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
87    ; GPRIDX: $m0 = COPY [[COPY2]]
88    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
89    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
90    %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
91    %1:sgpr(s32) = COPY $sgpr3
92    %2:sgpr(s32) = COPY $sgpr4
93    %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
94    S_ENDPGM 0, implicit %3
95...
96
97---
98name: insert_vector_elt_s_s32_v5s32
99legalized: true
100regBankSelected: true
101
102body: |
103  bb.0:
104    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6
105
106    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v5s32
107    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
108    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
109    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
110    ; MOVREL: $m0 = COPY [[COPY2]]
111    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0
112    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
113    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v5s32
114    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
115    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
116    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
117    ; GPRIDX: $m0 = COPY [[COPY2]]
118    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:sgpr_160 = S_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0
119    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
120    %0:sgpr(<5 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
121    %1:sgpr(s32) = COPY $sgpr5
122    %2:sgpr(s32) = COPY $sgpr6
123    %3:sgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
124    S_ENDPGM 0, implicit %3
125...
126
127---
128name: insert_vector_elt_s_s32_v8s32
129legalized: true
130regBankSelected: true
131
132body: |
133  bb.0:
134    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
135
136    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32
137    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
138    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
139    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
140    ; MOVREL: $m0 = COPY [[COPY2]]
141    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
142    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
143    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32
144    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
145    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
146    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
147    ; GPRIDX: $m0 = COPY [[COPY2]]
148    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
149    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
150    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
151    %1:sgpr(s32) = COPY $sgpr8
152    %2:sgpr(s32) = COPY $sgpr9
153    %3:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
154    S_ENDPGM 0, implicit %3
155...
156
157---
158name: insert_vector_elt_s_s32_v16s32
159legalized: true
160regBankSelected: true
161
162body: |
163  bb.0:
164    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17
165
166    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v16s32
167    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
168    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
169    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
170    ; MOVREL: $m0 = COPY [[COPY2]]
171    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0
172    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]]
173    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v16s32
174    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
175    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
176    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
177    ; GPRIDX: $m0 = COPY [[COPY2]]
178    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B32_V16 [[COPY]], [[COPY1]], 3, implicit $m0
179    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V16_]]
180    %0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
181    %1:sgpr(s32) = COPY $sgpr16
182    %2:sgpr(s32) = COPY $sgpr17
183    %3:sgpr(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
184    S_ENDPGM 0, implicit %3
185...
186
187---
188name: extract_vector_elt_s_s32_v32s32
189legalized: true
190regBankSelected: true
191
192body: |
193  bb.0:
194    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41
195
196    ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v32s32
197    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
198    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
199    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
200    ; MOVREL: $m0 = COPY [[COPY2]]
201    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0
202    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]]
203    ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32
204    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
205    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
206    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
207    ; GPRIDX: $m0 = COPY [[COPY2]]
208    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B32_V32 [[COPY]], [[COPY1]], 3, implicit $m0
209    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V32_]]
210    %0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
211    %1:sgpr(s32) = COPY $sgpr40
212    %2:sgpr(s32) = COPY $sgpr41
213    %3:sgpr(<32 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
214    S_ENDPGM 0, implicit %3
215...
216
217---
218name: insert_vector_elt_s_s64_v2s64
219legalized: true
220regBankSelected: true
221
222body: |
223  bb.0:
224    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6
225
226    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v2s64
227    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
228    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
229    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
230    ; MOVREL: $m0 = COPY [[COPY2]]
231    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
232    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
233    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v2s64
234    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
235    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
236    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
237    ; GPRIDX: $m0 = COPY [[COPY2]]
238    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
239    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
240    %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
241    %1:sgpr(s64) = COPY $sgpr4_sgpr5
242    %2:sgpr(s32) = COPY $sgpr6
243    %3:sgpr(<2 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
244    S_ENDPGM 0, implicit %3
245...
246
247---
248name: insert_vector_elt_s_s64_v4s64
249legalized: true
250regBankSelected: true
251
252body: |
253  bb.0:
254    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10
255
256    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v4s64
257    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
258    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
259    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
260    ; MOVREL: $m0 = COPY [[COPY2]]
261    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
262    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
263    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v4s64
264    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
265    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
266    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
267    ; GPRIDX: $m0 = COPY [[COPY2]]
268    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
269    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
270    %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
271    %1:sgpr(s64) = COPY $sgpr8_sgpr9
272    %2:sgpr(s32) = COPY $sgpr10
273    %3:sgpr(<4 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
274    S_ENDPGM 0, implicit %3
275...
276
277---
278name: insert_vector_elt_s_s64_v8s64
279legalized: true
280regBankSelected: true
281
282body: |
283  bb.0:
284    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18
285
286    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v8s64
287    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
288    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
289    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
290    ; MOVREL: $m0 = COPY [[COPY2]]
291    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
292    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
293    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v8s64
294    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
295    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
296    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
297    ; GPRIDX: $m0 = COPY [[COPY2]]
298    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
299    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
300    %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
301    %1:sgpr(s64) = COPY $sgpr16_sgpr17
302    %2:sgpr(s32) = COPY $sgpr18
303    %3:sgpr(<8 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
304    S_ENDPGM 0, implicit %3
305...
306
307---
308name: extract_vector_elt_s_s64_v16s64
309legalized: true
310regBankSelected: true
311
312body: |
313  bb.0:
314    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42
315
316    ; MOVREL-LABEL: name: extract_vector_elt_s_s64_v16s64
317    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
318    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
319    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
320    ; MOVREL: $m0 = COPY [[COPY2]]
321    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
322    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
323    ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64
324    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
325    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
326    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
327    ; GPRIDX: $m0 = COPY [[COPY2]]
328    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
329    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
330    %0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
331    %1:sgpr(s64) = COPY $sgpr40_sgpr41
332    %2:sgpr(s32) = COPY $sgpr42
333    %3:sgpr(<16 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
334    S_ENDPGM 0, implicit %3
335...
336
337---
338name: insert_vector_elt_vvs_s32_v2s32
339legalized: true
340regBankSelected: true
341
342body: |
343  bb.0:
344    liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3
345
346    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v2s32
347    ; MOVREL: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
348    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
349    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
350    ; MOVREL: $m0 = COPY [[COPY2]]
351    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
352    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V2_]]
353    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v2s32
354    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
355    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
356    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
357    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
358    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2_]]
359    %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
360    %1:vgpr(s32) = COPY $vgpr2
361    %2:sgpr(s32) = COPY $sgpr3
362    %3:vgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
363    S_ENDPGM 0, implicit %3
364...
365
366---
367name: insert_vector_elt_vvs_s32_v3s32
368legalized: true
369regBankSelected: true
370
371body: |
372  bb.0:
373    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4
374
375    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v3s32
376    ; MOVREL: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
377    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
378    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
379    ; MOVREL: $m0 = COPY [[COPY2]]
380    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_MOVREL_B32_V3 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
381    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V3_]]
382    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v3s32
383    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
384    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
385    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
386    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
387    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3_]]
388    %0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
389    %1:vgpr(s32) = COPY $vgpr3
390    %2:sgpr(s32) = COPY $sgpr4
391    %3:vgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
392    S_ENDPGM 0, implicit %3
393...
394
395---
396name: insert_vector_elt_vvs_s32_v4s32
397legalized: true
398regBankSelected: true
399
400body: |
401  bb.0:
402    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
403
404    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v4s32
405    ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
406    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
407    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
408    ; MOVREL: $m0 = COPY [[COPY2]]
409    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
410    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
411    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v4s32
412    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
413    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
414    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
415    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
416    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]]
417    %0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
418    %1:vgpr(s32) = COPY $vgpr3
419    %2:sgpr(s32) = COPY $sgpr4
420    %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
421    S_ENDPGM 0, implicit %3
422...
423
424---
425name: insert_vector_elt_vvs_s32_v5s32
426legalized: true
427regBankSelected: true
428
429body: |
430  bb.0:
431    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6
432
433    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v5s32
434    ; MOVREL: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
435    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
436    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
437    ; MOVREL: $m0 = COPY [[COPY2]]
438    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_MOVREL_B32_V5 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
439    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V5_]]
440    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v5s32
441    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
442    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
443    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
444    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
445    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5_]]
446    %0:vgpr(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
447    %1:vgpr(s32) = COPY $vgpr5
448    %2:sgpr(s32) = COPY $sgpr6
449    %3:vgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
450    S_ENDPGM 0, implicit %3
451...
452
453---
454name: insert_vector_elt_vvs_s32_v8s32
455legalized: true
456regBankSelected: true
457
458body: |
459  bb.0:
460    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
461
462    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32
463    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
464    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
465    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
466    ; MOVREL: $m0 = COPY [[COPY2]]
467    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
468    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
469    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32
470    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
471    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
472    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
473    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 3, implicit-def $m0, implicit $m0, implicit $exec
474    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
475    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
476    %1:vgpr(s32) = COPY $vgpr8
477    %2:sgpr(s32) = COPY $sgpr9
478    %3:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
479    S_ENDPGM 0, implicit %3
480...
481
482---
483name: insert_vector_elt_vvs_s32_v8s32_add_1
484legalized: true
485regBankSelected: true
486
487body: |
488  bb.0:
489    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
490
491    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
492    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
493    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
494    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
495    ; MOVREL: $m0 = COPY [[COPY2]]
496    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0, implicit $exec
497    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
498    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
499    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
500    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
501    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
502    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 11, implicit-def $m0, implicit $m0, implicit $exec
503    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
504    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
505    %1:vgpr(s32) = COPY $vgpr8
506    %2:sgpr(s32) = COPY $sgpr9
507    %3:sgpr(s32) = G_CONSTANT i32 1
508    %4:sgpr(s32) = G_ADD %2, %3
509    %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
510    S_ENDPGM 0, implicit %5
511...
512
513---
514name: insert_vector_elt_vvs_s32_v8s32_add_8
515legalized: true
516regBankSelected: true
517
518body: |
519  bb.0:
520    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
521
522    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
523    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
524    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
525    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
526    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
527    ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
528    ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
529    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
530    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
531    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
532    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
533    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
534    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
535    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
536    ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
537    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[S_ADD_I32_]], 3, implicit-def $m0, implicit $m0, implicit $exec
538    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
539    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
540    %1:vgpr(s32) = COPY $vgpr8
541    %2:sgpr(s32) = COPY $sgpr9
542    %3:sgpr(s32) = G_CONSTANT i32 8
543    %4:sgpr(s32) = G_ADD %2, %3
544    %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
545    S_ENDPGM 0, implicit %5
546...
547
548---
549name: insert_vector_elt_s_s32_v8s32_add_1
550legalized: true
551regBankSelected: true
552
553body: |
554  bb.0:
555    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
556
557    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
558    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
559    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
560    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
561    ; MOVREL: $m0 = COPY [[COPY2]]
562    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
563    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
564    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
565    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
566    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
567    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
568    ; GPRIDX: $m0 = COPY [[COPY2]]
569    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
570    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
571    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
572    %1:sgpr(s32) = COPY $sgpr8
573    %2:sgpr(s32) = COPY $sgpr9
574    %3:sgpr(s32) = G_CONSTANT i32 1
575    %4:sgpr(s32) = G_ADD %2, %3
576    %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
577    S_ENDPGM 0, implicit %5
578...
579
580---
581name: insert_vector_elt_s_s32_v8s32_add_8
582legalized: true
583regBankSelected: true
584
585body: |
586  bb.0:
587    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
588
589    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
590    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
591    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
592    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
593    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
594    ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
595    ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
596    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
597    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
598    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
599    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
600    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
601    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
602    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
603    ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
604    ; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
605    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 3, implicit $m0
606    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
607    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
608    %1:sgpr(s32) = COPY $sgpr8
609    %2:sgpr(s32) = COPY $sgpr9
610    %3:sgpr(s32) = G_CONSTANT i32 8
611    %4:sgpr(s32) = G_ADD %2, %3
612    %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
613    S_ENDPGM 0, implicit %5
614...
615
616# This should have been folded out in the legalizer, but make sure it
617# doesn't crash.
618---
619name: insert_vector_elt_s_s32_v4s32_const_idx
620legalized: true
621regBankSelected: true
622
623body: |
624  bb.0:
625    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
626
627    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
628    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
629    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
630    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
631    ; MOVREL: $m0 = COPY [[S_MOV_B32_]]
632    ; MOVREL: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
633    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
634    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32_const_idx
635    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
636    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
637    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
638    ; GPRIDX: $m0 = COPY [[S_MOV_B32_]]
639    ; GPRIDX: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0
640    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
641    %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
642    %1:sgpr(s32) = COPY $sgpr4
643    %2:sgpr(s32) = G_CONSTANT i32 0
644    %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
645    S_ENDPGM 0, implicit %3
646...
647
648---
649name: insert_vector_elt_v_s32_v4s32_const_idx
650legalized: true
651regBankSelected: true
652
653body: |
654  bb.0:
655    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
656
657    ; MOVREL-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
658    ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
659    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
660    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
661    ; MOVREL: $m0 = COPY [[S_MOV_B32_]]
662    ; MOVREL: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_MOVREL_B32_V4 [[COPY]], [[COPY1]], 3, implicit $m0, implicit $exec
663    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V4_]]
664    ; GPRIDX-LABEL: name: insert_vector_elt_v_s32_v4s32_const_idx
665    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
666    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
667    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
668    ; GPRIDX: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 [[COPY]], [[COPY1]], [[S_MOV_B32_]], 3, implicit-def $m0, implicit $m0, implicit $exec
669    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4_]]
670    %0:vgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
671    %1:sgpr(s32) = COPY $sgpr4
672    %2:sgpr(s32) = G_CONSTANT i32 0
673    %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
674    S_ENDPGM 0, implicit %3
675...
676