1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s
4
5---
6name: insert_vector_elt_s_s32_v2s32
7legalized: true
8regBankSelected: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
13
14    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v2s32
15    ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
16    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
17    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
18    ; MOVREL: $m0 = COPY [[COPY2]]
19    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_B32_V2 [[COPY]], [[COPY1]], 1, implicit $m0
20    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V2_]]
21    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v2s32
22    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
23    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
24    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
25    ; GPRIDX: $m0 = COPY [[COPY2]]
26    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_B32_V2 [[COPY]], [[COPY1]], 1, implicit $m0
27    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V2_]]
28    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
29    %1:sgpr(s32) = COPY $sgpr2
30    %2:sgpr(s32) = COPY $sgpr3
31    %3:sgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
32    S_ENDPGM 0, implicit %3
33...
34
35---
36name: insert_vector_elt_s_s32_v3s32
37legalized: true
38regBankSelected: true
39
40body: |
41  bb.0:
42    liveins: $sgpr0_sgpr1_sgpr2, $sgpr3, $sgpr4
43
44    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v3s32
45    ; MOVREL: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
46    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
47    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
48    ; MOVREL: $m0 = COPY [[COPY2]]
49    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V3_:%[0-9]+]]:sreg_96 = S_INDIRECT_REG_WRITE_B32_V3 [[COPY]], [[COPY1]], 1, implicit $m0
50    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V3_]]
51    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v3s32
52    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
53    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
54    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
55    ; GPRIDX: $m0 = COPY [[COPY2]]
56    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V3_:%[0-9]+]]:sreg_96 = S_INDIRECT_REG_WRITE_B32_V3 [[COPY]], [[COPY1]], 1, implicit $m0
57    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V3_]]
58    %0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
59    %1:sgpr(s32) = COPY $sgpr3
60    %2:sgpr(s32) = COPY $sgpr4
61    %3:sgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
62    S_ENDPGM 0, implicit %3
63...
64
65---
66name: insert_vector_elt_s_s32_v4s32
67legalized: true
68regBankSelected: true
69
70body: |
71  bb.0:
72    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
73
74    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v4s32
75    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
76    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
77    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
78    ; MOVREL: $m0 = COPY [[COPY2]]
79    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0
80    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V4_]]
81    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v4s32
82    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
83    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
84    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
85    ; GPRIDX: $m0 = COPY [[COPY2]]
86    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0
87    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V4_]]
88    %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
89    %1:sgpr(s32) = COPY $sgpr3
90    %2:sgpr(s32) = COPY $sgpr4
91    %3:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
92    S_ENDPGM 0, implicit %3
93...
94
95---
96name: insert_vector_elt_s_s32_v5s32
97legalized: true
98regBankSelected: true
99
100body: |
101  bb.0:
102    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr5, $sgpr6
103
104    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v5s32
105    ; MOVREL: [[COPY:%[0-9]+]]:sreg_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
106    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
107    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
108    ; MOVREL: $m0 = COPY [[COPY2]]
109    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V5_:%[0-9]+]]:sreg_160 = S_INDIRECT_REG_WRITE_B32_V5 [[COPY]], [[COPY1]], 1, implicit $m0
110    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V5_]]
111    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v5s32
112    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_160 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
113    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
114    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
115    ; GPRIDX: $m0 = COPY [[COPY2]]
116    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V5_:%[0-9]+]]:sreg_160 = S_INDIRECT_REG_WRITE_B32_V5 [[COPY]], [[COPY1]], 1, implicit $m0
117    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V5_]]
118    %0:sgpr(<5 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
119    %1:sgpr(s32) = COPY $sgpr5
120    %2:sgpr(s32) = COPY $sgpr6
121    %3:sgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
122    S_ENDPGM 0, implicit %3
123...
124
125---
126name: insert_vector_elt_s_s32_v8s32
127legalized: true
128regBankSelected: true
129
130body: |
131  bb.0:
132    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
133
134    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32
135    ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
136    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
137    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
138    ; MOVREL: $m0 = COPY [[COPY2]]
139    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
140    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
141    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32
142    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
143    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
144    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
145    ; GPRIDX: $m0 = COPY [[COPY2]]
146    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
147    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
148    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
149    %1:sgpr(s32) = COPY $sgpr8
150    %2:sgpr(s32) = COPY $sgpr9
151    %3:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
152    S_ENDPGM 0, implicit %3
153...
154
155---
156name: insert_vector_elt_s_s32_v16s32
157legalized: true
158regBankSelected: true
159
160body: |
161  bb.0:
162    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17
163
164    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v16s32
165    ; MOVREL: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
166    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
167    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
168    ; MOVREL: $m0 = COPY [[COPY2]]
169    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V16_:%[0-9]+]]:sreg_512 = S_INDIRECT_REG_WRITE_B32_V16 [[COPY]], [[COPY1]], 1, implicit $m0
170    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V16_]]
171    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v16s32
172    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
173    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16
174    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17
175    ; GPRIDX: $m0 = COPY [[COPY2]]
176    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V16_:%[0-9]+]]:sreg_512 = S_INDIRECT_REG_WRITE_B32_V16 [[COPY]], [[COPY1]], 1, implicit $m0
177    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V16_]]
178    %0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
179    %1:sgpr(s32) = COPY $sgpr16
180    %2:sgpr(s32) = COPY $sgpr17
181    %3:sgpr(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
182    S_ENDPGM 0, implicit %3
183...
184
185---
186name: extract_vector_elt_s_s32_v32s32
187legalized: true
188regBankSelected: true
189
190body: |
191  bb.0:
192    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40, $sgpr41
193
194    ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v32s32
195    ; MOVREL: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
196    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
197    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
198    ; MOVREL: $m0 = COPY [[COPY2]]
199    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V32_:%[0-9]+]]:sreg_1024 = S_INDIRECT_REG_WRITE_B32_V32 [[COPY]], [[COPY1]], 1, implicit $m0
200    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V32_]]
201    ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32
202    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
203    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
204    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr41
205    ; GPRIDX: $m0 = COPY [[COPY2]]
206    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V32_:%[0-9]+]]:sreg_1024 = S_INDIRECT_REG_WRITE_B32_V32 [[COPY]], [[COPY1]], 1, implicit $m0
207    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V32_]]
208    %0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
209    %1:sgpr(s32) = COPY $sgpr40
210    %2:sgpr(s32) = COPY $sgpr41
211    %3:sgpr(<32 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
212    S_ENDPGM 0, implicit %3
213...
214
215---
216name: insert_vector_elt_s_s64_v2s64
217legalized: true
218regBankSelected: true
219
220body: |
221  bb.0:
222    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6
223
224    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v2s64
225    ; MOVREL: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
226    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
227    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
228    ; MOVREL: $m0 = COPY [[COPY2]]
229    ; MOVREL: [[S_INDIRECT_REG_WRITE_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_B64_V2 [[COPY]], [[COPY1]], 35, implicit $m0
230    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V2_]]
231    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v2s64
232    ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
233    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
234    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
235    ; GPRIDX: $m0 = COPY [[COPY2]]
236    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_B64_V2 [[COPY]], [[COPY1]], 35, implicit $m0
237    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V2_]]
238    %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
239    %1:sgpr(s64) = COPY $sgpr4_sgpr5
240    %2:sgpr(s32) = COPY $sgpr6
241    %3:sgpr(<2 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
242    S_ENDPGM 0, implicit %3
243...
244
245---
246name: insert_vector_elt_s_s64_v4s64
247legalized: true
248regBankSelected: true
249
250body: |
251  bb.0:
252    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10
253
254    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v4s64
255    ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
256    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
257    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
258    ; MOVREL: $m0 = COPY [[COPY2]]
259    ; MOVREL: [[S_INDIRECT_REG_WRITE_B64_V4_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B64_V4 [[COPY]], [[COPY1]], 35, implicit $m0
260    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V4_]]
261    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v4s64
262    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
263    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
264    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
265    ; GPRIDX: $m0 = COPY [[COPY2]]
266    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B64_V4_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B64_V4 [[COPY]], [[COPY1]], 35, implicit $m0
267    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V4_]]
268    %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
269    %1:sgpr(s64) = COPY $sgpr8_sgpr9
270    %2:sgpr(s32) = COPY $sgpr10
271    %3:sgpr(<4 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
272    S_ENDPGM 0, implicit %3
273...
274
275---
276name: insert_vector_elt_s_s64_v8s64
277legalized: true
278regBankSelected: true
279
280body: |
281  bb.0:
282    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16_sgpr17, $sgpr18
283
284    ; MOVREL-LABEL: name: insert_vector_elt_s_s64_v8s64
285    ; MOVREL: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
286    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
287    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
288    ; MOVREL: $m0 = COPY [[COPY2]]
289    ; MOVREL: [[S_INDIRECT_REG_WRITE_B64_V8_:%[0-9]+]]:sreg_512 = S_INDIRECT_REG_WRITE_B64_V8 [[COPY]], [[COPY1]], 35, implicit $m0
290    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V8_]]
291    ; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v8s64
292    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
293    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
294    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
295    ; GPRIDX: $m0 = COPY [[COPY2]]
296    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B64_V8_:%[0-9]+]]:sreg_512 = S_INDIRECT_REG_WRITE_B64_V8 [[COPY]], [[COPY1]], 35, implicit $m0
297    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V8_]]
298    %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
299    %1:sgpr(s64) = COPY $sgpr16_sgpr17
300    %2:sgpr(s32) = COPY $sgpr18
301    %3:sgpr(<8 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
302    S_ENDPGM 0, implicit %3
303...
304
305---
306name: extract_vector_elt_s_s64_v16s64
307legalized: true
308regBankSelected: true
309
310body: |
311  bb.0:
312    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr42
313
314    ; MOVREL-LABEL: name: extract_vector_elt_s_s64_v16s64
315    ; MOVREL: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
316    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
317    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
318    ; MOVREL: $m0 = COPY [[COPY2]]
319    ; MOVREL: [[S_INDIRECT_REG_WRITE_B64_V16_:%[0-9]+]]:sreg_1024 = S_INDIRECT_REG_WRITE_B64_V16 [[COPY]], [[COPY1]], 35, implicit $m0
320    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V16_]]
321    ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64
322    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
323    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
324    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
325    ; GPRIDX: $m0 = COPY [[COPY2]]
326    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B64_V16_:%[0-9]+]]:sreg_1024 = S_INDIRECT_REG_WRITE_B64_V16 [[COPY]], [[COPY1]], 35, implicit $m0
327    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B64_V16_]]
328    %0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
329    %1:sgpr(s64) = COPY $sgpr40_sgpr41
330    %2:sgpr(s32) = COPY $sgpr42
331    %3:sgpr(<16 x s64>) = G_INSERT_VECTOR_ELT %0, %1, %2
332    S_ENDPGM 0, implicit %3
333...
334
335---
336name: insert_vector_elt_vvs_s32_v2s32
337legalized: true
338regBankSelected: true
339
340body: |
341  bb.0:
342    liveins: $vgpr0_vgpr1, $vgpr2, $sgpr3
343
344    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v2s32
345    ; MOVREL: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
346    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
347    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
348    ; MOVREL: $m0 = COPY [[COPY2]]
349    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_B32_V2 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
350    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V2_]]
351    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v2s32
352    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
353    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
354    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
355    ; GPRIDX: S_SET_GPR_IDX_ON [[COPY2]], 8, implicit-def $m0, implicit $m0
356    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V2_:%[0-9]+]]:vreg_64 = V_INDIRECT_REG_WRITE_B32_V2 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
357    ; GPRIDX: S_SET_GPR_IDX_OFF
358    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V2_]]
359    %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
360    %1:vgpr(s32) = COPY $vgpr2
361    %2:sgpr(s32) = COPY $sgpr3
362    %3:vgpr(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
363    S_ENDPGM 0, implicit %3
364...
365
366---
367name: insert_vector_elt_vvs_s32_v3s32
368legalized: true
369regBankSelected: true
370
371body: |
372  bb.0:
373    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3, $sgpr4
374
375    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v3s32
376    ; MOVREL: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
377    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
378    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
379    ; MOVREL: $m0 = COPY [[COPY2]]
380    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_B32_V3 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
381    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V3_]]
382    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v3s32
383    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
384    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
385    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
386    ; GPRIDX: S_SET_GPR_IDX_ON [[COPY2]], 8, implicit-def $m0, implicit $m0
387    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V3_:%[0-9]+]]:vreg_96 = V_INDIRECT_REG_WRITE_B32_V3 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
388    ; GPRIDX: S_SET_GPR_IDX_OFF
389    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V3_]]
390    %0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
391    %1:vgpr(s32) = COPY $vgpr3
392    %2:sgpr(s32) = COPY $sgpr4
393    %3:vgpr(<3 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
394    S_ENDPGM 0, implicit %3
395...
396
397---
398name: insert_vector_elt_vvs_s32_v4s32
399legalized: true
400regBankSelected: true
401
402body: |
403  bb.0:
404    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
405
406    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v4s32
407    ; MOVREL: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
408    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
409    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
410    ; MOVREL: $m0 = COPY [[COPY2]]
411    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
412    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V4_]]
413    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v4s32
414    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
415    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
416    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
417    ; GPRIDX: S_SET_GPR_IDX_ON [[COPY2]], 8, implicit-def $m0, implicit $m0
418    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V4_:%[0-9]+]]:vreg_128 = V_INDIRECT_REG_WRITE_B32_V4 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
419    ; GPRIDX: S_SET_GPR_IDX_OFF
420    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V4_]]
421    %0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
422    %1:vgpr(s32) = COPY $vgpr3
423    %2:sgpr(s32) = COPY $sgpr4
424    %3:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
425    S_ENDPGM 0, implicit %3
426...
427
428---
429name: insert_vector_elt_vvs_s32_v5s32
430legalized: true
431regBankSelected: true
432
433body: |
434  bb.0:
435    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5, $sgpr6
436
437    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v5s32
438    ; MOVREL: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
439    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
440    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
441    ; MOVREL: $m0 = COPY [[COPY2]]
442    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_B32_V5 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
443    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V5_]]
444    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v5s32
445    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_160 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
446    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr5
447    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
448    ; GPRIDX: S_SET_GPR_IDX_ON [[COPY2]], 8, implicit-def $m0, implicit $m0
449    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V5_:%[0-9]+]]:vreg_160 = V_INDIRECT_REG_WRITE_B32_V5 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
450    ; GPRIDX: S_SET_GPR_IDX_OFF
451    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V5_]]
452    %0:vgpr(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
453    %1:vgpr(s32) = COPY $vgpr5
454    %2:sgpr(s32) = COPY $sgpr6
455    %3:vgpr(<5 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
456    S_ENDPGM 0, implicit %3
457...
458
459---
460name: insert_vector_elt_vvs_s32_v8s32
461legalized: true
462regBankSelected: true
463
464body: |
465  bb.0:
466    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
467
468    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32
469    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
470    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
471    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
472    ; MOVREL: $m0 = COPY [[COPY2]]
473    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
474    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
475    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32
476    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
477    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
478    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
479    ; GPRIDX: S_SET_GPR_IDX_ON [[COPY2]], 8, implicit-def $m0, implicit $m0
480    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
481    ; GPRIDX: S_SET_GPR_IDX_OFF
482    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
483    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
484    %1:vgpr(s32) = COPY $vgpr8
485    %2:sgpr(s32) = COPY $sgpr9
486    %3:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
487    S_ENDPGM 0, implicit %3
488...
489
490---
491name: insert_vector_elt_vvs_s32_v8s32_add_1
492legalized: true
493regBankSelected: true
494
495body: |
496  bb.0:
497    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
498
499    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
500    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
501    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
502    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
503    ; MOVREL: $m0 = COPY [[COPY2]]
504    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 2, implicit $m0, implicit $exec
505    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
506    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
507    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
508    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
509    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
510    ; GPRIDX: S_SET_GPR_IDX_ON [[COPY2]], 8, implicit-def $m0, implicit $m0
511    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 2, implicit $m0, implicit $exec
512    ; GPRIDX: S_SET_GPR_IDX_OFF
513    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
514    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
515    %1:vgpr(s32) = COPY $vgpr8
516    %2:sgpr(s32) = COPY $sgpr9
517    %3:sgpr(s32) = G_CONSTANT i32 1
518    %4:sgpr(s32) = G_ADD %2, %3
519    %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
520    S_ENDPGM 0, implicit %5
521...
522
523---
524name: insert_vector_elt_vvs_s32_v8s32_add_8
525legalized: true
526regBankSelected: true
527
528body: |
529  bb.0:
530    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
531
532    ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
533    ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
534    ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
535    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
536    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
537    ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
538    ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
539    ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
540    ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
541    ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
542    ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
543    ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
544    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
545    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
546    ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
547    ; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 8, implicit-def $m0, implicit $m0
548    ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
549    ; GPRIDX: S_SET_GPR_IDX_OFF
550    ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
551    %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
552    %1:vgpr(s32) = COPY $vgpr8
553    %2:sgpr(s32) = COPY $sgpr9
554    %3:sgpr(s32) = G_CONSTANT i32 8
555    %4:sgpr(s32) = G_ADD %2, %3
556    %5:vgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
557    S_ENDPGM 0, implicit %5
558...
559
560---
561name: insert_vector_elt_s_s32_v8s32_add_1
562legalized: true
563regBankSelected: true
564
565body: |
566  bb.0:
567    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
568
569    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
570    ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
571    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
572    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
573    ; MOVREL: $m0 = COPY [[COPY2]]
574    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 2, implicit $m0
575    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
576    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
577    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
578    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
579    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
580    ; GPRIDX: $m0 = COPY [[COPY2]]
581    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 2, implicit $m0
582    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
583    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
584    %1:sgpr(s32) = COPY $sgpr8
585    %2:sgpr(s32) = COPY $sgpr9
586    %3:sgpr(s32) = G_CONSTANT i32 1
587    %4:sgpr(s32) = G_ADD %2, %3
588    %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
589    S_ENDPGM 0, implicit %5
590...
591
592---
593name: insert_vector_elt_s_s32_v8s32_add_8
594legalized: true
595regBankSelected: true
596
597body: |
598  bb.0:
599    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
600
601    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
602    ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
603    ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
604    ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
605    ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
606    ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
607    ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
608    ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
609    ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
610    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
611    ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
612    ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
613    ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
614    ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
615    ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
616    ; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
617    ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
618    ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
619    %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
620    %1:sgpr(s32) = COPY $sgpr8
621    %2:sgpr(s32) = COPY $sgpr9
622    %3:sgpr(s32) = G_CONSTANT i32 8
623    %4:sgpr(s32) = G_ADD %2, %3
624    %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
625    S_ENDPGM 0, implicit %5
626...
627