1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
6
7define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
8; GFX6-LABEL: s_fshr_i7:
9; GFX6:       ; %bb.0:
10; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
11; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
12; GFX6-NEXT:    s_sub_i32 s3, 0, 7
13; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
14; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
15; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
16; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
17; GFX6-NEXT:    s_movk_i32 s3, 0x7f
18; GFX6-NEXT:    s_and_b32 s2, s2, s3
19; GFX6-NEXT:    s_and_b32 s1, s1, s3
20; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
21; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
22; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
23; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 7
24; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
25; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 7, v0
26; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
27; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
28; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 7, v0
29; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
30; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
31; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 6, v0
32; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
33; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
34; GFX6-NEXT:    v_lshl_b32_e32 v1, s0, v1
35; GFX6-NEXT:    v_lshr_b32_e32 v0, s1, v0
36; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
37; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
38; GFX6-NEXT:    ; return to shader part epilog
39;
40; GFX8-LABEL: s_fshr_i7:
41; GFX8:       ; %bb.0:
42; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
43; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
44; GFX8-NEXT:    s_sub_i32 s3, 0, 7
45; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
46; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
47; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
48; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
49; GFX8-NEXT:    s_movk_i32 s3, 0x7f
50; GFX8-NEXT:    s_and_b32 s2, s2, s3
51; GFX8-NEXT:    s_and_b32 s1, s1, s3
52; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
53; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
54; GFX8-NEXT:    v_mul_hi_u32 v0, s2, v0
55; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 7
56; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
57; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 7, v0
58; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
59; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
60; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 7, v0
61; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
62; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
63; GFX8-NEXT:    v_sub_u16_e32 v1, 6, v0
64; GFX8-NEXT:    v_and_b32_e32 v0, s3, v0
65; GFX8-NEXT:    v_and_b32_e32 v1, s3, v1
66; GFX8-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
67; GFX8-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
68; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
69; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
70; GFX8-NEXT:    ; return to shader part epilog
71;
72; GFX9-LABEL: s_fshr_i7:
73; GFX9:       ; %bb.0:
74; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
75; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
76; GFX9-NEXT:    s_sub_i32 s3, 0, 7
77; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
78; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
79; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
80; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
81; GFX9-NEXT:    s_movk_i32 s3, 0x7f
82; GFX9-NEXT:    s_and_b32 s2, s2, s3
83; GFX9-NEXT:    s_and_b32 s1, s1, s3
84; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
85; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
86; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
87; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 7
88; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
89; GFX9-NEXT:    v_subrev_u32_e32 v1, 7, v0
90; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
91; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
92; GFX9-NEXT:    v_subrev_u32_e32 v1, 7, v0
93; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
94; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
95; GFX9-NEXT:    v_sub_u16_e32 v1, 6, v0
96; GFX9-NEXT:    v_and_b32_e32 v0, s3, v0
97; GFX9-NEXT:    v_and_b32_e32 v1, s3, v1
98; GFX9-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
99; GFX9-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
100; GFX9-NEXT:    v_or_b32_e32 v0, v1, v0
101; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
102; GFX9-NEXT:    ; return to shader part epilog
103;
104; GFX10-LABEL: s_fshr_i7:
105; GFX10:       ; %bb.0:
106; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
107; GFX10-NEXT:    s_sub_i32 s3, 0, 7
108; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
109; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
110; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
111; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
112; GFX10-NEXT:    v_mul_lo_u32 v1, s3, v0
113; GFX10-NEXT:    s_movk_i32 s3, 0x7f
114; GFX10-NEXT:    s_and_b32 s2, s2, s3
115; GFX10-NEXT:    s_and_b32 s1, s1, s3
116; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
117; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
118; GFX10-NEXT:    v_mul_hi_u32 v0, s2, v0
119; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 7
120; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
121; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
122; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
123; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
124; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
125; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
126; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
127; GFX10-NEXT:    v_sub_nc_u16_e64 v1, 6, v0
128; GFX10-NEXT:    v_and_b32_e32 v0, s3, v0
129; GFX10-NEXT:    v_and_b32_e32 v1, s3, v1
130; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
131; GFX10-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
132; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
133; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
134; GFX10-NEXT:    ; return to shader part epilog
135  %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
136  ret i7 %result
137}
138
139define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
140; GFX6-LABEL: v_fshr_i7:
141; GFX6:       ; %bb.0:
142; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
143; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
144; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
145; GFX6-NEXT:    s_sub_i32 s4, 0, 7
146; GFX6-NEXT:    v_and_b32_e32 v2, 0x7f, v2
147; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
148; GFX6-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
149; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
150; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
151; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
152; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
153; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
154; GFX6-NEXT:    v_mov_b32_e32 v4, 0x7f
155; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
156; GFX6-NEXT:    v_mul_lo_u32 v3, v3, 7
157; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
158; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 7, v2
159; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
160; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
161; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 7, v2
162; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
163; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
164; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 6, v2
165; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
166; GFX6-NEXT:    v_and_b32_e32 v3, v3, v4
167; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
168; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
169; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
170; GFX6-NEXT:    s_setpc_b64 s[30:31]
171;
172; GFX8-LABEL: v_fshr_i7:
173; GFX8:       ; %bb.0:
174; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
175; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
176; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
177; GFX8-NEXT:    s_sub_i32 s4, 0, 7
178; GFX8-NEXT:    v_and_b32_e32 v2, 0x7f, v2
179; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
180; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
181; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
182; GFX8-NEXT:    v_mul_lo_u32 v4, s4, v3
183; GFX8-NEXT:    v_mul_hi_u32 v4, v3, v4
184; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v4
185; GFX8-NEXT:    v_mul_hi_u32 v3, v2, v3
186; GFX8-NEXT:    v_mov_b32_e32 v4, 0x7f
187; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
188; GFX8-NEXT:    v_mul_lo_u32 v3, v3, 7
189; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
190; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 7, v2
191; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
192; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
193; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 7, v2
194; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
195; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
196; GFX8-NEXT:    v_sub_u16_e32 v3, 6, v2
197; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
198; GFX8-NEXT:    v_and_b32_e32 v3, v3, v4
199; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
200; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
201; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
202; GFX8-NEXT:    s_setpc_b64 s[30:31]
203;
204; GFX9-LABEL: v_fshr_i7:
205; GFX9:       ; %bb.0:
206; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
207; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
208; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
209; GFX9-NEXT:    s_sub_i32 s4, 0, 7
210; GFX9-NEXT:    v_and_b32_e32 v2, 0x7f, v2
211; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
212; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
213; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
214; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v3
215; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
216; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
217; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
218; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7f
219; GFX9-NEXT:    v_and_b32_e32 v1, v1, v4
220; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 7
221; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
222; GFX9-NEXT:    v_subrev_u32_e32 v3, 7, v2
223; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
224; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
225; GFX9-NEXT:    v_subrev_u32_e32 v3, 7, v2
226; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
227; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
228; GFX9-NEXT:    v_sub_u16_e32 v3, 6, v2
229; GFX9-NEXT:    v_and_b32_e32 v2, v2, v4
230; GFX9-NEXT:    v_and_b32_e32 v3, v3, v4
231; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
232; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
233; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
234; GFX9-NEXT:    s_setpc_b64 s[30:31]
235;
236; GFX10-LABEL: v_fshr_i7:
237; GFX10:       ; %bb.0:
238; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
239; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
240; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
241; GFX10-NEXT:    s_sub_i32 s4, 0, 7
242; GFX10-NEXT:    v_and_b32_e32 v2, 0x7f, v2
243; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
244; GFX10-NEXT:    v_and_b32_e32 v1, 0x7f, v1
245; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
246; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
247; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
248; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v3
249; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
250; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
251; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
252; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 7
253; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
254; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
255; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
256; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
257; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
258; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
259; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
260; GFX10-NEXT:    v_mov_b32_e32 v3, 0x7f
261; GFX10-NEXT:    v_sub_nc_u16_e64 v4, 6, v2
262; GFX10-NEXT:    v_and_b32_e32 v2, v2, v3
263; GFX10-NEXT:    v_and_b32_e32 v7, v4, v3
264; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
265; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v7, v0
266; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
267; GFX10-NEXT:    s_setpc_b64 s[30:31]
268  %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
269  ret i7 %result
270}
271
272define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
273; GFX6-LABEL: s_fshr_i8:
274; GFX6:       ; %bb.0:
275; GFX6-NEXT:    s_and_b32 s3, s2, 7
276; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
277; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
278; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
279; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
280; GFX6-NEXT:    s_lshr_b32 s1, s1, s3
281; GFX6-NEXT:    s_or_b32 s0, s0, s1
282; GFX6-NEXT:    ; return to shader part epilog
283;
284; GFX8-LABEL: s_fshr_i8:
285; GFX8:       ; %bb.0:
286; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
287; GFX8-NEXT:    s_and_b32 s3, s2, 7
288; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
289; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
290; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
291; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
292; GFX8-NEXT:    s_lshr_b32 s1, s1, s3
293; GFX8-NEXT:    s_or_b32 s0, s0, s1
294; GFX8-NEXT:    ; return to shader part epilog
295;
296; GFX9-LABEL: s_fshr_i8:
297; GFX9:       ; %bb.0:
298; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
299; GFX9-NEXT:    s_and_b32 s3, s2, 7
300; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
301; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
302; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
303; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
304; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
305; GFX9-NEXT:    s_or_b32 s0, s0, s1
306; GFX9-NEXT:    ; return to shader part epilog
307;
308; GFX10-LABEL: s_fshr_i8:
309; GFX10:       ; %bb.0:
310; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
311; GFX10-NEXT:    s_and_b32 s3, s2, 7
312; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
313; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
314; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
315; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
316; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
317; GFX10-NEXT:    s_or_b32 s0, s0, s1
318; GFX10-NEXT:    ; return to shader part epilog
319  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 %amt)
320  ret i8 %result
321}
322
323define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
324; GFX6-LABEL: v_fshr_i8:
325; GFX6:       ; %bb.0:
326; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
327; GFX6-NEXT:    v_and_b32_e32 v3, 7, v2
328; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
329; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
330; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
331; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
332; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
333; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v3, v1
334; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
335; GFX6-NEXT:    s_setpc_b64 s[30:31]
336;
337; GFX8-LABEL: v_fshr_i8:
338; GFX8:       ; %bb.0:
339; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
340; GFX8-NEXT:    v_and_b32_e32 v3, 7, v2
341; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
342; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
343; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
344; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
345; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
346; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
347; GFX8-NEXT:    s_setpc_b64 s[30:31]
348;
349; GFX9-LABEL: v_fshr_i8:
350; GFX9:       ; %bb.0:
351; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
352; GFX9-NEXT:    v_and_b32_e32 v3, 7, v2
353; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
354; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
355; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
356; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
357; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
358; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
359; GFX9-NEXT:    s_setpc_b64 s[30:31]
360;
361; GFX10-LABEL: v_fshr_i8:
362; GFX10:       ; %bb.0:
363; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
364; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
365; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
366; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
367; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
368; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
369; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
370; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
371; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v3, v0
372; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
373; GFX10-NEXT:    s_setpc_b64 s[30:31]
374  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 %amt)
375  ret i8 %result
376}
377
378define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
379; GFX6-LABEL: s_fshr_i8_4:
380; GFX6:       ; %bb.0:
381; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
382; GFX6-NEXT:    s_lshl_b32 s0, s0, 4
383; GFX6-NEXT:    s_lshr_b32 s1, s1, 4
384; GFX6-NEXT:    s_or_b32 s0, s0, s1
385; GFX6-NEXT:    ; return to shader part epilog
386;
387; GFX8-LABEL: s_fshr_i8_4:
388; GFX8:       ; %bb.0:
389; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
390; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
391; GFX8-NEXT:    s_lshl_b32 s0, s0, 4
392; GFX8-NEXT:    s_lshr_b32 s1, s1, 4
393; GFX8-NEXT:    s_or_b32 s0, s0, s1
394; GFX8-NEXT:    ; return to shader part epilog
395;
396; GFX9-LABEL: s_fshr_i8_4:
397; GFX9:       ; %bb.0:
398; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
399; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
400; GFX9-NEXT:    s_lshl_b32 s0, s0, 4
401; GFX9-NEXT:    s_lshr_b32 s1, s1, 4
402; GFX9-NEXT:    s_or_b32 s0, s0, s1
403; GFX9-NEXT:    ; return to shader part epilog
404;
405; GFX10-LABEL: s_fshr_i8_4:
406; GFX10:       ; %bb.0:
407; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
408; GFX10-NEXT:    s_lshl_b32 s0, s0, 4
409; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
410; GFX10-NEXT:    s_lshr_b32 s1, s1, 4
411; GFX10-NEXT:    s_or_b32 s0, s0, s1
412; GFX10-NEXT:    ; return to shader part epilog
413  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
414  ret i8 %result
415}
416
417define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
418; GFX6-LABEL: v_fshr_i8_4:
419; GFX6:       ; %bb.0:
420; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
421; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
422; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
423; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 4, v1
424; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
425; GFX6-NEXT:    s_setpc_b64 s[30:31]
426;
427; GFX8-LABEL: v_fshr_i8_4:
428; GFX8:       ; %bb.0:
429; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
430; GFX8-NEXT:    v_mov_b32_e32 v2, 4
431; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
432; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
433; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
434; GFX8-NEXT:    s_setpc_b64 s[30:31]
435;
436; GFX9-LABEL: v_fshr_i8_4:
437; GFX9:       ; %bb.0:
438; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
439; GFX9-NEXT:    s_mov_b32 s4, 4
440; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
441; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
442; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
443; GFX9-NEXT:    s_setpc_b64 s[30:31]
444;
445; GFX10-LABEL: v_fshr_i8_4:
446; GFX10:       ; %bb.0:
447; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
448; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
449; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
450; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 4, v0
451; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 4, v1
452; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
453; GFX10-NEXT:    s_setpc_b64 s[30:31]
454  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
455  ret i8 %result
456}
457
458define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
459; GFX6-LABEL: s_fshr_i8_5:
460; GFX6:       ; %bb.0:
461; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
462; GFX6-NEXT:    s_lshl_b32 s0, s0, 3
463; GFX6-NEXT:    s_lshr_b32 s1, s1, 5
464; GFX6-NEXT:    s_or_b32 s0, s0, s1
465; GFX6-NEXT:    ; return to shader part epilog
466;
467; GFX8-LABEL: s_fshr_i8_5:
468; GFX8:       ; %bb.0:
469; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
470; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
471; GFX8-NEXT:    s_lshl_b32 s0, s0, 3
472; GFX8-NEXT:    s_lshr_b32 s1, s1, 5
473; GFX8-NEXT:    s_or_b32 s0, s0, s1
474; GFX8-NEXT:    ; return to shader part epilog
475;
476; GFX9-LABEL: s_fshr_i8_5:
477; GFX9:       ; %bb.0:
478; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
479; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
480; GFX9-NEXT:    s_lshl_b32 s0, s0, 3
481; GFX9-NEXT:    s_lshr_b32 s1, s1, 5
482; GFX9-NEXT:    s_or_b32 s0, s0, s1
483; GFX9-NEXT:    ; return to shader part epilog
484;
485; GFX10-LABEL: s_fshr_i8_5:
486; GFX10:       ; %bb.0:
487; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
488; GFX10-NEXT:    s_lshl_b32 s0, s0, 3
489; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
490; GFX10-NEXT:    s_lshr_b32 s1, s1, 5
491; GFX10-NEXT:    s_or_b32 s0, s0, s1
492; GFX10-NEXT:    ; return to shader part epilog
493  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
494  ret i8 %result
495}
496
497define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
498; GFX6-LABEL: v_fshr_i8_5:
499; GFX6:       ; %bb.0:
500; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
501; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
502; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
503; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 5, v1
504; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
505; GFX6-NEXT:    s_setpc_b64 s[30:31]
506;
507; GFX8-LABEL: v_fshr_i8_5:
508; GFX8:       ; %bb.0:
509; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
510; GFX8-NEXT:    v_mov_b32_e32 v2, 5
511; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 3, v0
512; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
513; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
514; GFX8-NEXT:    s_setpc_b64 s[30:31]
515;
516; GFX9-LABEL: v_fshr_i8_5:
517; GFX9:       ; %bb.0:
518; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
519; GFX9-NEXT:    v_mov_b32_e32 v2, 5
520; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 3, v0
521; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
522; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
523; GFX9-NEXT:    s_setpc_b64 s[30:31]
524;
525; GFX10-LABEL: v_fshr_i8_5:
526; GFX10:       ; %bb.0:
527; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
528; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
529; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
530; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 3, v0
531; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 5, v1
532; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
533; GFX10-NEXT:    s_setpc_b64 s[30:31]
534  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
535  ret i8 %result
536}
537
538define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 inreg %amt.arg) {
539; GFX6-LABEL: s_fshr_v2i8:
540; GFX6:       ; %bb.0:
541; GFX6-NEXT:    s_movk_i32 s7, 0xff
542; GFX6-NEXT:    s_lshr_b32 s3, s0, 8
543; GFX6-NEXT:    s_lshr_b32 s4, s1, 8
544; GFX6-NEXT:    s_lshr_b32 s5, s2, 8
545; GFX6-NEXT:    s_and_b32 s6, s2, 7
546; GFX6-NEXT:    s_and_b32 s1, s1, s7
547; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
548; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
549; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
550; GFX6-NEXT:    s_lshr_b32 s1, s1, s6
551; GFX6-NEXT:    s_andn2_b32 s2, 7, s5
552; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
553; GFX6-NEXT:    s_or_b32 s0, s0, s1
554; GFX6-NEXT:    s_lshl_b32 s2, s3, s2
555; GFX6-NEXT:    s_and_b32 s1, s5, 7
556; GFX6-NEXT:    s_and_b32 s3, s4, s7
557; GFX6-NEXT:    s_lshr_b32 s1, s3, s1
558; GFX6-NEXT:    s_or_b32 s1, s2, s1
559; GFX6-NEXT:    s_and_b32 s1, s1, s7
560; GFX6-NEXT:    s_and_b32 s0, s0, s7
561; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
562; GFX6-NEXT:    s_or_b32 s0, s0, s1
563; GFX6-NEXT:    ; return to shader part epilog
564;
565; GFX8-LABEL: s_fshr_v2i8:
566; GFX8:       ; %bb.0:
567; GFX8-NEXT:    s_lshr_b32 s3, s0, 8
568; GFX8-NEXT:    s_lshr_b32 s5, s2, 8
569; GFX8-NEXT:    s_and_b32 s6, s2, 7
570; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
571; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
572; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
573; GFX8-NEXT:    s_movk_i32 s2, 0xff
574; GFX8-NEXT:    s_lshr_b32 s4, s1, 8
575; GFX8-NEXT:    s_and_b32 s1, s1, s2
576; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
577; GFX8-NEXT:    s_and_b32 s4, s4, s2
578; GFX8-NEXT:    s_lshr_b32 s1, s1, s6
579; GFX8-NEXT:    s_or_b32 s0, s0, s1
580; GFX8-NEXT:    s_and_b32 s1, s5, 7
581; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
582; GFX8-NEXT:    s_andn2_b32 s5, 7, s5
583; GFX8-NEXT:    s_lshl_b32 s3, s3, 1
584; GFX8-NEXT:    s_lshl_b32 s3, s3, s5
585; GFX8-NEXT:    s_lshr_b32 s1, s4, s1
586; GFX8-NEXT:    s_or_b32 s1, s3, s1
587; GFX8-NEXT:    s_and_b32 s0, s0, s2
588; GFX8-NEXT:    s_and_b32 s1, s1, s2
589; GFX8-NEXT:    s_bfe_u32 s2, 8, 0x100000
590; GFX8-NEXT:    s_lshl_b32 s1, s1, s2
591; GFX8-NEXT:    s_or_b32 s0, s0, s1
592; GFX8-NEXT:    ; return to shader part epilog
593;
594; GFX9-LABEL: s_fshr_v2i8:
595; GFX9:       ; %bb.0:
596; GFX9-NEXT:    s_lshr_b32 s3, s0, 8
597; GFX9-NEXT:    s_lshr_b32 s5, s2, 8
598; GFX9-NEXT:    s_and_b32 s6, s2, 7
599; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
600; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
601; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
602; GFX9-NEXT:    s_movk_i32 s2, 0xff
603; GFX9-NEXT:    s_lshr_b32 s4, s1, 8
604; GFX9-NEXT:    s_and_b32 s1, s1, s2
605; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
606; GFX9-NEXT:    s_and_b32 s4, s4, s2
607; GFX9-NEXT:    s_lshr_b32 s1, s1, s6
608; GFX9-NEXT:    s_or_b32 s0, s0, s1
609; GFX9-NEXT:    s_and_b32 s1, s5, 7
610; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
611; GFX9-NEXT:    s_andn2_b32 s5, 7, s5
612; GFX9-NEXT:    s_lshl_b32 s3, s3, 1
613; GFX9-NEXT:    s_lshl_b32 s3, s3, s5
614; GFX9-NEXT:    s_lshr_b32 s1, s4, s1
615; GFX9-NEXT:    s_or_b32 s1, s3, s1
616; GFX9-NEXT:    s_and_b32 s0, s0, s2
617; GFX9-NEXT:    s_and_b32 s1, s1, s2
618; GFX9-NEXT:    s_bfe_u32 s2, 8, 0x100000
619; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
620; GFX9-NEXT:    s_or_b32 s0, s0, s1
621; GFX9-NEXT:    ; return to shader part epilog
622;
623; GFX10-LABEL: s_fshr_v2i8:
624; GFX10:       ; %bb.0:
625; GFX10-NEXT:    s_lshr_b32 s4, s1, 8
626; GFX10-NEXT:    s_movk_i32 s7, 0xff
627; GFX10-NEXT:    s_lshr_b32 s3, s0, 8
628; GFX10-NEXT:    s_and_b32 s4, s4, s7
629; GFX10-NEXT:    s_lshr_b32 s5, s2, 8
630; GFX10-NEXT:    s_and_b32 s6, s2, 7
631; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
632; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
633; GFX10-NEXT:    s_and_b32 s1, s1, s7
634; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
635; GFX10-NEXT:    s_and_b32 s2, s5, 7
636; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
637; GFX10-NEXT:    s_andn2_b32 s5, 7, s5
638; GFX10-NEXT:    s_lshl_b32 s3, s3, 1
639; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
640; GFX10-NEXT:    s_lshl_b32 s3, s3, s5
641; GFX10-NEXT:    s_lshr_b32 s2, s4, s2
642; GFX10-NEXT:    s_lshr_b32 s1, s1, s6
643; GFX10-NEXT:    s_or_b32 s2, s3, s2
644; GFX10-NEXT:    s_or_b32 s0, s0, s1
645; GFX10-NEXT:    s_and_b32 s1, s2, s7
646; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
647; GFX10-NEXT:    s_and_b32 s0, s0, s7
648; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
649; GFX10-NEXT:    s_or_b32 s0, s0, s1
650; GFX10-NEXT:    ; return to shader part epilog
651  %lhs = bitcast i16 %lhs.arg to <2 x i8>
652  %rhs = bitcast i16 %rhs.arg to <2 x i8>
653  %amt = bitcast i16 %amt.arg to <2 x i8>
654  %result = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %lhs, <2 x i8> %rhs, <2 x i8> %amt)
655  %cast.result = bitcast <2 x i8> %result to i16
656  ret i16 %cast.result
657}
658
659define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
660; GFX6-LABEL: v_fshr_v2i8:
661; GFX6:       ; %bb.0:
662; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
663; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
664; GFX6-NEXT:    v_and_b32_e32 v6, 7, v2
665; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
666; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
667; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
668; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
669; GFX6-NEXT:    s_movk_i32 s4, 0xff
670; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
671; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
672; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
673; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v5
674; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v6, v1
675; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
676; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
677; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
678; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v2, v3
679; GFX6-NEXT:    v_and_b32_e32 v1, 7, v5
680; GFX6-NEXT:    v_and_b32_e32 v3, s4, v4
681; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v1, v3
682; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
683; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
684; GFX6-NEXT:    v_and_b32_e32 v0, 0xff, v0
685; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
686; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
687; GFX6-NEXT:    s_setpc_b64 s[30:31]
688;
689; GFX8-LABEL: v_fshr_v2i8:
690; GFX8:       ; %bb.0:
691; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
692; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
693; GFX8-NEXT:    v_and_b32_e32 v6, 7, v2
694; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
695; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
696; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
697; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
698; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
699; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
700; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v5
701; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
702; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
703; GFX8-NEXT:    v_and_b32_e32 v1, 7, v5
704; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
705; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
706; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v2, v3
707; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
708; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
709; GFX8-NEXT:    v_and_b32_e32 v1, 0xff, v1
710; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
711; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
712; GFX8-NEXT:    s_setpc_b64 s[30:31]
713;
714; GFX9-LABEL: v_fshr_v2i8:
715; GFX9:       ; %bb.0:
716; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
717; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
718; GFX9-NEXT:    v_and_b32_e32 v6, 7, v2
719; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
720; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
721; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
722; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
723; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
724; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
725; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v5
726; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
727; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
728; GFX9-NEXT:    v_and_b32_e32 v1, 7, v5
729; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
730; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
731; GFX9-NEXT:    v_lshlrev_b16_e32 v2, v2, v3
732; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
733; GFX9-NEXT:    v_or_b32_e32 v1, v2, v1
734; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v1
735; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
736; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
737; GFX9-NEXT:    s_setpc_b64 s[30:31]
738;
739; GFX10-LABEL: v_fshr_v2i8:
740; GFX10:       ; %bb.0:
741; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
742; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
743; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v2
744; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 8, v0
745; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
746; GFX10-NEXT:    s_movk_i32 s4, 0xff
747; GFX10-NEXT:    v_and_b32_e32 v7, 7, v2
748; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v3
749; GFX10-NEXT:    v_xor_b32_e32 v2, -1, v2
750; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
751; GFX10-NEXT:    v_and_b32_e32 v5, s4, v5
752; GFX10-NEXT:    v_lshlrev_b16_e64 v4, 1, v4
753; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
754; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
755; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
756; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
757; GFX10-NEXT:    v_lshrrev_b16_e64 v3, v3, v5
758; GFX10-NEXT:    v_lshlrev_b16_e64 v4, v6, v4
759; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v7, v1
760; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v2, v0
761; GFX10-NEXT:    v_or_b32_e32 v2, v4, v3
762; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
763; GFX10-NEXT:    v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
764; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
765; GFX10-NEXT:    s_setpc_b64 s[30:31]
766  %lhs = bitcast i16 %lhs.arg to <2 x i8>
767  %rhs = bitcast i16 %rhs.arg to <2 x i8>
768  %amt = bitcast i16 %amt.arg to <2 x i8>
769  %result = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %lhs, <2 x i8> %rhs, <2 x i8> %amt)
770  %cast.result = bitcast <2 x i8> %result to i16
771  ret i16 %cast.result
772}
773
774define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 inreg %amt.arg) {
775; GFX6-LABEL: s_fshr_v4i8:
776; GFX6:       ; %bb.0:
777; GFX6-NEXT:    s_movk_i32 s13, 0xff
778; GFX6-NEXT:    s_lshr_b32 s3, s0, 8
779; GFX6-NEXT:    s_lshr_b32 s4, s0, 16
780; GFX6-NEXT:    s_lshr_b32 s5, s0, 24
781; GFX6-NEXT:    s_lshr_b32 s6, s1, 8
782; GFX6-NEXT:    s_lshr_b32 s7, s1, 16
783; GFX6-NEXT:    s_lshr_b32 s8, s1, 24
784; GFX6-NEXT:    s_lshr_b32 s9, s2, 8
785; GFX6-NEXT:    s_lshr_b32 s10, s2, 16
786; GFX6-NEXT:    s_lshr_b32 s11, s2, 24
787; GFX6-NEXT:    s_and_b32 s12, s2, 7
788; GFX6-NEXT:    s_and_b32 s1, s1, s13
789; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
790; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
791; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
792; GFX6-NEXT:    s_lshr_b32 s1, s1, s12
793; GFX6-NEXT:    s_andn2_b32 s2, 7, s9
794; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
795; GFX6-NEXT:    s_or_b32 s0, s0, s1
796; GFX6-NEXT:    s_lshl_b32 s2, s3, s2
797; GFX6-NEXT:    s_and_b32 s1, s9, 7
798; GFX6-NEXT:    s_and_b32 s3, s6, s13
799; GFX6-NEXT:    s_lshr_b32 s1, s3, s1
800; GFX6-NEXT:    s_andn2_b32 s3, 7, s10
801; GFX6-NEXT:    s_lshl_b32 s4, s4, 1
802; GFX6-NEXT:    s_or_b32 s1, s2, s1
803; GFX6-NEXT:    s_lshl_b32 s3, s4, s3
804; GFX6-NEXT:    s_and_b32 s2, s10, 7
805; GFX6-NEXT:    s_and_b32 s4, s7, s13
806; GFX6-NEXT:    s_lshr_b32 s2, s4, s2
807; GFX6-NEXT:    s_and_b32 s1, s1, s13
808; GFX6-NEXT:    s_or_b32 s2, s3, s2
809; GFX6-NEXT:    s_and_b32 s3, s11, 7
810; GFX6-NEXT:    s_andn2_b32 s4, 7, s11
811; GFX6-NEXT:    s_lshl_b32 s5, s5, 1
812; GFX6-NEXT:    s_and_b32 s0, s0, s13
813; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
814; GFX6-NEXT:    s_or_b32 s0, s0, s1
815; GFX6-NEXT:    s_and_b32 s1, s2, s13
816; GFX6-NEXT:    s_lshl_b32 s4, s5, s4
817; GFX6-NEXT:    s_lshr_b32 s3, s8, s3
818; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
819; GFX6-NEXT:    s_or_b32 s3, s4, s3
820; GFX6-NEXT:    s_or_b32 s0, s0, s1
821; GFX6-NEXT:    s_and_b32 s1, s3, s13
822; GFX6-NEXT:    s_lshl_b32 s1, s1, 24
823; GFX6-NEXT:    s_or_b32 s0, s0, s1
824; GFX6-NEXT:    ; return to shader part epilog
825;
826; GFX8-LABEL: s_fshr_v4i8:
827; GFX8:       ; %bb.0:
828; GFX8-NEXT:    s_movk_i32 s13, 0xff
829; GFX8-NEXT:    s_lshr_b32 s3, s0, 8
830; GFX8-NEXT:    s_lshr_b32 s4, s0, 16
831; GFX8-NEXT:    s_lshr_b32 s5, s0, 24
832; GFX8-NEXT:    s_lshr_b32 s6, s1, 8
833; GFX8-NEXT:    s_lshr_b32 s7, s1, 16
834; GFX8-NEXT:    s_lshr_b32 s8, s1, 24
835; GFX8-NEXT:    s_and_b32 s1, s1, s13
836; GFX8-NEXT:    s_lshr_b32 s9, s2, 8
837; GFX8-NEXT:    s_lshr_b32 s10, s2, 16
838; GFX8-NEXT:    s_lshr_b32 s11, s2, 24
839; GFX8-NEXT:    s_and_b32 s12, s2, 7
840; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
841; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
842; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
843; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
844; GFX8-NEXT:    s_andn2_b32 s2, 7, s9
845; GFX8-NEXT:    s_lshl_b32 s3, s3, 1
846; GFX8-NEXT:    s_lshr_b32 s1, s1, s12
847; GFX8-NEXT:    s_lshl_b32 s2, s3, s2
848; GFX8-NEXT:    s_and_b32 s3, s6, s13
849; GFX8-NEXT:    s_or_b32 s0, s0, s1
850; GFX8-NEXT:    s_and_b32 s1, s9, 7
851; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
852; GFX8-NEXT:    s_lshr_b32 s1, s3, s1
853; GFX8-NEXT:    s_andn2_b32 s3, 7, s10
854; GFX8-NEXT:    s_lshl_b32 s4, s4, 1
855; GFX8-NEXT:    s_lshl_b32 s3, s4, s3
856; GFX8-NEXT:    s_and_b32 s4, s7, s13
857; GFX8-NEXT:    s_or_b32 s1, s2, s1
858; GFX8-NEXT:    s_and_b32 s2, s10, 7
859; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
860; GFX8-NEXT:    s_lshr_b32 s2, s4, s2
861; GFX8-NEXT:    s_and_b32 s1, s1, s13
862; GFX8-NEXT:    s_or_b32 s2, s3, s2
863; GFX8-NEXT:    s_and_b32 s3, s11, 7
864; GFX8-NEXT:    s_andn2_b32 s4, 7, s11
865; GFX8-NEXT:    s_lshl_b32 s5, s5, 1
866; GFX8-NEXT:    s_and_b32 s0, s0, s13
867; GFX8-NEXT:    s_lshl_b32 s1, s1, 8
868; GFX8-NEXT:    s_or_b32 s0, s0, s1
869; GFX8-NEXT:    s_and_b32 s1, s2, s13
870; GFX8-NEXT:    s_lshl_b32 s4, s5, s4
871; GFX8-NEXT:    s_lshr_b32 s3, s8, s3
872; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
873; GFX8-NEXT:    s_or_b32 s3, s4, s3
874; GFX8-NEXT:    s_or_b32 s0, s0, s1
875; GFX8-NEXT:    s_and_b32 s1, s3, s13
876; GFX8-NEXT:    s_lshl_b32 s1, s1, 24
877; GFX8-NEXT:    s_or_b32 s0, s0, s1
878; GFX8-NEXT:    ; return to shader part epilog
879;
880; GFX9-LABEL: s_fshr_v4i8:
881; GFX9:       ; %bb.0:
882; GFX9-NEXT:    s_movk_i32 s13, 0xff
883; GFX9-NEXT:    s_lshr_b32 s3, s0, 8
884; GFX9-NEXT:    s_lshr_b32 s4, s0, 16
885; GFX9-NEXT:    s_lshr_b32 s5, s0, 24
886; GFX9-NEXT:    s_lshr_b32 s6, s1, 8
887; GFX9-NEXT:    s_lshr_b32 s7, s1, 16
888; GFX9-NEXT:    s_lshr_b32 s8, s1, 24
889; GFX9-NEXT:    s_and_b32 s1, s1, s13
890; GFX9-NEXT:    s_lshr_b32 s9, s2, 8
891; GFX9-NEXT:    s_lshr_b32 s10, s2, 16
892; GFX9-NEXT:    s_lshr_b32 s11, s2, 24
893; GFX9-NEXT:    s_and_b32 s12, s2, 7
894; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
895; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
896; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
897; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
898; GFX9-NEXT:    s_andn2_b32 s2, 7, s9
899; GFX9-NEXT:    s_lshl_b32 s3, s3, 1
900; GFX9-NEXT:    s_lshr_b32 s1, s1, s12
901; GFX9-NEXT:    s_lshl_b32 s2, s3, s2
902; GFX9-NEXT:    s_and_b32 s3, s6, s13
903; GFX9-NEXT:    s_or_b32 s0, s0, s1
904; GFX9-NEXT:    s_and_b32 s1, s9, 7
905; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
906; GFX9-NEXT:    s_lshr_b32 s1, s3, s1
907; GFX9-NEXT:    s_andn2_b32 s3, 7, s10
908; GFX9-NEXT:    s_lshl_b32 s4, s4, 1
909; GFX9-NEXT:    s_lshl_b32 s3, s4, s3
910; GFX9-NEXT:    s_and_b32 s4, s7, s13
911; GFX9-NEXT:    s_or_b32 s1, s2, s1
912; GFX9-NEXT:    s_and_b32 s2, s10, 7
913; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
914; GFX9-NEXT:    s_lshr_b32 s2, s4, s2
915; GFX9-NEXT:    s_and_b32 s1, s1, s13
916; GFX9-NEXT:    s_or_b32 s2, s3, s2
917; GFX9-NEXT:    s_and_b32 s3, s11, 7
918; GFX9-NEXT:    s_andn2_b32 s4, 7, s11
919; GFX9-NEXT:    s_lshl_b32 s5, s5, 1
920; GFX9-NEXT:    s_and_b32 s0, s0, s13
921; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
922; GFX9-NEXT:    s_or_b32 s0, s0, s1
923; GFX9-NEXT:    s_and_b32 s1, s2, s13
924; GFX9-NEXT:    s_lshl_b32 s4, s5, s4
925; GFX9-NEXT:    s_lshr_b32 s3, s8, s3
926; GFX9-NEXT:    s_lshl_b32 s1, s1, 16
927; GFX9-NEXT:    s_or_b32 s3, s4, s3
928; GFX9-NEXT:    s_or_b32 s0, s0, s1
929; GFX9-NEXT:    s_and_b32 s1, s3, s13
930; GFX9-NEXT:    s_lshl_b32 s1, s1, 24
931; GFX9-NEXT:    s_or_b32 s0, s0, s1
932; GFX9-NEXT:    ; return to shader part epilog
933;
934; GFX10-LABEL: s_fshr_v4i8:
935; GFX10:       ; %bb.0:
936; GFX10-NEXT:    s_lshr_b32 s6, s1, 8
937; GFX10-NEXT:    s_movk_i32 s13, 0xff
938; GFX10-NEXT:    s_lshr_b32 s3, s0, 8
939; GFX10-NEXT:    s_lshr_b32 s4, s0, 16
940; GFX10-NEXT:    s_lshr_b32 s5, s0, 24
941; GFX10-NEXT:    s_and_b32 s6, s6, s13
942; GFX10-NEXT:    s_lshr_b32 s7, s1, 16
943; GFX10-NEXT:    s_lshr_b32 s8, s1, 24
944; GFX10-NEXT:    s_and_b32 s1, s1, s13
945; GFX10-NEXT:    s_lshr_b32 s9, s2, 8
946; GFX10-NEXT:    s_lshr_b32 s10, s2, 16
947; GFX10-NEXT:    s_lshr_b32 s11, s2, 24
948; GFX10-NEXT:    s_and_b32 s12, s2, 7
949; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
950; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
951; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
952; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
953; GFX10-NEXT:    s_and_b32 s2, s9, 7
954; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
955; GFX10-NEXT:    s_andn2_b32 s9, 7, s9
956; GFX10-NEXT:    s_lshl_b32 s3, s3, 1
957; GFX10-NEXT:    s_lshr_b32 s1, s1, s12
958; GFX10-NEXT:    s_lshr_b32 s2, s6, s2
959; GFX10-NEXT:    s_and_b32 s6, s7, s13
960; GFX10-NEXT:    s_lshl_b32 s3, s3, s9
961; GFX10-NEXT:    s_or_b32 s0, s0, s1
962; GFX10-NEXT:    s_or_b32 s1, s3, s2
963; GFX10-NEXT:    s_and_b32 s2, s10, 7
964; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
965; GFX10-NEXT:    s_andn2_b32 s3, 7, s10
966; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
967; GFX10-NEXT:    s_lshr_b32 s2, s6, s2
968; GFX10-NEXT:    s_lshl_b32 s3, s4, s3
969; GFX10-NEXT:    s_andn2_b32 s4, 7, s11
970; GFX10-NEXT:    s_lshl_b32 s5, s5, 1
971; GFX10-NEXT:    s_and_b32 s6, s11, 7
972; GFX10-NEXT:    s_or_b32 s2, s3, s2
973; GFX10-NEXT:    s_and_b32 s1, s1, s13
974; GFX10-NEXT:    s_lshl_b32 s4, s5, s4
975; GFX10-NEXT:    s_lshr_b32 s5, s8, s6
976; GFX10-NEXT:    s_and_b32 s0, s0, s13
977; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
978; GFX10-NEXT:    s_or_b32 s3, s4, s5
979; GFX10-NEXT:    s_and_b32 s2, s2, s13
980; GFX10-NEXT:    s_or_b32 s0, s0, s1
981; GFX10-NEXT:    s_lshl_b32 s1, s2, 16
982; GFX10-NEXT:    s_and_b32 s2, s3, s13
983; GFX10-NEXT:    s_or_b32 s0, s0, s1
984; GFX10-NEXT:    s_lshl_b32 s1, s2, 24
985; GFX10-NEXT:    s_or_b32 s0, s0, s1
986; GFX10-NEXT:    ; return to shader part epilog
987  %lhs = bitcast i32 %lhs.arg to <4 x i8>
988  %rhs = bitcast i32 %rhs.arg to <4 x i8>
989  %amt = bitcast i32 %amt.arg to <4 x i8>
990  %result = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %lhs, <4 x i8> %rhs, <4 x i8> %amt)
991  %cast.result = bitcast <4 x i8> %result to i32
992  ret i32 %cast.result
993}
994
995define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
996; GFX6-LABEL: v_fshr_v4i8:
997; GFX6:       ; %bb.0:
998; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
999; GFX6-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
1000; GFX6-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
1001; GFX6-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
1002; GFX6-NEXT:    v_and_b32_e32 v12, 7, v2
1003; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
1004; GFX6-NEXT:    s_movk_i32 s4, 0xff
1005; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1006; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
1007; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
1008; GFX6-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
1009; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
1010; GFX6-NEXT:    v_lshrrev_b32_e32 v8, 24, v1
1011; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
1012; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
1013; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1014; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
1015; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v12, v1
1016; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1017; GFX6-NEXT:    v_and_b32_e32 v1, 7, v9
1018; GFX6-NEXT:    v_xor_b32_e32 v9, -1, v9
1019; GFX6-NEXT:    v_and_b32_e32 v6, s4, v6
1020; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v1, v6
1021; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v10
1022; GFX6-NEXT:    v_and_b32_e32 v9, 7, v9
1023; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
1024; GFX6-NEXT:    v_mov_b32_e32 v2, 0xff
1025; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v9, v3
1026; GFX6-NEXT:    v_and_b32_e32 v6, 7, v6
1027; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v4
1028; GFX6-NEXT:    v_or_b32_e32 v1, v3, v1
1029; GFX6-NEXT:    v_lshlrev_b32_e32 v4, v6, v4
1030; GFX6-NEXT:    v_and_b32_e32 v3, 7, v10
1031; GFX6-NEXT:    v_and_b32_e32 v6, v7, v2
1032; GFX6-NEXT:    v_lshrrev_b32_e32 v3, v3, v6
1033; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v11
1034; GFX6-NEXT:    v_and_b32_e32 v1, v1, v2
1035; GFX6-NEXT:    v_or_b32_e32 v3, v4, v3
1036; GFX6-NEXT:    v_and_b32_e32 v4, 7, v11
1037; GFX6-NEXT:    v_and_b32_e32 v6, 7, v6
1038; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 1, v5
1039; GFX6-NEXT:    v_and_b32_e32 v0, v0, v2
1040; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1041; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1042; GFX6-NEXT:    v_and_b32_e32 v1, v3, v2
1043; GFX6-NEXT:    v_lshlrev_b32_e32 v5, v6, v5
1044; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v4, v8
1045; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1046; GFX6-NEXT:    v_or_b32_e32 v4, v5, v4
1047; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1048; GFX6-NEXT:    v_and_b32_e32 v1, v4, v2
1049; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
1050; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1051; GFX6-NEXT:    s_setpc_b64 s[30:31]
1052;
1053; GFX8-LABEL: v_fshr_v4i8:
1054; GFX8:       ; %bb.0:
1055; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1056; GFX8-NEXT:    v_and_b32_e32 v8, 7, v2
1057; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1058; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1059; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 24, v2
1060; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
1061; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
1062; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 1, v0
1063; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v2, v9
1064; GFX8-NEXT:    v_lshrrev_b16_sdwa v8, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1065; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1066; GFX8-NEXT:    v_or_b32_e32 v2, v2, v8
1067; GFX8-NEXT:    v_and_b32_e32 v8, 7, v5
1068; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
1069; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1070; GFX8-NEXT:    v_and_b32_e32 v5, 7, v5
1071; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
1072; GFX8-NEXT:    v_lshlrev_b16_e32 v3, v5, v3
1073; GFX8-NEXT:    v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1074; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v6
1075; GFX8-NEXT:    v_or_b32_e32 v3, v3, v4
1076; GFX8-NEXT:    v_and_b32_e32 v4, 7, v6
1077; GFX8-NEXT:    v_mov_b32_e32 v6, 1
1078; GFX8-NEXT:    v_lshlrev_b16_sdwa v8, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
1079; GFX8-NEXT:    v_and_b32_e32 v5, 7, v5
1080; GFX8-NEXT:    v_mov_b32_e32 v9, 0xff
1081; GFX8-NEXT:    v_lshlrev_b16_e32 v5, v5, v8
1082; GFX8-NEXT:    v_and_b32_sdwa v8, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1083; GFX8-NEXT:    v_lshrrev_b16_e32 v4, v4, v8
1084; GFX8-NEXT:    v_or_b32_e32 v4, v5, v4
1085; GFX8-NEXT:    v_and_b32_e32 v5, 7, v7
1086; GFX8-NEXT:    v_xor_b32_e32 v7, -1, v7
1087; GFX8-NEXT:    v_and_b32_e32 v7, 7, v7
1088; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1089; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v7, v0
1090; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1091; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1092; GFX8-NEXT:    v_mov_b32_e32 v1, 8
1093; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1094; GFX8-NEXT:    s_movk_i32 s4, 0xff
1095; GFX8-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1096; GFX8-NEXT:    v_and_b32_e32 v2, s4, v4
1097; GFX8-NEXT:    v_and_b32_e32 v0, s4, v0
1098; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1099; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
1100; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
1101; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
1102; GFX8-NEXT:    s_setpc_b64 s[30:31]
1103;
1104; GFX9-LABEL: v_fshr_v4i8:
1105; GFX9:       ; %bb.0:
1106; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1107; GFX9-NEXT:    v_and_b32_e32 v8, 7, v2
1108; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1109; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1110; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v2
1111; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
1112; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
1113; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 1, v0
1114; GFX9-NEXT:    v_lshlrev_b16_e32 v2, v2, v9
1115; GFX9-NEXT:    v_lshrrev_b16_sdwa v8, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1116; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1117; GFX9-NEXT:    v_or_b32_e32 v2, v2, v8
1118; GFX9-NEXT:    v_and_b32_e32 v8, 7, v5
1119; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v5
1120; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1121; GFX9-NEXT:    v_and_b32_e32 v5, 7, v5
1122; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
1123; GFX9-NEXT:    v_lshlrev_b16_e32 v3, v5, v3
1124; GFX9-NEXT:    v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1125; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v6
1126; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
1127; GFX9-NEXT:    v_and_b32_e32 v4, 7, v6
1128; GFX9-NEXT:    v_mov_b32_e32 v6, 1
1129; GFX9-NEXT:    v_lshlrev_b16_sdwa v8, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
1130; GFX9-NEXT:    v_and_b32_e32 v5, 7, v5
1131; GFX9-NEXT:    v_mov_b32_e32 v9, 0xff
1132; GFX9-NEXT:    v_lshlrev_b16_e32 v5, v5, v8
1133; GFX9-NEXT:    v_and_b32_sdwa v8, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1134; GFX9-NEXT:    v_lshrrev_b16_e32 v4, v4, v8
1135; GFX9-NEXT:    v_or_b32_e32 v4, v5, v4
1136; GFX9-NEXT:    v_and_b32_e32 v5, 7, v7
1137; GFX9-NEXT:    v_xor_b32_e32 v7, -1, v7
1138; GFX9-NEXT:    v_and_b32_e32 v7, 7, v7
1139; GFX9-NEXT:    v_lshlrev_b16_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1140; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v7, v0
1141; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1142; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
1143; GFX9-NEXT:    v_mov_b32_e32 v1, 8
1144; GFX9-NEXT:    s_movk_i32 s4, 0xff
1145; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1146; GFX9-NEXT:    v_and_b32_e32 v0, s4, v0
1147; GFX9-NEXT:    v_and_or_b32 v1, v2, s4, v1
1148; GFX9-NEXT:    v_and_b32_e32 v2, s4, v4
1149; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1150; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
1151; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0
1152; GFX9-NEXT:    s_setpc_b64 s[30:31]
1153;
1154; GFX10-LABEL: v_fshr_v4i8:
1155; GFX10:       ; %bb.0:
1156; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1157; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1158; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 8, v2
1159; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1160; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v2
1161; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
1162; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
1163; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v6
1164; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
1165; GFX10-NEXT:    v_lshrrev_b32_e32 v12, 24, v2
1166; GFX10-NEXT:    v_and_b32_e32 v15, 7, v8
1167; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
1168; GFX10-NEXT:    v_and_b32_e32 v14, 7, v11
1169; GFX10-NEXT:    v_lshlrev_b16_e64 v3, 1, v3
1170; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v10
1171; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
1172; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v15, v0
1173; GFX10-NEXT:    v_mov_b32_e32 v15, 0xff
1174; GFX10-NEXT:    v_lshlrev_b16_e64 v3, v14, v3
1175; GFX10-NEXT:    v_xor_b32_e32 v14, -1, v12
1176; GFX10-NEXT:    s_movk_i32 s4, 0xff
1177; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 24, v1
1178; GFX10-NEXT:    v_and_b32_e32 v8, s4, v1
1179; GFX10-NEXT:    v_and_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1180; GFX10-NEXT:    v_and_b32_e32 v10, 7, v10
1181; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
1182; GFX10-NEXT:    v_and_b32_e32 v7, s4, v7
1183; GFX10-NEXT:    v_and_b32_e32 v11, 7, v11
1184; GFX10-NEXT:    v_lshlrev_b16_e64 v4, 1, v4
1185; GFX10-NEXT:    v_and_b32_e32 v15, 7, v14
1186; GFX10-NEXT:    v_lshlrev_b16_e64 v5, 1, v5
1187; GFX10-NEXT:    v_and_b32_e32 v12, 7, v12
1188; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
1189; GFX10-NEXT:    v_lshrrev_b16_e64 v6, v6, v7
1190; GFX10-NEXT:    v_lshlrev_b16_e64 v4, v11, v4
1191; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v10, v1
1192; GFX10-NEXT:    v_lshlrev_b16_e64 v5, v15, v5
1193; GFX10-NEXT:    v_lshrrev_b16_e64 v7, v12, v9
1194; GFX10-NEXT:    v_lshrrev_b16_e64 v2, v2, v8
1195; GFX10-NEXT:    v_or_b32_e32 v3, v3, v6
1196; GFX10-NEXT:    v_or_b32_e32 v1, v4, v1
1197; GFX10-NEXT:    v_mov_b32_e32 v6, 8
1198; GFX10-NEXT:    v_or_b32_e32 v4, v5, v7
1199; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
1200; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
1201; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1202; GFX10-NEXT:    v_and_b32_e32 v3, s4, v4
1203; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1204; GFX10-NEXT:    v_and_or_b32 v0, v0, s4, v2
1205; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 24, v3
1206; GFX10-NEXT:    v_or3_b32 v0, v0, v1, v2
1207; GFX10-NEXT:    s_setpc_b64 s[30:31]
1208  %lhs = bitcast i32 %lhs.arg to <4 x i8>
1209  %rhs = bitcast i32 %rhs.arg to <4 x i8>
1210  %amt = bitcast i32 %amt.arg to <4 x i8>
1211  %result = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %lhs, <4 x i8> %rhs, <4 x i8> %amt)
1212  %cast.result = bitcast <4 x i8> %result to i32
1213  ret i32 %cast.result
1214}
1215
1216define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) {
1217; GFX6-LABEL: s_fshr_i24:
1218; GFX6:       ; %bb.0:
1219; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1220; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1221; GFX6-NEXT:    s_sub_i32 s3, 0, 24
1222; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
1223; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1224; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1225; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
1226; GFX6-NEXT:    s_mov_b32 s3, 0xffffff
1227; GFX6-NEXT:    s_and_b32 s2, s2, s3
1228; GFX6-NEXT:    s_and_b32 s1, s1, s3
1229; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
1230; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1231; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
1232; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
1233; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1234; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 24, v0
1235; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1236; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1237; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 24, v0
1238; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1239; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1240; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 23, v0
1241; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
1242; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
1243; GFX6-NEXT:    v_lshl_b32_e32 v1, s0, v1
1244; GFX6-NEXT:    v_lshr_b32_e32 v0, s1, v0
1245; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
1246; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
1247; GFX6-NEXT:    ; return to shader part epilog
1248;
1249; GFX8-LABEL: s_fshr_i24:
1250; GFX8:       ; %bb.0:
1251; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1252; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1253; GFX8-NEXT:    s_sub_i32 s3, 0, 24
1254; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
1255; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1256; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
1257; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
1258; GFX8-NEXT:    s_mov_b32 s3, 0xffffff
1259; GFX8-NEXT:    s_and_b32 s2, s2, s3
1260; GFX8-NEXT:    s_and_b32 s1, s1, s3
1261; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
1262; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
1263; GFX8-NEXT:    v_mul_hi_u32 v0, s2, v0
1264; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
1265; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
1266; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 24, v0
1267; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1268; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1269; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 24, v0
1270; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1271; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1272; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 23, v0
1273; GFX8-NEXT:    v_and_b32_e32 v0, s3, v0
1274; GFX8-NEXT:    v_and_b32_e32 v1, s3, v1
1275; GFX8-NEXT:    v_lshlrev_b32_e64 v1, v1, s0
1276; GFX8-NEXT:    v_lshrrev_b32_e64 v0, v0, s1
1277; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
1278; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
1279; GFX8-NEXT:    ; return to shader part epilog
1280;
1281; GFX9-LABEL: s_fshr_i24:
1282; GFX9:       ; %bb.0:
1283; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1284; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1285; GFX9-NEXT:    s_sub_i32 s3, 0, 24
1286; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
1287; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1288; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1289; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
1290; GFX9-NEXT:    s_mov_b32 s3, 0xffffff
1291; GFX9-NEXT:    s_and_b32 s2, s2, s3
1292; GFX9-NEXT:    s_and_b32 s1, s1, s3
1293; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1294; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
1295; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
1296; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 24
1297; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
1298; GFX9-NEXT:    v_subrev_u32_e32 v1, 24, v0
1299; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1300; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1301; GFX9-NEXT:    v_subrev_u32_e32 v1, 24, v0
1302; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1303; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1304; GFX9-NEXT:    v_sub_u32_e32 v1, 23, v0
1305; GFX9-NEXT:    v_and_b32_e32 v0, s3, v0
1306; GFX9-NEXT:    v_and_b32_e32 v1, s3, v1
1307; GFX9-NEXT:    v_lshrrev_b32_e64 v0, v0, s1
1308; GFX9-NEXT:    v_lshl_or_b32 v0, s0, v1, v0
1309; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
1310; GFX9-NEXT:    ; return to shader part epilog
1311;
1312; GFX10-LABEL: s_fshr_i24:
1313; GFX10:       ; %bb.0:
1314; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1315; GFX10-NEXT:    s_sub_i32 s3, 0, 24
1316; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
1317; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1318; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1319; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1320; GFX10-NEXT:    v_mul_lo_u32 v1, s3, v0
1321; GFX10-NEXT:    s_mov_b32 s3, 0xffffff
1322; GFX10-NEXT:    s_and_b32 s2, s2, s3
1323; GFX10-NEXT:    s_and_b32 s1, s1, s3
1324; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
1325; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
1326; GFX10-NEXT:    v_mul_hi_u32 v0, s2, v0
1327; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 24
1328; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
1329; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 24, v0
1330; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1331; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
1332; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 24, v0
1333; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1334; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
1335; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 23, v0
1336; GFX10-NEXT:    v_and_b32_e32 v0, s3, v0
1337; GFX10-NEXT:    v_and_b32_e32 v1, s3, v1
1338; GFX10-NEXT:    v_lshrrev_b32_e64 v0, v0, s1
1339; GFX10-NEXT:    v_lshl_or_b32 v0, s0, v1, v0
1340; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
1341; GFX10-NEXT:    ; return to shader part epilog
1342  %result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt)
1343  ret i24 %result
1344}
1345
1346define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
1347; GFX6-LABEL: v_fshr_i24:
1348; GFX6:       ; %bb.0:
1349; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1350; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1351; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1352; GFX6-NEXT:    s_sub_i32 s4, 0, 24
1353; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1354; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1355; GFX6-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1356; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1357; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
1358; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
1359; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
1360; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
1361; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffff
1362; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
1363; GFX6-NEXT:    v_mul_lo_u32 v3, v3, 24
1364; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
1365; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v2
1366; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1367; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1368; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v2
1369; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1370; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1371; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v2
1372; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
1373; GFX6-NEXT:    v_and_b32_e32 v3, v3, v4
1374; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
1375; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1376; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1377; GFX6-NEXT:    s_setpc_b64 s[30:31]
1378;
1379; GFX8-LABEL: v_fshr_i24:
1380; GFX8:       ; %bb.0:
1381; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1382; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1383; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1384; GFX8-NEXT:    s_sub_i32 s4, 0, 24
1385; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1386; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1387; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1388; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
1389; GFX8-NEXT:    v_mul_lo_u32 v4, s4, v3
1390; GFX8-NEXT:    v_mul_hi_u32 v4, v3, v4
1391; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v4
1392; GFX8-NEXT:    v_mul_hi_u32 v3, v2, v3
1393; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffff
1394; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
1395; GFX8-NEXT:    v_mul_lo_u32 v3, v3, 24
1396; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
1397; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v2
1398; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1399; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1400; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v2
1401; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1402; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1403; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v2
1404; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
1405; GFX8-NEXT:    v_and_b32_e32 v3, v3, v4
1406; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
1407; GFX8-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1408; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1409; GFX8-NEXT:    s_setpc_b64 s[30:31]
1410;
1411; GFX9-LABEL: v_fshr_i24:
1412; GFX9:       ; %bb.0:
1413; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1414; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1415; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1416; GFX9-NEXT:    s_sub_i32 s4, 0, 24
1417; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1418; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1419; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1420; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1421; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v3
1422; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
1423; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
1424; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
1425; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffffff
1426; GFX9-NEXT:    v_and_b32_e32 v1, v1, v4
1427; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 24
1428; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
1429; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v2
1430; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1431; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1432; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v2
1433; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1434; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1435; GFX9-NEXT:    v_sub_u32_e32 v3, 23, v2
1436; GFX9-NEXT:    v_and_b32_e32 v2, v2, v4
1437; GFX9-NEXT:    v_and_b32_e32 v3, v3, v4
1438; GFX9-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1439; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v3, v1
1440; GFX9-NEXT:    s_setpc_b64 s[30:31]
1441;
1442; GFX10-LABEL: v_fshr_i24:
1443; GFX10:       ; %bb.0:
1444; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1445; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1446; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1447; GFX10-NEXT:    s_sub_i32 s4, 0, 24
1448; GFX10-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1449; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1450; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1451; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1452; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
1453; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v3
1454; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
1455; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
1456; GFX10-NEXT:    v_mov_b32_e32 v4, 0xffffff
1457; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
1458; GFX10-NEXT:    v_and_b32_e32 v1, v1, v4
1459; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 24
1460; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
1461; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v2
1462; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v2
1463; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
1464; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v2
1465; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v2
1466; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
1467; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 23, v2
1468; GFX10-NEXT:    v_and_b32_e32 v2, v2, v4
1469; GFX10-NEXT:    v_and_b32_e32 v3, v3, v4
1470; GFX10-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1471; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v3, v1
1472; GFX10-NEXT:    s_setpc_b64 s[30:31]
1473  %result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt)
1474  ret i24 %result
1475}
1476
1477define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
1478; GFX6-LABEL: s_fshr_v2i24:
1479; GFX6:       ; %bb.0:
1480; GFX6-NEXT:    s_movk_i32 s10, 0xff
1481; GFX6-NEXT:    s_lshr_b32 s9, s1, 8
1482; GFX6-NEXT:    s_and_b32 s1, s1, s10
1483; GFX6-NEXT:    s_lshr_b32 s6, s0, 8
1484; GFX6-NEXT:    s_lshr_b32 s8, s0, 24
1485; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
1486; GFX6-NEXT:    s_or_b32 s1, s8, s1
1487; GFX6-NEXT:    s_and_b32 s6, s6, s10
1488; GFX6-NEXT:    s_lshr_b32 s8, s2, 8
1489; GFX6-NEXT:    s_and_b32 s8, s8, s10
1490; GFX6-NEXT:    s_lshr_b32 s7, s0, 16
1491; GFX6-NEXT:    s_and_b32 s0, s0, s10
1492; GFX6-NEXT:    s_lshl_b32 s6, s6, 8
1493; GFX6-NEXT:    s_or_b32 s0, s0, s6
1494; GFX6-NEXT:    s_and_b32 s6, s7, s10
1495; GFX6-NEXT:    s_and_b32 s7, s9, s10
1496; GFX6-NEXT:    s_lshr_b32 s9, s2, 16
1497; GFX6-NEXT:    s_lshr_b32 s11, s2, 24
1498; GFX6-NEXT:    s_and_b32 s2, s2, s10
1499; GFX6-NEXT:    s_lshl_b32 s8, s8, 8
1500; GFX6-NEXT:    s_or_b32 s2, s2, s8
1501; GFX6-NEXT:    s_and_b32 s8, s9, s10
1502; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1503; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1504; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1505; GFX6-NEXT:    s_lshr_b32 s12, s3, 8
1506; GFX6-NEXT:    s_and_b32 s3, s3, s10
1507; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
1508; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1509; GFX6-NEXT:    s_lshl_b32 s3, s3, 8
1510; GFX6-NEXT:    s_or_b32 s2, s2, s8
1511; GFX6-NEXT:    s_and_b32 s8, s12, s10
1512; GFX6-NEXT:    s_or_b32 s3, s11, s3
1513; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1514; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1515; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
1516; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1517; GFX6-NEXT:    s_or_b32 s3, s3, s8
1518; GFX6-NEXT:    s_lshr_b32 s8, s4, 8
1519; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1520; GFX6-NEXT:    s_and_b32 s8, s8, s10
1521; GFX6-NEXT:    s_lshr_b32 s9, s4, 16
1522; GFX6-NEXT:    s_lshr_b32 s11, s4, 24
1523; GFX6-NEXT:    s_and_b32 s4, s4, s10
1524; GFX6-NEXT:    s_lshl_b32 s8, s8, 8
1525; GFX6-NEXT:    s_or_b32 s4, s4, s8
1526; GFX6-NEXT:    s_and_b32 s8, s9, s10
1527; GFX6-NEXT:    s_sub_i32 s9, 0, 24
1528; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v0
1529; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1530; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
1531; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1532; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
1533; GFX6-NEXT:    s_or_b32 s4, s4, s8
1534; GFX6-NEXT:    s_lshr_b32 s12, s5, 8
1535; GFX6-NEXT:    s_and_b32 s5, s5, s10
1536; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1537; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1538; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1539; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1540; GFX6-NEXT:    s_lshl_b32 s5, s5, 8
1541; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
1542; GFX6-NEXT:    s_and_b32 s8, s12, s10
1543; GFX6-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1544; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1545; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1546; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1547; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1548; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1549; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1550; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1551; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1552; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
1553; GFX6-NEXT:    s_or_b32 s5, s11, s5
1554; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1555; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
1556; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
1557; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1558; GFX6-NEXT:    s_or_b32 s5, s5, s8
1559; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
1560; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
1561; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1562; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1563; GFX6-NEXT:    s_mov_b32 s8, 0xffffff
1564; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v0
1565; GFX6-NEXT:    v_mul_lo_u32 v1, v1, 24
1566; GFX6-NEXT:    s_lshl_b32 s4, s6, 17
1567; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
1568; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
1569; GFX6-NEXT:    s_or_b32 s0, s4, s0
1570; GFX6-NEXT:    v_and_b32_e32 v2, s8, v3
1571; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
1572; GFX6-NEXT:    v_lshr_b32_e32 v0, s2, v0
1573; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
1574; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
1575; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
1576; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1577; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1578; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
1579; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1580; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1581; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
1582; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
1583; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffff
1584; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v1
1585; GFX6-NEXT:    s_lshl_b32 s0, s7, 17
1586; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
1587; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
1588; GFX6-NEXT:    s_or_b32 s0, s0, s1
1589; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
1590; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
1591; GFX6-NEXT:    v_lshr_b32_e32 v1, s3, v1
1592; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
1593; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
1594; GFX6-NEXT:    v_and_b32_e32 v2, s10, v2
1595; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
1596; GFX6-NEXT:    v_and_b32_e32 v0, s10, v0
1597; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1598; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1599; GFX6-NEXT:    v_and_b32_e32 v2, s10, v3
1600; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1601; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1602; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
1603; GFX6-NEXT:    v_and_b32_e32 v1, s10, v1
1604; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1605; GFX6-NEXT:    v_and_b32_e32 v2, s10, v5
1606; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
1607; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1608; GFX6-NEXT:    v_and_b32_e32 v1, s10, v4
1609; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1610; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
1611; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
1612; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
1613; GFX6-NEXT:    ; return to shader part epilog
1614;
1615; GFX8-LABEL: s_fshr_v2i24:
1616; GFX8:       ; %bb.0:
1617; GFX8-NEXT:    s_movk_i32 s10, 0xff
1618; GFX8-NEXT:    s_lshr_b32 s9, s1, 8
1619; GFX8-NEXT:    s_bfe_u32 s11, 8, 0x100000
1620; GFX8-NEXT:    s_and_b32 s1, s1, s10
1621; GFX8-NEXT:    s_lshr_b32 s6, s0, 8
1622; GFX8-NEXT:    s_lshr_b32 s8, s0, 24
1623; GFX8-NEXT:    s_lshl_b32 s1, s1, s11
1624; GFX8-NEXT:    s_or_b32 s1, s8, s1
1625; GFX8-NEXT:    s_and_b32 s6, s6, s10
1626; GFX8-NEXT:    s_lshr_b32 s8, s2, 8
1627; GFX8-NEXT:    s_and_b32 s8, s8, s10
1628; GFX8-NEXT:    s_lshr_b32 s7, s0, 16
1629; GFX8-NEXT:    s_and_b32 s0, s0, s10
1630; GFX8-NEXT:    s_lshl_b32 s6, s6, s11
1631; GFX8-NEXT:    s_or_b32 s0, s0, s6
1632; GFX8-NEXT:    s_and_b32 s6, s7, s10
1633; GFX8-NEXT:    s_and_b32 s7, s9, s10
1634; GFX8-NEXT:    s_lshr_b32 s9, s2, 16
1635; GFX8-NEXT:    s_lshr_b32 s12, s2, 24
1636; GFX8-NEXT:    s_and_b32 s2, s2, s10
1637; GFX8-NEXT:    s_lshl_b32 s8, s8, s11
1638; GFX8-NEXT:    s_or_b32 s2, s2, s8
1639; GFX8-NEXT:    s_and_b32 s8, s9, s10
1640; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1641; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1642; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1643; GFX8-NEXT:    s_lshr_b32 s13, s3, 8
1644; GFX8-NEXT:    s_and_b32 s3, s3, s10
1645; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
1646; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1647; GFX8-NEXT:    s_lshl_b32 s3, s3, s11
1648; GFX8-NEXT:    s_or_b32 s2, s2, s8
1649; GFX8-NEXT:    s_and_b32 s8, s13, s10
1650; GFX8-NEXT:    s_or_b32 s3, s12, s3
1651; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1652; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1653; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
1654; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1655; GFX8-NEXT:    s_or_b32 s3, s3, s8
1656; GFX8-NEXT:    s_lshr_b32 s8, s4, 8
1657; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
1658; GFX8-NEXT:    s_and_b32 s8, s8, s10
1659; GFX8-NEXT:    s_lshr_b32 s9, s4, 16
1660; GFX8-NEXT:    s_lshr_b32 s12, s4, 24
1661; GFX8-NEXT:    s_and_b32 s4, s4, s10
1662; GFX8-NEXT:    s_lshl_b32 s8, s8, s11
1663; GFX8-NEXT:    s_or_b32 s4, s4, s8
1664; GFX8-NEXT:    s_and_b32 s8, s9, s10
1665; GFX8-NEXT:    s_sub_i32 s9, 0, 24
1666; GFX8-NEXT:    v_mul_lo_u32 v1, s9, v0
1667; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1668; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
1669; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1670; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
1671; GFX8-NEXT:    s_or_b32 s4, s4, s8
1672; GFX8-NEXT:    s_lshr_b32 s13, s5, 8
1673; GFX8-NEXT:    s_and_b32 s5, s5, s10
1674; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
1675; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
1676; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1677; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1678; GFX8-NEXT:    s_lshl_b32 s5, s5, s11
1679; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
1680; GFX8-NEXT:    s_and_b32 s8, s13, s10
1681; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1682; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
1683; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
1684; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
1685; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1686; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1687; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
1688; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1689; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1690; GFX8-NEXT:    v_mul_lo_u32 v2, s9, v1
1691; GFX8-NEXT:    s_or_b32 s5, s12, s5
1692; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1693; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
1694; GFX8-NEXT:    v_mul_hi_u32 v2, v1, v2
1695; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1696; GFX8-NEXT:    s_or_b32 s5, s5, s8
1697; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
1698; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
1699; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
1700; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1701; GFX8-NEXT:    s_mov_b32 s8, 0xffffff
1702; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v0
1703; GFX8-NEXT:    v_mul_lo_u32 v1, v1, 24
1704; GFX8-NEXT:    s_lshl_b32 s4, s6, 17
1705; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
1706; GFX8-NEXT:    v_and_b32_e32 v0, s8, v0
1707; GFX8-NEXT:    s_or_b32 s0, s4, s0
1708; GFX8-NEXT:    v_and_b32_e32 v2, s8, v3
1709; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
1710; GFX8-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
1711; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
1712; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
1713; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
1714; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1715; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1716; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
1717; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1718; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1719; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
1720; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
1721; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffff
1722; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v1
1723; GFX8-NEXT:    s_lshl_b32 s0, s7, 17
1724; GFX8-NEXT:    s_lshl_b32 s1, s1, 1
1725; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
1726; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
1727; GFX8-NEXT:    s_or_b32 s0, s0, s1
1728; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
1729; GFX8-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
1730; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
1731; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
1732; GFX8-NEXT:    v_mov_b32_e32 v4, 8
1733; GFX8-NEXT:    v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1734; GFX8-NEXT:    v_mov_b32_e32 v4, s10
1735; GFX8-NEXT:    v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1736; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1737; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
1738; GFX8-NEXT:    v_and_b32_e32 v2, s10, v1
1739; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
1740; GFX8-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1741; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1742; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
1743; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
1744; GFX8-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1745; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
1746; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
1747; GFX8-NEXT:    ; return to shader part epilog
1748;
1749; GFX9-LABEL: s_fshr_v2i24:
1750; GFX9:       ; %bb.0:
1751; GFX9-NEXT:    s_movk_i32 s11, 0xff
1752; GFX9-NEXT:    s_lshr_b32 s10, s1, 8
1753; GFX9-NEXT:    s_bfe_u32 s12, 8, 0x100000
1754; GFX9-NEXT:    s_and_b32 s1, s1, s11
1755; GFX9-NEXT:    s_lshr_b32 s7, s0, 8
1756; GFX9-NEXT:    s_lshr_b32 s9, s0, 24
1757; GFX9-NEXT:    s_lshl_b32 s1, s1, s12
1758; GFX9-NEXT:    s_or_b32 s1, s9, s1
1759; GFX9-NEXT:    s_and_b32 s7, s7, s11
1760; GFX9-NEXT:    s_lshr_b32 s9, s2, 8
1761; GFX9-NEXT:    s_and_b32 s9, s9, s11
1762; GFX9-NEXT:    s_lshr_b32 s8, s0, 16
1763; GFX9-NEXT:    s_and_b32 s0, s0, s11
1764; GFX9-NEXT:    s_lshl_b32 s7, s7, s12
1765; GFX9-NEXT:    s_or_b32 s0, s0, s7
1766; GFX9-NEXT:    s_and_b32 s7, s8, s11
1767; GFX9-NEXT:    s_and_b32 s8, s10, s11
1768; GFX9-NEXT:    s_lshr_b32 s10, s2, 16
1769; GFX9-NEXT:    s_lshr_b32 s13, s2, 24
1770; GFX9-NEXT:    s_and_b32 s2, s2, s11
1771; GFX9-NEXT:    s_lshl_b32 s9, s9, s12
1772; GFX9-NEXT:    s_or_b32 s2, s2, s9
1773; GFX9-NEXT:    s_and_b32 s9, s10, s11
1774; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1775; GFX9-NEXT:    s_bfe_u32 s9, s9, 0x100000
1776; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1777; GFX9-NEXT:    s_lshr_b32 s14, s3, 8
1778; GFX9-NEXT:    s_and_b32 s3, s3, s11
1779; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
1780; GFX9-NEXT:    s_lshl_b32 s9, s9, 16
1781; GFX9-NEXT:    s_lshl_b32 s3, s3, s12
1782; GFX9-NEXT:    s_or_b32 s2, s2, s9
1783; GFX9-NEXT:    s_and_b32 s9, s14, s11
1784; GFX9-NEXT:    s_or_b32 s3, s13, s3
1785; GFX9-NEXT:    s_bfe_u32 s9, s9, 0x100000
1786; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1787; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
1788; GFX9-NEXT:    s_lshl_b32 s9, s9, 16
1789; GFX9-NEXT:    s_or_b32 s3, s3, s9
1790; GFX9-NEXT:    s_lshr_b32 s9, s4, 8
1791; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1792; GFX9-NEXT:    s_and_b32 s9, s9, s11
1793; GFX9-NEXT:    s_lshr_b32 s10, s4, 16
1794; GFX9-NEXT:    s_lshr_b32 s13, s4, 24
1795; GFX9-NEXT:    s_and_b32 s4, s4, s11
1796; GFX9-NEXT:    s_lshl_b32 s9, s9, s12
1797; GFX9-NEXT:    s_or_b32 s4, s4, s9
1798; GFX9-NEXT:    s_and_b32 s9, s10, s11
1799; GFX9-NEXT:    s_sub_i32 s10, 0, 24
1800; GFX9-NEXT:    v_mul_lo_u32 v1, s10, v0
1801; GFX9-NEXT:    s_bfe_u32 s9, s9, 0x100000
1802; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
1803; GFX9-NEXT:    s_lshl_b32 s9, s9, 16
1804; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1805; GFX9-NEXT:    s_or_b32 s4, s4, s9
1806; GFX9-NEXT:    s_lshr_b32 s14, s5, 8
1807; GFX9-NEXT:    s_and_b32 s5, s5, s11
1808; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
1809; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1810; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1811; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1812; GFX9-NEXT:    s_lshl_b32 s5, s5, s12
1813; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 24
1814; GFX9-NEXT:    s_and_b32 s9, s14, s11
1815; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1816; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1817; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1818; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v0
1819; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1820; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1821; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v1
1822; GFX9-NEXT:    s_or_b32 s5, s13, s5
1823; GFX9-NEXT:    s_bfe_u32 s9, s9, 0x100000
1824; GFX9-NEXT:    s_bfe_u32 s5, s5, 0x100000
1825; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v2
1826; GFX9-NEXT:    s_lshl_b32 s9, s9, 16
1827; GFX9-NEXT:    s_or_b32 s5, s5, s9
1828; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v0
1829; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
1830; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1831; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1832; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
1833; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1834; GFX9-NEXT:    v_mul_lo_u32 v1, v1, 24
1835; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1836; GFX9-NEXT:    s_mov_b32 s9, 0xffffff
1837; GFX9-NEXT:    v_sub_u32_e32 v3, 23, v0
1838; GFX9-NEXT:    v_and_b32_e32 v0, s9, v0
1839; GFX9-NEXT:    s_lshl_b32 s4, s7, 17
1840; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
1841; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
1842; GFX9-NEXT:    s_or_b32 s0, s4, s0
1843; GFX9-NEXT:    v_and_b32_e32 v3, s9, v3
1844; GFX9-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
1845; GFX9-NEXT:    v_lshl_or_b32 v0, s0, v3, v0
1846; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v1
1847; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1848; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1849; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v1
1850; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1851; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
1852; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1853; GFX9-NEXT:    s_bfe_u32 s8, s8, 0x100000
1854; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffffff
1855; GFX9-NEXT:    v_sub_u32_e32 v3, 23, v1
1856; GFX9-NEXT:    v_and_b32_e32 v1, v1, v2
1857; GFX9-NEXT:    s_lshl_b32 s0, s8, 17
1858; GFX9-NEXT:    s_lshl_b32 s1, s1, 1
1859; GFX9-NEXT:    v_and_b32_e32 v3, v3, v2
1860; GFX9-NEXT:    s_or_b32 s0, s0, s1
1861; GFX9-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
1862; GFX9-NEXT:    v_lshl_or_b32 v1, s0, v3, v1
1863; GFX9-NEXT:    s_mov_b32 s6, 8
1864; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
1865; GFX9-NEXT:    v_lshlrev_b32_sdwa v2, s6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1866; GFX9-NEXT:    v_and_b32_e32 v4, s11, v1
1867; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
1868; GFX9-NEXT:    v_and_b32_sdwa v1, v1, s11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1869; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1870; GFX9-NEXT:    v_and_or_b32 v2, v0, s11, v2
1871; GFX9-NEXT:    v_and_b32_sdwa v0, v0, s11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1872; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 24, v4
1873; GFX9-NEXT:    v_or3_b32 v0, v2, v0, v4
1874; GFX9-NEXT:    v_and_or_b32 v1, v3, s11, v1
1875; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
1876; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
1877; GFX9-NEXT:    ; return to shader part epilog
1878;
1879; GFX10-LABEL: s_fshr_v2i24:
1880; GFX10:       ; %bb.0:
1881; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1882; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1883; GFX10-NEXT:    s_sub_i32 s12, 0, 24
1884; GFX10-NEXT:    s_movk_i32 s9, 0xff
1885; GFX10-NEXT:    s_lshr_b32 s14, s4, 8
1886; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1887; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1888; GFX10-NEXT:    s_lshr_b32 s15, s4, 16
1889; GFX10-NEXT:    s_bfe_u32 s10, 8, 0x100000
1890; GFX10-NEXT:    s_and_b32 s14, s14, s9
1891; GFX10-NEXT:    s_and_b32 s16, s4, s9
1892; GFX10-NEXT:    s_lshl_b32 s14, s14, s10
1893; GFX10-NEXT:    s_and_b32 s15, s15, s9
1894; GFX10-NEXT:    s_or_b32 s14, s16, s14
1895; GFX10-NEXT:    s_lshr_b32 s4, s4, 24
1896; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1897; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1898; GFX10-NEXT:    s_bfe_u32 s14, s14, 0x100000
1899; GFX10-NEXT:    s_lshr_b32 s6, s0, 8
1900; GFX10-NEXT:    s_lshr_b32 s11, s1, 8
1901; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1902; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
1903; GFX10-NEXT:    s_and_b32 s1, s1, s9
1904; GFX10-NEXT:    s_and_b32 s6, s6, s9
1905; GFX10-NEXT:    s_lshr_b32 s8, s0, 24
1906; GFX10-NEXT:    v_mul_lo_u32 v2, s12, v0
1907; GFX10-NEXT:    v_mul_lo_u32 v3, s12, v1
1908; GFX10-NEXT:    s_bfe_u32 s12, s15, 0x100000
1909; GFX10-NEXT:    s_lshr_b32 s15, s5, 8
1910; GFX10-NEXT:    s_lshl_b32 s12, s12, 16
1911; GFX10-NEXT:    s_and_b32 s5, s5, s9
1912; GFX10-NEXT:    s_or_b32 s12, s14, s12
1913; GFX10-NEXT:    s_lshl_b32 s5, s5, s10
1914; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2
1915; GFX10-NEXT:    s_and_b32 s14, s15, s9
1916; GFX10-NEXT:    s_or_b32 s4, s4, s5
1917; GFX10-NEXT:    s_bfe_u32 s5, s14, 0x100000
1918; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
1919; GFX10-NEXT:    s_lshl_b32 s5, s5, 16
1920; GFX10-NEXT:    s_lshl_b32 s1, s1, s10
1921; GFX10-NEXT:    s_or_b32 s4, s4, s5
1922; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
1923; GFX10-NEXT:    v_mul_hi_u32 v2, v1, v3
1924; GFX10-NEXT:    s_or_b32 s1, s8, s1
1925; GFX10-NEXT:    s_lshr_b32 s8, s2, 8
1926; GFX10-NEXT:    s_lshr_b32 s7, s0, 16
1927; GFX10-NEXT:    v_mul_hi_u32 v0, s12, v0
1928; GFX10-NEXT:    s_and_b32 s0, s0, s9
1929; GFX10-NEXT:    s_lshl_b32 s6, s6, s10
1930; GFX10-NEXT:    s_and_b32 s8, s8, s9
1931; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v2
1932; GFX10-NEXT:    s_or_b32 s0, s0, s6
1933; GFX10-NEXT:    s_and_b32 s6, s7, s9
1934; GFX10-NEXT:    s_and_b32 s7, s11, s9
1935; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 24
1936; GFX10-NEXT:    v_mul_hi_u32 v1, s4, v1
1937; GFX10-NEXT:    s_lshr_b32 s11, s2, 16
1938; GFX10-NEXT:    s_and_b32 s13, s2, s9
1939; GFX10-NEXT:    s_lshl_b32 s5, s8, s10
1940; GFX10-NEXT:    s_and_b32 s8, s11, s9
1941; GFX10-NEXT:    s_lshr_b32 s11, s3, 8
1942; GFX10-NEXT:    s_and_b32 s3, s3, s9
1943; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s12, v0
1944; GFX10-NEXT:    v_mul_lo_u32 v1, v1, 24
1945; GFX10-NEXT:    s_or_b32 s5, s13, s5
1946; GFX10-NEXT:    s_bfe_u32 s8, s8, 0x100000
1947; GFX10-NEXT:    s_lshr_b32 s2, s2, 24
1948; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v0
1949; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1950; GFX10-NEXT:    s_lshl_b32 s3, s3, s10
1951; GFX10-NEXT:    v_mov_b32_e32 v4, 0xffffff
1952; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s4, v1
1953; GFX10-NEXT:    s_mov_b32 s4, 0xffffff
1954; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
1955; GFX10-NEXT:    s_bfe_u32 s5, s5, 0x100000
1956; GFX10-NEXT:    s_lshl_b32 s8, s8, 16
1957; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v1
1958; GFX10-NEXT:    s_or_b32 s2, s2, s3
1959; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v0
1960; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1961; GFX10-NEXT:    s_and_b32 s3, s11, s9
1962; GFX10-NEXT:    s_or_b32 s5, s5, s8
1963; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
1964; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
1965; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
1966; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v1
1967; GFX10-NEXT:    s_bfe_u32 s3, s3, 0x100000
1968; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
1969; GFX10-NEXT:    s_lshl_b32 s3, s3, 16
1970; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 23, v0
1971; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
1972; GFX10-NEXT:    v_and_b32_e32 v0, s4, v0
1973; GFX10-NEXT:    s_lshl_b32 s6, s6, 17
1974; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
1975; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
1976; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v1
1977; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v1
1978; GFX10-NEXT:    v_lshrrev_b32_e64 v0, v0, s5
1979; GFX10-NEXT:    s_or_b32 s0, s6, s0
1980; GFX10-NEXT:    s_or_b32 s2, s2, s3
1981; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
1982; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
1983; GFX10-NEXT:    s_bfe_u32 s7, s7, 0x100000
1984; GFX10-NEXT:    v_lshl_or_b32 v0, s0, v2, v0
1985; GFX10-NEXT:    s_lshl_b32 s0, s7, 17
1986; GFX10-NEXT:    s_lshl_b32 s1, s1, 1
1987; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 23, v1
1988; GFX10-NEXT:    v_and_b32_e32 v1, v1, v4
1989; GFX10-NEXT:    s_or_b32 s0, s0, s1
1990; GFX10-NEXT:    v_and_b32_e32 v2, v3, v4
1991; GFX10-NEXT:    v_lshrrev_b32_e64 v1, v1, s2
1992; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1993; GFX10-NEXT:    v_lshl_or_b32 v1, s0, v2, v1
1994; GFX10-NEXT:    s_mov_b32 s0, 8
1995; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, s0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1996; GFX10-NEXT:    v_and_b32_e32 v3, s9, v1
1997; GFX10-NEXT:    v_and_b32_sdwa v4, v1, s9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1998; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
1999; GFX10-NEXT:    v_and_or_b32 v2, v0, s9, v2
2000; GFX10-NEXT:    v_and_b32_sdwa v0, v0, s9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
2001; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
2002; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 8, v4
2003; GFX10-NEXT:    v_or3_b32 v0, v2, v0, v3
2004; GFX10-NEXT:    v_and_or_b32 v1, v1, s9, v4
2005; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2006; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
2007; GFX10-NEXT:    ; return to shader part epilog
2008  %lhs = bitcast i48 %lhs.arg to <2 x i24>
2009  %rhs = bitcast i48 %rhs.arg to <2 x i24>
2010  %amt = bitcast i48 %amt.arg to <2 x i24>
2011  %result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
2012  %cast.result = bitcast <2 x i24> %result to i48
2013  ret i48 %cast.result
2014}
2015
2016define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
2017; GFX6-LABEL: v_fshr_v2i24:
2018; GFX6:       ; %bb.0:
2019; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2020; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2021; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2022; GFX6-NEXT:    s_sub_i32 s4, 0, 24
2023; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2024; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
2025; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2026; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
2027; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2028; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2029; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v6
2030; GFX6-NEXT:    v_mul_hi_u32 v7, v6, v7
2031; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
2032; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
2033; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v8
2034; GFX6-NEXT:    v_mov_b32_e32 v8, 0xffffff
2035; GFX6-NEXT:    v_and_b32_e32 v5, v5, v8
2036; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
2037; GFX6-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2038; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
2039; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
2040; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
2041; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
2042; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2043; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2044; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
2045; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2046; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2047; GFX6-NEXT:    v_mul_lo_u32 v6, s4, v7
2048; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 23, v4
2049; GFX6-NEXT:    v_and_b32_e32 v9, v9, v8
2050; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
2051; GFX6-NEXT:    v_mul_hi_u32 v6, v7, v6
2052; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
2053; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2054; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2055; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
2056; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
2057; GFX6-NEXT:    v_and_b32_e32 v3, v3, v8
2058; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
2059; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
2060; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
2061; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2062; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2063; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
2064; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2065; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2066; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
2067; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
2068; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
2069; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
2070; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
2071; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
2072; GFX6-NEXT:    s_setpc_b64 s[30:31]
2073;
2074; GFX8-LABEL: v_fshr_v2i24:
2075; GFX8:       ; %bb.0:
2076; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2077; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2078; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2079; GFX8-NEXT:    s_sub_i32 s4, 0, 24
2080; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2081; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
2082; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2083; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
2084; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2085; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2086; GFX8-NEXT:    v_mul_lo_u32 v7, s4, v6
2087; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7
2088; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v7
2089; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
2090; GFX8-NEXT:    v_rcp_iflag_f32_e32 v7, v8
2091; GFX8-NEXT:    v_mov_b32_e32 v8, 0xffffff
2092; GFX8-NEXT:    v_and_b32_e32 v5, v5, v8
2093; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
2094; GFX8-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2095; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v7
2096; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
2097; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
2098; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
2099; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2100; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2101; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
2102; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2103; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2104; GFX8-NEXT:    v_mul_lo_u32 v6, s4, v7
2105; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, 23, v4
2106; GFX8-NEXT:    v_and_b32_e32 v9, v9, v8
2107; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
2108; GFX8-NEXT:    v_mul_hi_u32 v6, v7, v6
2109; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
2110; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2111; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
2112; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
2113; GFX8-NEXT:    v_mul_hi_u32 v6, v5, v6
2114; GFX8-NEXT:    v_and_b32_e32 v3, v3, v8
2115; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
2116; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
2117; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
2118; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2119; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2120; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
2121; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2122; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2123; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
2124; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
2125; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
2126; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
2127; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
2128; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
2129; GFX8-NEXT:    s_setpc_b64 s[30:31]
2130;
2131; GFX9-LABEL: v_fshr_v2i24:
2132; GFX9:       ; %bb.0:
2133; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2134; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2135; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2136; GFX9-NEXT:    s_sub_i32 s4, 0, 24
2137; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
2138; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v8
2139; GFX9-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2140; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
2141; GFX9-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2142; GFX9-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
2143; GFX9-NEXT:    v_mov_b32_e32 v9, 0xffffff
2144; GFX9-NEXT:    v_mul_lo_u32 v7, s4, v6
2145; GFX9-NEXT:    v_and_b32_e32 v5, v5, v9
2146; GFX9-NEXT:    v_and_b32_e32 v2, v2, v9
2147; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2148; GFX9-NEXT:    v_mul_hi_u32 v7, v6, v7
2149; GFX9-NEXT:    v_and_b32_e32 v3, v3, v9
2150; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2151; GFX9-NEXT:    v_add_u32_e32 v6, v6, v7
2152; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v8
2153; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v6
2154; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v7
2155; GFX9-NEXT:    v_mul_lo_u32 v6, v6, 24
2156; GFX9-NEXT:    v_mul_hi_u32 v8, v7, v8
2157; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v6
2158; GFX9-NEXT:    v_subrev_u32_e32 v6, 24, v4
2159; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2160; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
2161; GFX9-NEXT:    v_mul_hi_u32 v7, v5, v7
2162; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2163; GFX9-NEXT:    v_subrev_u32_e32 v6, 24, v4
2164; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2165; GFX9-NEXT:    v_mul_lo_u32 v7, v7, 24
2166; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2167; GFX9-NEXT:    v_sub_u32_e32 v6, 23, v4
2168; GFX9-NEXT:    v_and_b32_e32 v4, v4, v9
2169; GFX9-NEXT:    v_and_b32_e32 v6, v6, v9
2170; GFX9-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2171; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v6, v2
2172; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v7
2173; GFX9-NEXT:    v_subrev_u32_e32 v4, 24, v2
2174; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2175; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2176; GFX9-NEXT:    v_subrev_u32_e32 v4, 24, v2
2177; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2178; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2179; GFX9-NEXT:    v_sub_u32_e32 v4, 23, v2
2180; GFX9-NEXT:    v_and_b32_e32 v2, v2, v9
2181; GFX9-NEXT:    v_and_b32_e32 v4, v4, v9
2182; GFX9-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
2183; GFX9-NEXT:    v_lshl_or_b32 v1, v1, v4, v2
2184; GFX9-NEXT:    s_setpc_b64 s[30:31]
2185;
2186; GFX10-LABEL: v_fshr_v2i24:
2187; GFX10:       ; %bb.0:
2188; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2189; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2190; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2191; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v7, 24
2192; GFX10-NEXT:    s_sub_i32 s4, 0, 24
2193; GFX10-NEXT:    v_mov_b32_e32 v12, 0xffffff
2194; GFX10-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2195; GFX10-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2196; GFX10-NEXT:    v_rcp_iflag_f32_e32 v7, v7
2197; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2198; GFX10-NEXT:    v_and_b32_e32 v5, v5, v12
2199; GFX10-NEXT:    v_and_b32_e32 v2, v2, v12
2200; GFX10-NEXT:    v_and_b32_e32 v3, v3, v12
2201; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2202; GFX10-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2203; GFX10-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2204; GFX10-NEXT:    v_cvt_u32_f32_e32 v6, v6
2205; GFX10-NEXT:    v_cvt_u32_f32_e32 v7, v7
2206; GFX10-NEXT:    v_mul_lo_u32 v8, s4, v6
2207; GFX10-NEXT:    v_mul_lo_u32 v9, s4, v7
2208; GFX10-NEXT:    v_mul_hi_u32 v8, v6, v8
2209; GFX10-NEXT:    v_mul_hi_u32 v9, v7, v9
2210; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v8
2211; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v9
2212; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v6
2213; GFX10-NEXT:    v_mul_hi_u32 v7, v5, v7
2214; GFX10-NEXT:    v_mul_lo_u32 v6, v6, 24
2215; GFX10-NEXT:    v_mul_lo_u32 v7, v7, 24
2216; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v4, v6
2217; GFX10-NEXT:    v_sub_nc_u32_e32 v5, v5, v7
2218; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 24, v4
2219; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v4
2220; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 24, v5
2221; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
2222; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v5
2223; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 24, v4
2224; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
2225; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v4
2226; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 24, v5
2227; GFX10-NEXT:    v_cndmask_b32_e32 v11, v4, v6, vcc_lo
2228; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v5
2229; GFX10-NEXT:    v_and_b32_e32 v4, v11, v12
2230; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
2231; GFX10-NEXT:    v_sub_nc_u32_e32 v6, 23, v11
2232; GFX10-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2233; GFX10-NEXT:    v_sub_nc_u32_e32 v7, 23, v5
2234; GFX10-NEXT:    v_and_b32_e32 v5, v5, v12
2235; GFX10-NEXT:    v_and_b32_e32 v11, v6, v12
2236; GFX10-NEXT:    v_and_b32_e32 v4, v7, v12
2237; GFX10-NEXT:    v_lshrrev_b32_e32 v3, v5, v3
2238; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v11, v2
2239; GFX10-NEXT:    v_lshl_or_b32 v1, v1, v4, v3
2240; GFX10-NEXT:    s_setpc_b64 s[30:31]
2241  %result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
2242  ret <2 x i24> %result
2243}
2244
2245define amdgpu_ps i32 @s_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
2246; GFX6-LABEL: s_fshr_i32:
2247; GFX6:       ; %bb.0:
2248; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2249; GFX6-NEXT:    v_mov_b32_e32 v1, s2
2250; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2251; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2252; GFX6-NEXT:    ; return to shader part epilog
2253;
2254; GFX8-LABEL: s_fshr_i32:
2255; GFX8:       ; %bb.0:
2256; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2257; GFX8-NEXT:    v_mov_b32_e32 v1, s2
2258; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2259; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2260; GFX8-NEXT:    ; return to shader part epilog
2261;
2262; GFX9-LABEL: s_fshr_i32:
2263; GFX9:       ; %bb.0:
2264; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2265; GFX9-NEXT:    v_mov_b32_e32 v1, s2
2266; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2267; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2268; GFX9-NEXT:    ; return to shader part epilog
2269;
2270; GFX10-LABEL: s_fshr_i32:
2271; GFX10:       ; %bb.0:
2272; GFX10-NEXT:    v_mov_b32_e32 v0, s2
2273; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, v0
2274; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2275; GFX10-NEXT:    ; return to shader part epilog
2276  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2277  ret i32 %result
2278}
2279
2280define amdgpu_ps i32 @s_fshr_i32_5(i32 inreg %lhs, i32 inreg %rhs) {
2281; GFX6-LABEL: s_fshr_i32_5:
2282; GFX6:       ; %bb.0:
2283; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2284; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 5
2285; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2286; GFX6-NEXT:    ; return to shader part epilog
2287;
2288; GFX8-LABEL: s_fshr_i32_5:
2289; GFX8:       ; %bb.0:
2290; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2291; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 5
2292; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2293; GFX8-NEXT:    ; return to shader part epilog
2294;
2295; GFX9-LABEL: s_fshr_i32_5:
2296; GFX9:       ; %bb.0:
2297; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2298; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 5
2299; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2300; GFX9-NEXT:    ; return to shader part epilog
2301;
2302; GFX10-LABEL: s_fshr_i32_5:
2303; GFX10:       ; %bb.0:
2304; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, 5
2305; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2306; GFX10-NEXT:    ; return to shader part epilog
2307  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 5)
2308  ret i32 %result
2309}
2310
2311define amdgpu_ps i32 @s_fshr_i32_8(i32 inreg %lhs, i32 inreg %rhs) {
2312; GFX6-LABEL: s_fshr_i32_8:
2313; GFX6:       ; %bb.0:
2314; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2315; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 8
2316; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2317; GFX6-NEXT:    ; return to shader part epilog
2318;
2319; GFX8-LABEL: s_fshr_i32_8:
2320; GFX8:       ; %bb.0:
2321; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2322; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 8
2323; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2324; GFX8-NEXT:    ; return to shader part epilog
2325;
2326; GFX9-LABEL: s_fshr_i32_8:
2327; GFX9:       ; %bb.0:
2328; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2329; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 8
2330; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2331; GFX9-NEXT:    ; return to shader part epilog
2332;
2333; GFX10-LABEL: s_fshr_i32_8:
2334; GFX10:       ; %bb.0:
2335; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, 8
2336; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2337; GFX10-NEXT:    ; return to shader part epilog
2338  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 8)
2339  ret i32 %result
2340}
2341
2342define i32 @v_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt) {
2343; GFX6-LABEL: v_fshr_i32:
2344; GFX6:       ; %bb.0:
2345; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2346; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2347; GFX6-NEXT:    s_setpc_b64 s[30:31]
2348;
2349; GFX8-LABEL: v_fshr_i32:
2350; GFX8:       ; %bb.0:
2351; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2352; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2353; GFX8-NEXT:    s_setpc_b64 s[30:31]
2354;
2355; GFX9-LABEL: v_fshr_i32:
2356; GFX9:       ; %bb.0:
2357; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2358; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2359; GFX9-NEXT:    s_setpc_b64 s[30:31]
2360;
2361; GFX10-LABEL: v_fshr_i32:
2362; GFX10:       ; %bb.0:
2363; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2364; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2365; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2366; GFX10-NEXT:    s_setpc_b64 s[30:31]
2367  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2368  ret i32 %result
2369}
2370
2371define i32 @v_fshr_i32_5(i32 %lhs, i32 %rhs) {
2372; GFX6-LABEL: v_fshr_i32_5:
2373; GFX6:       ; %bb.0:
2374; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2375; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2376; GFX6-NEXT:    s_setpc_b64 s[30:31]
2377;
2378; GFX8-LABEL: v_fshr_i32_5:
2379; GFX8:       ; %bb.0:
2380; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2381; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2382; GFX8-NEXT:    s_setpc_b64 s[30:31]
2383;
2384; GFX9-LABEL: v_fshr_i32_5:
2385; GFX9:       ; %bb.0:
2386; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2387; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2388; GFX9-NEXT:    s_setpc_b64 s[30:31]
2389;
2390; GFX10-LABEL: v_fshr_i32_5:
2391; GFX10:       ; %bb.0:
2392; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2393; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2394; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2395; GFX10-NEXT:    s_setpc_b64 s[30:31]
2396  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 5)
2397  ret i32 %result
2398}
2399
2400define i32 @v_fshr_i32_8(i32 %lhs, i32 %rhs) {
2401; GFX6-LABEL: v_fshr_i32_8:
2402; GFX6:       ; %bb.0:
2403; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2404; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2405; GFX6-NEXT:    s_setpc_b64 s[30:31]
2406;
2407; GFX8-LABEL: v_fshr_i32_8:
2408; GFX8:       ; %bb.0:
2409; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2410; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2411; GFX8-NEXT:    s_setpc_b64 s[30:31]
2412;
2413; GFX9-LABEL: v_fshr_i32_8:
2414; GFX9:       ; %bb.0:
2415; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2416; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2417; GFX9-NEXT:    s_setpc_b64 s[30:31]
2418;
2419; GFX10-LABEL: v_fshr_i32_8:
2420; GFX10:       ; %bb.0:
2421; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2422; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2423; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2424; GFX10-NEXT:    s_setpc_b64 s[30:31]
2425  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 8)
2426  ret i32 %result
2427}
2428
2429define amdgpu_ps float @v_fshr_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) {
2430; GFX6-LABEL: v_fshr_i32_ssv:
2431; GFX6:       ; %bb.0:
2432; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2433; GFX6-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2434; GFX6-NEXT:    ; return to shader part epilog
2435;
2436; GFX8-LABEL: v_fshr_i32_ssv:
2437; GFX8:       ; %bb.0:
2438; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2439; GFX8-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2440; GFX8-NEXT:    ; return to shader part epilog
2441;
2442; GFX9-LABEL: v_fshr_i32_ssv:
2443; GFX9:       ; %bb.0:
2444; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2445; GFX9-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2446; GFX9-NEXT:    ; return to shader part epilog
2447;
2448; GFX10-LABEL: v_fshr_i32_ssv:
2449; GFX10:       ; %bb.0:
2450; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, v0
2451; GFX10-NEXT:    ; return to shader part epilog
2452  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2453  %cast.result = bitcast i32 %result to float
2454  ret float %cast.result
2455}
2456
2457define amdgpu_ps float @v_fshr_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt) {
2458; GFX6-LABEL: v_fshr_i32_svs:
2459; GFX6:       ; %bb.0:
2460; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2461; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2462; GFX6-NEXT:    ; return to shader part epilog
2463;
2464; GFX8-LABEL: v_fshr_i32_svs:
2465; GFX8:       ; %bb.0:
2466; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2467; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2468; GFX8-NEXT:    ; return to shader part epilog
2469;
2470; GFX9-LABEL: v_fshr_i32_svs:
2471; GFX9:       ; %bb.0:
2472; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2473; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2474; GFX9-NEXT:    ; return to shader part epilog
2475;
2476; GFX10-LABEL: v_fshr_i32_svs:
2477; GFX10:       ; %bb.0:
2478; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
2479; GFX10-NEXT:    ; return to shader part epilog
2480  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2481  %cast.result = bitcast i32 %result to float
2482  ret float %cast.result
2483}
2484
2485define amdgpu_ps float @v_fshr_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
2486; GFX6-LABEL: v_fshr_i32_vss:
2487; GFX6:       ; %bb.0:
2488; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2489; GFX6-NEXT:    v_mov_b32_e32 v1, s2
2490; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2491; GFX6-NEXT:    ; return to shader part epilog
2492;
2493; GFX8-LABEL: v_fshr_i32_vss:
2494; GFX8:       ; %bb.0:
2495; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2496; GFX8-NEXT:    v_mov_b32_e32 v1, s2
2497; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2498; GFX8-NEXT:    ; return to shader part epilog
2499;
2500; GFX9-LABEL: v_fshr_i32_vss:
2501; GFX9:       ; %bb.0:
2502; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2503; GFX9-NEXT:    v_mov_b32_e32 v1, s2
2504; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2505; GFX9-NEXT:    ; return to shader part epilog
2506;
2507; GFX10-LABEL: v_fshr_i32_vss:
2508; GFX10:       ; %bb.0:
2509; GFX10-NEXT:    v_mov_b32_e32 v0, s2
2510; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, v0
2511; GFX10-NEXT:    ; return to shader part epilog
2512  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2513  %cast.result = bitcast i32 %result to float
2514  ret float %cast.result
2515}
2516
2517define <2 x i32> @v_fshr_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
2518; GFX6-LABEL: v_fshr_v2i32:
2519; GFX6:       ; %bb.0:
2520; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2521; GFX6-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2522; GFX6-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2523; GFX6-NEXT:    s_setpc_b64 s[30:31]
2524;
2525; GFX8-LABEL: v_fshr_v2i32:
2526; GFX8:       ; %bb.0:
2527; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2528; GFX8-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2529; GFX8-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2530; GFX8-NEXT:    s_setpc_b64 s[30:31]
2531;
2532; GFX9-LABEL: v_fshr_v2i32:
2533; GFX9:       ; %bb.0:
2534; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2535; GFX9-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2536; GFX9-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2537; GFX9-NEXT:    s_setpc_b64 s[30:31]
2538;
2539; GFX10-LABEL: v_fshr_v2i32:
2540; GFX10:       ; %bb.0:
2541; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2542; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2543; GFX10-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2544; GFX10-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2545; GFX10-NEXT:    s_setpc_b64 s[30:31]
2546  %result = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt)
2547  ret <2 x i32> %result
2548}
2549
2550define <3 x i32> @v_fshr_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
2551; GFX6-LABEL: v_fshr_v3i32:
2552; GFX6:       ; %bb.0:
2553; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2554; GFX6-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2555; GFX6-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2556; GFX6-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2557; GFX6-NEXT:    s_setpc_b64 s[30:31]
2558;
2559; GFX8-LABEL: v_fshr_v3i32:
2560; GFX8:       ; %bb.0:
2561; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2562; GFX8-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2563; GFX8-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2564; GFX8-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2565; GFX8-NEXT:    s_setpc_b64 s[30:31]
2566;
2567; GFX9-LABEL: v_fshr_v3i32:
2568; GFX9:       ; %bb.0:
2569; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2570; GFX9-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2571; GFX9-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2572; GFX9-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2573; GFX9-NEXT:    s_setpc_b64 s[30:31]
2574;
2575; GFX10-LABEL: v_fshr_v3i32:
2576; GFX10:       ; %bb.0:
2577; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2578; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2579; GFX10-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2580; GFX10-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2581; GFX10-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2582; GFX10-NEXT:    s_setpc_b64 s[30:31]
2583  %result = call <3 x i32> @llvm.fshr.v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt)
2584  ret <3 x i32> %result
2585}
2586
2587define <4 x i32> @v_fshr_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
2588; GFX6-LABEL: v_fshr_v4i32:
2589; GFX6:       ; %bb.0:
2590; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2591; GFX6-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2592; GFX6-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2593; GFX6-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2594; GFX6-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2595; GFX6-NEXT:    s_setpc_b64 s[30:31]
2596;
2597; GFX8-LABEL: v_fshr_v4i32:
2598; GFX8:       ; %bb.0:
2599; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2600; GFX8-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2601; GFX8-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2602; GFX8-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2603; GFX8-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2604; GFX8-NEXT:    s_setpc_b64 s[30:31]
2605;
2606; GFX9-LABEL: v_fshr_v4i32:
2607; GFX9:       ; %bb.0:
2608; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2609; GFX9-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2610; GFX9-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2611; GFX9-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2612; GFX9-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2613; GFX9-NEXT:    s_setpc_b64 s[30:31]
2614;
2615; GFX10-LABEL: v_fshr_v4i32:
2616; GFX10:       ; %bb.0:
2617; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2618; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2619; GFX10-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2620; GFX10-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2621; GFX10-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2622; GFX10-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2623; GFX10-NEXT:    s_setpc_b64 s[30:31]
2624  %result = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt)
2625  ret <4 x i32> %result
2626}
2627
2628define amdgpu_ps i16 @s_fshr_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt) {
2629; GFX6-LABEL: s_fshr_i16:
2630; GFX6:       ; %bb.0:
2631; GFX6-NEXT:    s_and_b32 s3, s2, 15
2632; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
2633; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
2634; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
2635; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
2636; GFX6-NEXT:    s_bfe_u32 s2, s3, 0x100000
2637; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2638; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
2639; GFX6-NEXT:    s_or_b32 s0, s0, s1
2640; GFX6-NEXT:    ; return to shader part epilog
2641;
2642; GFX8-LABEL: s_fshr_i16:
2643; GFX8:       ; %bb.0:
2644; GFX8-NEXT:    s_and_b32 s3, s2, 15
2645; GFX8-NEXT:    s_andn2_b32 s2, 15, s2
2646; GFX8-NEXT:    s_bfe_u32 s4, 1, 0x100000
2647; GFX8-NEXT:    s_lshl_b32 s0, s0, s4
2648; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
2649; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2650; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2651; GFX8-NEXT:    s_bfe_u32 s2, s3, 0x100000
2652; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2653; GFX8-NEXT:    s_or_b32 s0, s0, s1
2654; GFX8-NEXT:    ; return to shader part epilog
2655;
2656; GFX9-LABEL: s_fshr_i16:
2657; GFX9:       ; %bb.0:
2658; GFX9-NEXT:    s_and_b32 s3, s2, 15
2659; GFX9-NEXT:    s_andn2_b32 s2, 15, s2
2660; GFX9-NEXT:    s_bfe_u32 s4, 1, 0x100000
2661; GFX9-NEXT:    s_lshl_b32 s0, s0, s4
2662; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
2663; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2664; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2665; GFX9-NEXT:    s_bfe_u32 s2, s3, 0x100000
2666; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2667; GFX9-NEXT:    s_or_b32 s0, s0, s1
2668; GFX9-NEXT:    ; return to shader part epilog
2669;
2670; GFX10-LABEL: s_fshr_i16:
2671; GFX10:       ; %bb.0:
2672; GFX10-NEXT:    s_and_b32 s3, s2, 15
2673; GFX10-NEXT:    s_andn2_b32 s2, 15, s2
2674; GFX10-NEXT:    s_bfe_u32 s4, 1, 0x100000
2675; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
2676; GFX10-NEXT:    s_lshl_b32 s0, s0, s4
2677; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2678; GFX10-NEXT:    s_bfe_u32 s3, s3, 0x100000
2679; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2680; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2681; GFX10-NEXT:    s_or_b32 s0, s0, s1
2682; GFX10-NEXT:    ; return to shader part epilog
2683  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2684  ret i16 %result
2685}
2686
2687define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
2688; GFX6-LABEL: s_fshr_i16_4:
2689; GFX6:       ; %bb.0:
2690; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2691; GFX6-NEXT:    s_lshl_b32 s0, s0, 12
2692; GFX6-NEXT:    s_lshr_b32 s1, s1, 4
2693; GFX6-NEXT:    s_or_b32 s0, s0, s1
2694; GFX6-NEXT:    ; return to shader part epilog
2695;
2696; GFX8-LABEL: s_fshr_i16_4:
2697; GFX8:       ; %bb.0:
2698; GFX8-NEXT:    s_bfe_u32 s2, 12, 0x100000
2699; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2700; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2701; GFX8-NEXT:    s_bfe_u32 s2, 4, 0x100000
2702; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2703; GFX8-NEXT:    s_or_b32 s0, s0, s1
2704; GFX8-NEXT:    ; return to shader part epilog
2705;
2706; GFX9-LABEL: s_fshr_i16_4:
2707; GFX9:       ; %bb.0:
2708; GFX9-NEXT:    s_bfe_u32 s2, 12, 0x100000
2709; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2710; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2711; GFX9-NEXT:    s_bfe_u32 s2, 4, 0x100000
2712; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2713; GFX9-NEXT:    s_or_b32 s0, s0, s1
2714; GFX9-NEXT:    ; return to shader part epilog
2715;
2716; GFX10-LABEL: s_fshr_i16_4:
2717; GFX10:       ; %bb.0:
2718; GFX10-NEXT:    s_bfe_u32 s2, 12, 0x100000
2719; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2720; GFX10-NEXT:    s_bfe_u32 s3, 4, 0x100000
2721; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2722; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2723; GFX10-NEXT:    s_or_b32 s0, s0, s1
2724; GFX10-NEXT:    ; return to shader part epilog
2725  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 4)
2726  ret i16 %result
2727}
2728
2729define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
2730; GFX6-LABEL: s_fshr_i16_5:
2731; GFX6:       ; %bb.0:
2732; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2733; GFX6-NEXT:    s_lshl_b32 s0, s0, 11
2734; GFX6-NEXT:    s_lshr_b32 s1, s1, 5
2735; GFX6-NEXT:    s_or_b32 s0, s0, s1
2736; GFX6-NEXT:    ; return to shader part epilog
2737;
2738; GFX8-LABEL: s_fshr_i16_5:
2739; GFX8:       ; %bb.0:
2740; GFX8-NEXT:    s_bfe_u32 s2, 11, 0x100000
2741; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2742; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2743; GFX8-NEXT:    s_bfe_u32 s2, 5, 0x100000
2744; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2745; GFX8-NEXT:    s_or_b32 s0, s0, s1
2746; GFX8-NEXT:    ; return to shader part epilog
2747;
2748; GFX9-LABEL: s_fshr_i16_5:
2749; GFX9:       ; %bb.0:
2750; GFX9-NEXT:    s_bfe_u32 s2, 11, 0x100000
2751; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2752; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2753; GFX9-NEXT:    s_bfe_u32 s2, 5, 0x100000
2754; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2755; GFX9-NEXT:    s_or_b32 s0, s0, s1
2756; GFX9-NEXT:    ; return to shader part epilog
2757;
2758; GFX10-LABEL: s_fshr_i16_5:
2759; GFX10:       ; %bb.0:
2760; GFX10-NEXT:    s_bfe_u32 s2, 11, 0x100000
2761; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2762; GFX10-NEXT:    s_bfe_u32 s3, 5, 0x100000
2763; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2764; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2765; GFX10-NEXT:    s_or_b32 s0, s0, s1
2766; GFX10-NEXT:    ; return to shader part epilog
2767  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 5)
2768  ret i16 %result
2769}
2770
2771define i16 @v_fshr_i16(i16 %lhs, i16 %rhs, i16 %amt) {
2772; GFX6-LABEL: v_fshr_i16:
2773; GFX6:       ; %bb.0:
2774; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2775; GFX6-NEXT:    v_and_b32_e32 v3, 15, v2
2776; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
2777; GFX6-NEXT:    v_and_b32_e32 v2, 15, v2
2778; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2779; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
2780; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
2781; GFX6-NEXT:    v_bfe_u32 v2, v3, 0, 16
2782; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2783; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
2784; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2785; GFX6-NEXT:    s_setpc_b64 s[30:31]
2786;
2787; GFX8-LABEL: v_fshr_i16:
2788; GFX8:       ; %bb.0:
2789; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2790; GFX8-NEXT:    v_and_b32_e32 v3, 15, v2
2791; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
2792; GFX8-NEXT:    v_and_b32_e32 v2, 15, v2
2793; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
2794; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
2795; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v3, v1
2796; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2797; GFX8-NEXT:    s_setpc_b64 s[30:31]
2798;
2799; GFX9-LABEL: v_fshr_i16:
2800; GFX9:       ; %bb.0:
2801; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2802; GFX9-NEXT:    v_and_b32_e32 v3, 15, v2
2803; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
2804; GFX9-NEXT:    v_and_b32_e32 v2, 15, v2
2805; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
2806; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
2807; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v3, v1
2808; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2809; GFX9-NEXT:    s_setpc_b64 s[30:31]
2810;
2811; GFX10-LABEL: v_fshr_i16:
2812; GFX10:       ; %bb.0:
2813; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2814; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2815; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
2816; GFX10-NEXT:    v_and_b32_e32 v2, 15, v2
2817; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
2818; GFX10-NEXT:    v_and_b32_e32 v3, 15, v3
2819; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
2820; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v3, v0
2821; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2822; GFX10-NEXT:    s_setpc_b64 s[30:31]
2823  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2824  ret i16 %result
2825}
2826
2827define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
2828; GFX6-LABEL: v_fshr_i16_4:
2829; GFX6:       ; %bb.0:
2830; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2831; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2832; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 12, v0
2833; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 4, v1
2834; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2835; GFX6-NEXT:    s_setpc_b64 s[30:31]
2836;
2837; GFX8-LABEL: v_fshr_i16_4:
2838; GFX8:       ; %bb.0:
2839; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2840; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 12, v0
2841; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 4, v1
2842; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2843; GFX8-NEXT:    s_setpc_b64 s[30:31]
2844;
2845; GFX9-LABEL: v_fshr_i16_4:
2846; GFX9:       ; %bb.0:
2847; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2848; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 12, v0
2849; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 4, v1
2850; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2851; GFX9-NEXT:    s_setpc_b64 s[30:31]
2852;
2853; GFX10-LABEL: v_fshr_i16_4:
2854; GFX10:       ; %bb.0:
2855; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2856; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2857; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 12, v0
2858; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 4, v1
2859; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2860; GFX10-NEXT:    s_setpc_b64 s[30:31]
2861  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 4)
2862  ret i16 %result
2863}
2864
2865define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
2866; GFX6-LABEL: v_fshr_i16_5:
2867; GFX6:       ; %bb.0:
2868; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2869; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2870; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 11, v0
2871; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 5, v1
2872; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2873; GFX6-NEXT:    s_setpc_b64 s[30:31]
2874;
2875; GFX8-LABEL: v_fshr_i16_5:
2876; GFX8:       ; %bb.0:
2877; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2878; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 11, v0
2879; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 5, v1
2880; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2881; GFX8-NEXT:    s_setpc_b64 s[30:31]
2882;
2883; GFX9-LABEL: v_fshr_i16_5:
2884; GFX9:       ; %bb.0:
2885; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2886; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 11, v0
2887; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 5, v1
2888; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2889; GFX9-NEXT:    s_setpc_b64 s[30:31]
2890;
2891; GFX10-LABEL: v_fshr_i16_5:
2892; GFX10:       ; %bb.0:
2893; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2894; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2895; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 11, v0
2896; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 5, v1
2897; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2898; GFX10-NEXT:    s_setpc_b64 s[30:31]
2899  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 5)
2900  ret i16 %result
2901}
2902
2903define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt) {
2904; GFX6-LABEL: v_fshr_i16_ssv:
2905; GFX6:       ; %bb.0:
2906; GFX6-NEXT:    v_and_b32_e32 v1, 15, v0
2907; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
2908; GFX6-NEXT:    v_and_b32_e32 v0, 15, v0
2909; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
2910; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
2911; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0
2912; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
2913; GFX6-NEXT:    s_and_b32 s0, s1, 0xffff
2914; GFX6-NEXT:    v_lshr_b32_e32 v1, s0, v1
2915; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2916; GFX6-NEXT:    ; return to shader part epilog
2917;
2918; GFX8-LABEL: v_fshr_i16_ssv:
2919; GFX8:       ; %bb.0:
2920; GFX8-NEXT:    v_and_b32_e32 v1, 15, v0
2921; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
2922; GFX8-NEXT:    s_bfe_u32 s2, 1, 0x100000
2923; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
2924; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2925; GFX8-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
2926; GFX8-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
2927; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2928; GFX8-NEXT:    ; return to shader part epilog
2929;
2930; GFX9-LABEL: v_fshr_i16_ssv:
2931; GFX9:       ; %bb.0:
2932; GFX9-NEXT:    v_and_b32_e32 v1, 15, v0
2933; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
2934; GFX9-NEXT:    s_bfe_u32 s2, 1, 0x100000
2935; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
2936; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2937; GFX9-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
2938; GFX9-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
2939; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2940; GFX9-NEXT:    ; return to shader part epilog
2941;
2942; GFX10-LABEL: v_fshr_i16_ssv:
2943; GFX10:       ; %bb.0:
2944; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
2945; GFX10-NEXT:    v_and_b32_e32 v0, 15, v0
2946; GFX10-NEXT:    s_bfe_u32 s2, 1, 0x100000
2947; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2948; GFX10-NEXT:    v_and_b32_e32 v1, 15, v1
2949; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
2950; GFX10-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
2951; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
2952; GFX10-NEXT:    ; return to shader part epilog
2953  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2954  %cast.result = bitcast i16 %result to half
2955  ret half %cast.result
2956}
2957
2958define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt) {
2959; GFX6-LABEL: v_fshr_i16_svs:
2960; GFX6:       ; %bb.0:
2961; GFX6-NEXT:    s_and_b32 s2, s1, 15
2962; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
2963; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
2964; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
2965; GFX6-NEXT:    s_lshl_b32 s0, s0, s1
2966; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
2967; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
2968; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s1, v0
2969; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
2970; GFX6-NEXT:    ; return to shader part epilog
2971;
2972; GFX8-LABEL: v_fshr_i16_svs:
2973; GFX8:       ; %bb.0:
2974; GFX8-NEXT:    s_and_b32 s2, s1, 15
2975; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
2976; GFX8-NEXT:    s_bfe_u32 s3, 1, 0x100000
2977; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
2978; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2979; GFX8-NEXT:    s_lshl_b32 s0, s0, s1
2980; GFX8-NEXT:    v_lshrrev_b16_e32 v0, s2, v0
2981; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
2982; GFX8-NEXT:    ; return to shader part epilog
2983;
2984; GFX9-LABEL: v_fshr_i16_svs:
2985; GFX9:       ; %bb.0:
2986; GFX9-NEXT:    s_and_b32 s2, s1, 15
2987; GFX9-NEXT:    s_andn2_b32 s1, 15, s1
2988; GFX9-NEXT:    s_bfe_u32 s3, 1, 0x100000
2989; GFX9-NEXT:    s_lshl_b32 s0, s0, s3
2990; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2991; GFX9-NEXT:    s_lshl_b32 s0, s0, s1
2992; GFX9-NEXT:    v_lshrrev_b16_e32 v0, s2, v0
2993; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
2994; GFX9-NEXT:    ; return to shader part epilog
2995;
2996; GFX10-LABEL: v_fshr_i16_svs:
2997; GFX10:       ; %bb.0:
2998; GFX10-NEXT:    s_and_b32 s2, s1, 15
2999; GFX10-NEXT:    s_andn2_b32 s1, 15, s1
3000; GFX10-NEXT:    s_bfe_u32 s3, 1, 0x100000
3001; GFX10-NEXT:    v_lshrrev_b16_e64 v0, s2, v0
3002; GFX10-NEXT:    s_lshl_b32 s0, s0, s3
3003; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
3004; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
3005; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3006; GFX10-NEXT:    ; return to shader part epilog
3007  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
3008  %cast.result = bitcast i16 %result to half
3009  ret half %cast.result
3010}
3011
3012define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt) {
3013; GFX6-LABEL: v_fshr_i16_vss:
3014; GFX6:       ; %bb.0:
3015; GFX6-NEXT:    s_and_b32 s2, s1, 15
3016; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3017; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
3018; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3019; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s1, v0
3020; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
3021; GFX6-NEXT:    s_and_b32 s0, s0, 0xffff
3022; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
3023; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
3024; GFX6-NEXT:    ; return to shader part epilog
3025;
3026; GFX8-LABEL: v_fshr_i16_vss:
3027; GFX8:       ; %bb.0:
3028; GFX8-NEXT:    s_and_b32 s2, s1, 15
3029; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3030; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
3031; GFX8-NEXT:    v_lshlrev_b16_e32 v0, s1, v0
3032; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3033; GFX8-NEXT:    s_bfe_u32 s1, s2, 0x100000
3034; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3035; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3036; GFX8-NEXT:    ; return to shader part epilog
3037;
3038; GFX9-LABEL: v_fshr_i16_vss:
3039; GFX9:       ; %bb.0:
3040; GFX9-NEXT:    s_and_b32 s2, s1, 15
3041; GFX9-NEXT:    s_andn2_b32 s1, 15, s1
3042; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
3043; GFX9-NEXT:    v_lshlrev_b16_e32 v0, s1, v0
3044; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
3045; GFX9-NEXT:    s_bfe_u32 s1, s2, 0x100000
3046; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
3047; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3048; GFX9-NEXT:    ; return to shader part epilog
3049;
3050; GFX10-LABEL: v_fshr_i16_vss:
3051; GFX10:       ; %bb.0:
3052; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
3053; GFX10-NEXT:    s_andn2_b32 s2, 15, s1
3054; GFX10-NEXT:    s_and_b32 s1, s1, 15
3055; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
3056; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
3057; GFX10-NEXT:    v_lshlrev_b16_e64 v0, s2, v0
3058; GFX10-NEXT:    s_lshr_b32 s0, s0, s1
3059; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3060; GFX10-NEXT:    ; return to shader part epilog
3061  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
3062  %cast.result = bitcast i16 %result to half
3063  ret half %cast.result
3064}
3065
3066define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
3067; GFX6-LABEL: s_fshr_v2i16:
3068; GFX6:       ; %bb.0:
3069; GFX6-NEXT:    s_mov_b32 s5, 0xffff
3070; GFX6-NEXT:    s_lshr_b32 s3, s0, 16
3071; GFX6-NEXT:    s_bfe_u32 s4, 1, 0x100000
3072; GFX6-NEXT:    s_and_b32 s6, s1, s5
3073; GFX6-NEXT:    s_lshl_b32 s0, s0, s4
3074; GFX6-NEXT:    s_lshl_b32 s3, s3, s4
3075; GFX6-NEXT:    s_bfe_u32 s7, 14, 0x100000
3076; GFX6-NEXT:    s_lshr_b32 s4, s1, 17
3077; GFX6-NEXT:    s_lshr_b32 s6, s6, 1
3078; GFX6-NEXT:    s_lshr_b32 s4, s4, s7
3079; GFX6-NEXT:    s_lshr_b32 s6, s6, s7
3080; GFX6-NEXT:    s_or_b32 s3, s3, s4
3081; GFX6-NEXT:    s_lshr_b32 s4, s1, 16
3082; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
3083; GFX6-NEXT:    s_xor_b32 s2, s2, -1
3084; GFX6-NEXT:    s_and_b32 s7, s2, 15
3085; GFX6-NEXT:    s_and_b32 s1, s1, s5
3086; GFX6-NEXT:    s_or_b32 s0, s0, s6
3087; GFX6-NEXT:    s_lshr_b32 s6, s2, 16
3088; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
3089; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
3090; GFX6-NEXT:    s_lshr_b32 s1, s1, 1
3091; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3092; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
3093; GFX6-NEXT:    s_lshl_b32 s0, s0, s7
3094; GFX6-NEXT:    s_or_b32 s0, s0, s1
3095; GFX6-NEXT:    s_and_b32 s1, s6, 15
3096; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3097; GFX6-NEXT:    s_lshl_b32 s4, s4, 1
3098; GFX6-NEXT:    s_andn2_b32 s2, 15, s6
3099; GFX6-NEXT:    s_lshl_b32 s1, s3, s1
3100; GFX6-NEXT:    s_and_b32 s3, s4, s5
3101; GFX6-NEXT:    s_lshr_b32 s3, s3, 1
3102; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3103; GFX6-NEXT:    s_lshr_b32 s2, s3, s2
3104; GFX6-NEXT:    s_or_b32 s1, s1, s2
3105; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3106; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3107; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
3108; GFX6-NEXT:    s_or_b32 s0, s0, s1
3109; GFX6-NEXT:    ; return to shader part epilog
3110;
3111; GFX8-LABEL: s_fshr_v2i16:
3112; GFX8:       ; %bb.0:
3113; GFX8-NEXT:    s_bfe_u32 s5, 1, 0x100000
3114; GFX8-NEXT:    s_bfe_u32 s6, s1, 0x100000
3115; GFX8-NEXT:    s_lshr_b32 s6, s6, s5
3116; GFX8-NEXT:    s_bfe_u32 s7, 14, 0x100000
3117; GFX8-NEXT:    s_lshr_b32 s3, s0, 16
3118; GFX8-NEXT:    s_lshr_b32 s4, s1, 16
3119; GFX8-NEXT:    s_lshl_b32 s0, s0, s5
3120; GFX8-NEXT:    s_lshr_b32 s6, s6, s7
3121; GFX8-NEXT:    s_or_b32 s0, s0, s6
3122; GFX8-NEXT:    s_lshr_b32 s6, s4, s5
3123; GFX8-NEXT:    s_lshl_b32 s1, s1, s5
3124; GFX8-NEXT:    s_lshl_b32 s3, s3, s5
3125; GFX8-NEXT:    s_lshr_b32 s6, s6, s7
3126; GFX8-NEXT:    s_xor_b32 s2, s2, -1
3127; GFX8-NEXT:    s_and_b32 s7, s2, 15
3128; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3129; GFX8-NEXT:    s_or_b32 s3, s3, s6
3130; GFX8-NEXT:    s_lshr_b32 s6, s2, 16
3131; GFX8-NEXT:    s_andn2_b32 s2, 15, s2
3132; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
3133; GFX8-NEXT:    s_lshr_b32 s1, s1, s5
3134; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3135; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
3136; GFX8-NEXT:    s_lshl_b32 s0, s0, s7
3137; GFX8-NEXT:    s_or_b32 s0, s0, s1
3138; GFX8-NEXT:    s_and_b32 s1, s6, 15
3139; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3140; GFX8-NEXT:    s_lshl_b32 s4, s4, s5
3141; GFX8-NEXT:    s_andn2_b32 s2, 15, s6
3142; GFX8-NEXT:    s_lshl_b32 s1, s3, s1
3143; GFX8-NEXT:    s_bfe_u32 s3, s4, 0x100000
3144; GFX8-NEXT:    s_lshr_b32 s3, s3, s5
3145; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3146; GFX8-NEXT:    s_lshr_b32 s2, s3, s2
3147; GFX8-NEXT:    s_or_b32 s1, s1, s2
3148; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3149; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3150; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
3151; GFX8-NEXT:    s_or_b32 s0, s0, s1
3152; GFX8-NEXT:    ; return to shader part epilog
3153;
3154; GFX9-LABEL: s_fshr_v2i16:
3155; GFX9:       ; %bb.0:
3156; GFX9-NEXT:    s_mov_b32 s3, 0xf000f
3157; GFX9-NEXT:    s_and_b32 s4, s2, s3
3158; GFX9-NEXT:    s_andn2_b32 s2, s3, s2
3159; GFX9-NEXT:    s_lshr_b32 s3, s0, 16
3160; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3161; GFX9-NEXT:    s_lshl_b32 s3, s3, 1
3162; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
3163; GFX9-NEXT:    s_lshr_b32 s3, s0, 16
3164; GFX9-NEXT:    s_lshr_b32 s5, s2, 16
3165; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
3166; GFX9-NEXT:    s_lshl_b32 s2, s3, s5
3167; GFX9-NEXT:    s_mov_b32 s3, 0xffff
3168; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3169; GFX9-NEXT:    s_lshr_b32 s2, s1, 16
3170; GFX9-NEXT:    s_and_b32 s1, s1, s3
3171; GFX9-NEXT:    s_lshr_b32 s5, s4, 16
3172; GFX9-NEXT:    s_and_b32 s3, s4, s3
3173; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
3174; GFX9-NEXT:    s_lshr_b32 s2, s2, s5
3175; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
3176; GFX9-NEXT:    s_or_b32 s0, s0, s1
3177; GFX9-NEXT:    ; return to shader part epilog
3178;
3179; GFX10-LABEL: s_fshr_v2i16:
3180; GFX10:       ; %bb.0:
3181; GFX10-NEXT:    s_lshr_b32 s4, s0, 16
3182; GFX10-NEXT:    s_mov_b32 s3, 0xf000f
3183; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3184; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
3185; GFX10-NEXT:    s_and_b32 s5, s2, s3
3186; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
3187; GFX10-NEXT:    s_andn2_b32 s2, s3, s2
3188; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3189; GFX10-NEXT:    s_lshr_b32 s4, s2, 16
3190; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
3191; GFX10-NEXT:    s_lshl_b32 s2, s3, s4
3192; GFX10-NEXT:    s_mov_b32 s3, 0xffff
3193; GFX10-NEXT:    s_lshr_b32 s4, s1, 16
3194; GFX10-NEXT:    s_and_b32 s1, s1, s3
3195; GFX10-NEXT:    s_and_b32 s3, s5, s3
3196; GFX10-NEXT:    s_lshr_b32 s5, s5, 16
3197; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
3198; GFX10-NEXT:    s_lshr_b32 s3, s4, s5
3199; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3200; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
3201; GFX10-NEXT:    s_or_b32 s0, s0, s1
3202; GFX10-NEXT:    ; return to shader part epilog
3203  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3204  %cast = bitcast <2 x i16> %result to i32
3205  ret i32 %cast
3206}
3207
3208define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
3209; GFX6-LABEL: v_fshr_v2i16:
3210; GFX6:       ; %bb.0:
3211; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3212; GFX6-NEXT:    s_mov_b32 s5, 0xffff
3213; GFX6-NEXT:    v_and_b32_e32 v4, s5, v1
3214; GFX6-NEXT:    s_bfe_u32 s4, 1, 0x100000
3215; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
3216; GFX6-NEXT:    s_bfe_u32 s6, 14, 0x100000
3217; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
3218; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
3219; GFX6-NEXT:    v_lshrrev_b32_e32 v4, s6, v4
3220; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
3221; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 17, v1
3222; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
3223; GFX6-NEXT:    v_lshlrev_b32_e32 v3, s4, v3
3224; GFX6-NEXT:    v_lshrrev_b32_e32 v4, s6, v4
3225; GFX6-NEXT:    v_and_b32_e32 v6, 15, v2
3226; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
3227; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
3228; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
3229; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
3230; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
3231; GFX6-NEXT:    v_and_b32_e32 v2, 15, v2
3232; GFX6-NEXT:    v_and_b32_e32 v1, s5, v1
3233; GFX6-NEXT:    v_bfe_u32 v6, v6, 0, 16
3234; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
3235; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3236; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
3237; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v6, v0
3238; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3239; GFX6-NEXT:    v_and_b32_e32 v1, 15, v5
3240; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v5
3241; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3242; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v4
3243; GFX6-NEXT:    v_and_b32_e32 v2, 15, v2
3244; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v1, v3
3245; GFX6-NEXT:    v_and_b32_e32 v3, s5, v4
3246; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
3247; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3248; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
3249; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3250; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3251; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3252; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3253; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3254; GFX6-NEXT:    s_setpc_b64 s[30:31]
3255;
3256; GFX8-LABEL: v_fshr_v2i16:
3257; GFX8:       ; %bb.0:
3258; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3259; GFX8-NEXT:    v_lshrrev_b16_e32 v4, 1, v1
3260; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v0
3261; GFX8-NEXT:    v_lshrrev_b16_e32 v4, 14, v4
3262; GFX8-NEXT:    v_or_b32_e32 v3, v3, v4
3263; GFX8-NEXT:    v_mov_b32_e32 v4, 1
3264; GFX8-NEXT:    v_lshrrev_b16_sdwa v5, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3265; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
3266; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3267; GFX8-NEXT:    v_lshrrev_b16_e32 v5, 14, v5
3268; GFX8-NEXT:    v_or_b32_e32 v0, v0, v5
3269; GFX8-NEXT:    v_lshlrev_b16_e32 v5, 1, v1
3270; GFX8-NEXT:    v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3271; GFX8-NEXT:    v_and_b32_e32 v6, 15, v2
3272; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
3273; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
3274; GFX8-NEXT:    v_and_b32_e32 v2, 15, v2
3275; GFX8-NEXT:    v_lshrrev_b16_e32 v5, 1, v5
3276; GFX8-NEXT:    v_lshlrev_b16_e32 v3, v6, v3
3277; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v2, v5
3278; GFX8-NEXT:    v_or_b32_e32 v2, v3, v2
3279; GFX8-NEXT:    v_and_b32_e32 v3, 15, v4
3280; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
3281; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
3282; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 1, v1
3283; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
3284; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v4, v1
3285; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
3286; GFX8-NEXT:    v_mov_b32_e32 v1, 16
3287; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3288; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3289; GFX8-NEXT:    s_setpc_b64 s[30:31]
3290;
3291; GFX9-LABEL: v_fshr_v2i16:
3292; GFX9:       ; %bb.0:
3293; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3294; GFX9-NEXT:    s_mov_b32 s4, 0xf000f
3295; GFX9-NEXT:    v_and_b32_e32 v3, s4, v2
3296; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
3297; GFX9-NEXT:    v_and_b32_e32 v2, s4, v2
3298; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3299; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
3300; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v3, v1
3301; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3302; GFX9-NEXT:    s_setpc_b64 s[30:31]
3303;
3304; GFX10-LABEL: v_fshr_v2i16:
3305; GFX10:       ; %bb.0:
3306; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3307; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3308; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
3309; GFX10-NEXT:    s_mov_b32 s4, 0xf000f
3310; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3311; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
3312; GFX10-NEXT:    v_and_b32_e32 v3, s4, v3
3313; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
3314; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v3, v0
3315; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3316; GFX10-NEXT:    s_setpc_b64 s[30:31]
3317  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3318  ret <2 x i16> %result
3319}
3320
3321define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
3322; GFX6-LABEL: v_fshr_v2i16_4_8:
3323; GFX6:       ; %bb.0:
3324; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3325; GFX6-NEXT:    s_sub_i32 s4, 0, 4
3326; GFX6-NEXT:    s_and_b32 s6, s4, 15
3327; GFX6-NEXT:    v_and_b32_e32 v3, 0xffff, v1
3328; GFX6-NEXT:    s_xor_b32 s4, s4, -1
3329; GFX6-NEXT:    s_sub_i32 s5, 0, 8
3330; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
3331; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3332; GFX6-NEXT:    v_lshrrev_b32_e32 v3, s4, v3
3333; GFX6-NEXT:    s_and_b32 s4, s5, 15
3334; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
3335; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3336; GFX6-NEXT:    s_xor_b32 s5, s5, -1
3337; GFX6-NEXT:    v_lshlrev_b32_e32 v2, s4, v2
3338; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 17, v1
3339; GFX6-NEXT:    s_bfe_u32 s4, s5, 0x100000
3340; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s4, v1
3341; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
3342; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s6, v0
3343; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3344; GFX6-NEXT:    v_or_b32_e32 v0, v0, v3
3345; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3346; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3347; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3348; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3349; GFX6-NEXT:    s_setpc_b64 s[30:31]
3350;
3351; GFX8-LABEL: v_fshr_v2i16_4_8:
3352; GFX8:       ; %bb.0:
3353; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3354; GFX8-NEXT:    s_sub_i32 s4, 0, 4
3355; GFX8-NEXT:    s_and_b32 s6, s4, 15
3356; GFX8-NEXT:    s_sub_i32 s5, 0, 8
3357; GFX8-NEXT:    s_xor_b32 s4, s4, -1
3358; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 1, v1
3359; GFX8-NEXT:    v_lshrrev_b16_e32 v3, s4, v3
3360; GFX8-NEXT:    v_lshlrev_b16_e32 v2, s6, v0
3361; GFX8-NEXT:    s_and_b32 s4, s5, 15
3362; GFX8-NEXT:    v_or_b32_e32 v2, v2, v3
3363; GFX8-NEXT:    v_mov_b32_e32 v3, s4
3364; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3365; GFX8-NEXT:    v_mov_b32_e32 v3, 1
3366; GFX8-NEXT:    s_xor_b32 s5, s5, -1
3367; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3368; GFX8-NEXT:    v_lshrrev_b16_e32 v1, s5, v1
3369; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
3370; GFX8-NEXT:    v_mov_b32_e32 v1, 16
3371; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3372; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3373; GFX8-NEXT:    s_setpc_b64 s[30:31]
3374;
3375; GFX9-LABEL: v_fshr_v2i16_4_8:
3376; GFX9:       ; %bb.0:
3377; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3378; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, 16
3379; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
3380; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 16
3381; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
3382; GFX9-NEXT:    s_sub_i32 s4, 0, 16
3383; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
3384; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
3385; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
3386; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
3387; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v2
3388; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v3
3389; GFX9-NEXT:    v_mul_hi_u32 v4, v2, v4
3390; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
3391; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
3392; GFX9-NEXT:    v_mul_hi_u32 v2, 4, v2
3393; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
3394; GFX9-NEXT:    v_mul_hi_u32 v3, 8, v3
3395; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
3396; GFX9-NEXT:    v_sub_u32_e32 v2, 4, v2
3397; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v2
3398; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v2
3399; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3400; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 4, v3
3401; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v2
3402; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v2
3403; GFX9-NEXT:    v_sub_u32_e32 v3, 8, v3
3404; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3405; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v3
3406; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v3
3407; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3408; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v3
3409; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v3
3410; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3411; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
3412; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
3413; GFX9-NEXT:    v_and_or_b32 v2, v2, v4, v3
3414; GFX9-NEXT:    v_pk_sub_i16 v3, 16, v2 op_sel_hi:[0,1]
3415; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v3, v0
3416; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
3417; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3418; GFX9-NEXT:    s_setpc_b64 s[30:31]
3419;
3420; GFX10-LABEL: v_fshr_v2i16_4_8:
3421; GFX10:       ; %bb.0:
3422; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3423; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3424; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v2, 16
3425; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 16
3426; GFX10-NEXT:    s_sub_i32 s4, 0, 16
3427; GFX10-NEXT:    v_rcp_iflag_f32_e32 v2, v2
3428; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
3429; GFX10-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
3430; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
3431; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
3432; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
3433; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v2
3434; GFX10-NEXT:    v_mul_lo_u32 v5, s4, v3
3435; GFX10-NEXT:    v_mul_hi_u32 v4, v2, v4
3436; GFX10-NEXT:    v_mul_hi_u32 v5, v3, v5
3437; GFX10-NEXT:    v_add_nc_u32_e32 v2, v2, v4
3438; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v5
3439; GFX10-NEXT:    v_mul_hi_u32 v2, 8, v2
3440; GFX10-NEXT:    v_mul_hi_u32 v3, 4, v3
3441; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
3442; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 4, v3
3443; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 8, v2
3444; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 4, v3
3445; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 16, v2
3446; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v2
3447; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, 16, v3
3448; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
3449; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v3
3450; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 16, v2
3451; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
3452; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v2
3453; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, 16, v3
3454; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
3455; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v3
3456; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3457; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
3458; GFX10-NEXT:    v_and_or_b32 v2, v3, 0xffff, v2
3459; GFX10-NEXT:    v_pk_sub_i16 v3, 16, v2 op_sel_hi:[0,1]
3460; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
3461; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v3, v0
3462; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3463; GFX10-NEXT:    s_setpc_b64 s[30:31]
3464  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> <i16 4, i16 8>)
3465  ret <2 x i16> %result
3466}
3467
3468define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> %amt) {
3469; GFX6-LABEL: v_fshr_v2i16_ssv:
3470; GFX6:       ; %bb.0:
3471; GFX6-NEXT:    s_mov_b32 s4, 0xffff
3472; GFX6-NEXT:    s_and_b32 s5, s1, s4
3473; GFX6-NEXT:    s_lshr_b32 s2, s0, 16
3474; GFX6-NEXT:    s_bfe_u32 s3, 1, 0x100000
3475; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
3476; GFX6-NEXT:    s_lshl_b32 s0, s0, s3
3477; GFX6-NEXT:    s_lshl_b32 s2, s2, s3
3478; GFX6-NEXT:    s_lshr_b32 s5, s5, 1
3479; GFX6-NEXT:    s_bfe_u32 s6, 14, 0x100000
3480; GFX6-NEXT:    s_lshr_b32 s3, s1, 17
3481; GFX6-NEXT:    v_and_b32_e32 v2, 15, v0
3482; GFX6-NEXT:    s_lshr_b32 s5, s5, s6
3483; GFX6-NEXT:    s_lshr_b32 s3, s3, s6
3484; GFX6-NEXT:    s_or_b32 s2, s2, s3
3485; GFX6-NEXT:    s_lshr_b32 s3, s1, 16
3486; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3487; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
3488; GFX6-NEXT:    s_or_b32 s0, s0, s5
3489; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3490; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
3491; GFX6-NEXT:    v_and_b32_e32 v0, 15, v0
3492; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
3493; GFX6-NEXT:    s_and_b32 s0, s1, s4
3494; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3495; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3496; GFX6-NEXT:    v_lshr_b32_e32 v0, s0, v0
3497; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
3498; GFX6-NEXT:    v_and_b32_e32 v2, 15, v1
3499; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1
3500; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
3501; GFX6-NEXT:    v_and_b32_e32 v1, 15, v1
3502; GFX6-NEXT:    s_and_b32 s0, s3, s4
3503; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3504; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3505; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3506; GFX6-NEXT:    v_lshl_b32_e32 v2, s2, v2
3507; GFX6-NEXT:    v_lshr_b32_e32 v1, s0, v1
3508; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3509; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3510; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3511; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3512; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3513; GFX6-NEXT:    ; return to shader part epilog
3514;
3515; GFX8-LABEL: v_fshr_v2i16_ssv:
3516; GFX8:       ; %bb.0:
3517; GFX8-NEXT:    s_bfe_u32 s4, 1, 0x100000
3518; GFX8-NEXT:    s_bfe_u32 s5, s1, 0x100000
3519; GFX8-NEXT:    s_lshr_b32 s5, s5, s4
3520; GFX8-NEXT:    s_bfe_u32 s6, 14, 0x100000
3521; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3522; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
3523; GFX8-NEXT:    s_lshl_b32 s0, s0, s4
3524; GFX8-NEXT:    s_lshr_b32 s5, s5, s6
3525; GFX8-NEXT:    s_lshr_b32 s3, s1, 16
3526; GFX8-NEXT:    s_or_b32 s0, s0, s5
3527; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
3528; GFX8-NEXT:    s_lshl_b32 s1, s1, s4
3529; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3530; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
3531; GFX8-NEXT:    v_lshlrev_b16_e64 v2, v2, s0
3532; GFX8-NEXT:    s_bfe_u32 s0, s1, 0x100000
3533; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
3534; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3535; GFX8-NEXT:    s_lshr_b32 s5, s3, s4
3536; GFX8-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
3537; GFX8-NEXT:    s_lshl_b32 s3, s3, s4
3538; GFX8-NEXT:    s_bfe_u32 s0, s3, 0x100000
3539; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
3540; GFX8-NEXT:    v_and_b32_e32 v2, 15, v1
3541; GFX8-NEXT:    v_xor_b32_e32 v1, -1, v1
3542; GFX8-NEXT:    s_lshl_b32 s2, s2, s4
3543; GFX8-NEXT:    s_lshr_b32 s5, s5, s6
3544; GFX8-NEXT:    s_or_b32 s2, s2, s5
3545; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
3546; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3547; GFX8-NEXT:    v_lshlrev_b16_e64 v2, v2, s2
3548; GFX8-NEXT:    v_lshrrev_b16_e64 v1, v1, s0
3549; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
3550; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3551; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3552; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3553; GFX8-NEXT:    ; return to shader part epilog
3554;
3555; GFX9-LABEL: v_fshr_v2i16_ssv:
3556; GFX9:       ; %bb.0:
3557; GFX9-NEXT:    s_mov_b32 s2, 0xf000f
3558; GFX9-NEXT:    v_and_b32_e32 v1, s2, v0
3559; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
3560; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
3561; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3562; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3563; GFX9-NEXT:    s_lshl_b32 s2, s2, 1
3564; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3565; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v0, s0
3566; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v1, s1
3567; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3568; GFX9-NEXT:    ; return to shader part epilog
3569;
3570; GFX10-LABEL: v_fshr_v2i16_ssv:
3571; GFX10:       ; %bb.0:
3572; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
3573; GFX10-NEXT:    s_mov_b32 s2, 0xf000f
3574; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3575; GFX10-NEXT:    v_and_b32_e32 v0, s2, v0
3576; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3577; GFX10-NEXT:    v_and_b32_e32 v1, s2, v1
3578; GFX10-NEXT:    s_lshl_b32 s2, s3, 1
3579; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3580; GFX10-NEXT:    v_pk_lshrrev_b16 v0, v0, s1
3581; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v1, s0
3582; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
3583; GFX10-NEXT:    ; return to shader part epilog
3584  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3585  %cast = bitcast <2 x i16> %result to float
3586  ret float %cast
3587}
3588
3589define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <2 x i16> inreg %amt) {
3590; GFX6-LABEL: v_fshr_v2i16_svs:
3591; GFX6:       ; %bb.0:
3592; GFX6-NEXT:    s_mov_b32 s4, 0xffff
3593; GFX6-NEXT:    v_and_b32_e32 v1, s4, v0
3594; GFX6-NEXT:    s_bfe_u32 s3, 1, 0x100000
3595; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
3596; GFX6-NEXT:    s_bfe_u32 s5, 14, 0x100000
3597; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 17, v0
3598; GFX6-NEXT:    s_lshr_b32 s2, s0, 16
3599; GFX6-NEXT:    s_lshl_b32 s0, s0, s3
3600; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s5, v1
3601; GFX6-NEXT:    v_or_b32_e32 v1, s0, v1
3602; GFX6-NEXT:    s_lshl_b32 s0, s2, s3
3603; GFX6-NEXT:    v_lshrrev_b32_e32 v2, s5, v2
3604; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
3605; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
3606; GFX6-NEXT:    v_or_b32_e32 v2, s0, v2
3607; GFX6-NEXT:    s_xor_b32 s0, s1, -1
3608; GFX6-NEXT:    s_and_b32 s2, s0, 15
3609; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
3610; GFX6-NEXT:    s_lshr_b32 s1, s0, 16
3611; GFX6-NEXT:    s_andn2_b32 s0, 15, s0
3612; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
3613; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3614; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3615; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s0, v0
3616; GFX6-NEXT:    s_and_b32 s0, s1, 15
3617; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s2, v1
3618; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
3619; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3620; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
3621; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s0, v2
3622; GFX6-NEXT:    v_and_b32_e32 v2, s4, v3
3623; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3624; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
3625; GFX6-NEXT:    s_bfe_u32 s0, s1, 0x100000
3626; GFX6-NEXT:    v_lshrrev_b32_e32 v2, s0, v2
3627; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3628; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3629; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3630; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3631; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3632; GFX6-NEXT:    ; return to shader part epilog
3633;
3634; GFX8-LABEL: v_fshr_v2i16_svs:
3635; GFX8:       ; %bb.0:
3636; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 1, v0
3637; GFX8-NEXT:    v_mov_b32_e32 v2, 1
3638; GFX8-NEXT:    s_bfe_u32 s3, 1, 0x100000
3639; GFX8-NEXT:    v_lshrrev_b16_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3640; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3641; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
3642; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 14, v1
3643; GFX8-NEXT:    v_or_b32_e32 v1, s0, v1
3644; GFX8-NEXT:    s_lshl_b32 s0, s2, s3
3645; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 14, v3
3646; GFX8-NEXT:    v_or_b32_e32 v3, s0, v3
3647; GFX8-NEXT:    s_xor_b32 s0, s1, -1
3648; GFX8-NEXT:    v_lshlrev_b16_e32 v4, 1, v0
3649; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3650; GFX8-NEXT:    s_and_b32 s2, s0, 15
3651; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
3652; GFX8-NEXT:    s_andn2_b32 s0, 15, s0
3653; GFX8-NEXT:    v_lshrrev_b16_e32 v2, 1, v4
3654; GFX8-NEXT:    v_lshrrev_b16_e32 v2, s0, v2
3655; GFX8-NEXT:    v_lshlrev_b16_e32 v1, s2, v1
3656; GFX8-NEXT:    s_and_b32 s0, s1, 15
3657; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3658; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 1, v0
3659; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
3660; GFX8-NEXT:    v_lshlrev_b16_e32 v2, s0, v3
3661; GFX8-NEXT:    v_lshrrev_b16_e32 v0, s1, v0
3662; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
3663; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3664; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3665; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3666; GFX8-NEXT:    ; return to shader part epilog
3667;
3668; GFX9-LABEL: v_fshr_v2i16_svs:
3669; GFX9:       ; %bb.0:
3670; GFX9-NEXT:    s_mov_b32 s2, 0xf000f
3671; GFX9-NEXT:    s_and_b32 s3, s1, s2
3672; GFX9-NEXT:    s_andn2_b32 s1, s2, s1
3673; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3674; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3675; GFX9-NEXT:    s_lshl_b32 s2, s2, 1
3676; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3677; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3678; GFX9-NEXT:    s_lshr_b32 s4, s1, 16
3679; GFX9-NEXT:    s_lshl_b32 s0, s0, s1
3680; GFX9-NEXT:    s_lshl_b32 s1, s2, s4
3681; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3682; GFX9-NEXT:    v_pk_lshrrev_b16 v0, s3, v0
3683; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3684; GFX9-NEXT:    ; return to shader part epilog
3685;
3686; GFX10-LABEL: v_fshr_v2i16_svs:
3687; GFX10:       ; %bb.0:
3688; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3689; GFX10-NEXT:    s_mov_b32 s2, 0xf000f
3690; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3691; GFX10-NEXT:    s_lshl_b32 s3, s3, 1
3692; GFX10-NEXT:    s_and_b32 s4, s1, s2
3693; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
3694; GFX10-NEXT:    s_andn2_b32 s1, s2, s1
3695; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3696; GFX10-NEXT:    s_lshr_b32 s3, s1, 16
3697; GFX10-NEXT:    v_pk_lshrrev_b16 v0, s4, v0
3698; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
3699; GFX10-NEXT:    s_lshl_b32 s1, s2, s3
3700; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3701; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3702; GFX10-NEXT:    ; return to shader part epilog
3703  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3704  %cast = bitcast <2 x i16> %result to float
3705  ret float %cast
3706}
3707
3708define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
3709; GFX6-LABEL: v_fshr_v2i16_vss:
3710; GFX6:       ; %bb.0:
3711; GFX6-NEXT:    s_mov_b32 s3, 0xffff
3712; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3713; GFX6-NEXT:    s_bfe_u32 s2, 1, 0x100000
3714; GFX6-NEXT:    s_and_b32 s4, s0, s3
3715; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
3716; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s2, v1
3717; GFX6-NEXT:    s_bfe_u32 s5, 14, 0x100000
3718; GFX6-NEXT:    s_lshr_b32 s2, s0, 17
3719; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3720; GFX6-NEXT:    s_lshr_b32 s2, s2, s5
3721; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3722; GFX6-NEXT:    v_or_b32_e32 v1, s2, v1
3723; GFX6-NEXT:    s_lshr_b32 s2, s0, 16
3724; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
3725; GFX6-NEXT:    s_xor_b32 s1, s1, -1
3726; GFX6-NEXT:    s_and_b32 s5, s1, 15
3727; GFX6-NEXT:    s_and_b32 s0, s0, s3
3728; GFX6-NEXT:    v_or_b32_e32 v0, s4, v0
3729; GFX6-NEXT:    s_lshr_b32 s4, s1, 16
3730; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3731; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
3732; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3733; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3734; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
3735; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s5, v0
3736; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
3737; GFX6-NEXT:    s_and_b32 s0, s4, 15
3738; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3739; GFX6-NEXT:    s_lshl_b32 s2, s2, 1
3740; GFX6-NEXT:    s_andn2_b32 s1, 15, s4
3741; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s0, v1
3742; GFX6-NEXT:    s_and_b32 s0, s2, s3
3743; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3744; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3745; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
3746; GFX6-NEXT:    v_or_b32_e32 v1, s0, v1
3747; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3748; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3749; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3750; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3751; GFX6-NEXT:    ; return to shader part epilog
3752;
3753; GFX8-LABEL: v_fshr_v2i16_vss:
3754; GFX8:       ; %bb.0:
3755; GFX8-NEXT:    s_bfe_u32 s3, s0, 0x100000
3756; GFX8-NEXT:    s_bfe_u32 s4, 1, 0x100000
3757; GFX8-NEXT:    s_lshr_b32 s3, s3, s4
3758; GFX8-NEXT:    s_bfe_u32 s5, 14, 0x100000
3759; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3760; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 1, v0
3761; GFX8-NEXT:    s_lshr_b32 s3, s3, s5
3762; GFX8-NEXT:    v_or_b32_e32 v1, s3, v1
3763; GFX8-NEXT:    s_lshr_b32 s3, s2, s4
3764; GFX8-NEXT:    v_mov_b32_e32 v2, 1
3765; GFX8-NEXT:    s_lshl_b32 s0, s0, s4
3766; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3767; GFX8-NEXT:    s_lshr_b32 s3, s3, s5
3768; GFX8-NEXT:    s_xor_b32 s1, s1, -1
3769; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3770; GFX8-NEXT:    v_or_b32_e32 v0, s3, v0
3771; GFX8-NEXT:    s_and_b32 s5, s1, 15
3772; GFX8-NEXT:    s_lshr_b32 s3, s1, 16
3773; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3774; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3775; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3776; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3777; GFX8-NEXT:    v_lshlrev_b16_e32 v1, s5, v1
3778; GFX8-NEXT:    v_or_b32_e32 v1, s0, v1
3779; GFX8-NEXT:    s_and_b32 s0, s3, 15
3780; GFX8-NEXT:    s_lshl_b32 s2, s2, s4
3781; GFX8-NEXT:    s_andn2_b32 s1, 15, s3
3782; GFX8-NEXT:    v_lshlrev_b16_e32 v0, s0, v0
3783; GFX8-NEXT:    s_bfe_u32 s0, s2, 0x100000
3784; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3785; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3786; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3787; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3788; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3789; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3790; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3791; GFX8-NEXT:    ; return to shader part epilog
3792;
3793; GFX9-LABEL: v_fshr_v2i16_vss:
3794; GFX9:       ; %bb.0:
3795; GFX9-NEXT:    s_mov_b32 s2, 0xf000f
3796; GFX9-NEXT:    s_and_b32 s3, s1, s2
3797; GFX9-NEXT:    s_andn2_b32 s1, s2, s1
3798; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3799; GFX9-NEXT:    s_mov_b32 s2, 0xffff
3800; GFX9-NEXT:    v_pk_lshlrev_b16 v0, s1, v0
3801; GFX9-NEXT:    s_lshr_b32 s1, s0, 16
3802; GFX9-NEXT:    s_and_b32 s0, s0, s2
3803; GFX9-NEXT:    s_lshr_b32 s4, s3, 16
3804; GFX9-NEXT:    s_and_b32 s2, s3, s2
3805; GFX9-NEXT:    s_lshr_b32 s0, s0, s2
3806; GFX9-NEXT:    s_lshr_b32 s1, s1, s4
3807; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3808; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3809; GFX9-NEXT:    ; return to shader part epilog
3810;
3811; GFX10-LABEL: v_fshr_v2i16_vss:
3812; GFX10:       ; %bb.0:
3813; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3814; GFX10-NEXT:    s_mov_b32 s2, 0xf000f
3815; GFX10-NEXT:    s_mov_b32 s3, 0xffff
3816; GFX10-NEXT:    s_and_b32 s4, s1, s2
3817; GFX10-NEXT:    s_andn2_b32 s1, s2, s1
3818; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3819; GFX10-NEXT:    v_pk_lshlrev_b16 v0, s1, v0
3820; GFX10-NEXT:    s_and_b32 s0, s0, s3
3821; GFX10-NEXT:    s_and_b32 s1, s4, s3
3822; GFX10-NEXT:    s_lshr_b32 s3, s4, 16
3823; GFX10-NEXT:    s_lshr_b32 s0, s0, s1
3824; GFX10-NEXT:    s_lshr_b32 s1, s2, s3
3825; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3826; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3827; GFX10-NEXT:    ; return to shader part epilog
3828  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3829  %cast = bitcast <2 x i16> %result to float
3830  ret float %cast
3831}
3832
3833; ; FIXME
3834; define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <3 x i16> inreg %amt) {
3835;   %result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
3836;   %cast = bitcast <3 x i16> %result to i48
3837;   ret i48 %cast
3838; }
3839
3840; ; FIXME
3841; define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt) {
3842;   %result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
3843;   %cast.result = bitcast <3 x i16> %result to <3 x half>
3844;   ret <3 x half> %cast.result
3845; }
3846
3847define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs, <4 x i16> inreg %amt) {
3848; GFX6-LABEL: s_fshr_v4i16:
3849; GFX6:       ; %bb.0:
3850; GFX6-NEXT:    s_mov_b32 s12, 0xffff
3851; GFX6-NEXT:    s_lshl_b32 s9, s9, 16
3852; GFX6-NEXT:    s_and_b32 s8, s8, s12
3853; GFX6-NEXT:    s_or_b32 s8, s9, s8
3854; GFX6-NEXT:    s_lshl_b32 s9, s11, 16
3855; GFX6-NEXT:    s_and_b32 s11, s4, s12
3856; GFX6-NEXT:    s_and_b32 s10, s10, s12
3857; GFX6-NEXT:    s_or_b32 s9, s9, s10
3858; GFX6-NEXT:    s_bfe_u32 s10, 1, 0x100000
3859; GFX6-NEXT:    s_lshr_b32 s11, s11, 1
3860; GFX6-NEXT:    s_bfe_u32 s13, 14, 0x100000
3861; GFX6-NEXT:    s_lshl_b32 s0, s0, s10
3862; GFX6-NEXT:    s_lshr_b32 s11, s11, s13
3863; GFX6-NEXT:    s_or_b32 s0, s0, s11
3864; GFX6-NEXT:    s_and_b32 s11, s5, s12
3865; GFX6-NEXT:    s_lshr_b32 s11, s11, 1
3866; GFX6-NEXT:    s_lshl_b32 s4, s4, 1
3867; GFX6-NEXT:    s_xor_b32 s8, s8, -1
3868; GFX6-NEXT:    s_lshl_b32 s1, s1, s10
3869; GFX6-NEXT:    s_lshr_b32 s11, s11, s13
3870; GFX6-NEXT:    s_and_b32 s14, s8, 15
3871; GFX6-NEXT:    s_and_b32 s4, s4, s12
3872; GFX6-NEXT:    s_or_b32 s1, s1, s11
3873; GFX6-NEXT:    s_lshr_b32 s11, s8, 16
3874; GFX6-NEXT:    s_andn2_b32 s8, 15, s8
3875; GFX6-NEXT:    s_bfe_u32 s14, s14, 0x100000
3876; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3877; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
3878; GFX6-NEXT:    s_lshr_b32 s4, s4, s8
3879; GFX6-NEXT:    s_lshl_b32 s0, s0, s14
3880; GFX6-NEXT:    s_or_b32 s0, s0, s4
3881; GFX6-NEXT:    s_and_b32 s4, s11, 15
3882; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3883; GFX6-NEXT:    s_lshl_b32 s5, s5, 1
3884; GFX6-NEXT:    s_lshl_b32 s1, s1, s4
3885; GFX6-NEXT:    s_and_b32 s4, s5, s12
3886; GFX6-NEXT:    s_andn2_b32 s8, 15, s11
3887; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3888; GFX6-NEXT:    s_bfe_u32 s5, s8, 0x100000
3889; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3890; GFX6-NEXT:    s_or_b32 s1, s1, s4
3891; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3892; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3893; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
3894; GFX6-NEXT:    s_or_b32 s0, s0, s1
3895; GFX6-NEXT:    s_lshl_b32 s1, s2, s10
3896; GFX6-NEXT:    s_and_b32 s2, s6, s12
3897; GFX6-NEXT:    s_lshr_b32 s2, s2, 1
3898; GFX6-NEXT:    s_lshr_b32 s2, s2, s13
3899; GFX6-NEXT:    s_or_b32 s1, s1, s2
3900; GFX6-NEXT:    s_lshl_b32 s2, s3, s10
3901; GFX6-NEXT:    s_and_b32 s3, s7, s12
3902; GFX6-NEXT:    s_lshr_b32 s3, s3, 1
3903; GFX6-NEXT:    s_lshr_b32 s3, s3, s13
3904; GFX6-NEXT:    s_or_b32 s2, s2, s3
3905; GFX6-NEXT:    s_lshl_b32 s3, s6, 1
3906; GFX6-NEXT:    s_xor_b32 s5, s9, -1
3907; GFX6-NEXT:    s_and_b32 s3, s3, s12
3908; GFX6-NEXT:    s_lshl_b32 s4, s7, 1
3909; GFX6-NEXT:    s_and_b32 s7, s5, 15
3910; GFX6-NEXT:    s_lshr_b32 s6, s5, 16
3911; GFX6-NEXT:    s_andn2_b32 s5, 15, s5
3912; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
3913; GFX6-NEXT:    s_lshr_b32 s3, s3, 1
3914; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
3915; GFX6-NEXT:    s_lshr_b32 s3, s3, s5
3916; GFX6-NEXT:    s_lshl_b32 s1, s1, s7
3917; GFX6-NEXT:    s_or_b32 s1, s1, s3
3918; GFX6-NEXT:    s_and_b32 s3, s6, 15
3919; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
3920; GFX6-NEXT:    s_lshl_b32 s2, s2, s3
3921; GFX6-NEXT:    s_and_b32 s3, s4, s12
3922; GFX6-NEXT:    s_andn2_b32 s5, 15, s6
3923; GFX6-NEXT:    s_lshr_b32 s3, s3, 1
3924; GFX6-NEXT:    s_bfe_u32 s4, s5, 0x100000
3925; GFX6-NEXT:    s_lshr_b32 s3, s3, s4
3926; GFX6-NEXT:    s_or_b32 s2, s2, s3
3927; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3928; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3929; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
3930; GFX6-NEXT:    s_or_b32 s1, s1, s2
3931; GFX6-NEXT:    ; return to shader part epilog
3932;
3933; GFX8-LABEL: s_fshr_v4i16:
3934; GFX8:       ; %bb.0:
3935; GFX8-NEXT:    s_bfe_u32 s8, 1, 0x100000
3936; GFX8-NEXT:    s_bfe_u32 s9, s2, 0x100000
3937; GFX8-NEXT:    s_lshr_b32 s9, s9, s8
3938; GFX8-NEXT:    s_bfe_u32 s10, 14, 0x100000
3939; GFX8-NEXT:    s_lshr_b32 s6, s0, 16
3940; GFX8-NEXT:    s_lshr_b32 s7, s2, 16
3941; GFX8-NEXT:    s_lshl_b32 s0, s0, s8
3942; GFX8-NEXT:    s_lshr_b32 s9, s9, s10
3943; GFX8-NEXT:    s_or_b32 s0, s0, s9
3944; GFX8-NEXT:    s_lshr_b32 s9, s7, s8
3945; GFX8-NEXT:    s_lshl_b32 s2, s2, s8
3946; GFX8-NEXT:    s_xor_b32 s4, s4, -1
3947; GFX8-NEXT:    s_lshl_b32 s6, s6, s8
3948; GFX8-NEXT:    s_lshr_b32 s9, s9, s10
3949; GFX8-NEXT:    s_and_b32 s11, s4, 15
3950; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3951; GFX8-NEXT:    s_or_b32 s6, s6, s9
3952; GFX8-NEXT:    s_lshr_b32 s9, s4, 16
3953; GFX8-NEXT:    s_andn2_b32 s4, 15, s4
3954; GFX8-NEXT:    s_bfe_u32 s11, s11, 0x100000
3955; GFX8-NEXT:    s_lshr_b32 s2, s2, s8
3956; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3957; GFX8-NEXT:    s_lshr_b32 s2, s2, s4
3958; GFX8-NEXT:    s_lshl_b32 s0, s0, s11
3959; GFX8-NEXT:    s_or_b32 s0, s0, s2
3960; GFX8-NEXT:    s_and_b32 s2, s9, 15
3961; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3962; GFX8-NEXT:    s_lshl_b32 s7, s7, s8
3963; GFX8-NEXT:    s_andn2_b32 s4, 15, s9
3964; GFX8-NEXT:    s_lshl_b32 s2, s6, s2
3965; GFX8-NEXT:    s_bfe_u32 s6, s7, 0x100000
3966; GFX8-NEXT:    s_lshr_b32 s6, s6, s8
3967; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3968; GFX8-NEXT:    s_lshr_b32 s4, s6, s4
3969; GFX8-NEXT:    s_or_b32 s2, s2, s4
3970; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3971; GFX8-NEXT:    s_bfe_u32 s6, s3, 0x100000
3972; GFX8-NEXT:    s_lshr_b32 s6, s6, s8
3973; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3974; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
3975; GFX8-NEXT:    s_or_b32 s0, s0, s2
3976; GFX8-NEXT:    s_lshr_b32 s2, s1, 16
3977; GFX8-NEXT:    s_lshr_b32 s4, s3, 16
3978; GFX8-NEXT:    s_lshl_b32 s1, s1, s8
3979; GFX8-NEXT:    s_lshr_b32 s6, s6, s10
3980; GFX8-NEXT:    s_or_b32 s1, s1, s6
3981; GFX8-NEXT:    s_lshr_b32 s6, s4, s8
3982; GFX8-NEXT:    s_lshl_b32 s3, s3, s8
3983; GFX8-NEXT:    s_xor_b32 s5, s5, -1
3984; GFX8-NEXT:    s_lshl_b32 s2, s2, s8
3985; GFX8-NEXT:    s_lshr_b32 s6, s6, s10
3986; GFX8-NEXT:    s_and_b32 s7, s5, 15
3987; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
3988; GFX8-NEXT:    s_or_b32 s2, s2, s6
3989; GFX8-NEXT:    s_lshr_b32 s6, s5, 16
3990; GFX8-NEXT:    s_andn2_b32 s5, 15, s5
3991; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
3992; GFX8-NEXT:    s_lshr_b32 s3, s3, s8
3993; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
3994; GFX8-NEXT:    s_lshr_b32 s3, s3, s5
3995; GFX8-NEXT:    s_lshl_b32 s1, s1, s7
3996; GFX8-NEXT:    s_or_b32 s1, s1, s3
3997; GFX8-NEXT:    s_and_b32 s3, s6, 15
3998; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
3999; GFX8-NEXT:    s_lshl_b32 s4, s4, s8
4000; GFX8-NEXT:    s_lshl_b32 s2, s2, s3
4001; GFX8-NEXT:    s_bfe_u32 s3, s4, 0x100000
4002; GFX8-NEXT:    s_andn2_b32 s5, 15, s6
4003; GFX8-NEXT:    s_lshr_b32 s3, s3, s8
4004; GFX8-NEXT:    s_bfe_u32 s4, s5, 0x100000
4005; GFX8-NEXT:    s_lshr_b32 s3, s3, s4
4006; GFX8-NEXT:    s_or_b32 s2, s2, s3
4007; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
4008; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
4009; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
4010; GFX8-NEXT:    s_or_b32 s1, s1, s2
4011; GFX8-NEXT:    ; return to shader part epilog
4012;
4013; GFX9-LABEL: s_fshr_v4i16:
4014; GFX9:       ; %bb.0:
4015; GFX9-NEXT:    s_lshr_b32 s9, s0, 16
4016; GFX9-NEXT:    s_mov_b32 s8, 0x10001
4017; GFX9-NEXT:    s_mov_b32 s6, 0xf000f
4018; GFX9-NEXT:    s_lshl_b32 s0, s0, s8
4019; GFX9-NEXT:    s_lshl_b32 s9, s9, 1
4020; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s9
4021; GFX9-NEXT:    s_and_b32 s7, s4, s6
4022; GFX9-NEXT:    s_andn2_b32 s4, s6, s4
4023; GFX9-NEXT:    s_lshr_b32 s9, s0, 16
4024; GFX9-NEXT:    s_lshr_b32 s10, s4, 16
4025; GFX9-NEXT:    s_lshl_b32 s0, s0, s4
4026; GFX9-NEXT:    s_lshl_b32 s4, s9, s10
4027; GFX9-NEXT:    s_mov_b32 s9, 0xffff
4028; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
4029; GFX9-NEXT:    s_lshr_b32 s4, s2, 16
4030; GFX9-NEXT:    s_lshr_b32 s10, s7, 16
4031; GFX9-NEXT:    s_and_b32 s2, s2, s9
4032; GFX9-NEXT:    s_and_b32 s7, s7, s9
4033; GFX9-NEXT:    s_lshr_b32 s2, s2, s7
4034; GFX9-NEXT:    s_lshr_b32 s4, s4, s10
4035; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s4
4036; GFX9-NEXT:    s_or_b32 s0, s0, s2
4037; GFX9-NEXT:    s_and_b32 s2, s5, s6
4038; GFX9-NEXT:    s_andn2_b32 s4, s6, s5
4039; GFX9-NEXT:    s_lshr_b32 s5, s1, 16
4040; GFX9-NEXT:    s_lshl_b32 s1, s1, s8
4041; GFX9-NEXT:    s_lshl_b32 s5, s5, 1
4042; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s5
4043; GFX9-NEXT:    s_lshr_b32 s5, s1, 16
4044; GFX9-NEXT:    s_lshr_b32 s6, s4, 16
4045; GFX9-NEXT:    s_lshl_b32 s1, s1, s4
4046; GFX9-NEXT:    s_lshl_b32 s4, s5, s6
4047; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
4048; GFX9-NEXT:    s_lshr_b32 s4, s3, 16
4049; GFX9-NEXT:    s_lshr_b32 s5, s2, 16
4050; GFX9-NEXT:    s_and_b32 s3, s3, s9
4051; GFX9-NEXT:    s_and_b32 s2, s2, s9
4052; GFX9-NEXT:    s_lshr_b32 s2, s3, s2
4053; GFX9-NEXT:    s_lshr_b32 s3, s4, s5
4054; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
4055; GFX9-NEXT:    s_or_b32 s1, s1, s2
4056; GFX9-NEXT:    ; return to shader part epilog
4057;
4058; GFX10-LABEL: s_fshr_v4i16:
4059; GFX10:       ; %bb.0:
4060; GFX10-NEXT:    s_lshr_b32 s8, s0, 16
4061; GFX10-NEXT:    s_mov_b32 s7, 0x10001
4062; GFX10-NEXT:    s_mov_b32 s6, 0xf000f
4063; GFX10-NEXT:    s_lshl_b32 s0, s0, s7
4064; GFX10-NEXT:    s_lshl_b32 s8, s8, 1
4065; GFX10-NEXT:    s_and_b32 s9, s4, s6
4066; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s8
4067; GFX10-NEXT:    s_andn2_b32 s4, s6, s4
4068; GFX10-NEXT:    s_lshr_b32 s8, s0, 16
4069; GFX10-NEXT:    s_lshr_b32 s10, s4, 16
4070; GFX10-NEXT:    s_lshl_b32 s0, s0, s4
4071; GFX10-NEXT:    s_lshl_b32 s4, s8, s10
4072; GFX10-NEXT:    s_mov_b32 s8, 0xffff
4073; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
4074; GFX10-NEXT:    s_lshr_b32 s4, s1, 16
4075; GFX10-NEXT:    s_lshl_b32 s1, s1, s7
4076; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
4077; GFX10-NEXT:    s_and_b32 s7, s5, s6
4078; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
4079; GFX10-NEXT:    s_andn2_b32 s4, s6, s5
4080; GFX10-NEXT:    s_lshr_b32 s5, s1, 16
4081; GFX10-NEXT:    s_lshr_b32 s6, s4, 16
4082; GFX10-NEXT:    s_lshr_b32 s10, s2, 16
4083; GFX10-NEXT:    s_and_b32 s11, s9, s8
4084; GFX10-NEXT:    s_and_b32 s2, s2, s8
4085; GFX10-NEXT:    s_lshr_b32 s9, s9, 16
4086; GFX10-NEXT:    s_lshl_b32 s1, s1, s4
4087; GFX10-NEXT:    s_lshl_b32 s4, s5, s6
4088; GFX10-NEXT:    s_lshr_b32 s5, s3, 16
4089; GFX10-NEXT:    s_and_b32 s6, s7, s8
4090; GFX10-NEXT:    s_and_b32 s3, s3, s8
4091; GFX10-NEXT:    s_lshr_b32 s7, s7, 16
4092; GFX10-NEXT:    s_lshr_b32 s2, s2, s11
4093; GFX10-NEXT:    s_lshr_b32 s9, s10, s9
4094; GFX10-NEXT:    s_lshr_b32 s3, s3, s6
4095; GFX10-NEXT:    s_lshr_b32 s5, s5, s7
4096; GFX10-NEXT:    s_pack_ll_b32_b16 s2, s2, s9
4097; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
4098; GFX10-NEXT:    s_pack_ll_b32_b16 s3, s3, s5
4099; GFX10-NEXT:    s_or_b32 s0, s0, s2
4100; GFX10-NEXT:    s_or_b32 s1, s1, s3
4101; GFX10-NEXT:    ; return to shader part epilog
4102  %result = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
4103  %cast.result = bitcast <4 x i16> %result to <2 x i32>
4104  ret <2 x i32> %cast.result
4105}
4106
4107define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt) {
4108; GFX6-LABEL: v_fshr_v4i16:
4109; GFX6:       ; %bb.0:
4110; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4111; GFX6-NEXT:    v_mov_b32_e32 v12, 0xffff
4112; GFX6-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
4113; GFX6-NEXT:    v_and_b32_e32 v8, v8, v12
4114; GFX6-NEXT:    v_or_b32_e32 v8, v9, v8
4115; GFX6-NEXT:    v_lshlrev_b32_e32 v9, 16, v11
4116; GFX6-NEXT:    v_and_b32_e32 v10, v10, v12
4117; GFX6-NEXT:    s_mov_b32 s5, 0xffff
4118; GFX6-NEXT:    v_or_b32_e32 v9, v9, v10
4119; GFX6-NEXT:    v_and_b32_e32 v10, s5, v4
4120; GFX6-NEXT:    s_bfe_u32 s4, 1, 0x100000
4121; GFX6-NEXT:    v_lshrrev_b32_e32 v10, 1, v10
4122; GFX6-NEXT:    s_bfe_u32 s6, 14, 0x100000
4123; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
4124; GFX6-NEXT:    v_lshrrev_b32_e32 v10, s6, v10
4125; GFX6-NEXT:    v_or_b32_e32 v0, v0, v10
4126; GFX6-NEXT:    v_and_b32_e32 v10, s5, v5
4127; GFX6-NEXT:    v_lshrrev_b32_e32 v10, 1, v10
4128; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4129; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s4, v1
4130; GFX6-NEXT:    v_lshrrev_b32_e32 v10, s6, v10
4131; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v4
4132; GFX6-NEXT:    v_and_b32_e32 v11, 15, v8
4133; GFX6-NEXT:    v_or_b32_e32 v1, v1, v10
4134; GFX6-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
4135; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4136; GFX6-NEXT:    v_and_b32_e32 v8, 15, v8
4137; GFX6-NEXT:    v_and_b32_e32 v4, s5, v4
4138; GFX6-NEXT:    v_bfe_u32 v11, v11, 0, 16
4139; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4140; GFX6-NEXT:    v_bfe_u32 v8, v8, 0, 16
4141; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v8, v4
4142; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v11, v0
4143; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
4144; GFX6-NEXT:    v_and_b32_e32 v4, 15, v10
4145; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v10
4146; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
4147; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 1, v5
4148; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
4149; GFX6-NEXT:    v_and_b32_e32 v4, s5, v5
4150; GFX6-NEXT:    v_and_b32_e32 v8, 15, v8
4151; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4152; GFX6-NEXT:    v_bfe_u32 v5, v8, 0, 16
4153; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
4154; GFX6-NEXT:    v_or_b32_e32 v1, v1, v4
4155; GFX6-NEXT:    v_and_b32_e32 v4, s5, v6
4156; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4157; GFX6-NEXT:    v_lshlrev_b32_e32 v2, s4, v2
4158; GFX6-NEXT:    v_lshrrev_b32_e32 v4, s6, v4
4159; GFX6-NEXT:    v_or_b32_e32 v2, v2, v4
4160; GFX6-NEXT:    v_and_b32_e32 v4, s5, v7
4161; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4162; GFX6-NEXT:    v_lshlrev_b32_e32 v3, s4, v3
4163; GFX6-NEXT:    v_lshrrev_b32_e32 v4, s6, v4
4164; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
4165; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v6
4166; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v9
4167; GFX6-NEXT:    v_and_b32_e32 v8, 15, v6
4168; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 1, v7
4169; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
4170; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v6
4171; GFX6-NEXT:    v_and_b32_e32 v6, 15, v6
4172; GFX6-NEXT:    v_and_b32_e32 v4, s5, v4
4173; GFX6-NEXT:    v_bfe_u32 v8, v8, 0, 16
4174; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4175; GFX6-NEXT:    v_bfe_u32 v6, v6, 0, 16
4176; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v6, v4
4177; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v8, v2
4178; GFX6-NEXT:    v_or_b32_e32 v2, v2, v4
4179; GFX6-NEXT:    v_and_b32_e32 v4, 15, v7
4180; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v7
4181; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
4182; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v4, v3
4183; GFX6-NEXT:    v_and_b32_e32 v4, s5, v5
4184; GFX6-NEXT:    v_and_b32_e32 v6, 15, v6
4185; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4186; GFX6-NEXT:    v_bfe_u32 v5, v6, 0, 16
4187; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
4188; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
4189; GFX6-NEXT:    s_setpc_b64 s[30:31]
4190;
4191; GFX8-LABEL: v_fshr_v4i16:
4192; GFX8:       ; %bb.0:
4193; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4194; GFX8-NEXT:    v_lshrrev_b16_e32 v7, 1, v2
4195; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 1, v0
4196; GFX8-NEXT:    v_lshrrev_b16_e32 v7, 14, v7
4197; GFX8-NEXT:    v_or_b32_e32 v6, v6, v7
4198; GFX8-NEXT:    v_mov_b32_e32 v7, 1
4199; GFX8-NEXT:    v_lshrrev_b16_sdwa v8, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4200; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
4201; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4202; GFX8-NEXT:    v_lshrrev_b16_e32 v8, 14, v8
4203; GFX8-NEXT:    v_or_b32_e32 v0, v0, v8
4204; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 1, v2
4205; GFX8-NEXT:    v_and_b32_e32 v10, 15, v4
4206; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v4
4207; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
4208; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
4209; GFX8-NEXT:    v_lshrrev_b16_e32 v8, 1, v8
4210; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4211; GFX8-NEXT:    v_lshrrev_b16_e32 v4, v4, v8
4212; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v9
4213; GFX8-NEXT:    v_lshlrev_b16_e32 v6, v10, v6
4214; GFX8-NEXT:    v_or_b32_e32 v4, v6, v4
4215; GFX8-NEXT:    v_and_b32_e32 v6, 15, v9
4216; GFX8-NEXT:    v_and_b32_e32 v8, 15, v8
4217; GFX8-NEXT:    v_lshrrev_b16_e32 v2, 1, v2
4218; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v6, v0
4219; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v8, v2
4220; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4221; GFX8-NEXT:    v_mov_b32_e32 v2, 16
4222; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4223; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 1, v3
4224; GFX8-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4225; GFX8-NEXT:    v_lshlrev_b16_e32 v4, 1, v1
4226; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 14, v6
4227; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
4228; GFX8-NEXT:    v_lshrrev_b16_sdwa v6, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4229; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
4230; GFX8-NEXT:    v_lshlrev_b16_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4231; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 14, v6
4232; GFX8-NEXT:    v_or_b32_e32 v1, v1, v6
4233; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 1, v3
4234; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4235; GFX8-NEXT:    v_and_b32_e32 v8, 15, v5
4236; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v5
4237; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
4238; GFX8-NEXT:    v_and_b32_e32 v5, 15, v5
4239; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 1, v6
4240; GFX8-NEXT:    v_lshrrev_b16_e32 v5, v5, v6
4241; GFX8-NEXT:    v_lshlrev_b16_e32 v4, v8, v4
4242; GFX8-NEXT:    v_xor_b32_e32 v6, -1, v7
4243; GFX8-NEXT:    v_or_b32_e32 v4, v4, v5
4244; GFX8-NEXT:    v_and_b32_e32 v5, 15, v7
4245; GFX8-NEXT:    v_and_b32_e32 v6, 15, v6
4246; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 1, v3
4247; GFX8-NEXT:    v_lshlrev_b16_e32 v1, v5, v1
4248; GFX8-NEXT:    v_lshrrev_b16_e32 v3, v6, v3
4249; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4250; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4251; GFX8-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4252; GFX8-NEXT:    s_setpc_b64 s[30:31]
4253;
4254; GFX9-LABEL: v_fshr_v4i16:
4255; GFX9:       ; %bb.0:
4256; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4257; GFX9-NEXT:    s_mov_b32 s4, 0xf000f
4258; GFX9-NEXT:    v_and_b32_e32 v6, s4, v4
4259; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
4260; GFX9-NEXT:    v_and_b32_e32 v4, s4, v4
4261; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
4262; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v4, v0
4263; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v5
4264; GFX9-NEXT:    v_pk_lshrrev_b16 v2, v6, v2
4265; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4266; GFX9-NEXT:    v_and_b32_e32 v2, s4, v5
4267; GFX9-NEXT:    v_and_b32_e32 v4, s4, v4
4268; GFX9-NEXT:    v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
4269; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v4, v1
4270; GFX9-NEXT:    v_pk_lshrrev_b16 v2, v2, v3
4271; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
4272; GFX9-NEXT:    s_setpc_b64 s[30:31]
4273;
4274; GFX10-LABEL: v_fshr_v4i16:
4275; GFX10:       ; %bb.0:
4276; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4277; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4278; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v4
4279; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v5
4280; GFX10-NEXT:    s_mov_b32 s4, 0xf000f
4281; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
4282; GFX10-NEXT:    v_and_b32_e32 v4, s4, v4
4283; GFX10-NEXT:    v_and_b32_e32 v6, s4, v6
4284; GFX10-NEXT:    v_and_b32_e32 v5, s4, v5
4285; GFX10-NEXT:    v_and_b32_e32 v7, s4, v7
4286; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
4287; GFX10-NEXT:    v_pk_lshrrev_b16 v2, v4, v2
4288; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v6, v0
4289; GFX10-NEXT:    v_pk_lshrrev_b16 v3, v5, v3
4290; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v7, v1
4291; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4292; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4293; GFX10-NEXT:    s_setpc_b64 s[30:31]
4294  %result = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
4295  %cast.result = bitcast <4 x i16> %result to <4 x half>
4296  ret <4 x half> %cast.result
4297}
4298
4299define amdgpu_ps i64 @s_fshr_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt) {
4300; GFX6-LABEL: s_fshr_i64:
4301; GFX6:       ; %bb.0:
4302; GFX6-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4303; GFX6-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4304; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4305; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4306; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], s6
4307; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4308; GFX6-NEXT:    ; return to shader part epilog
4309;
4310; GFX8-LABEL: s_fshr_i64:
4311; GFX8:       ; %bb.0:
4312; GFX8-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4313; GFX8-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4314; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4315; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4316; GFX8-NEXT:    s_lshr_b64 s[2:3], s[2:3], s6
4317; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4318; GFX8-NEXT:    ; return to shader part epilog
4319;
4320; GFX9-LABEL: s_fshr_i64:
4321; GFX9:       ; %bb.0:
4322; GFX9-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4323; GFX9-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4324; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4325; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4326; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s6
4327; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4328; GFX9-NEXT:    ; return to shader part epilog
4329;
4330; GFX10-LABEL: s_fshr_i64:
4331; GFX10:       ; %bb.0:
4332; GFX10-NEXT:    s_andn2_b64 s[6:7], 63, s[4:5]
4333; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4334; GFX10-NEXT:    s_and_b64 s[4:5], s[4:5], 63
4335; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s6
4336; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s4
4337; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4338; GFX10-NEXT:    ; return to shader part epilog
4339  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4340  ret i64 %result
4341}
4342
4343define amdgpu_ps i64 @s_fshr_i64_5(i64 inreg %lhs, i64 inreg %rhs) {
4344; GCN-LABEL: s_fshr_i64_5:
4345; GCN:       ; %bb.0:
4346; GCN-NEXT:    s_lshl_b32 s1, s0, 27
4347; GCN-NEXT:    s_mov_b32 s0, 0
4348; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], 5
4349; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4350; GCN-NEXT:    ; return to shader part epilog
4351  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5)
4352  ret i64 %result
4353}
4354
4355define amdgpu_ps i64 @s_fshr_i64_32(i64 inreg %lhs, i64 inreg %rhs) {
4356; GCN-LABEL: s_fshr_i64_32:
4357; GCN:       ; %bb.0:
4358; GCN-NEXT:    s_mov_b32 s1, s0
4359; GCN-NEXT:    s_mov_b32 s0, 0
4360; GCN-NEXT:    s_mov_b32 s2, s3
4361; GCN-NEXT:    s_mov_b32 s3, s0
4362; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4363; GCN-NEXT:    ; return to shader part epilog
4364  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 32)
4365  ret i64 %result
4366}
4367
4368define amdgpu_ps i64 @s_fshr_i64_48(i64 inreg %lhs, i64 inreg %rhs) {
4369; GCN-LABEL: s_fshr_i64_48:
4370; GCN:       ; %bb.0:
4371; GCN-NEXT:    s_lshr_b32 s2, s3, 16
4372; GCN-NEXT:    s_lshl_b64 s[0:1], s[0:1], 16
4373; GCN-NEXT:    s_mov_b32 s3, 0
4374; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4375; GCN-NEXT:    ; return to shader part epilog
4376  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 48)
4377  ret i64 %result
4378}
4379
4380define i64 @v_fshr_i64(i64 %lhs, i64 %rhs, i64 %amt) {
4381; GFX6-LABEL: v_fshr_i64:
4382; GFX6:       ; %bb.0:
4383; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4384; GFX6-NEXT:    v_and_b32_e32 v5, 63, v4
4385; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
4386; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
4387; GFX6-NEXT:    v_and_b32_e32 v4, 63, v4
4388; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
4389; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], v5
4390; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4391; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
4392; GFX6-NEXT:    s_setpc_b64 s[30:31]
4393;
4394; GFX8-LABEL: v_fshr_i64:
4395; GFX8:       ; %bb.0:
4396; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4397; GFX8-NEXT:    v_and_b32_e32 v5, 63, v4
4398; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
4399; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4400; GFX8-NEXT:    v_and_b32_e32 v4, 63, v4
4401; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
4402; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
4403; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4404; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4405; GFX8-NEXT:    s_setpc_b64 s[30:31]
4406;
4407; GFX9-LABEL: v_fshr_i64:
4408; GFX9:       ; %bb.0:
4409; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4410; GFX9-NEXT:    v_and_b32_e32 v5, 63, v4
4411; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
4412; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4413; GFX9-NEXT:    v_and_b32_e32 v4, 63, v4
4414; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
4415; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
4416; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4417; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
4418; GFX9-NEXT:    s_setpc_b64 s[30:31]
4419;
4420; GFX10-LABEL: v_fshr_i64:
4421; GFX10:       ; %bb.0:
4422; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4423; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4424; GFX10-NEXT:    v_xor_b32_e32 v5, -1, v4
4425; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4426; GFX10-NEXT:    v_and_b32_e32 v4, 63, v4
4427; GFX10-NEXT:    v_and_b32_e32 v7, 63, v5
4428; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]
4429; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v7, v[0:1]
4430; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4431; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4432; GFX10-NEXT:    s_setpc_b64 s[30:31]
4433  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4434  ret i64 %result
4435}
4436
4437define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
4438; GFX6-LABEL: v_fshr_i64_5:
4439; GFX6:       ; %bb.0:
4440; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4441; GFX6-NEXT:    v_mov_b32_e32 v4, v0
4442; GFX6-NEXT:    v_lshr_b64 v[0:1], v[2:3], 5
4443; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4444; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
4445; GFX6-NEXT:    s_setpc_b64 s[30:31]
4446;
4447; GFX8-LABEL: v_fshr_i64_5:
4448; GFX8:       ; %bb.0:
4449; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4450; GFX8-NEXT:    v_mov_b32_e32 v4, v0
4451; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 5, v[2:3]
4452; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4453; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
4454; GFX8-NEXT:    s_setpc_b64 s[30:31]
4455;
4456; GFX9-LABEL: v_fshr_i64_5:
4457; GFX9:       ; %bb.0:
4458; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4459; GFX9-NEXT:    v_mov_b32_e32 v4, v0
4460; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 5, v[2:3]
4461; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4462; GFX9-NEXT:    v_or_b32_e32 v1, v2, v1
4463; GFX9-NEXT:    s_setpc_b64 s[30:31]
4464;
4465; GFX10-LABEL: v_fshr_i64_5:
4466; GFX10:       ; %bb.0:
4467; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4468; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4469; GFX10-NEXT:    v_mov_b32_e32 v4, v0
4470; GFX10-NEXT:    v_lshrrev_b64 v[0:1], 5, v[2:3]
4471; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4472; GFX10-NEXT:    v_or_b32_e32 v1, v2, v1
4473; GFX10-NEXT:    s_setpc_b64 s[30:31]
4474  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5)
4475  ret i64 %result
4476}
4477
4478define i64 @v_fshr_i64_32(i64 %lhs, i64 %rhs) {
4479; GFX6-LABEL: v_fshr_i64_32:
4480; GFX6:       ; %bb.0:
4481; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4482; GFX6-NEXT:    v_mov_b32_e32 v1, v0
4483; GFX6-NEXT:    v_mov_b32_e32 v0, v3
4484; GFX6-NEXT:    s_setpc_b64 s[30:31]
4485;
4486; GFX8-LABEL: v_fshr_i64_32:
4487; GFX8:       ; %bb.0:
4488; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4489; GFX8-NEXT:    v_mov_b32_e32 v1, v0
4490; GFX8-NEXT:    v_mov_b32_e32 v0, v3
4491; GFX8-NEXT:    s_setpc_b64 s[30:31]
4492;
4493; GFX9-LABEL: v_fshr_i64_32:
4494; GFX9:       ; %bb.0:
4495; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4496; GFX9-NEXT:    v_mov_b32_e32 v1, v0
4497; GFX9-NEXT:    v_mov_b32_e32 v0, v3
4498; GFX9-NEXT:    s_setpc_b64 s[30:31]
4499;
4500; GFX10-LABEL: v_fshr_i64_32:
4501; GFX10:       ; %bb.0:
4502; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4503; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4504; GFX10-NEXT:    v_mov_b32_e32 v1, v0
4505; GFX10-NEXT:    v_mov_b32_e32 v0, v3
4506; GFX10-NEXT:    s_setpc_b64 s[30:31]
4507  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 32)
4508  ret i64 %result
4509}
4510
4511define i64 @v_fshr_i64_48(i64 %lhs, i64 %rhs) {
4512; GFX6-LABEL: v_fshr_i64_48:
4513; GFX6:       ; %bb.0:
4514; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4515; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 16
4516; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
4517; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4518; GFX6-NEXT:    s_setpc_b64 s[30:31]
4519;
4520; GFX8-LABEL: v_fshr_i64_48:
4521; GFX8:       ; %bb.0:
4522; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4523; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]
4524; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4525; GFX8-NEXT:    s_setpc_b64 s[30:31]
4526;
4527; GFX9-LABEL: v_fshr_i64_48:
4528; GFX9:       ; %bb.0:
4529; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4530; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]
4531; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4532; GFX9-NEXT:    s_setpc_b64 s[30:31]
4533;
4534; GFX10-LABEL: v_fshr_i64_48:
4535; GFX10:       ; %bb.0:
4536; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4537; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4538; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]
4539; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4540; GFX10-NEXT:    s_setpc_b64 s[30:31]
4541  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 48)
4542  ret i64 %result
4543}
4544
4545define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64 %amt) {
4546; GFX6-LABEL: v_fshr_i64_ssv:
4547; GFX6:       ; %bb.0:
4548; GFX6-NEXT:    v_and_b32_e32 v2, 63, v0
4549; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
4550; GFX6-NEXT:    v_and_b32_e32 v0, 63, v0
4551; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4552; GFX6-NEXT:    v_lshl_b64 v[0:1], s[0:1], v0
4553; GFX6-NEXT:    v_lshr_b64 v[2:3], s[2:3], v2
4554; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4555; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
4556; GFX6-NEXT:    ; return to shader part epilog
4557;
4558; GFX8-LABEL: v_fshr_i64_ssv:
4559; GFX8:       ; %bb.0:
4560; GFX8-NEXT:    v_and_b32_e32 v2, 63, v0
4561; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
4562; GFX8-NEXT:    v_and_b32_e32 v0, 63, v0
4563; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4564; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v0, s[0:1]
4565; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v2, s[2:3]
4566; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4567; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4568; GFX8-NEXT:    ; return to shader part epilog
4569;
4570; GFX9-LABEL: v_fshr_i64_ssv:
4571; GFX9:       ; %bb.0:
4572; GFX9-NEXT:    v_and_b32_e32 v2, 63, v0
4573; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
4574; GFX9-NEXT:    v_and_b32_e32 v0, 63, v0
4575; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4576; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v0, s[0:1]
4577; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v2, s[2:3]
4578; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4579; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
4580; GFX9-NEXT:    ; return to shader part epilog
4581;
4582; GFX10-LABEL: v_fshr_i64_ssv:
4583; GFX10:       ; %bb.0:
4584; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
4585; GFX10-NEXT:    v_and_b32_e32 v0, 63, v0
4586; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4587; GFX10-NEXT:    v_and_b32_e32 v2, 63, v1
4588; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v0, s[2:3]
4589; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v2, s[0:1]
4590; GFX10-NEXT:    v_or_b32_e32 v0, v2, v0
4591; GFX10-NEXT:    v_or_b32_e32 v1, v3, v1
4592; GFX10-NEXT:    ; return to shader part epilog
4593  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4594  %cast = bitcast i64 %result to <2 x float>
4595  ret <2 x float> %cast
4596}
4597
4598define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg %amt) {
4599; GFX6-LABEL: v_fshr_i64_svs:
4600; GFX6:       ; %bb.0:
4601; GFX6-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4602; GFX6-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4603; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4604; GFX6-NEXT:    v_lshr_b64 v[0:1], v[0:1], s4
4605; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4606; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
4607; GFX6-NEXT:    v_or_b32_e32 v1, s1, v1
4608; GFX6-NEXT:    ; return to shader part epilog
4609;
4610; GFX8-LABEL: v_fshr_i64_svs:
4611; GFX8:       ; %bb.0:
4612; GFX8-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4613; GFX8-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4614; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4615; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4616; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4617; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
4618; GFX8-NEXT:    v_or_b32_e32 v1, s1, v1
4619; GFX8-NEXT:    ; return to shader part epilog
4620;
4621; GFX9-LABEL: v_fshr_i64_svs:
4622; GFX9:       ; %bb.0:
4623; GFX9-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4624; GFX9-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4625; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4626; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4627; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4628; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
4629; GFX9-NEXT:    v_or_b32_e32 v1, s1, v1
4630; GFX9-NEXT:    ; return to shader part epilog
4631;
4632; GFX10-LABEL: v_fshr_i64_svs:
4633; GFX10:       ; %bb.0:
4634; GFX10-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4635; GFX10-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4636; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4637; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4638; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4639; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
4640; GFX10-NEXT:    v_or_b32_e32 v1, s1, v1
4641; GFX10-NEXT:    ; return to shader part epilog
4642  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4643  %cast = bitcast i64 %result to <2 x float>
4644  ret <2 x float> %cast
4645}
4646
4647define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg %amt) {
4648; GFX6-LABEL: v_fshr_i64_vss:
4649; GFX6:       ; %bb.0:
4650; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
4651; GFX6-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4652; GFX6-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4653; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s2
4654; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
4655; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
4656; GFX6-NEXT:    v_or_b32_e32 v1, s1, v1
4657; GFX6-NEXT:    ; return to shader part epilog
4658;
4659; GFX8-LABEL: v_fshr_i64_vss:
4660; GFX8:       ; %bb.0:
4661; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4662; GFX8-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4663; GFX8-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4664; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s2, v[0:1]
4665; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
4666; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
4667; GFX8-NEXT:    v_or_b32_e32 v1, s1, v1
4668; GFX8-NEXT:    ; return to shader part epilog
4669;
4670; GFX9-LABEL: v_fshr_i64_vss:
4671; GFX9:       ; %bb.0:
4672; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4673; GFX9-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4674; GFX9-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4675; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s2, v[0:1]
4676; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
4677; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
4678; GFX9-NEXT:    v_or_b32_e32 v1, s1, v1
4679; GFX9-NEXT:    ; return to shader part epilog
4680;
4681; GFX10-LABEL: v_fshr_i64_vss:
4682; GFX10:       ; %bb.0:
4683; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4684; GFX10-NEXT:    s_andn2_b64 s[4:5], 63, s[2:3]
4685; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], 63
4686; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
4687; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
4688; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
4689; GFX10-NEXT:    v_or_b32_e32 v1, s1, v1
4690; GFX10-NEXT:    ; return to shader part epilog
4691  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4692  %cast = bitcast i64 %result to <2 x float>
4693  ret <2 x float> %cast
4694}
4695
4696define amdgpu_ps <2 x i64> @s_fshr_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs, <2 x i64> inreg %amt) {
4697; GFX6-LABEL: s_fshr_v2i64:
4698; GFX6:       ; %bb.0:
4699; GFX6-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4700; GFX6-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4701; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4702; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
4703; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], s12
4704; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4705; GFX6-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4706; GFX6-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4707; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4708; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4709; GFX6-NEXT:    s_lshr_b64 s[4:5], s[6:7], s4
4710; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4711; GFX6-NEXT:    ; return to shader part epilog
4712;
4713; GFX8-LABEL: s_fshr_v2i64:
4714; GFX8:       ; %bb.0:
4715; GFX8-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4716; GFX8-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4717; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4718; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
4719; GFX8-NEXT:    s_lshr_b64 s[4:5], s[4:5], s12
4720; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4721; GFX8-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4722; GFX8-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4723; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4724; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4725; GFX8-NEXT:    s_lshr_b64 s[4:5], s[6:7], s4
4726; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4727; GFX8-NEXT:    ; return to shader part epilog
4728;
4729; GFX9-LABEL: s_fshr_v2i64:
4730; GFX9:       ; %bb.0:
4731; GFX9-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4732; GFX9-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4733; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4734; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
4735; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s12
4736; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4737; GFX9-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4738; GFX9-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4739; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4740; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4741; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], s4
4742; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4743; GFX9-NEXT:    ; return to shader part epilog
4744;
4745; GFX10-LABEL: s_fshr_v2i64:
4746; GFX10:       ; %bb.0:
4747; GFX10-NEXT:    s_andn2_b64 s[12:13], 63, s[8:9]
4748; GFX10-NEXT:    s_and_b64 s[8:9], s[8:9], 63
4749; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4750; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4751; GFX10-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4752; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4753; GFX10-NEXT:    s_and_b64 s[10:11], s[10:11], 63
4754; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s12
4755; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4756; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s10
4757; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4758; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
4759; GFX10-NEXT:    ; return to shader part epilog
4760  %result = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
4761  ret <2 x i64> %result
4762}
4763
4764define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
4765; GFX6-LABEL: v_fshr_v2i64:
4766; GFX6:       ; %bb.0:
4767; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4768; GFX6-NEXT:    v_and_b32_e32 v9, 63, v8
4769; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4770; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
4771; GFX6-NEXT:    v_and_b32_e32 v8, 63, v8
4772; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v8
4773; GFX6-NEXT:    v_lshr_b64 v[4:5], v[4:5], v9
4774; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v10
4775; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
4776; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
4777; GFX6-NEXT:    v_and_b32_e32 v4, 63, v10
4778; GFX6-NEXT:    v_and_b32_e32 v8, 63, v8
4779; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], v8
4780; GFX6-NEXT:    v_lshr_b64 v[6:7], v[6:7], v4
4781; GFX6-NEXT:    v_or_b32_e32 v1, v1, v5
4782; GFX6-NEXT:    v_or_b32_e32 v2, v2, v6
4783; GFX6-NEXT:    v_or_b32_e32 v3, v3, v7
4784; GFX6-NEXT:    s_setpc_b64 s[30:31]
4785;
4786; GFX8-LABEL: v_fshr_v2i64:
4787; GFX8:       ; %bb.0:
4788; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4789; GFX8-NEXT:    v_and_b32_e32 v9, 63, v8
4790; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
4791; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4792; GFX8-NEXT:    v_and_b32_e32 v8, 63, v8
4793; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
4794; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
4795; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v10
4796; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4797; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
4798; GFX8-NEXT:    v_and_b32_e32 v4, 63, v10
4799; GFX8-NEXT:    v_and_b32_e32 v8, 63, v8
4800; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v8, v[2:3]
4801; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v4, v[6:7]
4802; GFX8-NEXT:    v_or_b32_e32 v1, v1, v5
4803; GFX8-NEXT:    v_or_b32_e32 v2, v2, v6
4804; GFX8-NEXT:    v_or_b32_e32 v3, v3, v7
4805; GFX8-NEXT:    s_setpc_b64 s[30:31]
4806;
4807; GFX9-LABEL: v_fshr_v2i64:
4808; GFX9:       ; %bb.0:
4809; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4810; GFX9-NEXT:    v_and_b32_e32 v9, 63, v8
4811; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
4812; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4813; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
4814; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
4815; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
4816; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v10
4817; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4818; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
4819; GFX9-NEXT:    v_and_b32_e32 v4, 63, v10
4820; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
4821; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v8, v[2:3]
4822; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v4, v[6:7]
4823; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
4824; GFX9-NEXT:    v_or_b32_e32 v2, v2, v6
4825; GFX9-NEXT:    v_or_b32_e32 v3, v3, v7
4826; GFX9-NEXT:    s_setpc_b64 s[30:31]
4827;
4828; GFX10-LABEL: v_fshr_v2i64:
4829; GFX10:       ; %bb.0:
4830; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4831; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4832; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v8
4833; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v10
4834; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4835; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4836; GFX10-NEXT:    v_and_b32_e32 v19, 63, v8
4837; GFX10-NEXT:    v_and_b32_e32 v15, 63, v9
4838; GFX10-NEXT:    v_and_b32_e32 v9, 63, v11
4839; GFX10-NEXT:    v_and_b32_e32 v13, 63, v10
4840; GFX10-NEXT:    v_lshrrev_b64 v[4:5], v19, v[4:5]
4841; GFX10-NEXT:    v_lshlrev_b64 v[11:12], v15, v[0:1]
4842; GFX10-NEXT:    v_lshlrev_b64 v[15:16], v9, v[2:3]
4843; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v13, v[6:7]
4844; GFX10-NEXT:    v_or_b32_e32 v0, v11, v4
4845; GFX10-NEXT:    v_or_b32_e32 v1, v12, v5
4846; GFX10-NEXT:    v_or_b32_e32 v2, v15, v6
4847; GFX10-NEXT:    v_or_b32_e32 v3, v16, v7
4848; GFX10-NEXT:    s_setpc_b64 s[30:31]
4849  %result = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
4850  ret <2 x i64> %result
4851}
4852
4853define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg %amt) {
4854; GFX6-LABEL: s_fshr_i128:
4855; GFX6:       ; %bb.0:
4856; GFX6-NEXT:    s_movk_i32 s10, 0x7f
4857; GFX6-NEXT:    s_mov_b32 s11, 0
4858; GFX6-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4859; GFX6-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4860; GFX6-NEXT:    s_sub_i32 s9, 1, 64
4861; GFX6-NEXT:    s_sub_i32 s13, 64, 1
4862; GFX6-NEXT:    s_cmp_lt_u32 1, 64
4863; GFX6-NEXT:    s_cselect_b32 s18, 1, 0
4864; GFX6-NEXT:    s_cmp_eq_u32 1, 0
4865; GFX6-NEXT:    s_cselect_b32 s19, 1, 0
4866; GFX6-NEXT:    s_lshr_b64 s[14:15], s[0:1], s13
4867; GFX6-NEXT:    s_lshl_b64 s[16:17], s[2:3], 1
4868; GFX6-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
4869; GFX6-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
4870; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4871; GFX6-NEXT:    s_cmp_lg_u32 s18, 0
4872; GFX6-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
4873; GFX6-NEXT:    s_cselect_b64 s[0:1], s[14:15], s[0:1]
4874; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
4875; GFX6-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
4876; GFX6-NEXT:    s_sub_i32 s13, s8, 64
4877; GFX6-NEXT:    s_sub_i32 s9, 64, s8
4878; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
4879; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4880; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
4881; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
4882; GFX6-NEXT:    s_lshl_b64 s[2:3], s[10:11], s8
4883; GFX6-NEXT:    s_lshr_b64 s[14:15], s[10:11], s9
4884; GFX6-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
4885; GFX6-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
4886; GFX6-NEXT:    s_lshl_b64 s[10:11], s[10:11], s13
4887; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4888; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
4889; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
4890; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
4891; GFX6-NEXT:    s_cselect_b64 s[8:9], s[0:1], s[8:9]
4892; GFX6-NEXT:    s_sub_i32 s14, s12, 64
4893; GFX6-NEXT:    s_sub_i32 s13, 64, s12
4894; GFX6-NEXT:    s_cmp_lt_u32 s12, 64
4895; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
4896; GFX6-NEXT:    s_cmp_eq_u32 s12, 0
4897; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4898; GFX6-NEXT:    s_lshr_b64 s[0:1], s[6:7], s12
4899; GFX6-NEXT:    s_lshr_b64 s[10:11], s[4:5], s12
4900; GFX6-NEXT:    s_lshl_b64 s[12:13], s[6:7], s13
4901; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
4902; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
4903; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
4904; GFX6-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
4905; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4906; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4907; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
4908; GFX6-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
4909; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
4910; GFX6-NEXT:    s_or_b64 s[2:3], s[8:9], s[6:7]
4911; GFX6-NEXT:    ; return to shader part epilog
4912;
4913; GFX8-LABEL: s_fshr_i128:
4914; GFX8:       ; %bb.0:
4915; GFX8-NEXT:    s_movk_i32 s10, 0x7f
4916; GFX8-NEXT:    s_mov_b32 s11, 0
4917; GFX8-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4918; GFX8-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4919; GFX8-NEXT:    s_sub_i32 s9, 1, 64
4920; GFX8-NEXT:    s_sub_i32 s13, 64, 1
4921; GFX8-NEXT:    s_cmp_lt_u32 1, 64
4922; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
4923; GFX8-NEXT:    s_cmp_eq_u32 1, 0
4924; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
4925; GFX8-NEXT:    s_lshr_b64 s[14:15], s[0:1], s13
4926; GFX8-NEXT:    s_lshl_b64 s[16:17], s[2:3], 1
4927; GFX8-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
4928; GFX8-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
4929; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4930; GFX8-NEXT:    s_cmp_lg_u32 s18, 0
4931; GFX8-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
4932; GFX8-NEXT:    s_cselect_b64 s[0:1], s[14:15], s[0:1]
4933; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
4934; GFX8-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
4935; GFX8-NEXT:    s_sub_i32 s13, s8, 64
4936; GFX8-NEXT:    s_sub_i32 s9, 64, s8
4937; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
4938; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4939; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
4940; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
4941; GFX8-NEXT:    s_lshl_b64 s[2:3], s[10:11], s8
4942; GFX8-NEXT:    s_lshr_b64 s[14:15], s[10:11], s9
4943; GFX8-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
4944; GFX8-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
4945; GFX8-NEXT:    s_lshl_b64 s[10:11], s[10:11], s13
4946; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4947; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
4948; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
4949; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
4950; GFX8-NEXT:    s_cselect_b64 s[8:9], s[0:1], s[8:9]
4951; GFX8-NEXT:    s_sub_i32 s14, s12, 64
4952; GFX8-NEXT:    s_sub_i32 s13, 64, s12
4953; GFX8-NEXT:    s_cmp_lt_u32 s12, 64
4954; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
4955; GFX8-NEXT:    s_cmp_eq_u32 s12, 0
4956; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4957; GFX8-NEXT:    s_lshr_b64 s[0:1], s[6:7], s12
4958; GFX8-NEXT:    s_lshr_b64 s[10:11], s[4:5], s12
4959; GFX8-NEXT:    s_lshl_b64 s[12:13], s[6:7], s13
4960; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
4961; GFX8-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
4962; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
4963; GFX8-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
4964; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4965; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4966; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
4967; GFX8-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
4968; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
4969; GFX8-NEXT:    s_or_b64 s[2:3], s[8:9], s[6:7]
4970; GFX8-NEXT:    ; return to shader part epilog
4971;
4972; GFX9-LABEL: s_fshr_i128:
4973; GFX9:       ; %bb.0:
4974; GFX9-NEXT:    s_movk_i32 s10, 0x7f
4975; GFX9-NEXT:    s_mov_b32 s11, 0
4976; GFX9-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4977; GFX9-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4978; GFX9-NEXT:    s_sub_i32 s9, 1, 64
4979; GFX9-NEXT:    s_sub_i32 s13, 64, 1
4980; GFX9-NEXT:    s_cmp_lt_u32 1, 64
4981; GFX9-NEXT:    s_cselect_b32 s18, 1, 0
4982; GFX9-NEXT:    s_cmp_eq_u32 1, 0
4983; GFX9-NEXT:    s_cselect_b32 s19, 1, 0
4984; GFX9-NEXT:    s_lshr_b64 s[14:15], s[0:1], s13
4985; GFX9-NEXT:    s_lshl_b64 s[16:17], s[2:3], 1
4986; GFX9-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
4987; GFX9-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
4988; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4989; GFX9-NEXT:    s_cmp_lg_u32 s18, 0
4990; GFX9-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
4991; GFX9-NEXT:    s_cselect_b64 s[0:1], s[14:15], s[0:1]
4992; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
4993; GFX9-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
4994; GFX9-NEXT:    s_sub_i32 s13, s8, 64
4995; GFX9-NEXT:    s_sub_i32 s9, 64, s8
4996; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
4997; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
4998; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
4999; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
5000; GFX9-NEXT:    s_lshl_b64 s[2:3], s[10:11], s8
5001; GFX9-NEXT:    s_lshr_b64 s[14:15], s[10:11], s9
5002; GFX9-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
5003; GFX9-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
5004; GFX9-NEXT:    s_lshl_b64 s[10:11], s[10:11], s13
5005; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
5006; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5007; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
5008; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
5009; GFX9-NEXT:    s_cselect_b64 s[8:9], s[0:1], s[8:9]
5010; GFX9-NEXT:    s_sub_i32 s14, s12, 64
5011; GFX9-NEXT:    s_sub_i32 s13, 64, s12
5012; GFX9-NEXT:    s_cmp_lt_u32 s12, 64
5013; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
5014; GFX9-NEXT:    s_cmp_eq_u32 s12, 0
5015; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
5016; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], s12
5017; GFX9-NEXT:    s_lshr_b64 s[10:11], s[4:5], s12
5018; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], s13
5019; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5020; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
5021; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
5022; GFX9-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
5023; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
5024; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5025; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
5026; GFX9-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
5027; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
5028; GFX9-NEXT:    s_or_b64 s[2:3], s[8:9], s[6:7]
5029; GFX9-NEXT:    ; return to shader part epilog
5030;
5031; GFX10-LABEL: s_fshr_i128:
5032; GFX10:       ; %bb.0:
5033; GFX10-NEXT:    s_movk_i32 s10, 0x7f
5034; GFX10-NEXT:    s_mov_b32 s11, 0
5035; GFX10-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
5036; GFX10-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
5037; GFX10-NEXT:    s_sub_i32 s9, 1, 64
5038; GFX10-NEXT:    s_sub_i32 s10, 64, 1
5039; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5040; GFX10-NEXT:    s_cselect_b32 s13, 1, 0
5041; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5042; GFX10-NEXT:    s_cselect_b32 s18, 1, 0
5043; GFX10-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
5044; GFX10-NEXT:    s_lshl_b64 s[14:15], s[2:3], 1
5045; GFX10-NEXT:    s_lshl_b64 s[16:17], s[0:1], 1
5046; GFX10-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
5047; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
5048; GFX10-NEXT:    s_cmp_lg_u32 s13, 0
5049; GFX10-NEXT:    s_cselect_b64 s[14:15], s[16:17], 0
5050; GFX10-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5051; GFX10-NEXT:    s_cmp_lg_u32 s18, 0
5052; GFX10-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5053; GFX10-NEXT:    s_sub_i32 s13, s8, 64
5054; GFX10-NEXT:    s_sub_i32 s2, 64, s8
5055; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
5056; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
5057; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
5058; GFX10-NEXT:    s_cselect_b32 s17, 1, 0
5059; GFX10-NEXT:    s_lshl_b64 s[10:11], s[0:1], s8
5060; GFX10-NEXT:    s_lshr_b64 s[2:3], s[14:15], s2
5061; GFX10-NEXT:    s_lshl_b64 s[8:9], s[14:15], s8
5062; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
5063; GFX10-NEXT:    s_lshl_b64 s[10:11], s[14:15], s13
5064; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
5065; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
5066; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[10:11]
5067; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
5068; GFX10-NEXT:    s_cselect_b64 s[2:3], s[0:1], s[2:3]
5069; GFX10-NEXT:    s_sub_i32 s14, s12, 64
5070; GFX10-NEXT:    s_sub_i32 s10, 64, s12
5071; GFX10-NEXT:    s_cmp_lt_u32 s12, 64
5072; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
5073; GFX10-NEXT:    s_cmp_eq_u32 s12, 0
5074; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
5075; GFX10-NEXT:    s_lshr_b64 s[0:1], s[4:5], s12
5076; GFX10-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
5077; GFX10-NEXT:    s_lshr_b64 s[12:13], s[6:7], s12
5078; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
5079; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
5080; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
5081; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
5082; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
5083; GFX10-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
5084; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
5085; GFX10-NEXT:    s_cselect_b64 s[4:5], s[12:13], 0
5086; GFX10-NEXT:    s_or_b64 s[0:1], s[8:9], s[0:1]
5087; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
5088; GFX10-NEXT:    ; return to shader part epilog
5089  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5090  ret i128 %result
5091}
5092
5093define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
5094; GFX6-LABEL: v_fshr_i128:
5095; GFX6:       ; %bb.0:
5096; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5097; GFX6-NEXT:    s_movk_i32 s4, 0x7f
5098; GFX6-NEXT:    v_and_b32_e32 v14, s4, v8
5099; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
5100; GFX6-NEXT:    v_and_b32_e32 v15, s4, v8
5101; GFX6-NEXT:    s_sub_i32 s5, 64, 1
5102; GFX6-NEXT:    s_sub_i32 s4, 1, 64
5103; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5104; GFX6-NEXT:    s_cselect_b32 s6, 1, 0
5105; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5106; GFX6-NEXT:    v_lshr_b64 v[8:9], v[0:1], s5
5107; GFX6-NEXT:    v_lshl_b64 v[10:11], v[2:3], 1
5108; GFX6-NEXT:    v_lshl_b64 v[12:13], v[0:1], 1
5109; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5110; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s4
5111; GFX6-NEXT:    s_and_b32 s4, 1, s6
5112; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5113; GFX6-NEXT:    v_or_b32_e32 v10, v8, v10
5114; GFX6-NEXT:    v_or_b32_e32 v11, v9, v11
5115; GFX6-NEXT:    s_and_b32 s4, 1, s7
5116; GFX6-NEXT:    v_cndmask_b32_e32 v8, 0, v12, vcc
5117; GFX6-NEXT:    v_cndmask_b32_e32 v9, 0, v13, vcc
5118; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
5119; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
5120; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5121; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5122; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5123; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v15
5124; GFX6-NEXT:    v_lshr_b64 v[2:3], v[8:9], v2
5125; GFX6-NEXT:    v_lshl_b64 v[10:11], v[0:1], v15
5126; GFX6-NEXT:    v_subrev_i32_e32 v16, vcc, 64, v15
5127; GFX6-NEXT:    v_lshl_b64 v[12:13], v[8:9], v15
5128; GFX6-NEXT:    v_or_b32_e32 v10, v2, v10
5129; GFX6-NEXT:    v_or_b32_e32 v11, v3, v11
5130; GFX6-NEXT:    v_lshl_b64 v[2:3], v[8:9], v16
5131; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
5132; GFX6-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
5133; GFX6-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
5134; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
5135; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
5136; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v15
5137; GFX6-NEXT:    v_cndmask_b32_e32 v10, v2, v0, vcc
5138; GFX6-NEXT:    v_cndmask_b32_e32 v11, v3, v1, vcc
5139; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v14
5140; GFX6-NEXT:    v_lshr_b64 v[0:1], v[4:5], v14
5141; GFX6-NEXT:    v_lshl_b64 v[2:3], v[6:7], v2
5142; GFX6-NEXT:    v_subrev_i32_e32 v15, vcc, 64, v14
5143; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5144; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5145; GFX6-NEXT:    v_lshr_b64 v[0:1], v[6:7], v15
5146; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
5147; GFX6-NEXT:    v_lshr_b64 v[8:9], v[6:7], v14
5148; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5149; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5150; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v14
5151; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[4:5]
5152; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[4:5]
5153; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5154; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5155; GFX6-NEXT:    v_or_b32_e32 v0, v12, v0
5156; GFX6-NEXT:    v_or_b32_e32 v1, v13, v1
5157; GFX6-NEXT:    v_or_b32_e32 v2, v10, v2
5158; GFX6-NEXT:    v_or_b32_e32 v3, v11, v3
5159; GFX6-NEXT:    s_setpc_b64 s[30:31]
5160;
5161; GFX8-LABEL: v_fshr_i128:
5162; GFX8:       ; %bb.0:
5163; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5164; GFX8-NEXT:    s_movk_i32 s4, 0x7f
5165; GFX8-NEXT:    v_and_b32_e32 v14, s4, v8
5166; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
5167; GFX8-NEXT:    v_and_b32_e32 v15, s4, v8
5168; GFX8-NEXT:    s_sub_i32 s5, 64, 1
5169; GFX8-NEXT:    s_sub_i32 s4, 1, 64
5170; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5171; GFX8-NEXT:    s_cselect_b32 s6, 1, 0
5172; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5173; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s5, v[0:1]
5174; GFX8-NEXT:    v_lshlrev_b64 v[10:11], 1, v[2:3]
5175; GFX8-NEXT:    v_lshlrev_b64 v[12:13], 1, v[0:1]
5176; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5177; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
5178; GFX8-NEXT:    s_and_b32 s4, 1, s6
5179; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5180; GFX8-NEXT:    v_or_b32_e32 v10, v8, v10
5181; GFX8-NEXT:    v_or_b32_e32 v11, v9, v11
5182; GFX8-NEXT:    s_and_b32 s4, 1, s7
5183; GFX8-NEXT:    v_cndmask_b32_e32 v8, 0, v12, vcc
5184; GFX8-NEXT:    v_cndmask_b32_e32 v9, 0, v13, vcc
5185; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
5186; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
5187; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5188; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5189; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5190; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v15
5191; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v2, v[8:9]
5192; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v15, v[0:1]
5193; GFX8-NEXT:    v_subrev_u32_e32 v16, vcc, 64, v15
5194; GFX8-NEXT:    v_lshlrev_b64 v[12:13], v15, v[8:9]
5195; GFX8-NEXT:    v_or_b32_e32 v10, v2, v10
5196; GFX8-NEXT:    v_or_b32_e32 v11, v3, v11
5197; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v16, v[8:9]
5198; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
5199; GFX8-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
5200; GFX8-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
5201; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
5202; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
5203; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v15
5204; GFX8-NEXT:    v_cndmask_b32_e32 v10, v2, v0, vcc
5205; GFX8-NEXT:    v_cndmask_b32_e32 v11, v3, v1, vcc
5206; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v14
5207; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v14, v[4:5]
5208; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, v[6:7]
5209; GFX8-NEXT:    v_subrev_u32_e32 v15, vcc, 64, v14
5210; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5211; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5212; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v15, v[6:7]
5213; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
5214; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v14, v[6:7]
5215; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5216; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5217; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v14
5218; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[4:5]
5219; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[4:5]
5220; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5221; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5222; GFX8-NEXT:    v_or_b32_e32 v0, v12, v0
5223; GFX8-NEXT:    v_or_b32_e32 v1, v13, v1
5224; GFX8-NEXT:    v_or_b32_e32 v2, v10, v2
5225; GFX8-NEXT:    v_or_b32_e32 v3, v11, v3
5226; GFX8-NEXT:    s_setpc_b64 s[30:31]
5227;
5228; GFX9-LABEL: v_fshr_i128:
5229; GFX9:       ; %bb.0:
5230; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5231; GFX9-NEXT:    s_movk_i32 s4, 0x7f
5232; GFX9-NEXT:    v_and_b32_e32 v14, s4, v8
5233; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
5234; GFX9-NEXT:    v_and_b32_e32 v15, s4, v8
5235; GFX9-NEXT:    s_sub_i32 s5, 64, 1
5236; GFX9-NEXT:    s_sub_i32 s4, 1, 64
5237; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5238; GFX9-NEXT:    s_cselect_b32 s6, 1, 0
5239; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5240; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s5, v[0:1]
5241; GFX9-NEXT:    v_lshlrev_b64 v[10:11], 1, v[2:3]
5242; GFX9-NEXT:    v_lshlrev_b64 v[12:13], 1, v[0:1]
5243; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
5244; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
5245; GFX9-NEXT:    s_and_b32 s4, 1, s6
5246; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5247; GFX9-NEXT:    v_or_b32_e32 v10, v8, v10
5248; GFX9-NEXT:    v_or_b32_e32 v11, v9, v11
5249; GFX9-NEXT:    s_and_b32 s4, 1, s7
5250; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v12, vcc
5251; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v13, vcc
5252; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
5253; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
5254; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5255; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5256; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5257; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v15
5258; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v2, v[8:9]
5259; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v15, v[0:1]
5260; GFX9-NEXT:    v_subrev_u32_e32 v16, 64, v15
5261; GFX9-NEXT:    v_lshlrev_b64 v[12:13], v15, v[8:9]
5262; GFX9-NEXT:    v_or_b32_e32 v10, v2, v10
5263; GFX9-NEXT:    v_or_b32_e32 v11, v3, v11
5264; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v16, v[8:9]
5265; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
5266; GFX9-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
5267; GFX9-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
5268; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
5269; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
5270; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v15
5271; GFX9-NEXT:    v_cndmask_b32_e32 v10, v2, v0, vcc
5272; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v14
5273; GFX9-NEXT:    v_cndmask_b32_e32 v11, v3, v1, vcc
5274; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v14, v[4:5]
5275; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, v[6:7]
5276; GFX9-NEXT:    v_subrev_u32_e32 v15, 64, v14
5277; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5278; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5279; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v15, v[6:7]
5280; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
5281; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v14, v[6:7]
5282; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5283; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5284; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v14
5285; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[4:5]
5286; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[4:5]
5287; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5288; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5289; GFX9-NEXT:    v_or_b32_e32 v0, v12, v0
5290; GFX9-NEXT:    v_or_b32_e32 v1, v13, v1
5291; GFX9-NEXT:    v_or_b32_e32 v2, v10, v2
5292; GFX9-NEXT:    v_or_b32_e32 v3, v11, v3
5293; GFX9-NEXT:    s_setpc_b64 s[30:31]
5294;
5295; GFX10-LABEL: v_fshr_i128:
5296; GFX10:       ; %bb.0:
5297; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5298; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
5299; GFX10-NEXT:    s_sub_i32 s4, 64, 1
5300; GFX10-NEXT:    s_sub_i32 s6, 1, 64
5301; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5302; GFX10-NEXT:    v_lshrrev_b64 v[9:10], s4, v[0:1]
5303; GFX10-NEXT:    v_lshlrev_b64 v[11:12], 1, v[2:3]
5304; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
5305; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5306; GFX10-NEXT:    v_lshlrev_b64 v[13:14], 1, v[0:1]
5307; GFX10-NEXT:    s_cselect_b32 s7, 1, 0
5308; GFX10-NEXT:    s_and_b32 s4, 1, vcc_lo
5309; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s6, v[0:1]
5310; GFX10-NEXT:    v_or_b32_e32 v11, v9, v11
5311; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
5312; GFX10-NEXT:    v_or_b32_e32 v10, v10, v12
5313; GFX10-NEXT:    v_xor_b32_e32 v15, -1, v8
5314; GFX10-NEXT:    s_movk_i32 s5, 0x7f
5315; GFX10-NEXT:    s_and_b32 s6, 1, s7
5316; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v11, s4
5317; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v10, s4
5318; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s6
5319; GFX10-NEXT:    v_and_b32_e32 v19, s5, v15
5320; GFX10-NEXT:    v_and_b32_e32 v20, s5, v8
5321; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0, v13, vcc_lo
5322; GFX10-NEXT:    v_cndmask_b32_e32 v10, 0, v14, vcc_lo
5323; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s4
5324; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s4
5325; GFX10-NEXT:    v_sub_nc_u32_e32 v11, 64, v19
5326; GFX10-NEXT:    v_sub_nc_u32_e32 v17, 64, v20
5327; GFX10-NEXT:    v_mov_b32_e32 v25, v4
5328; GFX10-NEXT:    v_mov_b32_e32 v26, v5
5329; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, 64, v19
5330; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v11, v[9:10]
5331; GFX10-NEXT:    v_lshlrev_b64 v[11:12], v19, v[0:1]
5332; GFX10-NEXT:    v_lshlrev_b64 v[13:14], v19, v[9:10]
5333; GFX10-NEXT:    v_subrev_nc_u32_e32 v21, 64, v20
5334; GFX10-NEXT:    v_lshlrev_b64 v[8:9], v8, v[9:10]
5335; GFX10-NEXT:    v_lshrrev_b64 v[15:16], v20, v[25:26]
5336; GFX10-NEXT:    v_lshlrev_b64 v[17:18], v17, v[6:7]
5337; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v19
5338; GFX10-NEXT:    v_or_b32_e32 v10, v3, v12
5339; GFX10-NEXT:    v_or_b32_e32 v11, v2, v11
5340; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v21, v[6:7]
5341; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v20
5342; GFX10-NEXT:    v_cndmask_b32_e32 v23, 0, v13, vcc_lo
5343; GFX10-NEXT:    v_or_b32_e32 v13, v15, v17
5344; GFX10-NEXT:    v_cndmask_b32_e32 v15, v9, v10, vcc_lo
5345; GFX10-NEXT:    v_or_b32_e32 v10, v16, v18
5346; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v20, v[6:7]
5347; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v19
5348; GFX10-NEXT:    v_cndmask_b32_e32 v11, v8, v11, vcc_lo
5349; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v13, s4
5350; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v10, s4
5351; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v20
5352; GFX10-NEXT:    v_cndmask_b32_e64 v9, v15, v1, s6
5353; GFX10-NEXT:    v_cndmask_b32_e64 v8, v11, v0, s6
5354; GFX10-NEXT:    v_cndmask_b32_e32 v10, 0, v14, vcc_lo
5355; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, v25, s5
5356; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, v26, s5
5357; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v6, s4
5358; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v7, s4
5359; GFX10-NEXT:    v_or_b32_e32 v0, v23, v0
5360; GFX10-NEXT:    v_or_b32_e32 v1, v10, v1
5361; GFX10-NEXT:    v_or_b32_e32 v2, v8, v2
5362; GFX10-NEXT:    v_or_b32_e32 v3, v9, v3
5363; GFX10-NEXT:    s_setpc_b64 s[30:31]
5364  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5365  ret i128 %result
5366}
5367
5368define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
5369; GFX6-LABEL: v_fshr_i128_ssv:
5370; GFX6:       ; %bb.0:
5371; GFX6-NEXT:    s_sub_i32 s14, 1, 64
5372; GFX6-NEXT:    s_sub_i32 s10, 64, 1
5373; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5374; GFX6-NEXT:    s_movk_i32 s8, 0x7f
5375; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
5376; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5377; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
5378; GFX6-NEXT:    v_and_b32_e32 v6, s8, v0
5379; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
5380; GFX6-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
5381; GFX6-NEXT:    s_lshl_b64 s[12:13], s[2:3], 1
5382; GFX6-NEXT:    v_and_b32_e32 v7, s8, v0
5383; GFX6-NEXT:    s_lshl_b64 s[8:9], s[0:1], 1
5384; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5385; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
5386; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
5387; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
5388; GFX6-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5389; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
5390; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, 64, v7
5391; GFX6-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5392; GFX6-NEXT:    v_lshr_b64 v[0:1], s[8:9], v0
5393; GFX6-NEXT:    v_lshl_b64 v[2:3], s[0:1], v7
5394; GFX6-NEXT:    v_subrev_i32_e32 v8, vcc, 64, v7
5395; GFX6-NEXT:    v_lshl_b64 v[4:5], s[8:9], v7
5396; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5397; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5398; GFX6-NEXT:    v_lshl_b64 v[0:1], s[8:9], v8
5399; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5400; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5401; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5402; GFX6-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5403; GFX6-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5404; GFX6-NEXT:    v_mov_b32_e32 v2, s0
5405; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
5406; GFX6-NEXT:    v_mov_b32_e32 v3, s1
5407; GFX6-NEXT:    v_cndmask_b32_e32 v7, v0, v2, vcc
5408; GFX6-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5409; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v6
5410; GFX6-NEXT:    v_lshr_b64 v[0:1], s[4:5], v6
5411; GFX6-NEXT:    v_lshl_b64 v[2:3], s[6:7], v2
5412; GFX6-NEXT:    v_subrev_i32_e32 v11, vcc, 64, v6
5413; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5414; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5415; GFX6-NEXT:    v_lshr_b64 v[0:1], s[6:7], v11
5416; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5417; GFX6-NEXT:    v_lshr_b64 v[4:5], s[6:7], v6
5418; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5419; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5420; GFX6-NEXT:    v_mov_b32_e32 v2, s4
5421; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
5422; GFX6-NEXT:    v_mov_b32_e32 v3, s5
5423; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5424; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5425; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5426; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5427; GFX6-NEXT:    v_or_b32_e32 v0, v8, v0
5428; GFX6-NEXT:    v_or_b32_e32 v1, v9, v1
5429; GFX6-NEXT:    v_or_b32_e32 v2, v7, v2
5430; GFX6-NEXT:    v_or_b32_e32 v3, v10, v3
5431; GFX6-NEXT:    ; return to shader part epilog
5432;
5433; GFX8-LABEL: v_fshr_i128_ssv:
5434; GFX8:       ; %bb.0:
5435; GFX8-NEXT:    s_sub_i32 s14, 1, 64
5436; GFX8-NEXT:    s_sub_i32 s10, 64, 1
5437; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5438; GFX8-NEXT:    s_movk_i32 s8, 0x7f
5439; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
5440; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5441; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
5442; GFX8-NEXT:    v_and_b32_e32 v6, s8, v0
5443; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
5444; GFX8-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
5445; GFX8-NEXT:    s_lshl_b64 s[12:13], s[2:3], 1
5446; GFX8-NEXT:    v_and_b32_e32 v7, s8, v0
5447; GFX8-NEXT:    s_lshl_b64 s[8:9], s[0:1], 1
5448; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5449; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
5450; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
5451; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
5452; GFX8-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5453; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
5454; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, 64, v7
5455; GFX8-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5456; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v0, s[8:9]
5457; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v7, s[0:1]
5458; GFX8-NEXT:    v_subrev_u32_e32 v8, vcc, 64, v7
5459; GFX8-NEXT:    v_lshlrev_b64 v[4:5], v7, s[8:9]
5460; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5461; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5462; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v8, s[8:9]
5463; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5464; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5465; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5466; GFX8-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5467; GFX8-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5468; GFX8-NEXT:    v_mov_b32_e32 v2, s0
5469; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
5470; GFX8-NEXT:    v_mov_b32_e32 v3, s1
5471; GFX8-NEXT:    v_cndmask_b32_e32 v7, v0, v2, vcc
5472; GFX8-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5473; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v6
5474; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v6, s[4:5]
5475; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, s[6:7]
5476; GFX8-NEXT:    v_subrev_u32_e32 v11, vcc, 64, v6
5477; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5478; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5479; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v11, s[6:7]
5480; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5481; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v6, s[6:7]
5482; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5483; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5484; GFX8-NEXT:    v_mov_b32_e32 v2, s4
5485; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
5486; GFX8-NEXT:    v_mov_b32_e32 v3, s5
5487; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5488; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5489; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5490; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5491; GFX8-NEXT:    v_or_b32_e32 v0, v8, v0
5492; GFX8-NEXT:    v_or_b32_e32 v1, v9, v1
5493; GFX8-NEXT:    v_or_b32_e32 v2, v7, v2
5494; GFX8-NEXT:    v_or_b32_e32 v3, v10, v3
5495; GFX8-NEXT:    ; return to shader part epilog
5496;
5497; GFX9-LABEL: v_fshr_i128_ssv:
5498; GFX9:       ; %bb.0:
5499; GFX9-NEXT:    s_sub_i32 s14, 1, 64
5500; GFX9-NEXT:    s_sub_i32 s10, 64, 1
5501; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5502; GFX9-NEXT:    s_movk_i32 s8, 0x7f
5503; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
5504; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5505; GFX9-NEXT:    v_and_b32_e32 v6, s8, v0
5506; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
5507; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
5508; GFX9-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
5509; GFX9-NEXT:    s_lshl_b64 s[12:13], s[2:3], 1
5510; GFX9-NEXT:    v_and_b32_e32 v7, s8, v0
5511; GFX9-NEXT:    s_lshl_b64 s[8:9], s[0:1], 1
5512; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5513; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
5514; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
5515; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
5516; GFX9-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5517; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
5518; GFX9-NEXT:    v_sub_u32_e32 v0, 64, v7
5519; GFX9-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5520; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v0, s[8:9]
5521; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v7, s[0:1]
5522; GFX9-NEXT:    v_subrev_u32_e32 v8, 64, v7
5523; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v7, s[8:9]
5524; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5525; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5526; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, s[8:9]
5527; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5528; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5529; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5530; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5531; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5532; GFX9-NEXT:    v_mov_b32_e32 v2, s0
5533; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
5534; GFX9-NEXT:    v_mov_b32_e32 v3, s1
5535; GFX9-NEXT:    v_cndmask_b32_e32 v7, v0, v2, vcc
5536; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v6
5537; GFX9-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5538; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v6, s[4:5]
5539; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, s[6:7]
5540; GFX9-NEXT:    v_subrev_u32_e32 v11, 64, v6
5541; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5542; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5543; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v11, s[6:7]
5544; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5545; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v6, s[6:7]
5546; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5547; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5548; GFX9-NEXT:    v_mov_b32_e32 v2, s4
5549; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
5550; GFX9-NEXT:    v_mov_b32_e32 v3, s5
5551; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5552; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5553; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5554; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5555; GFX9-NEXT:    v_or_b32_e32 v0, v8, v0
5556; GFX9-NEXT:    v_or_b32_e32 v1, v9, v1
5557; GFX9-NEXT:    v_or_b32_e32 v2, v7, v2
5558; GFX9-NEXT:    v_or_b32_e32 v3, v10, v3
5559; GFX9-NEXT:    ; return to shader part epilog
5560;
5561; GFX10-LABEL: v_fshr_i128_ssv:
5562; GFX10:       ; %bb.0:
5563; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
5564; GFX10-NEXT:    s_sub_i32 s14, 1, 64
5565; GFX10-NEXT:    s_sub_i32 s9, 64, 1
5566; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5567; GFX10-NEXT:    s_movk_i32 s8, 0x7f
5568; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
5569; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5570; GFX10-NEXT:    v_and_b32_e32 v13, s8, v1
5571; GFX10-NEXT:    v_and_b32_e32 v12, s8, v0
5572; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
5573; GFX10-NEXT:    s_lshr_b64 s[8:9], s[0:1], s9
5574; GFX10-NEXT:    s_lshl_b64 s[10:11], s[2:3], 1
5575; GFX10-NEXT:    s_lshl_b64 s[12:13], s[0:1], 1
5576; GFX10-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
5577; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
5578; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
5579; GFX10-NEXT:    v_sub_nc_u32_e32 v0, 64, v13
5580; GFX10-NEXT:    s_cselect_b64 s[10:11], s[12:13], 0
5581; GFX10-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
5582; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
5583; GFX10-NEXT:    v_sub_nc_u32_e32 v8, 64, v12
5584; GFX10-NEXT:    s_cselect_b64 s[8:9], s[2:3], s[0:1]
5585; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v0, s[10:11]
5586; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v13, s[8:9]
5587; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 64, v13
5588; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v12, s[4:5]
5589; GFX10-NEXT:    v_lshlrev_b64 v[8:9], v8, s[6:7]
5590; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v13
5591; GFX10-NEXT:    v_cmp_gt_u32_e64 s0, 64, v12
5592; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
5593; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, 64, v12
5594; GFX10-NEXT:    v_lshlrev_b64 v[15:16], v10, s[10:11]
5595; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
5596; GFX10-NEXT:    v_or_b32_e32 v6, v6, v8
5597; GFX10-NEXT:    v_or_b32_e32 v7, v7, v9
5598; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v0, s[6:7]
5599; GFX10-NEXT:    v_lshlrev_b64 v[4:5], v13, s[10:11]
5600; GFX10-NEXT:    v_cndmask_b32_e32 v8, v15, v2, vcc_lo
5601; GFX10-NEXT:    v_cndmask_b32_e32 v10, v16, v3, vcc_lo
5602; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v12, s[6:7]
5603; GFX10-NEXT:    v_cmp_eq_u32_e64 s2, 0, v13
5604; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s0
5605; GFX10-NEXT:    v_cmp_eq_u32_e64 s1, 0, v12
5606; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v7, s0
5607; GFX10-NEXT:    v_cndmask_b32_e32 v11, 0, v4, vcc_lo
5608; GFX10-NEXT:    v_cndmask_b32_e32 v15, 0, v5, vcc_lo
5609; GFX10-NEXT:    v_cndmask_b32_e64 v19, v8, s8, s2
5610; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s4, s1
5611; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s5, s1
5612; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5613; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, s9, s2
5614; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5615; GFX10-NEXT:    v_or_b32_e32 v0, v11, v0
5616; GFX10-NEXT:    v_or_b32_e32 v1, v15, v1
5617; GFX10-NEXT:    v_or_b32_e32 v2, v19, v2
5618; GFX10-NEXT:    v_or_b32_e32 v3, v6, v3
5619; GFX10-NEXT:    ; return to shader part epilog
5620  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5621  %cast.result = bitcast i128 %result to <4 x float>
5622  ret <4 x float> %cast.result
5623}
5624
5625define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 inreg %amt) {
5626; GFX6-LABEL: v_fshr_i128_svs:
5627; GFX6:       ; %bb.0:
5628; GFX6-NEXT:    s_movk_i32 s6, 0x7f
5629; GFX6-NEXT:    s_mov_b32 s7, 0
5630; GFX6-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5631; GFX6-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5632; GFX6-NEXT:    s_sub_i32 s5, 1, 64
5633; GFX6-NEXT:    s_sub_i32 s9, 64, 1
5634; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5635; GFX6-NEXT:    s_cselect_b32 s14, 1, 0
5636; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5637; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
5638; GFX6-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
5639; GFX6-NEXT:    s_lshl_b64 s[12:13], s[2:3], 1
5640; GFX6-NEXT:    s_lshl_b64 s[6:7], s[0:1], 1
5641; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5642; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5643; GFX6-NEXT:    s_cmp_lg_u32 s14, 0
5644; GFX6-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5645; GFX6-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5646; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
5647; GFX6-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5648; GFX6-NEXT:    s_sub_i32 s9, s4, 64
5649; GFX6-NEXT:    s_sub_i32 s5, 64, s4
5650; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
5651; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5652; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
5653; GFX6-NEXT:    s_cselect_b32 s13, 1, 0
5654; GFX6-NEXT:    s_lshl_b64 s[2:3], s[6:7], s4
5655; GFX6-NEXT:    s_lshr_b64 s[10:11], s[6:7], s5
5656; GFX6-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5657; GFX6-NEXT:    s_or_b64 s[4:5], s[10:11], s[4:5]
5658; GFX6-NEXT:    s_lshl_b64 s[6:7], s[6:7], s9
5659; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5660; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5661; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5662; GFX6-NEXT:    s_cmp_lg_u32 s13, 0
5663; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
5664; GFX6-NEXT:    s_sub_i32 s5, 64, s8
5665; GFX6-NEXT:    s_sub_i32 s4, s8, 64
5666; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5667; GFX6-NEXT:    s_cselect_b32 s6, 1, 0
5668; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5669; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], s8
5670; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], s5
5671; GFX6-NEXT:    v_lshr_b64 v[8:9], v[2:3], s8
5672; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5673; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], s4
5674; GFX6-NEXT:    s_and_b32 s4, 1, s6
5675; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5676; GFX6-NEXT:    v_or_b32_e32 v4, v4, v6
5677; GFX6-NEXT:    v_or_b32_e32 v5, v5, v7
5678; GFX6-NEXT:    s_and_b32 s4, 1, s7
5679; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5680; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5681; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5682; GFX6-NEXT:    s_and_b32 s4, 1, s6
5683; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5684; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5685; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5686; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5687; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5688; GFX6-NEXT:    v_or_b32_e32 v0, s2, v0
5689; GFX6-NEXT:    v_or_b32_e32 v1, s3, v1
5690; GFX6-NEXT:    v_or_b32_e32 v2, s0, v2
5691; GFX6-NEXT:    v_or_b32_e32 v3, s1, v3
5692; GFX6-NEXT:    ; return to shader part epilog
5693;
5694; GFX8-LABEL: v_fshr_i128_svs:
5695; GFX8:       ; %bb.0:
5696; GFX8-NEXT:    s_movk_i32 s6, 0x7f
5697; GFX8-NEXT:    s_mov_b32 s7, 0
5698; GFX8-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5699; GFX8-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5700; GFX8-NEXT:    s_sub_i32 s5, 1, 64
5701; GFX8-NEXT:    s_sub_i32 s9, 64, 1
5702; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5703; GFX8-NEXT:    s_cselect_b32 s14, 1, 0
5704; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5705; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
5706; GFX8-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
5707; GFX8-NEXT:    s_lshl_b64 s[12:13], s[2:3], 1
5708; GFX8-NEXT:    s_lshl_b64 s[6:7], s[0:1], 1
5709; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5710; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5711; GFX8-NEXT:    s_cmp_lg_u32 s14, 0
5712; GFX8-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5713; GFX8-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5714; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
5715; GFX8-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5716; GFX8-NEXT:    s_sub_i32 s9, s4, 64
5717; GFX8-NEXT:    s_sub_i32 s5, 64, s4
5718; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
5719; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5720; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
5721; GFX8-NEXT:    s_cselect_b32 s13, 1, 0
5722; GFX8-NEXT:    s_lshl_b64 s[2:3], s[6:7], s4
5723; GFX8-NEXT:    s_lshr_b64 s[10:11], s[6:7], s5
5724; GFX8-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5725; GFX8-NEXT:    s_or_b64 s[4:5], s[10:11], s[4:5]
5726; GFX8-NEXT:    s_lshl_b64 s[6:7], s[6:7], s9
5727; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5728; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5729; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5730; GFX8-NEXT:    s_cmp_lg_u32 s13, 0
5731; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
5732; GFX8-NEXT:    s_sub_i32 s5, 64, s8
5733; GFX8-NEXT:    s_sub_i32 s4, s8, 64
5734; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
5735; GFX8-NEXT:    s_cselect_b32 s6, 1, 0
5736; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
5737; GFX8-NEXT:    v_lshrrev_b64 v[4:5], s8, v[0:1]
5738; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s5, v[2:3]
5739; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s8, v[2:3]
5740; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5741; GFX8-NEXT:    v_lshrrev_b64 v[2:3], s4, v[2:3]
5742; GFX8-NEXT:    s_and_b32 s4, 1, s6
5743; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5744; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
5745; GFX8-NEXT:    v_or_b32_e32 v5, v5, v7
5746; GFX8-NEXT:    s_and_b32 s4, 1, s7
5747; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5748; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5749; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5750; GFX8-NEXT:    s_and_b32 s4, 1, s6
5751; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5752; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5753; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5754; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5755; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5756; GFX8-NEXT:    v_or_b32_e32 v0, s2, v0
5757; GFX8-NEXT:    v_or_b32_e32 v1, s3, v1
5758; GFX8-NEXT:    v_or_b32_e32 v2, s0, v2
5759; GFX8-NEXT:    v_or_b32_e32 v3, s1, v3
5760; GFX8-NEXT:    ; return to shader part epilog
5761;
5762; GFX9-LABEL: v_fshr_i128_svs:
5763; GFX9:       ; %bb.0:
5764; GFX9-NEXT:    s_movk_i32 s6, 0x7f
5765; GFX9-NEXT:    s_mov_b32 s7, 0
5766; GFX9-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5767; GFX9-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5768; GFX9-NEXT:    s_sub_i32 s5, 1, 64
5769; GFX9-NEXT:    s_sub_i32 s9, 64, 1
5770; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5771; GFX9-NEXT:    s_cselect_b32 s14, 1, 0
5772; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5773; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
5774; GFX9-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
5775; GFX9-NEXT:    s_lshl_b64 s[12:13], s[2:3], 1
5776; GFX9-NEXT:    s_lshl_b64 s[6:7], s[0:1], 1
5777; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
5778; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5779; GFX9-NEXT:    s_cmp_lg_u32 s14, 0
5780; GFX9-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5781; GFX9-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
5782; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
5783; GFX9-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5784; GFX9-NEXT:    s_sub_i32 s9, s4, 64
5785; GFX9-NEXT:    s_sub_i32 s5, 64, s4
5786; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
5787; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5788; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
5789; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
5790; GFX9-NEXT:    s_lshl_b64 s[2:3], s[6:7], s4
5791; GFX9-NEXT:    s_lshr_b64 s[10:11], s[6:7], s5
5792; GFX9-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5793; GFX9-NEXT:    s_or_b64 s[4:5], s[10:11], s[4:5]
5794; GFX9-NEXT:    s_lshl_b64 s[6:7], s[6:7], s9
5795; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5796; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5797; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5798; GFX9-NEXT:    s_cmp_lg_u32 s13, 0
5799; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
5800; GFX9-NEXT:    s_sub_i32 s5, 64, s8
5801; GFX9-NEXT:    s_sub_i32 s4, s8, 64
5802; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
5803; GFX9-NEXT:    s_cselect_b32 s6, 1, 0
5804; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
5805; GFX9-NEXT:    v_lshrrev_b64 v[4:5], s8, v[0:1]
5806; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s5, v[2:3]
5807; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s8, v[2:3]
5808; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
5809; GFX9-NEXT:    v_lshrrev_b64 v[2:3], s4, v[2:3]
5810; GFX9-NEXT:    s_and_b32 s4, 1, s6
5811; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5812; GFX9-NEXT:    v_or_b32_e32 v4, v4, v6
5813; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
5814; GFX9-NEXT:    s_and_b32 s4, 1, s7
5815; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5816; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5817; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5818; GFX9-NEXT:    s_and_b32 s4, 1, s6
5819; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5820; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5821; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5822; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5823; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5824; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
5825; GFX9-NEXT:    v_or_b32_e32 v1, s3, v1
5826; GFX9-NEXT:    v_or_b32_e32 v2, s0, v2
5827; GFX9-NEXT:    v_or_b32_e32 v3, s1, v3
5828; GFX9-NEXT:    ; return to shader part epilog
5829;
5830; GFX10-LABEL: v_fshr_i128_svs:
5831; GFX10:       ; %bb.0:
5832; GFX10-NEXT:    s_movk_i32 s6, 0x7f
5833; GFX10-NEXT:    s_mov_b32 s7, 0
5834; GFX10-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5835; GFX10-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5836; GFX10-NEXT:    s_sub_i32 s5, 1, 64
5837; GFX10-NEXT:    s_sub_i32 s6, 64, 1
5838; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5839; GFX10-NEXT:    v_lshrrev_b64 v[4:5], s8, v[0:1]
5840; GFX10-NEXT:    s_cselect_b32 s9, 1, 0
5841; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5842; GFX10-NEXT:    s_cselect_b32 s14, 1, 0
5843; GFX10-NEXT:    s_lshr_b64 s[6:7], s[0:1], s6
5844; GFX10-NEXT:    s_lshl_b64 s[10:11], s[2:3], 1
5845; GFX10-NEXT:    s_lshl_b64 s[12:13], s[0:1], 1
5846; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
5847; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5848; GFX10-NEXT:    s_cmp_lg_u32 s9, 0
5849; GFX10-NEXT:    s_cselect_b64 s[10:11], s[12:13], 0
5850; GFX10-NEXT:    s_cselect_b64 s[0:1], s[6:7], s[0:1]
5851; GFX10-NEXT:    s_cmp_lg_u32 s14, 0
5852; GFX10-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
5853; GFX10-NEXT:    s_sub_i32 s9, s4, 64
5854; GFX10-NEXT:    s_sub_i32 s2, 64, s4
5855; GFX10-NEXT:    s_cmp_lt_u32 s4, 64
5856; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
5857; GFX10-NEXT:    s_cmp_eq_u32 s4, 0
5858; GFX10-NEXT:    s_cselect_b32 s13, 1, 0
5859; GFX10-NEXT:    s_lshl_b64 s[6:7], s[0:1], s4
5860; GFX10-NEXT:    s_lshr_b64 s[2:3], s[10:11], s2
5861; GFX10-NEXT:    s_lshl_b64 s[4:5], s[10:11], s4
5862; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
5863; GFX10-NEXT:    s_lshl_b64 s[6:7], s[10:11], s9
5864; GFX10-NEXT:    s_cmp_lg_u32 s12, 0
5865; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], 0
5866; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[6:7]
5867; GFX10-NEXT:    s_cmp_lg_u32 s13, 0
5868; GFX10-NEXT:    s_cselect_b64 s[2:3], s[0:1], s[2:3]
5869; GFX10-NEXT:    s_sub_i32 s0, 64, s8
5870; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s0, v[2:3]
5871; GFX10-NEXT:    s_sub_i32 s0, s8, 64
5872; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
5873; GFX10-NEXT:    v_lshrrev_b64 v[11:12], s0, v[2:3]
5874; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
5875; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
5876; GFX10-NEXT:    v_or_b32_e32 v4, v4, v6
5877; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
5878; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
5879; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
5880; GFX10-NEXT:    s_and_b32 s0, 1, s0
5881; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s8, v[2:3]
5882; GFX10-NEXT:    v_cndmask_b32_e32 v7, v11, v4, vcc_lo
5883; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v5, vcc_lo
5884; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
5885; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
5886; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
5887; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
5888; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5889; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5890; GFX10-NEXT:    v_or_b32_e32 v0, s4, v0
5891; GFX10-NEXT:    v_or_b32_e32 v1, s5, v1
5892; GFX10-NEXT:    v_or_b32_e32 v2, s2, v2
5893; GFX10-NEXT:    v_or_b32_e32 v3, s3, v3
5894; GFX10-NEXT:    ; return to shader part epilog
5895  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5896  %cast.result = bitcast i128 %result to <4 x float>
5897  ret <4 x float> %cast.result
5898}
5899
5900define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 inreg %amt) {
5901; GFX6-LABEL: v_fshr_i128_vss:
5902; GFX6:       ; %bb.0:
5903; GFX6-NEXT:    s_movk_i32 s6, 0x7f
5904; GFX6-NEXT:    s_mov_b32 s7, 0
5905; GFX6-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5906; GFX6-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5907; GFX6-NEXT:    s_sub_i32 s6, 64, 1
5908; GFX6-NEXT:    s_sub_i32 s5, 1, 64
5909; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5910; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5911; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5912; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], s6
5913; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], 1
5914; GFX6-NEXT:    s_cselect_b32 s9, 1, 0
5915; GFX6-NEXT:    v_lshl_b64 v[8:9], v[0:1], 1
5916; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s5
5917; GFX6-NEXT:    s_and_b32 s5, 1, s7
5918; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5919; GFX6-NEXT:    v_or_b32_e32 v6, v4, v6
5920; GFX6-NEXT:    v_or_b32_e32 v7, v5, v7
5921; GFX6-NEXT:    s_and_b32 s5, 1, s9
5922; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
5923; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
5924; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
5925; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
5926; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5927; GFX6-NEXT:    s_sub_i32 s5, s4, 64
5928; GFX6-NEXT:    s_sub_i32 s6, 64, s4
5929; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
5930; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5931; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
5932; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5933; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5934; GFX6-NEXT:    s_cselect_b32 s9, 1, 0
5935; GFX6-NEXT:    v_lshr_b64 v[2:3], v[4:5], s6
5936; GFX6-NEXT:    v_lshl_b64 v[6:7], v[0:1], s4
5937; GFX6-NEXT:    v_lshl_b64 v[8:9], v[4:5], s4
5938; GFX6-NEXT:    s_and_b32 s4, 1, s7
5939; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5940; GFX6-NEXT:    s_and_b32 s4, 1, s9
5941; GFX6-NEXT:    s_sub_i32 s10, s8, 64
5942; GFX6-NEXT:    s_sub_i32 s9, 64, s8
5943; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5944; GFX6-NEXT:    v_or_b32_e32 v6, v2, v6
5945; GFX6-NEXT:    v_or_b32_e32 v7, v3, v7
5946; GFX6-NEXT:    v_lshl_b64 v[2:3], v[4:5], s5
5947; GFX6-NEXT:    s_cselect_b32 s11, 1, 0
5948; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5949; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5950; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
5951; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
5952; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
5953; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
5954; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5955; GFX6-NEXT:    s_lshr_b64 s[4:5], s[2:3], s8
5956; GFX6-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
5957; GFX6-NEXT:    s_lshl_b64 s[8:9], s[2:3], s9
5958; GFX6-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
5959; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5960; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5961; GFX6-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
5962; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5963; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5964; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5965; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc
5966; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc
5967; GFX6-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
5968; GFX6-NEXT:    v_or_b32_e32 v0, s0, v4
5969; GFX6-NEXT:    v_or_b32_e32 v1, s1, v5
5970; GFX6-NEXT:    v_or_b32_e32 v2, s2, v2
5971; GFX6-NEXT:    v_or_b32_e32 v3, s3, v3
5972; GFX6-NEXT:    ; return to shader part epilog
5973;
5974; GFX8-LABEL: v_fshr_i128_vss:
5975; GFX8:       ; %bb.0:
5976; GFX8-NEXT:    s_movk_i32 s6, 0x7f
5977; GFX8-NEXT:    s_mov_b32 s7, 0
5978; GFX8-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5979; GFX8-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5980; GFX8-NEXT:    s_sub_i32 s6, 64, 1
5981; GFX8-NEXT:    s_sub_i32 s5, 1, 64
5982; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5983; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5984; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5985; GFX8-NEXT:    v_lshrrev_b64 v[4:5], s6, v[0:1]
5986; GFX8-NEXT:    v_lshlrev_b64 v[6:7], 1, v[2:3]
5987; GFX8-NEXT:    s_cselect_b32 s9, 1, 0
5988; GFX8-NEXT:    v_lshlrev_b64 v[8:9], 1, v[0:1]
5989; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
5990; GFX8-NEXT:    s_and_b32 s5, 1, s7
5991; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5992; GFX8-NEXT:    v_or_b32_e32 v6, v4, v6
5993; GFX8-NEXT:    v_or_b32_e32 v7, v5, v7
5994; GFX8-NEXT:    s_and_b32 s5, 1, s9
5995; GFX8-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
5996; GFX8-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
5997; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
5998; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
5999; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
6000; GFX8-NEXT:    s_sub_i32 s5, s4, 64
6001; GFX8-NEXT:    s_sub_i32 s6, 64, s4
6002; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
6003; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
6004; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
6005; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6006; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6007; GFX8-NEXT:    s_cselect_b32 s9, 1, 0
6008; GFX8-NEXT:    v_lshrrev_b64 v[2:3], s6, v[4:5]
6009; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s4, v[0:1]
6010; GFX8-NEXT:    v_lshlrev_b64 v[8:9], s4, v[4:5]
6011; GFX8-NEXT:    s_and_b32 s4, 1, s7
6012; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6013; GFX8-NEXT:    s_and_b32 s4, 1, s9
6014; GFX8-NEXT:    s_sub_i32 s10, s8, 64
6015; GFX8-NEXT:    s_sub_i32 s9, 64, s8
6016; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
6017; GFX8-NEXT:    v_or_b32_e32 v6, v2, v6
6018; GFX8-NEXT:    v_or_b32_e32 v7, v3, v7
6019; GFX8-NEXT:    v_lshlrev_b64 v[2:3], s5, v[4:5]
6020; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
6021; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
6022; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
6023; GFX8-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
6024; GFX8-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
6025; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
6026; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
6027; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6028; GFX8-NEXT:    s_lshr_b64 s[4:5], s[2:3], s8
6029; GFX8-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
6030; GFX8-NEXT:    s_lshl_b64 s[8:9], s[2:3], s9
6031; GFX8-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6032; GFX8-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
6033; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
6034; GFX8-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
6035; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
6036; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
6037; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
6038; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc
6039; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc
6040; GFX8-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
6041; GFX8-NEXT:    v_or_b32_e32 v0, s0, v4
6042; GFX8-NEXT:    v_or_b32_e32 v1, s1, v5
6043; GFX8-NEXT:    v_or_b32_e32 v2, s2, v2
6044; GFX8-NEXT:    v_or_b32_e32 v3, s3, v3
6045; GFX8-NEXT:    ; return to shader part epilog
6046;
6047; GFX9-LABEL: v_fshr_i128_vss:
6048; GFX9:       ; %bb.0:
6049; GFX9-NEXT:    s_movk_i32 s6, 0x7f
6050; GFX9-NEXT:    s_mov_b32 s7, 0
6051; GFX9-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
6052; GFX9-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
6053; GFX9-NEXT:    s_sub_i32 s6, 64, 1
6054; GFX9-NEXT:    s_sub_i32 s5, 1, 64
6055; GFX9-NEXT:    s_cmp_lt_u32 1, 64
6056; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
6057; GFX9-NEXT:    s_cmp_eq_u32 1, 0
6058; GFX9-NEXT:    v_lshrrev_b64 v[4:5], s6, v[0:1]
6059; GFX9-NEXT:    v_lshlrev_b64 v[6:7], 1, v[2:3]
6060; GFX9-NEXT:    s_cselect_b32 s9, 1, 0
6061; GFX9-NEXT:    v_lshlrev_b64 v[8:9], 1, v[0:1]
6062; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
6063; GFX9-NEXT:    s_and_b32 s5, 1, s7
6064; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
6065; GFX9-NEXT:    v_or_b32_e32 v6, v4, v6
6066; GFX9-NEXT:    v_or_b32_e32 v7, v5, v7
6067; GFX9-NEXT:    s_and_b32 s5, 1, s9
6068; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
6069; GFX9-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
6070; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
6071; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
6072; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
6073; GFX9-NEXT:    s_sub_i32 s5, s4, 64
6074; GFX9-NEXT:    s_sub_i32 s6, 64, s4
6075; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
6076; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
6077; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
6078; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6079; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6080; GFX9-NEXT:    s_cselect_b32 s9, 1, 0
6081; GFX9-NEXT:    v_lshrrev_b64 v[2:3], s6, v[4:5]
6082; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s4, v[0:1]
6083; GFX9-NEXT:    v_lshlrev_b64 v[8:9], s4, v[4:5]
6084; GFX9-NEXT:    s_and_b32 s4, 1, s7
6085; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6086; GFX9-NEXT:    s_and_b32 s4, 1, s9
6087; GFX9-NEXT:    s_sub_i32 s10, s8, 64
6088; GFX9-NEXT:    s_sub_i32 s9, 64, s8
6089; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
6090; GFX9-NEXT:    v_or_b32_e32 v6, v2, v6
6091; GFX9-NEXT:    v_or_b32_e32 v7, v3, v7
6092; GFX9-NEXT:    v_lshlrev_b64 v[2:3], s5, v[4:5]
6093; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
6094; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
6095; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
6096; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
6097; GFX9-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
6098; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
6099; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
6100; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6101; GFX9-NEXT:    s_lshr_b64 s[4:5], s[2:3], s8
6102; GFX9-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
6103; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s9
6104; GFX9-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6105; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
6106; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
6107; GFX9-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
6108; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
6109; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
6110; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
6111; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc
6112; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc
6113; GFX9-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
6114; GFX9-NEXT:    v_or_b32_e32 v0, s0, v4
6115; GFX9-NEXT:    v_or_b32_e32 v1, s1, v5
6116; GFX9-NEXT:    v_or_b32_e32 v2, s2, v2
6117; GFX9-NEXT:    v_or_b32_e32 v3, s3, v3
6118; GFX9-NEXT:    ; return to shader part epilog
6119;
6120; GFX10-LABEL: v_fshr_i128_vss:
6121; GFX10:       ; %bb.0:
6122; GFX10-NEXT:    s_movk_i32 s6, 0x7f
6123; GFX10-NEXT:    s_mov_b32 s7, 0
6124; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 1, v[2:3]
6125; GFX10-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
6126; GFX10-NEXT:    s_andn2_b64 s[6:7], s[6:7], s[4:5]
6127; GFX10-NEXT:    s_sub_i32 s4, 64, 1
6128; GFX10-NEXT:    s_sub_i32 s5, 1, 64
6129; GFX10-NEXT:    v_lshrrev_b64 v[4:5], s4, v[0:1]
6130; GFX10-NEXT:    s_cmp_lt_u32 1, 64
6131; GFX10-NEXT:    v_lshlrev_b64 v[13:14], s5, v[0:1]
6132; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
6133; GFX10-NEXT:    s_cmp_eq_u32 1, 0
6134; GFX10-NEXT:    v_lshlrev_b64 v[8:9], 1, v[0:1]
6135; GFX10-NEXT:    s_cselect_b32 s7, 1, 0
6136; GFX10-NEXT:    s_and_b32 s4, 1, vcc_lo
6137; GFX10-NEXT:    v_or_b32_e32 v6, v4, v6
6138; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
6139; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
6140; GFX10-NEXT:    s_and_b32 s5, 1, s7
6141; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc_lo
6142; GFX10-NEXT:    v_cndmask_b32_e64 v0, v13, v6, s4
6143; GFX10-NEXT:    v_cndmask_b32_e64 v1, v14, v5, s4
6144; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
6145; GFX10-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc_lo
6146; GFX10-NEXT:    s_sub_i32 s5, s6, 64
6147; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s4
6148; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s4
6149; GFX10-NEXT:    s_sub_i32 s4, 64, s6
6150; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
6151; GFX10-NEXT:    v_lshrrev_b64 v[11:12], s4, v[4:5]
6152; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
6153; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s6, v[0:1]
6154; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
6155; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s6, v[4:5]
6156; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
6157; GFX10-NEXT:    s_and_b32 s4, 1, vcc_lo
6158; GFX10-NEXT:    v_lshlrev_b64 v[4:5], s5, v[4:5]
6159; GFX10-NEXT:    v_or_b32_e32 v2, v11, v6
6160; GFX10-NEXT:    v_or_b32_e32 v3, v12, v7
6161; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
6162; GFX10-NEXT:    s_sub_i32 s10, s8, 64
6163; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc_lo
6164; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc_lo
6165; GFX10-NEXT:    v_cndmask_b32_e64 v2, v4, v2, s4
6166; GFX10-NEXT:    v_cndmask_b32_e64 v3, v5, v3, s4
6167; GFX10-NEXT:    s_and_b32 s4, 1, s6
6168; GFX10-NEXT:    s_sub_i32 s6, 64, s8
6169; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
6170; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
6171; GFX10-NEXT:    s_cselect_b32 s11, 1, 0
6172; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
6173; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
6174; GFX10-NEXT:    s_lshr_b64 s[4:5], s[0:1], s8
6175; GFX10-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
6176; GFX10-NEXT:    s_lshr_b64 s[8:9], s[2:3], s8
6177; GFX10-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
6178; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
6179; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6180; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo
6181; GFX10-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
6182; GFX10-NEXT:    s_cmp_lg_u32 s12, 0
6183; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo
6184; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
6185; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6186; GFX10-NEXT:    v_or_b32_e32 v0, s0, v6
6187; GFX10-NEXT:    s_cselect_b64 s[2:3], s[8:9], 0
6188; GFX10-NEXT:    v_or_b32_e32 v1, s1, v7
6189; GFX10-NEXT:    v_or_b32_e32 v2, s2, v2
6190; GFX10-NEXT:    v_or_b32_e32 v3, s3, v3
6191; GFX10-NEXT:    ; return to shader part epilog
6192  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
6193  %cast.result = bitcast i128 %result to <4 x float>
6194  ret <4 x float> %cast.result
6195}
6196
6197define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
6198; GFX6-LABEL: s_fshr_i128_65:
6199; GFX6:       ; %bb.0:
6200; GFX6-NEXT:    s_sub_i32 s14, 63, 64
6201; GFX6-NEXT:    s_sub_i32 s10, 64, 63
6202; GFX6-NEXT:    s_cmp_lt_u32 63, 64
6203; GFX6-NEXT:    s_mov_b32 s8, 0
6204; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
6205; GFX6-NEXT:    s_cmp_eq_u32 63, 0
6206; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
6207; GFX6-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
6208; GFX6-NEXT:    s_lshl_b32 s13, s2, 31
6209; GFX6-NEXT:    s_mov_b32 s12, s8
6210; GFX6-NEXT:    s_lshl_b32 s9, s0, 31
6211; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6212; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
6213; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
6214; GFX6-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
6215; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
6216; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
6217; GFX6-NEXT:    s_movk_i32 s10, 0x41
6218; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6219; GFX6-NEXT:    s_sub_i32 s14, s10, 64
6220; GFX6-NEXT:    s_sub_i32 s12, 64, s10
6221; GFX6-NEXT:    s_cmp_lt_u32 s10, 64
6222; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
6223; GFX6-NEXT:    s_cmp_eq_u32 s10, 0
6224; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
6225; GFX6-NEXT:    s_lshr_b64 s[0:1], s[6:7], s10
6226; GFX6-NEXT:    s_lshl_b64 s[12:13], s[6:7], s12
6227; GFX6-NEXT:    s_lshr_b64 s[10:11], s[4:5], s10
6228; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6229; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6230; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
6231; GFX6-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
6232; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
6233; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
6234; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
6235; GFX6-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
6236; GFX6-NEXT:    s_or_b64 s[0:1], s[8:9], s[4:5]
6237; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
6238; GFX6-NEXT:    ; return to shader part epilog
6239;
6240; GFX8-LABEL: s_fshr_i128_65:
6241; GFX8:       ; %bb.0:
6242; GFX8-NEXT:    s_sub_i32 s14, 63, 64
6243; GFX8-NEXT:    s_sub_i32 s10, 64, 63
6244; GFX8-NEXT:    s_cmp_lt_u32 63, 64
6245; GFX8-NEXT:    s_mov_b32 s8, 0
6246; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
6247; GFX8-NEXT:    s_cmp_eq_u32 63, 0
6248; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
6249; GFX8-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
6250; GFX8-NEXT:    s_lshl_b32 s13, s2, 31
6251; GFX8-NEXT:    s_mov_b32 s12, s8
6252; GFX8-NEXT:    s_lshl_b32 s9, s0, 31
6253; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6254; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
6255; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
6256; GFX8-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
6257; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
6258; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
6259; GFX8-NEXT:    s_movk_i32 s10, 0x41
6260; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6261; GFX8-NEXT:    s_sub_i32 s14, s10, 64
6262; GFX8-NEXT:    s_sub_i32 s12, 64, s10
6263; GFX8-NEXT:    s_cmp_lt_u32 s10, 64
6264; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
6265; GFX8-NEXT:    s_cmp_eq_u32 s10, 0
6266; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
6267; GFX8-NEXT:    s_lshr_b64 s[0:1], s[6:7], s10
6268; GFX8-NEXT:    s_lshl_b64 s[12:13], s[6:7], s12
6269; GFX8-NEXT:    s_lshr_b64 s[10:11], s[4:5], s10
6270; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6271; GFX8-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6272; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
6273; GFX8-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
6274; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
6275; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
6276; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
6277; GFX8-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
6278; GFX8-NEXT:    s_or_b64 s[0:1], s[8:9], s[4:5]
6279; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
6280; GFX8-NEXT:    ; return to shader part epilog
6281;
6282; GFX9-LABEL: s_fshr_i128_65:
6283; GFX9:       ; %bb.0:
6284; GFX9-NEXT:    s_sub_i32 s14, 63, 64
6285; GFX9-NEXT:    s_sub_i32 s10, 64, 63
6286; GFX9-NEXT:    s_cmp_lt_u32 63, 64
6287; GFX9-NEXT:    s_mov_b32 s8, 0
6288; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
6289; GFX9-NEXT:    s_cmp_eq_u32 63, 0
6290; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
6291; GFX9-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
6292; GFX9-NEXT:    s_lshl_b32 s13, s2, 31
6293; GFX9-NEXT:    s_mov_b32 s12, s8
6294; GFX9-NEXT:    s_lshl_b32 s9, s0, 31
6295; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6296; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
6297; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
6298; GFX9-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
6299; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
6300; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
6301; GFX9-NEXT:    s_movk_i32 s10, 0x41
6302; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6303; GFX9-NEXT:    s_sub_i32 s14, s10, 64
6304; GFX9-NEXT:    s_sub_i32 s12, 64, s10
6305; GFX9-NEXT:    s_cmp_lt_u32 s10, 64
6306; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
6307; GFX9-NEXT:    s_cmp_eq_u32 s10, 0
6308; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
6309; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], s10
6310; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], s12
6311; GFX9-NEXT:    s_lshr_b64 s[10:11], s[4:5], s10
6312; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6313; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6314; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
6315; GFX9-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
6316; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
6317; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
6318; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
6319; GFX9-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
6320; GFX9-NEXT:    s_or_b64 s[0:1], s[8:9], s[4:5]
6321; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
6322; GFX9-NEXT:    ; return to shader part epilog
6323;
6324; GFX10-LABEL: s_fshr_i128_65:
6325; GFX10:       ; %bb.0:
6326; GFX10-NEXT:    s_sub_i32 s14, 63, 64
6327; GFX10-NEXT:    s_sub_i32 s9, 64, 63
6328; GFX10-NEXT:    s_cmp_lt_u32 63, 64
6329; GFX10-NEXT:    s_mov_b32 s8, 0
6330; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
6331; GFX10-NEXT:    s_cmp_eq_u32 63, 0
6332; GFX10-NEXT:    s_mov_b32 s12, s8
6333; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
6334; GFX10-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
6335; GFX10-NEXT:    s_lshl_b32 s13, s2, 31
6336; GFX10-NEXT:    s_lshl_b32 s9, s0, 31
6337; GFX10-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
6338; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
6339; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
6340; GFX10-NEXT:    s_movk_i32 s12, 0x41
6341; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
6342; GFX10-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
6343; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
6344; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6345; GFX10-NEXT:    s_sub_i32 s14, s12, 64
6346; GFX10-NEXT:    s_sub_i32 s10, 64, s12
6347; GFX10-NEXT:    s_cmp_lt_u32 s12, 64
6348; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
6349; GFX10-NEXT:    s_cmp_eq_u32 s12, 0
6350; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
6351; GFX10-NEXT:    s_lshr_b64 s[0:1], s[4:5], s12
6352; GFX10-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
6353; GFX10-NEXT:    s_lshr_b64 s[12:13], s[6:7], s12
6354; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
6355; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6356; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
6357; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
6358; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
6359; GFX10-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
6360; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
6361; GFX10-NEXT:    s_cselect_b64 s[4:5], s[12:13], 0
6362; GFX10-NEXT:    s_or_b64 s[0:1], s[8:9], s[0:1]
6363; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
6364; GFX10-NEXT:    ; return to shader part epilog
6365  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
6366  ret i128 %result
6367}
6368
6369define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
6370; GFX6-LABEL: v_fshr_i128_65:
6371; GFX6:       ; %bb.0:
6372; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6373; GFX6-NEXT:    s_sub_i32 s5, 64, 63
6374; GFX6-NEXT:    s_sub_i32 s4, 63, 64
6375; GFX6-NEXT:    s_cmp_lt_u32 63, 64
6376; GFX6-NEXT:    s_cselect_b32 s6, 1, 0
6377; GFX6-NEXT:    s_cmp_eq_u32 63, 0
6378; GFX6-NEXT:    v_lshr_b64 v[8:9], v[0:1], s5
6379; GFX6-NEXT:    v_lshlrev_b32_e32 v10, 31, v0
6380; GFX6-NEXT:    v_lshlrev_b32_e32 v11, 31, v2
6381; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
6382; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s4
6383; GFX6-NEXT:    s_and_b32 s4, 1, s6
6384; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6385; GFX6-NEXT:    v_or_b32_e32 v9, v9, v11
6386; GFX6-NEXT:    s_and_b32 s4, 1, s7
6387; GFX6-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
6388; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
6389; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
6390; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6391; GFX6-NEXT:    s_movk_i32 s4, 0x41
6392; GFX6-NEXT:    s_sub_i32 s5, s4, 64
6393; GFX6-NEXT:    s_sub_i32 s6, 64, s4
6394; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
6395; GFX6-NEXT:    v_cndmask_b32_e32 v11, v0, v2, vcc
6396; GFX6-NEXT:    v_cndmask_b32_e32 v12, v1, v3, vcc
6397; GFX6-NEXT:    v_lshr_b64 v[0:1], v[4:5], s4
6398; GFX6-NEXT:    v_lshl_b64 v[2:3], v[6:7], s6
6399; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
6400; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
6401; GFX6-NEXT:    s_cselect_b32 s8, 1, 0
6402; GFX6-NEXT:    v_lshr_b64 v[8:9], v[6:7], s4
6403; GFX6-NEXT:    s_and_b32 s4, 1, s7
6404; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
6405; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
6406; GFX6-NEXT:    v_lshr_b64 v[0:1], v[6:7], s5
6407; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6408; GFX6-NEXT:    s_and_b32 s4, 1, s8
6409; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6410; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6411; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6412; GFX6-NEXT:    s_and_b32 s4, 1, s7
6413; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
6414; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6415; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6416; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
6417; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
6418; GFX6-NEXT:    v_or_b32_e32 v1, v10, v1
6419; GFX6-NEXT:    v_or_b32_e32 v2, v11, v2
6420; GFX6-NEXT:    v_or_b32_e32 v3, v12, v3
6421; GFX6-NEXT:    s_setpc_b64 s[30:31]
6422;
6423; GFX8-LABEL: v_fshr_i128_65:
6424; GFX8:       ; %bb.0:
6425; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6426; GFX8-NEXT:    s_sub_i32 s5, 64, 63
6427; GFX8-NEXT:    s_sub_i32 s4, 63, 64
6428; GFX8-NEXT:    s_cmp_lt_u32 63, 64
6429; GFX8-NEXT:    s_cselect_b32 s6, 1, 0
6430; GFX8-NEXT:    s_cmp_eq_u32 63, 0
6431; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s5, v[0:1]
6432; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 31, v0
6433; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 31, v2
6434; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
6435; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
6436; GFX8-NEXT:    s_and_b32 s4, 1, s6
6437; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6438; GFX8-NEXT:    v_or_b32_e32 v9, v9, v11
6439; GFX8-NEXT:    s_and_b32 s4, 1, s7
6440; GFX8-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
6441; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
6442; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
6443; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6444; GFX8-NEXT:    s_movk_i32 s4, 0x41
6445; GFX8-NEXT:    s_sub_i32 s5, s4, 64
6446; GFX8-NEXT:    s_sub_i32 s6, 64, s4
6447; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
6448; GFX8-NEXT:    v_cndmask_b32_e32 v11, v0, v2, vcc
6449; GFX8-NEXT:    v_cndmask_b32_e32 v12, v1, v3, vcc
6450; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s4, v[4:5]
6451; GFX8-NEXT:    v_lshlrev_b64 v[2:3], s6, v[6:7]
6452; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
6453; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
6454; GFX8-NEXT:    s_cselect_b32 s8, 1, 0
6455; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s4, v[6:7]
6456; GFX8-NEXT:    s_and_b32 s4, 1, s7
6457; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
6458; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
6459; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s5, v[6:7]
6460; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6461; GFX8-NEXT:    s_and_b32 s4, 1, s8
6462; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6463; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6464; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6465; GFX8-NEXT:    s_and_b32 s4, 1, s7
6466; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
6467; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6468; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6469; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
6470; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
6471; GFX8-NEXT:    v_or_b32_e32 v1, v10, v1
6472; GFX8-NEXT:    v_or_b32_e32 v2, v11, v2
6473; GFX8-NEXT:    v_or_b32_e32 v3, v12, v3
6474; GFX8-NEXT:    s_setpc_b64 s[30:31]
6475;
6476; GFX9-LABEL: v_fshr_i128_65:
6477; GFX9:       ; %bb.0:
6478; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6479; GFX9-NEXT:    s_sub_i32 s5, 64, 63
6480; GFX9-NEXT:    s_sub_i32 s4, 63, 64
6481; GFX9-NEXT:    s_cmp_lt_u32 63, 64
6482; GFX9-NEXT:    s_cselect_b32 s6, 1, 0
6483; GFX9-NEXT:    s_cmp_eq_u32 63, 0
6484; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s5, v[0:1]
6485; GFX9-NEXT:    v_lshlrev_b32_e32 v10, 31, v0
6486; GFX9-NEXT:    v_lshlrev_b32_e32 v11, 31, v2
6487; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
6488; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
6489; GFX9-NEXT:    s_and_b32 s4, 1, s6
6490; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6491; GFX9-NEXT:    v_or_b32_e32 v9, v9, v11
6492; GFX9-NEXT:    s_and_b32 s4, 1, s7
6493; GFX9-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
6494; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
6495; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
6496; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6497; GFX9-NEXT:    s_movk_i32 s4, 0x41
6498; GFX9-NEXT:    s_sub_i32 s5, s4, 64
6499; GFX9-NEXT:    s_sub_i32 s6, 64, s4
6500; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
6501; GFX9-NEXT:    v_cndmask_b32_e32 v11, v0, v2, vcc
6502; GFX9-NEXT:    v_cndmask_b32_e32 v12, v1, v3, vcc
6503; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s4, v[4:5]
6504; GFX9-NEXT:    v_lshlrev_b64 v[2:3], s6, v[6:7]
6505; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
6506; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
6507; GFX9-NEXT:    s_cselect_b32 s8, 1, 0
6508; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s4, v[6:7]
6509; GFX9-NEXT:    s_and_b32 s4, 1, s7
6510; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
6511; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
6512; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s5, v[6:7]
6513; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6514; GFX9-NEXT:    s_and_b32 s4, 1, s8
6515; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
6516; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
6517; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6518; GFX9-NEXT:    s_and_b32 s4, 1, s7
6519; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
6520; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6521; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6522; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
6523; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
6524; GFX9-NEXT:    v_or_b32_e32 v1, v10, v1
6525; GFX9-NEXT:    v_or_b32_e32 v2, v11, v2
6526; GFX9-NEXT:    v_or_b32_e32 v3, v12, v3
6527; GFX9-NEXT:    s_setpc_b64 s[30:31]
6528;
6529; GFX10-LABEL: v_fshr_i128_65:
6530; GFX10:       ; %bb.0:
6531; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6532; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
6533; GFX10-NEXT:    s_sub_i32 s4, 64, 63
6534; GFX10-NEXT:    s_sub_i32 s5, 63, 64
6535; GFX10-NEXT:    s_cmp_lt_u32 63, 64
6536; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 31, v0
6537; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
6538; GFX10-NEXT:    s_cmp_eq_u32 63, 0
6539; GFX10-NEXT:    v_lshrrev_b64 v[8:9], s4, v[0:1]
6540; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
6541; GFX10-NEXT:    v_lshlrev_b64 v[14:15], s5, v[0:1]
6542; GFX10-NEXT:    s_and_b32 s5, 1, vcc_lo
6543; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 31, v2
6544; GFX10-NEXT:    v_cndmask_b32_e32 v23, 0, v11, vcc_lo
6545; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s5
6546; GFX10-NEXT:    s_movk_i32 s6, 0x41
6547; GFX10-NEXT:    s_and_b32 s4, 1, s4
6548; GFX10-NEXT:    s_sub_i32 s5, 64, s6
6549; GFX10-NEXT:    v_or_b32_e32 v12, v9, v10
6550; GFX10-NEXT:    v_cndmask_b32_e32 v19, v14, v8, vcc_lo
6551; GFX10-NEXT:    v_lshlrev_b64 v[10:11], s5, v[6:7]
6552; GFX10-NEXT:    v_lshrrev_b64 v[8:9], s6, v[4:5]
6553; GFX10-NEXT:    s_sub_i32 s5, s6, 64
6554; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
6555; GFX10-NEXT:    v_cndmask_b32_e32 v12, v15, v12, vcc_lo
6556; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s5, v[6:7]
6557; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
6558; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
6559; GFX10-NEXT:    v_or_b32_e32 v8, v8, v10
6560; GFX10-NEXT:    v_or_b32_e32 v9, v9, v11
6561; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
6562; GFX10-NEXT:    v_lshrrev_b64 v[6:7], s6, v[6:7]
6563; GFX10-NEXT:    s_and_b32 s5, 1, s5
6564; GFX10-NEXT:    s_and_b32 s6, 1, vcc_lo
6565; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
6566; GFX10-NEXT:    v_cndmask_b32_e32 v11, v15, v8, vcc_lo
6567; GFX10-NEXT:    v_cndmask_b32_e32 v15, v16, v9, vcc_lo
6568; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s5
6569; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s6
6570; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v2, s4
6571; GFX10-NEXT:    v_cndmask_b32_e64 v3, v12, v3, s4
6572; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v5, s5
6573; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v4, s5
6574; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0, v6, vcc_lo
6575; GFX10-NEXT:    v_cndmask_b32_e32 v5, 0, v7, vcc_lo
6576; GFX10-NEXT:    v_or_b32_e32 v1, v23, v1
6577; GFX10-NEXT:    v_or_b32_e32 v2, v2, v4
6578; GFX10-NEXT:    v_or_b32_e32 v3, v3, v5
6579; GFX10-NEXT:    s_setpc_b64 s[30:31]
6580  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
6581  ret i128 %result
6582}
6583
6584define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
6585; GFX6-LABEL: s_fshr_v2i128:
6586; GFX6:       ; %bb.0:
6587; GFX6-NEXT:    s_movk_i32 s18, 0x7f
6588; GFX6-NEXT:    s_mov_b32 s19, 0
6589; GFX6-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6590; GFX6-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6591; GFX6-NEXT:    s_sub_i32 s30, 1, 64
6592; GFX6-NEXT:    s_sub_i32 s31, 64, 1
6593; GFX6-NEXT:    s_cmp_lt_u32 1, 64
6594; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
6595; GFX6-NEXT:    s_cmp_eq_u32 1, 0
6596; GFX6-NEXT:    s_cselect_b32 s23, 1, 0
6597; GFX6-NEXT:    s_lshr_b64 s[26:27], s[0:1], s31
6598; GFX6-NEXT:    s_lshl_b64 s[28:29], s[2:3], 1
6599; GFX6-NEXT:    s_lshl_b64 s[24:25], s[0:1], 1
6600; GFX6-NEXT:    s_or_b64 s[26:27], s[26:27], s[28:29]
6601; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s30
6602; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
6603; GFX6-NEXT:    s_cselect_b64 s[24:25], s[24:25], 0
6604; GFX6-NEXT:    s_cselect_b64 s[0:1], s[26:27], s[0:1]
6605; GFX6-NEXT:    s_cmp_lg_u32 s23, 0
6606; GFX6-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
6607; GFX6-NEXT:    s_sub_i32 s23, s16, 64
6608; GFX6-NEXT:    s_sub_i32 s17, 64, s16
6609; GFX6-NEXT:    s_cmp_lt_u32 s16, 64
6610; GFX6-NEXT:    s_cselect_b32 s28, 1, 0
6611; GFX6-NEXT:    s_cmp_eq_u32 s16, 0
6612; GFX6-NEXT:    s_cselect_b32 s29, 1, 0
6613; GFX6-NEXT:    s_lshl_b64 s[2:3], s[24:25], s16
6614; GFX6-NEXT:    s_lshr_b64 s[26:27], s[24:25], s17
6615; GFX6-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
6616; GFX6-NEXT:    s_or_b64 s[16:17], s[26:27], s[16:17]
6617; GFX6-NEXT:    s_lshl_b64 s[24:25], s[24:25], s23
6618; GFX6-NEXT:    s_cmp_lg_u32 s28, 0
6619; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
6620; GFX6-NEXT:    s_cselect_b64 s[16:17], s[16:17], s[24:25]
6621; GFX6-NEXT:    s_cmp_lg_u32 s29, 0
6622; GFX6-NEXT:    s_cselect_b64 s[16:17], s[0:1], s[16:17]
6623; GFX6-NEXT:    s_sub_i32 s26, s22, 64
6624; GFX6-NEXT:    s_sub_i32 s24, 64, s22
6625; GFX6-NEXT:    s_cmp_lt_u32 s22, 64
6626; GFX6-NEXT:    s_cselect_b32 s27, 1, 0
6627; GFX6-NEXT:    s_cmp_eq_u32 s22, 0
6628; GFX6-NEXT:    s_cselect_b32 s28, 1, 0
6629; GFX6-NEXT:    s_lshr_b64 s[0:1], s[10:11], s22
6630; GFX6-NEXT:    s_lshl_b64 s[24:25], s[10:11], s24
6631; GFX6-NEXT:    s_lshr_b64 s[22:23], s[8:9], s22
6632; GFX6-NEXT:    s_or_b64 s[22:23], s[22:23], s[24:25]
6633; GFX6-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
6634; GFX6-NEXT:    s_cmp_lg_u32 s27, 0
6635; GFX6-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
6636; GFX6-NEXT:    s_cmp_lg_u32 s28, 0
6637; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
6638; GFX6-NEXT:    s_cmp_lg_u32 s27, 0
6639; GFX6-NEXT:    s_cselect_b64 s[10:11], s[0:1], 0
6640; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
6641; GFX6-NEXT:    s_or_b64 s[2:3], s[16:17], s[10:11]
6642; GFX6-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6643; GFX6-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6644; GFX6-NEXT:    s_cmp_lt_u32 1, 64
6645; GFX6-NEXT:    s_cselect_b32 s9, 1, 0
6646; GFX6-NEXT:    s_cmp_eq_u32 1, 0
6647; GFX6-NEXT:    s_cselect_b32 s11, 1, 0
6648; GFX6-NEXT:    s_lshr_b64 s[18:19], s[4:5], s31
6649; GFX6-NEXT:    s_lshl_b64 s[20:21], s[6:7], 1
6650; GFX6-NEXT:    s_lshl_b64 s[16:17], s[4:5], 1
6651; GFX6-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
6652; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s30
6653; GFX6-NEXT:    s_cmp_lg_u32 s9, 0
6654; GFX6-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6655; GFX6-NEXT:    s_cselect_b64 s[4:5], s[18:19], s[4:5]
6656; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
6657; GFX6-NEXT:    s_cselect_b64 s[4:5], s[6:7], s[4:5]
6658; GFX6-NEXT:    s_sub_i32 s9, s10, 64
6659; GFX6-NEXT:    s_sub_i32 s11, 64, s10
6660; GFX6-NEXT:    s_cmp_lt_u32 s10, 64
6661; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
6662; GFX6-NEXT:    s_cmp_eq_u32 s10, 0
6663; GFX6-NEXT:    s_cselect_b32 s21, 1, 0
6664; GFX6-NEXT:    s_lshl_b64 s[6:7], s[16:17], s10
6665; GFX6-NEXT:    s_lshr_b64 s[18:19], s[16:17], s11
6666; GFX6-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
6667; GFX6-NEXT:    s_or_b64 s[10:11], s[18:19], s[10:11]
6668; GFX6-NEXT:    s_lshl_b64 s[16:17], s[16:17], s9
6669; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
6670; GFX6-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
6671; GFX6-NEXT:    s_cselect_b64 s[10:11], s[10:11], s[16:17]
6672; GFX6-NEXT:    s_cmp_lg_u32 s21, 0
6673; GFX6-NEXT:    s_cselect_b64 s[10:11], s[4:5], s[10:11]
6674; GFX6-NEXT:    s_sub_i32 s18, s8, 64
6675; GFX6-NEXT:    s_sub_i32 s16, 64, s8
6676; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
6677; GFX6-NEXT:    s_cselect_b32 s19, 1, 0
6678; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
6679; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
6680; GFX6-NEXT:    s_lshr_b64 s[4:5], s[14:15], s8
6681; GFX6-NEXT:    s_lshl_b64 s[16:17], s[14:15], s16
6682; GFX6-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8
6683; GFX6-NEXT:    s_or_b64 s[8:9], s[8:9], s[16:17]
6684; GFX6-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
6685; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
6686; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6687; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
6688; GFX6-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6689; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
6690; GFX6-NEXT:    s_cselect_b64 s[12:13], s[4:5], 0
6691; GFX6-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
6692; GFX6-NEXT:    s_or_b64 s[6:7], s[10:11], s[12:13]
6693; GFX6-NEXT:    ; return to shader part epilog
6694;
6695; GFX8-LABEL: s_fshr_v2i128:
6696; GFX8:       ; %bb.0:
6697; GFX8-NEXT:    s_movk_i32 s18, 0x7f
6698; GFX8-NEXT:    s_mov_b32 s19, 0
6699; GFX8-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6700; GFX8-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6701; GFX8-NEXT:    s_sub_i32 s30, 1, 64
6702; GFX8-NEXT:    s_sub_i32 s31, 64, 1
6703; GFX8-NEXT:    s_cmp_lt_u32 1, 64
6704; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
6705; GFX8-NEXT:    s_cmp_eq_u32 1, 0
6706; GFX8-NEXT:    s_cselect_b32 s23, 1, 0
6707; GFX8-NEXT:    s_lshr_b64 s[26:27], s[0:1], s31
6708; GFX8-NEXT:    s_lshl_b64 s[28:29], s[2:3], 1
6709; GFX8-NEXT:    s_lshl_b64 s[24:25], s[0:1], 1
6710; GFX8-NEXT:    s_or_b64 s[26:27], s[26:27], s[28:29]
6711; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s30
6712; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
6713; GFX8-NEXT:    s_cselect_b64 s[24:25], s[24:25], 0
6714; GFX8-NEXT:    s_cselect_b64 s[0:1], s[26:27], s[0:1]
6715; GFX8-NEXT:    s_cmp_lg_u32 s23, 0
6716; GFX8-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
6717; GFX8-NEXT:    s_sub_i32 s23, s16, 64
6718; GFX8-NEXT:    s_sub_i32 s17, 64, s16
6719; GFX8-NEXT:    s_cmp_lt_u32 s16, 64
6720; GFX8-NEXT:    s_cselect_b32 s28, 1, 0
6721; GFX8-NEXT:    s_cmp_eq_u32 s16, 0
6722; GFX8-NEXT:    s_cselect_b32 s29, 1, 0
6723; GFX8-NEXT:    s_lshl_b64 s[2:3], s[24:25], s16
6724; GFX8-NEXT:    s_lshr_b64 s[26:27], s[24:25], s17
6725; GFX8-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
6726; GFX8-NEXT:    s_or_b64 s[16:17], s[26:27], s[16:17]
6727; GFX8-NEXT:    s_lshl_b64 s[24:25], s[24:25], s23
6728; GFX8-NEXT:    s_cmp_lg_u32 s28, 0
6729; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
6730; GFX8-NEXT:    s_cselect_b64 s[16:17], s[16:17], s[24:25]
6731; GFX8-NEXT:    s_cmp_lg_u32 s29, 0
6732; GFX8-NEXT:    s_cselect_b64 s[16:17], s[0:1], s[16:17]
6733; GFX8-NEXT:    s_sub_i32 s26, s22, 64
6734; GFX8-NEXT:    s_sub_i32 s24, 64, s22
6735; GFX8-NEXT:    s_cmp_lt_u32 s22, 64
6736; GFX8-NEXT:    s_cselect_b32 s27, 1, 0
6737; GFX8-NEXT:    s_cmp_eq_u32 s22, 0
6738; GFX8-NEXT:    s_cselect_b32 s28, 1, 0
6739; GFX8-NEXT:    s_lshr_b64 s[0:1], s[10:11], s22
6740; GFX8-NEXT:    s_lshl_b64 s[24:25], s[10:11], s24
6741; GFX8-NEXT:    s_lshr_b64 s[22:23], s[8:9], s22
6742; GFX8-NEXT:    s_or_b64 s[22:23], s[22:23], s[24:25]
6743; GFX8-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
6744; GFX8-NEXT:    s_cmp_lg_u32 s27, 0
6745; GFX8-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
6746; GFX8-NEXT:    s_cmp_lg_u32 s28, 0
6747; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
6748; GFX8-NEXT:    s_cmp_lg_u32 s27, 0
6749; GFX8-NEXT:    s_cselect_b64 s[10:11], s[0:1], 0
6750; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
6751; GFX8-NEXT:    s_or_b64 s[2:3], s[16:17], s[10:11]
6752; GFX8-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6753; GFX8-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6754; GFX8-NEXT:    s_cmp_lt_u32 1, 64
6755; GFX8-NEXT:    s_cselect_b32 s9, 1, 0
6756; GFX8-NEXT:    s_cmp_eq_u32 1, 0
6757; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
6758; GFX8-NEXT:    s_lshr_b64 s[18:19], s[4:5], s31
6759; GFX8-NEXT:    s_lshl_b64 s[20:21], s[6:7], 1
6760; GFX8-NEXT:    s_lshl_b64 s[16:17], s[4:5], 1
6761; GFX8-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
6762; GFX8-NEXT:    s_lshl_b64 s[4:5], s[4:5], s30
6763; GFX8-NEXT:    s_cmp_lg_u32 s9, 0
6764; GFX8-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6765; GFX8-NEXT:    s_cselect_b64 s[4:5], s[18:19], s[4:5]
6766; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
6767; GFX8-NEXT:    s_cselect_b64 s[4:5], s[6:7], s[4:5]
6768; GFX8-NEXT:    s_sub_i32 s9, s10, 64
6769; GFX8-NEXT:    s_sub_i32 s11, 64, s10
6770; GFX8-NEXT:    s_cmp_lt_u32 s10, 64
6771; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
6772; GFX8-NEXT:    s_cmp_eq_u32 s10, 0
6773; GFX8-NEXT:    s_cselect_b32 s21, 1, 0
6774; GFX8-NEXT:    s_lshl_b64 s[6:7], s[16:17], s10
6775; GFX8-NEXT:    s_lshr_b64 s[18:19], s[16:17], s11
6776; GFX8-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
6777; GFX8-NEXT:    s_or_b64 s[10:11], s[18:19], s[10:11]
6778; GFX8-NEXT:    s_lshl_b64 s[16:17], s[16:17], s9
6779; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
6780; GFX8-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
6781; GFX8-NEXT:    s_cselect_b64 s[10:11], s[10:11], s[16:17]
6782; GFX8-NEXT:    s_cmp_lg_u32 s21, 0
6783; GFX8-NEXT:    s_cselect_b64 s[10:11], s[4:5], s[10:11]
6784; GFX8-NEXT:    s_sub_i32 s18, s8, 64
6785; GFX8-NEXT:    s_sub_i32 s16, 64, s8
6786; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
6787; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
6788; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
6789; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
6790; GFX8-NEXT:    s_lshr_b64 s[4:5], s[14:15], s8
6791; GFX8-NEXT:    s_lshl_b64 s[16:17], s[14:15], s16
6792; GFX8-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8
6793; GFX8-NEXT:    s_or_b64 s[8:9], s[8:9], s[16:17]
6794; GFX8-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
6795; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
6796; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6797; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
6798; GFX8-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6799; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
6800; GFX8-NEXT:    s_cselect_b64 s[12:13], s[4:5], 0
6801; GFX8-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
6802; GFX8-NEXT:    s_or_b64 s[6:7], s[10:11], s[12:13]
6803; GFX8-NEXT:    ; return to shader part epilog
6804;
6805; GFX9-LABEL: s_fshr_v2i128:
6806; GFX9:       ; %bb.0:
6807; GFX9-NEXT:    s_movk_i32 s18, 0x7f
6808; GFX9-NEXT:    s_mov_b32 s19, 0
6809; GFX9-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6810; GFX9-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6811; GFX9-NEXT:    s_sub_i32 s30, 1, 64
6812; GFX9-NEXT:    s_sub_i32 s31, 64, 1
6813; GFX9-NEXT:    s_cmp_lt_u32 1, 64
6814; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
6815; GFX9-NEXT:    s_cmp_eq_u32 1, 0
6816; GFX9-NEXT:    s_cselect_b32 s23, 1, 0
6817; GFX9-NEXT:    s_lshr_b64 s[26:27], s[0:1], s31
6818; GFX9-NEXT:    s_lshl_b64 s[28:29], s[2:3], 1
6819; GFX9-NEXT:    s_lshl_b64 s[24:25], s[0:1], 1
6820; GFX9-NEXT:    s_or_b64 s[26:27], s[26:27], s[28:29]
6821; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s30
6822; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
6823; GFX9-NEXT:    s_cselect_b64 s[24:25], s[24:25], 0
6824; GFX9-NEXT:    s_cselect_b64 s[0:1], s[26:27], s[0:1]
6825; GFX9-NEXT:    s_cmp_lg_u32 s23, 0
6826; GFX9-NEXT:    s_cselect_b64 s[0:1], s[2:3], s[0:1]
6827; GFX9-NEXT:    s_sub_i32 s23, s16, 64
6828; GFX9-NEXT:    s_sub_i32 s17, 64, s16
6829; GFX9-NEXT:    s_cmp_lt_u32 s16, 64
6830; GFX9-NEXT:    s_cselect_b32 s28, 1, 0
6831; GFX9-NEXT:    s_cmp_eq_u32 s16, 0
6832; GFX9-NEXT:    s_cselect_b32 s29, 1, 0
6833; GFX9-NEXT:    s_lshl_b64 s[2:3], s[24:25], s16
6834; GFX9-NEXT:    s_lshr_b64 s[26:27], s[24:25], s17
6835; GFX9-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
6836; GFX9-NEXT:    s_or_b64 s[16:17], s[26:27], s[16:17]
6837; GFX9-NEXT:    s_lshl_b64 s[24:25], s[24:25], s23
6838; GFX9-NEXT:    s_cmp_lg_u32 s28, 0
6839; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
6840; GFX9-NEXT:    s_cselect_b64 s[16:17], s[16:17], s[24:25]
6841; GFX9-NEXT:    s_cmp_lg_u32 s29, 0
6842; GFX9-NEXT:    s_cselect_b64 s[16:17], s[0:1], s[16:17]
6843; GFX9-NEXT:    s_sub_i32 s26, s22, 64
6844; GFX9-NEXT:    s_sub_i32 s24, 64, s22
6845; GFX9-NEXT:    s_cmp_lt_u32 s22, 64
6846; GFX9-NEXT:    s_cselect_b32 s27, 1, 0
6847; GFX9-NEXT:    s_cmp_eq_u32 s22, 0
6848; GFX9-NEXT:    s_cselect_b32 s28, 1, 0
6849; GFX9-NEXT:    s_lshr_b64 s[0:1], s[10:11], s22
6850; GFX9-NEXT:    s_lshl_b64 s[24:25], s[10:11], s24
6851; GFX9-NEXT:    s_lshr_b64 s[22:23], s[8:9], s22
6852; GFX9-NEXT:    s_or_b64 s[22:23], s[22:23], s[24:25]
6853; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
6854; GFX9-NEXT:    s_cmp_lg_u32 s27, 0
6855; GFX9-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
6856; GFX9-NEXT:    s_cmp_lg_u32 s28, 0
6857; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
6858; GFX9-NEXT:    s_cmp_lg_u32 s27, 0
6859; GFX9-NEXT:    s_cselect_b64 s[10:11], s[0:1], 0
6860; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
6861; GFX9-NEXT:    s_or_b64 s[2:3], s[16:17], s[10:11]
6862; GFX9-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6863; GFX9-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6864; GFX9-NEXT:    s_cmp_lt_u32 1, 64
6865; GFX9-NEXT:    s_cselect_b32 s9, 1, 0
6866; GFX9-NEXT:    s_cmp_eq_u32 1, 0
6867; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
6868; GFX9-NEXT:    s_lshr_b64 s[18:19], s[4:5], s31
6869; GFX9-NEXT:    s_lshl_b64 s[20:21], s[6:7], 1
6870; GFX9-NEXT:    s_lshl_b64 s[16:17], s[4:5], 1
6871; GFX9-NEXT:    s_or_b64 s[18:19], s[18:19], s[20:21]
6872; GFX9-NEXT:    s_lshl_b64 s[4:5], s[4:5], s30
6873; GFX9-NEXT:    s_cmp_lg_u32 s9, 0
6874; GFX9-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6875; GFX9-NEXT:    s_cselect_b64 s[4:5], s[18:19], s[4:5]
6876; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
6877; GFX9-NEXT:    s_cselect_b64 s[4:5], s[6:7], s[4:5]
6878; GFX9-NEXT:    s_sub_i32 s9, s10, 64
6879; GFX9-NEXT:    s_sub_i32 s11, 64, s10
6880; GFX9-NEXT:    s_cmp_lt_u32 s10, 64
6881; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
6882; GFX9-NEXT:    s_cmp_eq_u32 s10, 0
6883; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
6884; GFX9-NEXT:    s_lshl_b64 s[6:7], s[16:17], s10
6885; GFX9-NEXT:    s_lshr_b64 s[18:19], s[16:17], s11
6886; GFX9-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
6887; GFX9-NEXT:    s_or_b64 s[10:11], s[18:19], s[10:11]
6888; GFX9-NEXT:    s_lshl_b64 s[16:17], s[16:17], s9
6889; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
6890; GFX9-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
6891; GFX9-NEXT:    s_cselect_b64 s[10:11], s[10:11], s[16:17]
6892; GFX9-NEXT:    s_cmp_lg_u32 s21, 0
6893; GFX9-NEXT:    s_cselect_b64 s[10:11], s[4:5], s[10:11]
6894; GFX9-NEXT:    s_sub_i32 s18, s8, 64
6895; GFX9-NEXT:    s_sub_i32 s16, 64, s8
6896; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
6897; GFX9-NEXT:    s_cselect_b32 s19, 1, 0
6898; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
6899; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
6900; GFX9-NEXT:    s_lshr_b64 s[4:5], s[14:15], s8
6901; GFX9-NEXT:    s_lshl_b64 s[16:17], s[14:15], s16
6902; GFX9-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8
6903; GFX9-NEXT:    s_or_b64 s[8:9], s[8:9], s[16:17]
6904; GFX9-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
6905; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
6906; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6907; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
6908; GFX9-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6909; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
6910; GFX9-NEXT:    s_cselect_b64 s[12:13], s[4:5], 0
6911; GFX9-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
6912; GFX9-NEXT:    s_or_b64 s[6:7], s[10:11], s[12:13]
6913; GFX9-NEXT:    ; return to shader part epilog
6914;
6915; GFX10-LABEL: s_fshr_v2i128:
6916; GFX10:       ; %bb.0:
6917; GFX10-NEXT:    s_movk_i32 s18, 0x7f
6918; GFX10-NEXT:    s_mov_b32 s19, 0
6919; GFX10-NEXT:    s_sub_i32 s30, 1, 64
6920; GFX10-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6921; GFX10-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6922; GFX10-NEXT:    s_sub_i32 s31, 64, 1
6923; GFX10-NEXT:    s_cmp_lt_u32 1, 64
6924; GFX10-NEXT:    s_mov_b32 s62, s10
6925; GFX10-NEXT:    s_cselect_b32 s17, 1, 0
6926; GFX10-NEXT:    s_cmp_eq_u32 1, 0
6927; GFX10-NEXT:    s_mov_b32 s63, s11
6928; GFX10-NEXT:    s_cselect_b32 s23, 1, 0
6929; GFX10-NEXT:    s_lshr_b64 s[24:25], s[0:1], s31
6930; GFX10-NEXT:    s_lshl_b64 s[26:27], s[2:3], 1
6931; GFX10-NEXT:    s_lshl_b64 s[28:29], s[0:1], 1
6932; GFX10-NEXT:    s_or_b64 s[24:25], s[24:25], s[26:27]
6933; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s30
6934; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
6935; GFX10-NEXT:    s_cselect_b64 s[26:27], s[28:29], 0
6936; GFX10-NEXT:    s_cselect_b64 s[0:1], s[24:25], s[0:1]
6937; GFX10-NEXT:    s_cmp_lg_u32 s23, 0
6938; GFX10-NEXT:    s_cselect_b64 s[46:47], s[2:3], s[0:1]
6939; GFX10-NEXT:    s_sub_i32 s23, s16, 64
6940; GFX10-NEXT:    s_sub_i32 s2, 64, s16
6941; GFX10-NEXT:    s_cmp_lt_u32 s16, 64
6942; GFX10-NEXT:    s_cselect_b32 s28, 1, 0
6943; GFX10-NEXT:    s_cmp_eq_u32 s16, 0
6944; GFX10-NEXT:    s_cselect_b32 s29, 1, 0
6945; GFX10-NEXT:    s_lshl_b64 s[24:25], s[46:47], s16
6946; GFX10-NEXT:    s_lshr_b64 s[2:3], s[26:27], s2
6947; GFX10-NEXT:    s_lshl_b64 s[16:17], s[26:27], s16
6948; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[24:25]
6949; GFX10-NEXT:    s_lshl_b64 s[24:25], s[26:27], s23
6950; GFX10-NEXT:    s_cmp_lg_u32 s28, 0
6951; GFX10-NEXT:    s_cselect_b64 s[78:79], s[16:17], 0
6952; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[24:25]
6953; GFX10-NEXT:    s_cmp_lg_u32 s29, 0
6954; GFX10-NEXT:    s_cselect_b64 s[2:3], s[46:47], s[2:3]
6955; GFX10-NEXT:    s_sub_i32 s26, s22, 64
6956; GFX10-NEXT:    s_sub_i32 s23, 64, s22
6957; GFX10-NEXT:    s_cmp_lt_u32 s22, 64
6958; GFX10-NEXT:    s_cselect_b32 s27, 1, 0
6959; GFX10-NEXT:    s_cmp_eq_u32 s22, 0
6960; GFX10-NEXT:    s_cselect_b32 s28, 1, 0
6961; GFX10-NEXT:    s_lshr_b64 s[0:1], s[8:9], s22
6962; GFX10-NEXT:    s_lshl_b64 s[24:25], s[62:63], s23
6963; GFX10-NEXT:    s_lshr_b64 s[22:23], s[62:63], s22
6964; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[24:25]
6965; GFX10-NEXT:    s_lshr_b64 s[10:11], s[62:63], s26
6966; GFX10-NEXT:    s_cmp_lg_u32 s27, 0
6967; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[10:11]
6968; GFX10-NEXT:    s_cmp_lg_u32 s28, 0
6969; GFX10-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6970; GFX10-NEXT:    s_cmp_lg_u32 s27, 0
6971; GFX10-NEXT:    s_cselect_b64 s[8:9], s[22:23], 0
6972; GFX10-NEXT:    s_or_b64 s[0:1], s[78:79], s[0:1]
6973; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
6974; GFX10-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6975; GFX10-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6976; GFX10-NEXT:    s_cmp_lt_u32 1, 64
6977; GFX10-NEXT:    s_cselect_b32 s9, 1, 0
6978; GFX10-NEXT:    s_cmp_eq_u32 1, 0
6979; GFX10-NEXT:    s_cselect_b32 s11, 1, 0
6980; GFX10-NEXT:    s_lshr_b64 s[16:17], s[4:5], s31
6981; GFX10-NEXT:    s_lshl_b64 s[18:19], s[6:7], 1
6982; GFX10-NEXT:    s_lshl_b64 s[20:21], s[4:5], 1
6983; GFX10-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
6984; GFX10-NEXT:    s_lshl_b64 s[4:5], s[4:5], s30
6985; GFX10-NEXT:    s_cmp_lg_u32 s9, 0
6986; GFX10-NEXT:    s_cselect_b64 s[18:19], s[20:21], 0
6987; GFX10-NEXT:    s_cselect_b64 s[4:5], s[16:17], s[4:5]
6988; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6989; GFX10-NEXT:    s_cselect_b64 s[4:5], s[6:7], s[4:5]
6990; GFX10-NEXT:    s_sub_i32 s9, s10, 64
6991; GFX10-NEXT:    s_sub_i32 s6, 64, s10
6992; GFX10-NEXT:    s_cmp_lt_u32 s10, 64
6993; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
6994; GFX10-NEXT:    s_cmp_eq_u32 s10, 0
6995; GFX10-NEXT:    s_cselect_b32 s21, 1, 0
6996; GFX10-NEXT:    s_lshl_b64 s[16:17], s[4:5], s10
6997; GFX10-NEXT:    s_lshr_b64 s[6:7], s[18:19], s6
6998; GFX10-NEXT:    s_lshl_b64 s[10:11], s[18:19], s10
6999; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[16:17]
7000; GFX10-NEXT:    s_lshl_b64 s[16:17], s[18:19], s9
7001; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
7002; GFX10-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
7003; GFX10-NEXT:    s_cselect_b64 s[6:7], s[6:7], s[16:17]
7004; GFX10-NEXT:    s_cmp_lg_u32 s21, 0
7005; GFX10-NEXT:    s_cselect_b64 s[6:7], s[4:5], s[6:7]
7006; GFX10-NEXT:    s_sub_i32 s18, s8, 64
7007; GFX10-NEXT:    s_sub_i32 s9, 64, s8
7008; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
7009; GFX10-NEXT:    s_cselect_b32 s19, 1, 0
7010; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
7011; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
7012; GFX10-NEXT:    s_lshr_b64 s[4:5], s[12:13], s8
7013; GFX10-NEXT:    s_lshl_b64 s[16:17], s[14:15], s9
7014; GFX10-NEXT:    s_lshr_b64 s[8:9], s[14:15], s8
7015; GFX10-NEXT:    s_or_b64 s[4:5], s[4:5], s[16:17]
7016; GFX10-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
7017; GFX10-NEXT:    s_cmp_lg_u32 s19, 0
7018; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[14:15]
7019; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
7020; GFX10-NEXT:    s_cselect_b64 s[4:5], s[12:13], s[4:5]
7021; GFX10-NEXT:    s_cmp_lg_u32 s19, 0
7022; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
7023; GFX10-NEXT:    s_or_b64 s[4:5], s[10:11], s[4:5]
7024; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
7025; GFX10-NEXT:    ; return to shader part epilog
7026  %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
7027  ret <2 x i128> %result
7028}
7029
7030define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) {
7031; GFX6-LABEL: v_fshr_v2i128:
7032; GFX6:       ; %bb.0:
7033; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7034; GFX6-NEXT:    s_sub_i32 s6, 64, 1
7035; GFX6-NEXT:    s_sub_i32 s7, 1, 64
7036; GFX6-NEXT:    s_cmp_lt_u32 1, 64
7037; GFX6-NEXT:    v_lshr_b64 v[17:18], v[0:1], s6
7038; GFX6-NEXT:    v_lshl_b64 v[21:22], v[2:3], 1
7039; GFX6-NEXT:    s_cselect_b32 s4, 1, 0
7040; GFX6-NEXT:    s_cmp_eq_u32 1, 0
7041; GFX6-NEXT:    v_or_b32_e32 v19, v17, v21
7042; GFX6-NEXT:    v_or_b32_e32 v21, v18, v22
7043; GFX6-NEXT:    s_cselect_b32 s5, 1, 0
7044; GFX6-NEXT:    v_lshl_b64 v[17:18], v[0:1], 1
7045; GFX6-NEXT:    s_and_b32 s4, 1, s4
7046; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s7
7047; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7048; GFX6-NEXT:    s_and_b32 s4, 1, s5
7049; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v19, vcc
7050; GFX6-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, s4
7051; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[4:5]
7052; GFX6-NEXT:    s_movk_i32 s8, 0x7f
7053; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v16
7054; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v21, vcc
7055; GFX6-NEXT:    v_and_b32_e32 v19, s8, v2
7056; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[4:5]
7057; GFX6-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
7058; GFX6-NEXT:    v_cndmask_b32_e32 v18, 0, v18, vcc
7059; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v19
7060; GFX6-NEXT:    v_lshr_b64 v[2:3], v[17:18], v2
7061; GFX6-NEXT:    v_lshl_b64 v[21:22], v[0:1], v19
7062; GFX6-NEXT:    v_and_b32_e32 v25, s8, v16
7063; GFX6-NEXT:    v_or_b32_e32 v23, v2, v21
7064; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v25
7065; GFX6-NEXT:    v_or_b32_e32 v24, v3, v22
7066; GFX6-NEXT:    v_lshl_b64 v[2:3], v[10:11], v2
7067; GFX6-NEXT:    v_lshr_b64 v[21:22], v[8:9], v25
7068; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v19
7069; GFX6-NEXT:    v_or_b32_e32 v21, v21, v2
7070; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 64, v19
7071; GFX6-NEXT:    v_or_b32_e32 v22, v22, v3
7072; GFX6-NEXT:    v_lshl_b64 v[2:3], v[17:18], v2
7073; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v19
7074; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v23, vcc
7075; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v24, vcc
7076; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v0, s[4:5]
7077; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v1, s[4:5]
7078; GFX6-NEXT:    v_subrev_i32_e64 v0, s[4:5], 64, v25
7079; GFX6-NEXT:    v_lshl_b64 v[16:17], v[17:18], v19
7080; GFX6-NEXT:    v_lshr_b64 v[0:1], v[10:11], v0
7081; GFX6-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v25
7082; GFX6-NEXT:    v_cndmask_b32_e32 v16, 0, v16, vcc
7083; GFX6-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
7084; GFX6-NEXT:    v_cndmask_b32_e64 v18, v0, v21, s[4:5]
7085; GFX6-NEXT:    v_cndmask_b32_e64 v19, v1, v22, s[4:5]
7086; GFX6-NEXT:    v_lshr_b64 v[0:1], v[10:11], v25
7087; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v25
7088; GFX6-NEXT:    v_cndmask_b32_e32 v8, v18, v8, vcc
7089; GFX6-NEXT:    v_cndmask_b32_e64 v10, 0, v0, s[4:5]
7090; GFX6-NEXT:    v_or_b32_e32 v0, v16, v8
7091; GFX6-NEXT:    v_cndmask_b32_e64 v11, 0, v1, s[4:5]
7092; GFX6-NEXT:    v_cndmask_b32_e32 v9, v19, v9, vcc
7093; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v20
7094; GFX6-NEXT:    v_or_b32_e32 v1, v17, v9
7095; GFX6-NEXT:    v_and_b32_e32 v17, s8, v8
7096; GFX6-NEXT:    s_cmp_lt_u32 1, 64
7097; GFX6-NEXT:    v_or_b32_e32 v2, v2, v10
7098; GFX6-NEXT:    v_or_b32_e32 v3, v3, v11
7099; GFX6-NEXT:    v_lshr_b64 v[8:9], v[4:5], s6
7100; GFX6-NEXT:    v_lshl_b64 v[10:11], v[6:7], 1
7101; GFX6-NEXT:    s_cselect_b32 s4, 1, 0
7102; GFX6-NEXT:    s_cmp_eq_u32 1, 0
7103; GFX6-NEXT:    s_cselect_b32 s5, 1, 0
7104; GFX6-NEXT:    s_and_b32 s4, 1, s4
7105; GFX6-NEXT:    v_or_b32_e32 v10, v8, v10
7106; GFX6-NEXT:    v_or_b32_e32 v11, v9, v11
7107; GFX6-NEXT:    v_lshl_b64 v[8:9], v[4:5], 1
7108; GFX6-NEXT:    v_lshl_b64 v[4:5], v[4:5], s7
7109; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7110; GFX6-NEXT:    s_and_b32 s4, 1, s5
7111; GFX6-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
7112; GFX6-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
7113; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
7114; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
7115; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7116; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
7117; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7118; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 64, v17
7119; GFX6-NEXT:    v_lshr_b64 v[6:7], v[8:9], v6
7120; GFX6-NEXT:    v_lshl_b64 v[10:11], v[4:5], v17
7121; GFX6-NEXT:    v_subrev_i32_e32 v18, vcc, 64, v17
7122; GFX6-NEXT:    v_or_b32_e32 v10, v6, v10
7123; GFX6-NEXT:    v_or_b32_e32 v11, v7, v11
7124; GFX6-NEXT:    v_lshl_b64 v[6:7], v[8:9], v17
7125; GFX6-NEXT:    v_lshl_b64 v[8:9], v[8:9], v18
7126; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
7127; GFX6-NEXT:    v_and_b32_e32 v16, s8, v20
7128; GFX6-NEXT:    v_cndmask_b32_e32 v18, 0, v6, vcc
7129; GFX6-NEXT:    v_cndmask_b32_e32 v19, 0, v7, vcc
7130; GFX6-NEXT:    v_cndmask_b32_e32 v6, v8, v10, vcc
7131; GFX6-NEXT:    v_cndmask_b32_e32 v7, v9, v11, vcc
7132; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v17
7133; GFX6-NEXT:    v_cndmask_b32_e32 v8, v6, v4, vcc
7134; GFX6-NEXT:    v_cndmask_b32_e32 v9, v7, v5, vcc
7135; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 64, v16
7136; GFX6-NEXT:    v_lshr_b64 v[4:5], v[12:13], v16
7137; GFX6-NEXT:    v_lshl_b64 v[6:7], v[14:15], v6
7138; GFX6-NEXT:    v_subrev_i32_e32 v10, vcc, 64, v16
7139; GFX6-NEXT:    v_or_b32_e32 v11, v4, v6
7140; GFX6-NEXT:    v_or_b32_e32 v17, v5, v7
7141; GFX6-NEXT:    v_lshr_b64 v[6:7], v[14:15], v10
7142; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
7143; GFX6-NEXT:    v_lshr_b64 v[4:5], v[14:15], v16
7144; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
7145; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v16
7146; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v17, vcc
7147; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
7148; GFX6-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
7149; GFX6-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
7150; GFX6-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
7151; GFX6-NEXT:    v_or_b32_e32 v4, v18, v6
7152; GFX6-NEXT:    v_or_b32_e32 v5, v19, v7
7153; GFX6-NEXT:    v_or_b32_e32 v6, v8, v10
7154; GFX6-NEXT:    v_or_b32_e32 v7, v9, v11
7155; GFX6-NEXT:    s_setpc_b64 s[30:31]
7156;
7157; GFX8-LABEL: v_fshr_v2i128:
7158; GFX8:       ; %bb.0:
7159; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7160; GFX8-NEXT:    s_sub_i32 s6, 64, 1
7161; GFX8-NEXT:    s_sub_i32 s7, 1, 64
7162; GFX8-NEXT:    s_cmp_lt_u32 1, 64
7163; GFX8-NEXT:    v_lshrrev_b64 v[17:18], s6, v[0:1]
7164; GFX8-NEXT:    v_lshlrev_b64 v[21:22], 1, v[2:3]
7165; GFX8-NEXT:    s_cselect_b32 s4, 1, 0
7166; GFX8-NEXT:    s_cmp_eq_u32 1, 0
7167; GFX8-NEXT:    v_or_b32_e32 v19, v17, v21
7168; GFX8-NEXT:    v_or_b32_e32 v21, v18, v22
7169; GFX8-NEXT:    s_cselect_b32 s5, 1, 0
7170; GFX8-NEXT:    v_lshlrev_b64 v[17:18], 1, v[0:1]
7171; GFX8-NEXT:    s_and_b32 s4, 1, s4
7172; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s7, v[0:1]
7173; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7174; GFX8-NEXT:    s_and_b32 s4, 1, s5
7175; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v19, vcc
7176; GFX8-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, s4
7177; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[4:5]
7178; GFX8-NEXT:    s_movk_i32 s8, 0x7f
7179; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v16
7180; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v21, vcc
7181; GFX8-NEXT:    v_and_b32_e32 v19, s8, v2
7182; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[4:5]
7183; GFX8-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
7184; GFX8-NEXT:    v_cndmask_b32_e32 v18, 0, v18, vcc
7185; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v19
7186; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v2, v[17:18]
7187; GFX8-NEXT:    v_lshlrev_b64 v[21:22], v19, v[0:1]
7188; GFX8-NEXT:    v_and_b32_e32 v25, s8, v16
7189; GFX8-NEXT:    v_or_b32_e32 v23, v2, v21
7190; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v25
7191; GFX8-NEXT:    v_or_b32_e32 v24, v3, v22
7192; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, v[10:11]
7193; GFX8-NEXT:    v_lshrrev_b64 v[21:22], v25, v[8:9]
7194; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v19
7195; GFX8-NEXT:    v_or_b32_e32 v21, v21, v2
7196; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 64, v19
7197; GFX8-NEXT:    v_or_b32_e32 v22, v22, v3
7198; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, v[17:18]
7199; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v19
7200; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v23, vcc
7201; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v24, vcc
7202; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, v0, s[4:5]
7203; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, v1, s[4:5]
7204; GFX8-NEXT:    v_subrev_u32_e64 v0, s[4:5], 64, v25
7205; GFX8-NEXT:    v_lshlrev_b64 v[16:17], v19, v[17:18]
7206; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v0, v[10:11]
7207; GFX8-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v25
7208; GFX8-NEXT:    v_cndmask_b32_e32 v16, 0, v16, vcc
7209; GFX8-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
7210; GFX8-NEXT:    v_cndmask_b32_e64 v18, v0, v21, s[4:5]
7211; GFX8-NEXT:    v_cndmask_b32_e64 v19, v1, v22, s[4:5]
7212; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v25, v[10:11]
7213; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v25
7214; GFX8-NEXT:    v_cndmask_b32_e32 v8, v18, v8, vcc
7215; GFX8-NEXT:    v_cndmask_b32_e64 v10, 0, v0, s[4:5]
7216; GFX8-NEXT:    v_or_b32_e32 v0, v16, v8
7217; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, v1, s[4:5]
7218; GFX8-NEXT:    v_cndmask_b32_e32 v9, v19, v9, vcc
7219; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v20
7220; GFX8-NEXT:    v_or_b32_e32 v1, v17, v9
7221; GFX8-NEXT:    v_and_b32_e32 v17, s8, v8
7222; GFX8-NEXT:    s_cmp_lt_u32 1, 64
7223; GFX8-NEXT:    v_or_b32_e32 v2, v2, v10
7224; GFX8-NEXT:    v_or_b32_e32 v3, v3, v11
7225; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s6, v[4:5]
7226; GFX8-NEXT:    v_lshlrev_b64 v[10:11], 1, v[6:7]
7227; GFX8-NEXT:    s_cselect_b32 s4, 1, 0
7228; GFX8-NEXT:    s_cmp_eq_u32 1, 0
7229; GFX8-NEXT:    s_cselect_b32 s5, 1, 0
7230; GFX8-NEXT:    s_and_b32 s4, 1, s4
7231; GFX8-NEXT:    v_or_b32_e32 v10, v8, v10
7232; GFX8-NEXT:    v_or_b32_e32 v11, v9, v11
7233; GFX8-NEXT:    v_lshlrev_b64 v[8:9], 1, v[4:5]
7234; GFX8-NEXT:    v_lshlrev_b64 v[4:5], s7, v[4:5]
7235; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7236; GFX8-NEXT:    s_and_b32 s4, 1, s5
7237; GFX8-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
7238; GFX8-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
7239; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
7240; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
7241; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7242; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
7243; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7244; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 64, v17
7245; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v6, v[8:9]
7246; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v17, v[4:5]
7247; GFX8-NEXT:    v_subrev_u32_e32 v18, vcc, 64, v17
7248; GFX8-NEXT:    v_or_b32_e32 v10, v6, v10
7249; GFX8-NEXT:    v_or_b32_e32 v11, v7, v11
7250; GFX8-NEXT:    v_lshlrev_b64 v[6:7], v17, v[8:9]
7251; GFX8-NEXT:    v_lshlrev_b64 v[8:9], v18, v[8:9]
7252; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
7253; GFX8-NEXT:    v_and_b32_e32 v16, s8, v20
7254; GFX8-NEXT:    v_cndmask_b32_e32 v18, 0, v6, vcc
7255; GFX8-NEXT:    v_cndmask_b32_e32 v19, 0, v7, vcc
7256; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v10, vcc
7257; GFX8-NEXT:    v_cndmask_b32_e32 v7, v9, v11, vcc
7258; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v17
7259; GFX8-NEXT:    v_cndmask_b32_e32 v8, v6, v4, vcc
7260; GFX8-NEXT:    v_cndmask_b32_e32 v9, v7, v5, vcc
7261; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 64, v16
7262; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v16, v[12:13]
7263; GFX8-NEXT:    v_lshlrev_b64 v[6:7], v6, v[14:15]
7264; GFX8-NEXT:    v_subrev_u32_e32 v10, vcc, 64, v16
7265; GFX8-NEXT:    v_or_b32_e32 v11, v4, v6
7266; GFX8-NEXT:    v_or_b32_e32 v17, v5, v7
7267; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v10, v[14:15]
7268; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
7269; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v16, v[14:15]
7270; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
7271; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v16
7272; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v17, vcc
7273; GFX8-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
7274; GFX8-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
7275; GFX8-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
7276; GFX8-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
7277; GFX8-NEXT:    v_or_b32_e32 v4, v18, v6
7278; GFX8-NEXT:    v_or_b32_e32 v5, v19, v7
7279; GFX8-NEXT:    v_or_b32_e32 v6, v8, v10
7280; GFX8-NEXT:    v_or_b32_e32 v7, v9, v11
7281; GFX8-NEXT:    s_setpc_b64 s[30:31]
7282;
7283; GFX9-LABEL: v_fshr_v2i128:
7284; GFX9:       ; %bb.0:
7285; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7286; GFX9-NEXT:    s_sub_i32 s6, 64, 1
7287; GFX9-NEXT:    s_sub_i32 s7, 1, 64
7288; GFX9-NEXT:    s_cmp_lt_u32 1, 64
7289; GFX9-NEXT:    v_lshrrev_b64 v[17:18], s6, v[0:1]
7290; GFX9-NEXT:    v_lshlrev_b64 v[21:22], 1, v[2:3]
7291; GFX9-NEXT:    s_cselect_b32 s4, 1, 0
7292; GFX9-NEXT:    s_cmp_eq_u32 1, 0
7293; GFX9-NEXT:    v_or_b32_e32 v19, v17, v21
7294; GFX9-NEXT:    v_or_b32_e32 v21, v18, v22
7295; GFX9-NEXT:    s_cselect_b32 s5, 1, 0
7296; GFX9-NEXT:    v_lshlrev_b64 v[17:18], 1, v[0:1]
7297; GFX9-NEXT:    s_and_b32 s4, 1, s4
7298; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s7, v[0:1]
7299; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7300; GFX9-NEXT:    s_and_b32 s4, 1, s5
7301; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v19, vcc
7302; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, s4
7303; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[4:5]
7304; GFX9-NEXT:    s_movk_i32 s8, 0x7f
7305; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v16
7306; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v21, vcc
7307; GFX9-NEXT:    v_and_b32_e32 v19, s8, v2
7308; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[4:5]
7309; GFX9-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
7310; GFX9-NEXT:    v_cndmask_b32_e32 v18, 0, v18, vcc
7311; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v19
7312; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v2, v[17:18]
7313; GFX9-NEXT:    v_lshlrev_b64 v[21:22], v19, v[0:1]
7314; GFX9-NEXT:    v_and_b32_e32 v25, s8, v16
7315; GFX9-NEXT:    v_or_b32_e32 v23, v2, v21
7316; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v25
7317; GFX9-NEXT:    v_or_b32_e32 v24, v3, v22
7318; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, v[10:11]
7319; GFX9-NEXT:    v_lshrrev_b64 v[21:22], v25, v[8:9]
7320; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v19
7321; GFX9-NEXT:    v_or_b32_e32 v21, v21, v2
7322; GFX9-NEXT:    v_subrev_u32_e32 v2, 64, v19
7323; GFX9-NEXT:    v_or_b32_e32 v22, v22, v3
7324; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, v[17:18]
7325; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v19
7326; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v23, vcc
7327; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v24, vcc
7328; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, v0, s[4:5]
7329; GFX9-NEXT:    v_subrev_u32_e32 v0, 64, v25
7330; GFX9-NEXT:    v_lshlrev_b64 v[16:17], v19, v[17:18]
7331; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v1, s[4:5]
7332; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v0, v[10:11]
7333; GFX9-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v25
7334; GFX9-NEXT:    v_cndmask_b32_e32 v16, 0, v16, vcc
7335; GFX9-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
7336; GFX9-NEXT:    v_cndmask_b32_e64 v18, v0, v21, s[4:5]
7337; GFX9-NEXT:    v_cndmask_b32_e64 v19, v1, v22, s[4:5]
7338; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v25, v[10:11]
7339; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v25
7340; GFX9-NEXT:    v_cndmask_b32_e32 v8, v18, v8, vcc
7341; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, v0, s[4:5]
7342; GFX9-NEXT:    v_or_b32_e32 v0, v16, v8
7343; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, v1, s[4:5]
7344; GFX9-NEXT:    v_cndmask_b32_e32 v9, v19, v9, vcc
7345; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v20
7346; GFX9-NEXT:    v_or_b32_e32 v1, v17, v9
7347; GFX9-NEXT:    v_and_b32_e32 v17, s8, v8
7348; GFX9-NEXT:    s_cmp_lt_u32 1, 64
7349; GFX9-NEXT:    v_or_b32_e32 v2, v2, v10
7350; GFX9-NEXT:    v_or_b32_e32 v3, v3, v11
7351; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s6, v[4:5]
7352; GFX9-NEXT:    v_lshlrev_b64 v[10:11], 1, v[6:7]
7353; GFX9-NEXT:    s_cselect_b32 s4, 1, 0
7354; GFX9-NEXT:    s_cmp_eq_u32 1, 0
7355; GFX9-NEXT:    s_cselect_b32 s5, 1, 0
7356; GFX9-NEXT:    s_and_b32 s4, 1, s4
7357; GFX9-NEXT:    v_or_b32_e32 v10, v8, v10
7358; GFX9-NEXT:    v_or_b32_e32 v11, v9, v11
7359; GFX9-NEXT:    v_lshlrev_b64 v[8:9], 1, v[4:5]
7360; GFX9-NEXT:    v_lshlrev_b64 v[4:5], s7, v[4:5]
7361; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7362; GFX9-NEXT:    s_and_b32 s4, 1, s5
7363; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
7364; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v9, vcc
7365; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
7366; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
7367; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7368; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
7369; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7370; GFX9-NEXT:    v_sub_u32_e32 v6, 64, v17
7371; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v6, v[8:9]
7372; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v17, v[4:5]
7373; GFX9-NEXT:    v_subrev_u32_e32 v18, 64, v17
7374; GFX9-NEXT:    v_or_b32_e32 v10, v6, v10
7375; GFX9-NEXT:    v_or_b32_e32 v11, v7, v11
7376; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v17, v[8:9]
7377; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v18, v[8:9]
7378; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
7379; GFX9-NEXT:    v_and_b32_e32 v16, s8, v20
7380; GFX9-NEXT:    v_cndmask_b32_e32 v18, 0, v6, vcc
7381; GFX9-NEXT:    v_cndmask_b32_e32 v19, 0, v7, vcc
7382; GFX9-NEXT:    v_cndmask_b32_e32 v6, v8, v10, vcc
7383; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v11, vcc
7384; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v17
7385; GFX9-NEXT:    v_cndmask_b32_e32 v8, v6, v4, vcc
7386; GFX9-NEXT:    v_sub_u32_e32 v6, 64, v16
7387; GFX9-NEXT:    v_cndmask_b32_e32 v9, v7, v5, vcc
7388; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v16, v[12:13]
7389; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v6, v[14:15]
7390; GFX9-NEXT:    v_subrev_u32_e32 v10, 64, v16
7391; GFX9-NEXT:    v_or_b32_e32 v11, v4, v6
7392; GFX9-NEXT:    v_or_b32_e32 v17, v5, v7
7393; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v10, v[14:15]
7394; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
7395; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v16, v[14:15]
7396; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
7397; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v16
7398; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v17, vcc
7399; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
7400; GFX9-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
7401; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
7402; GFX9-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
7403; GFX9-NEXT:    v_or_b32_e32 v4, v18, v6
7404; GFX9-NEXT:    v_or_b32_e32 v5, v19, v7
7405; GFX9-NEXT:    v_or_b32_e32 v6, v8, v10
7406; GFX9-NEXT:    v_or_b32_e32 v7, v9, v11
7407; GFX9-NEXT:    s_setpc_b64 s[30:31]
7408;
7409; GFX10-LABEL: v_fshr_v2i128:
7410; GFX10:       ; %bb.0:
7411; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7412; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
7413; GFX10-NEXT:    s_sub_i32 s5, 64, 1
7414; GFX10-NEXT:    s_sub_i32 s6, 1, 64
7415; GFX10-NEXT:    s_cmp_lt_u32 1, 64
7416; GFX10-NEXT:    v_lshrrev_b64 v[27:28], s5, v[0:1]
7417; GFX10-NEXT:    v_lshlrev_b64 v[21:22], 1, v[2:3]
7418; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
7419; GFX10-NEXT:    s_cmp_eq_u32 1, 0
7420; GFX10-NEXT:    v_lshlrev_b64 v[23:24], 1, v[0:1]
7421; GFX10-NEXT:    s_cselect_b32 s8, 1, 0
7422; GFX10-NEXT:    s_and_b32 s4, 1, vcc_lo
7423; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s6, v[0:1]
7424; GFX10-NEXT:    v_xor_b32_e32 v19, -1, v16
7425; GFX10-NEXT:    v_or_b32_e32 v21, v27, v21
7426; GFX10-NEXT:    v_or_b32_e32 v18, v28, v22
7427; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
7428; GFX10-NEXT:    s_movk_i32 s7, 0x7f
7429; GFX10-NEXT:    s_and_b32 s8, 1, s8
7430; GFX10-NEXT:    v_and_b32_e32 v31, s7, v19
7431; GFX10-NEXT:    v_cndmask_b32_e32 v17, 0, v23, vcc_lo
7432; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v18, s4
7433; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v21, s4
7434; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
7435; GFX10-NEXT:    v_cndmask_b32_e32 v18, 0, v24, vcc_lo
7436; GFX10-NEXT:    v_sub_nc_u32_e32 v19, 64, v31
7437; GFX10-NEXT:    v_and_b32_e32 v26, s7, v16
7438; GFX10-NEXT:    v_subrev_nc_u32_e32 v16, 64, v31
7439; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s4
7440; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s4
7441; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v19, v[17:18]
7442; GFX10-NEXT:    v_mov_b32_e32 v35, v10
7443; GFX10-NEXT:    v_mov_b32_e32 v36, v11
7444; GFX10-NEXT:    v_sub_nc_u32_e32 v25, 64, v26
7445; GFX10-NEXT:    v_lshlrev_b64 v[21:22], v31, v[0:1]
7446; GFX10-NEXT:    v_lshlrev_b64 v[23:24], v31, v[17:18]
7447; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v31
7448; GFX10-NEXT:    v_subrev_nc_u32_e32 v29, 64, v26
7449; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v26
7450; GFX10-NEXT:    v_lshrrev_b64 v[27:28], s5, v[4:5]
7451; GFX10-NEXT:    v_or_b32_e32 v21, v2, v21
7452; GFX10-NEXT:    v_or_b32_e32 v22, v3, v22
7453; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v16, v[17:18]
7454; GFX10-NEXT:    v_lshlrev_b64 v[18:19], v25, v[35:36]
7455; GFX10-NEXT:    v_lshrrev_b64 v[16:17], v26, v[8:9]
7456; GFX10-NEXT:    v_cndmask_b32_e32 v23, 0, v23, vcc_lo
7457; GFX10-NEXT:    v_cndmask_b32_e32 v39, 0, v24, vcc_lo
7458; GFX10-NEXT:    s_cmp_lt_u32 1, 64
7459; GFX10-NEXT:    v_cndmask_b32_e32 v21, v2, v21, vcc_lo
7460; GFX10-NEXT:    v_cndmask_b32_e32 v22, v3, v22, vcc_lo
7461; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v29, v[35:36]
7462; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v31
7463; GFX10-NEXT:    v_or_b32_e32 v16, v16, v18
7464; GFX10-NEXT:    v_or_b32_e32 v17, v17, v19
7465; GFX10-NEXT:    v_lshlrev_b64 v[10:11], 1, v[6:7]
7466; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
7467; GFX10-NEXT:    v_cndmask_b32_e32 v18, v21, v0, vcc_lo
7468; GFX10-NEXT:    v_cndmask_b32_e32 v31, v22, v1, vcc_lo
7469; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v16, s4
7470; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v26
7471; GFX10-NEXT:    s_cmp_eq_u32 1, 0
7472; GFX10-NEXT:    v_cndmask_b32_e64 v19, v3, v17, s4
7473; GFX10-NEXT:    s_cselect_b32 s8, 1, 0
7474; GFX10-NEXT:    v_lshlrev_b64 v[16:17], 1, v[4:5]
7475; GFX10-NEXT:    v_lshlrev_b64 v[4:5], s6, v[4:5]
7476; GFX10-NEXT:    s_and_b32 s6, 1, s5
7477; GFX10-NEXT:    v_cndmask_b32_e32 v21, v2, v8, vcc_lo
7478; GFX10-NEXT:    v_xor_b32_e32 v25, -1, v20
7479; GFX10-NEXT:    v_or_b32_e32 v2, v27, v10
7480; GFX10-NEXT:    v_or_b32_e32 v3, v28, v11
7481; GFX10-NEXT:    v_cmp_ne_u32_e64 s6, 0, s6
7482; GFX10-NEXT:    s_and_b32 s8, 1, s8
7483; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v26, v[35:36]
7484; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, v16, s5
7485; GFX10-NEXT:    v_cndmask_b32_e32 v16, v19, v9, vcc_lo
7486; GFX10-NEXT:    v_cndmask_b32_e64 v11, v4, v2, s6
7487; GFX10-NEXT:    v_and_b32_e32 v30, s7, v25
7488; GFX10-NEXT:    v_cndmask_b32_e64 v4, v5, v3, s6
7489; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s8
7490; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, v17, s5
7491; GFX10-NEXT:    v_cndmask_b32_e64 v19, 0, v0, s4
7492; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 64, v30
7493; GFX10-NEXT:    v_or_b32_e32 v0, v23, v21
7494; GFX10-NEXT:    v_cndmask_b32_e32 v3, v11, v6, vcc_lo
7495; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc_lo
7496; GFX10-NEXT:    v_and_b32_e32 v23, s7, v20
7497; GFX10-NEXT:    v_lshrrev_b64 v[5:6], v2, v[8:9]
7498; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 64, v30
7499; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, v1, s4
7500; GFX10-NEXT:    v_lshlrev_b64 v[10:11], v30, v[3:4]
7501; GFX10-NEXT:    v_sub_nc_u32_e32 v20, 64, v23
7502; GFX10-NEXT:    v_or_b32_e32 v1, v39, v16
7503; GFX10-NEXT:    v_or_b32_e32 v2, v18, v19
7504; GFX10-NEXT:    v_lshlrev_b64 v[16:17], v30, v[8:9]
7505; GFX10-NEXT:    v_lshrrev_b64 v[18:19], v23, v[12:13]
7506; GFX10-NEXT:    v_or_b32_e32 v10, v5, v10
7507; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, 64, v23
7508; GFX10-NEXT:    v_lshlrev_b64 v[20:21], v20, v[14:15]
7509; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v30
7510; GFX10-NEXT:    v_lshlrev_b64 v[7:8], v7, v[8:9]
7511; GFX10-NEXT:    v_or_b32_e32 v9, v6, v11
7512; GFX10-NEXT:    v_lshrrev_b64 v[34:35], v5, v[14:15]
7513; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v23
7514; GFX10-NEXT:    v_cndmask_b32_e32 v11, 0, v16, vcc_lo
7515; GFX10-NEXT:    v_or_b32_e32 v16, v18, v20
7516; GFX10-NEXT:    v_or_b32_e32 v18, v19, v21
7517; GFX10-NEXT:    v_cndmask_b32_e32 v10, v7, v10, vcc_lo
7518; GFX10-NEXT:    v_cndmask_b32_e32 v9, v8, v9, vcc_lo
7519; GFX10-NEXT:    v_lshrrev_b64 v[7:8], v23, v[14:15]
7520; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v30
7521; GFX10-NEXT:    v_cndmask_b32_e64 v5, v34, v16, s4
7522; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v23
7523; GFX10-NEXT:    v_cndmask_b32_e64 v6, v35, v18, s4
7524; GFX10-NEXT:    v_cndmask_b32_e32 v14, 0, v17, vcc_lo
7525; GFX10-NEXT:    v_cndmask_b32_e64 v15, v10, v3, s6
7526; GFX10-NEXT:    v_cndmask_b32_e64 v9, v9, v4, s6
7527; GFX10-NEXT:    v_cndmask_b32_e64 v4, v5, v12, s5
7528; GFX10-NEXT:    v_cndmask_b32_e64 v5, v6, v13, s5
7529; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, v7, s4
7530; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, v8, s4
7531; GFX10-NEXT:    v_or_b32_e32 v3, v31, v26
7532; GFX10-NEXT:    v_or_b32_e32 v4, v11, v4
7533; GFX10-NEXT:    v_or_b32_e32 v5, v14, v5
7534; GFX10-NEXT:    v_or_b32_e32 v6, v15, v6
7535; GFX10-NEXT:    v_or_b32_e32 v7, v9, v7
7536; GFX10-NEXT:    s_setpc_b64 s[30:31]
7537  %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
7538  ret <2 x i128> %result
7539}
7540
7541declare i7 @llvm.fshr.i7(i7, i7, i7) #0
7542declare i8 @llvm.fshr.i8(i8, i8, i8) #0
7543declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0
7544declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>) #0
7545
7546declare i16 @llvm.fshr.i16(i16, i16, i16) #0
7547declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>) #0
7548declare <3 x i16> @llvm.fshr.v3i16(<3 x i16>, <3 x i16>, <3 x i16>) #0
7549declare <4 x i16> @llvm.fshr.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) #0
7550declare <5 x i16> @llvm.fshr.v5i16(<5 x i16>, <5 x i16>, <5 x i16>) #0
7551declare <6 x i16> @llvm.fshr.v6i16(<6 x i16>, <6 x i16>, <6 x i16>) #0
7552declare <8 x i16> @llvm.fshr.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) #0
7553
7554declare i24 @llvm.fshr.i24(i24, i24, i24) #0
7555declare <2 x i24> @llvm.fshr.v2i24(<2 x i24>, <2 x i24>, <2 x i24>) #0
7556
7557declare i32 @llvm.fshr.i32(i32, i32, i32) #0
7558declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) #0
7559declare <3 x i32> @llvm.fshr.v3i32(<3 x i32>, <3 x i32>, <3 x i32>) #0
7560declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #0
7561declare <5 x i32> @llvm.fshr.v5i32(<5 x i32>, <5 x i32>, <5 x i32>) #0
7562declare <16 x i32> @llvm.fshr.v16i32(<16 x i32>, <16 x i32>, <16 x i32>) #0
7563
7564declare i48 @llvm.fshr.i48(i48, i48, i48) #0
7565
7566declare i64 @llvm.fshr.i64(i64, i64, i64) #0
7567declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) #0
7568
7569declare i128 @llvm.fshr.i128(i128, i128, i128) #0
7570declare <2 x i128> @llvm.fshr.v2i128(<2 x i128>, <2 x i128>, <2 x i128>) #0
7571
7572attributes #0 = { nounwind readnone speculatable willreturn }
7573