1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
6
7define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
8; GFX6-LABEL: s_fshr_i7:
9; GFX6:       ; %bb.0:
10; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
11; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
12; GFX6-NEXT:    s_and_b32 s2, s2, 0x7f
13; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
14; GFX6-NEXT:    s_and_b32 s1, s1, 0x7f
15; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
16; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
17; GFX6-NEXT:    v_mul_lo_u32 v1, -7, v0
18; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
19; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
20; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
21; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 7
22; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
23; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 7, v0
24; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
25; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
26; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 7, v0
27; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
28; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
29; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 6, v0
30; GFX6-NEXT:    v_and_b32_e32 v0, 0x7f, v0
31; GFX6-NEXT:    v_and_b32_e32 v1, 0x7f, v1
32; GFX6-NEXT:    v_lshl_b32_e32 v1, s0, v1
33; GFX6-NEXT:    v_lshr_b32_e32 v0, s1, v0
34; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
35; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
36; GFX6-NEXT:    ; return to shader part epilog
37;
38; GFX8-LABEL: s_fshr_i7:
39; GFX8:       ; %bb.0:
40; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
41; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
42; GFX8-NEXT:    s_and_b32 s2, s2, 0x7f
43; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
44; GFX8-NEXT:    s_and_b32 s1, s1, 0x7f
45; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
46; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
47; GFX8-NEXT:    v_mul_lo_u32 v1, -7, v0
48; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
49; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
50; GFX8-NEXT:    v_mul_hi_u32 v0, s2, v0
51; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 7
52; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
53; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 7, v0
54; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
55; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
56; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 7, v0
57; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
58; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
59; GFX8-NEXT:    v_sub_u16_e32 v1, 6, v0
60; GFX8-NEXT:    v_and_b32_e32 v0, 0x7f, v0
61; GFX8-NEXT:    v_and_b32_e32 v1, 0x7f, v1
62; GFX8-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
63; GFX8-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
64; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
65; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
66; GFX8-NEXT:    ; return to shader part epilog
67;
68; GFX9-LABEL: s_fshr_i7:
69; GFX9:       ; %bb.0:
70; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
71; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
72; GFX9-NEXT:    s_and_b32 s2, s2, 0x7f
73; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
74; GFX9-NEXT:    s_and_b32 s1, s1, 0x7f
75; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
76; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
77; GFX9-NEXT:    v_mul_lo_u32 v1, -7, v0
78; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
79; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
80; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
81; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 7
82; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
83; GFX9-NEXT:    v_subrev_u32_e32 v1, 7, v0
84; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
85; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
86; GFX9-NEXT:    v_subrev_u32_e32 v1, 7, v0
87; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
88; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
89; GFX9-NEXT:    v_sub_u16_e32 v1, 6, v0
90; GFX9-NEXT:    v_and_b32_e32 v0, 0x7f, v0
91; GFX9-NEXT:    v_and_b32_e32 v1, 0x7f, v1
92; GFX9-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
93; GFX9-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
94; GFX9-NEXT:    v_or_b32_e32 v0, v1, v0
95; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
96; GFX9-NEXT:    ; return to shader part epilog
97;
98; GFX10-LABEL: s_fshr_i7:
99; GFX10:       ; %bb.0:
100; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
101; GFX10-NEXT:    s_and_b32 s2, s2, 0x7f
102; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
103; GFX10-NEXT:    s_and_b32 s1, s1, 0x7f
104; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
105; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
106; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
107; GFX10-NEXT:    v_mul_lo_u32 v1, -7, v0
108; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
109; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
110; GFX10-NEXT:    v_mul_hi_u32 v0, s2, v0
111; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 7
112; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
113; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
114; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
115; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
116; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
117; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
118; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
119; GFX10-NEXT:    v_sub_nc_u16 v1, 6, v0
120; GFX10-NEXT:    v_and_b32_e32 v0, 0x7f, v0
121; GFX10-NEXT:    v_and_b32_e32 v1, 0x7f, v1
122; GFX10-NEXT:    v_lshrrev_b16 v0, v0, s1
123; GFX10-NEXT:    v_lshlrev_b16 v1, v1, s0
124; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
125; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
126; GFX10-NEXT:    ; return to shader part epilog
127  %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
128  ret i7 %result
129}
130
131define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
132; GFX6-LABEL: v_fshr_i7:
133; GFX6:       ; %bb.0:
134; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
135; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
136; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
137; GFX6-NEXT:    v_and_b32_e32 v2, 0x7f, v2
138; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
139; GFX6-NEXT:    v_and_b32_e32 v1, 0x7f, v1
140; GFX6-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
141; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
142; GFX6-NEXT:    v_mul_lo_u32 v4, -7, v3
143; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
144; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
145; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
146; GFX6-NEXT:    v_mul_lo_u32 v3, v3, 7
147; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
148; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 7, v2
149; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
150; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
151; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 7, v2
152; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
153; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
154; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 6, v2
155; GFX6-NEXT:    v_and_b32_e32 v2, 0x7f, v2
156; GFX6-NEXT:    v_and_b32_e32 v3, 0x7f, v3
157; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
158; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
159; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
160; GFX6-NEXT:    s_setpc_b64 s[30:31]
161;
162; GFX8-LABEL: v_fshr_i7:
163; GFX8:       ; %bb.0:
164; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
165; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
166; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
167; GFX8-NEXT:    v_and_b32_e32 v2, 0x7f, v2
168; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
169; GFX8-NEXT:    v_and_b32_e32 v1, 0x7f, v1
170; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
171; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
172; GFX8-NEXT:    v_mul_lo_u32 v4, -7, v3
173; GFX8-NEXT:    v_mul_hi_u32 v4, v3, v4
174; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v4
175; GFX8-NEXT:    v_mul_hi_u32 v3, v2, v3
176; GFX8-NEXT:    v_mul_lo_u32 v3, v3, 7
177; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
178; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 7, v2
179; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
180; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
181; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 7, v2
182; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
183; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
184; GFX8-NEXT:    v_sub_u16_e32 v3, 6, v2
185; GFX8-NEXT:    v_and_b32_e32 v2, 0x7f, v2
186; GFX8-NEXT:    v_and_b32_e32 v3, 0x7f, v3
187; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
188; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
189; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
190; GFX8-NEXT:    s_setpc_b64 s[30:31]
191;
192; GFX9-LABEL: v_fshr_i7:
193; GFX9:       ; %bb.0:
194; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
195; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
196; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
197; GFX9-NEXT:    v_and_b32_e32 v2, 0x7f, v2
198; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
199; GFX9-NEXT:    v_and_b32_e32 v1, 0x7f, v1
200; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
201; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
202; GFX9-NEXT:    v_mul_lo_u32 v4, -7, v3
203; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
204; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
205; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
206; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 7
207; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
208; GFX9-NEXT:    v_subrev_u32_e32 v3, 7, v2
209; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
210; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
211; GFX9-NEXT:    v_subrev_u32_e32 v3, 7, v2
212; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
213; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
214; GFX9-NEXT:    v_sub_u16_e32 v3, 6, v2
215; GFX9-NEXT:    v_and_b32_e32 v2, 0x7f, v2
216; GFX9-NEXT:    v_and_b32_e32 v3, 0x7f, v3
217; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
218; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
219; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
220; GFX9-NEXT:    s_setpc_b64 s[30:31]
221;
222; GFX10-LABEL: v_fshr_i7:
223; GFX10:       ; %bb.0:
224; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
225; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
226; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
227; GFX10-NEXT:    v_and_b32_e32 v2, 0x7f, v2
228; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
229; GFX10-NEXT:    v_and_b32_e32 v1, 0x7f, v1
230; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
231; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
232; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
233; GFX10-NEXT:    v_mul_lo_u32 v4, -7, v3
234; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
235; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
236; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
237; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 7
238; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
239; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
240; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
241; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
242; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
243; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
244; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
245; GFX10-NEXT:    v_sub_nc_u16 v3, 6, v2
246; GFX10-NEXT:    v_and_b32_e32 v2, 0x7f, v2
247; GFX10-NEXT:    v_and_b32_e32 v3, 0x7f, v3
248; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
249; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v0
250; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
251; GFX10-NEXT:    s_setpc_b64 s[30:31]
252  %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
253  ret i7 %result
254}
255
256define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
257; GFX6-LABEL: s_fshr_i8:
258; GFX6:       ; %bb.0:
259; GFX6-NEXT:    s_and_b32 s3, s2, 7
260; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
261; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
262; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
263; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
264; GFX6-NEXT:    s_lshr_b32 s1, s1, s3
265; GFX6-NEXT:    s_or_b32 s0, s0, s1
266; GFX6-NEXT:    ; return to shader part epilog
267;
268; GFX8-LABEL: s_fshr_i8:
269; GFX8:       ; %bb.0:
270; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
271; GFX8-NEXT:    s_and_b32 s3, s2, 7
272; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
273; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
274; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
275; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
276; GFX8-NEXT:    s_lshr_b32 s1, s1, s3
277; GFX8-NEXT:    s_or_b32 s0, s0, s1
278; GFX8-NEXT:    ; return to shader part epilog
279;
280; GFX9-LABEL: s_fshr_i8:
281; GFX9:       ; %bb.0:
282; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
283; GFX9-NEXT:    s_and_b32 s3, s2, 7
284; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
285; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
286; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
287; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
288; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
289; GFX9-NEXT:    s_or_b32 s0, s0, s1
290; GFX9-NEXT:    ; return to shader part epilog
291;
292; GFX10-LABEL: s_fshr_i8:
293; GFX10:       ; %bb.0:
294; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
295; GFX10-NEXT:    s_and_b32 s3, s2, 7
296; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
297; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
298; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
299; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
300; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
301; GFX10-NEXT:    s_or_b32 s0, s0, s1
302; GFX10-NEXT:    ; return to shader part epilog
303  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 %amt)
304  ret i8 %result
305}
306
307define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
308; GFX6-LABEL: v_fshr_i8:
309; GFX6:       ; %bb.0:
310; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
311; GFX6-NEXT:    v_and_b32_e32 v3, 7, v2
312; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
313; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
314; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
315; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
316; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
317; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v3, v1
318; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
319; GFX6-NEXT:    s_setpc_b64 s[30:31]
320;
321; GFX8-LABEL: v_fshr_i8:
322; GFX8:       ; %bb.0:
323; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
324; GFX8-NEXT:    v_and_b32_e32 v3, 7, v2
325; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
326; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
327; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
328; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
329; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
330; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
331; GFX8-NEXT:    s_setpc_b64 s[30:31]
332;
333; GFX9-LABEL: v_fshr_i8:
334; GFX9:       ; %bb.0:
335; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
336; GFX9-NEXT:    v_and_b32_e32 v3, 7, v2
337; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
338; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
339; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
340; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
341; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
342; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
343; GFX9-NEXT:    s_setpc_b64 s[30:31]
344;
345; GFX10-LABEL: v_fshr_i8:
346; GFX10:       ; %bb.0:
347; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
348; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
349; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
350; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
351; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
352; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
353; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
354; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
355; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v0
356; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
357; GFX10-NEXT:    s_setpc_b64 s[30:31]
358  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 %amt)
359  ret i8 %result
360}
361
362define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
363; GFX6-LABEL: s_fshr_i8_4:
364; GFX6:       ; %bb.0:
365; GFX6-NEXT:    s_lshl_b32 s0, s0, 4
366; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x40004
367; GFX6-NEXT:    s_or_b32 s0, s0, s1
368; GFX6-NEXT:    ; return to shader part epilog
369;
370; GFX8-LABEL: s_fshr_i8_4:
371; GFX8:       ; %bb.0:
372; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
373; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
374; GFX8-NEXT:    s_lshl_b32 s0, s0, 4
375; GFX8-NEXT:    s_lshr_b32 s1, s1, 4
376; GFX8-NEXT:    s_or_b32 s0, s0, s1
377; GFX8-NEXT:    ; return to shader part epilog
378;
379; GFX9-LABEL: s_fshr_i8_4:
380; GFX9:       ; %bb.0:
381; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
382; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
383; GFX9-NEXT:    s_lshl_b32 s0, s0, 4
384; GFX9-NEXT:    s_lshr_b32 s1, s1, 4
385; GFX9-NEXT:    s_or_b32 s0, s0, s1
386; GFX9-NEXT:    ; return to shader part epilog
387;
388; GFX10-LABEL: s_fshr_i8_4:
389; GFX10:       ; %bb.0:
390; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
391; GFX10-NEXT:    s_lshl_b32 s0, s0, 4
392; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
393; GFX10-NEXT:    s_lshr_b32 s1, s1, 4
394; GFX10-NEXT:    s_or_b32 s0, s0, s1
395; GFX10-NEXT:    ; return to shader part epilog
396  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
397  ret i8 %result
398}
399
400define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
401; GFX6-LABEL: v_fshr_i8_4:
402; GFX6:       ; %bb.0:
403; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
404; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
405; GFX6-NEXT:    v_bfe_u32 v1, v1, 4, 4
406; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
407; GFX6-NEXT:    s_setpc_b64 s[30:31]
408;
409; GFX8-LABEL: v_fshr_i8_4:
410; GFX8:       ; %bb.0:
411; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
412; GFX8-NEXT:    v_mov_b32_e32 v2, 4
413; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
414; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
415; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
416; GFX8-NEXT:    s_setpc_b64 s[30:31]
417;
418; GFX9-LABEL: v_fshr_i8_4:
419; GFX9:       ; %bb.0:
420; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
421; GFX9-NEXT:    s_mov_b32 s4, 4
422; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
423; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
424; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
425; GFX9-NEXT:    s_setpc_b64 s[30:31]
426;
427; GFX10-LABEL: v_fshr_i8_4:
428; GFX10:       ; %bb.0:
429; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
430; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
431; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
432; GFX10-NEXT:    v_lshlrev_b16 v0, 4, v0
433; GFX10-NEXT:    v_lshrrev_b16 v1, 4, v1
434; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
435; GFX10-NEXT:    s_setpc_b64 s[30:31]
436  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
437  ret i8 %result
438}
439
440define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
441; GFX6-LABEL: s_fshr_i8_5:
442; GFX6:       ; %bb.0:
443; GFX6-NEXT:    s_lshl_b32 s0, s0, 3
444; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x30005
445; GFX6-NEXT:    s_or_b32 s0, s0, s1
446; GFX6-NEXT:    ; return to shader part epilog
447;
448; GFX8-LABEL: s_fshr_i8_5:
449; GFX8:       ; %bb.0:
450; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
451; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
452; GFX8-NEXT:    s_lshl_b32 s0, s0, 3
453; GFX8-NEXT:    s_lshr_b32 s1, s1, 5
454; GFX8-NEXT:    s_or_b32 s0, s0, s1
455; GFX8-NEXT:    ; return to shader part epilog
456;
457; GFX9-LABEL: s_fshr_i8_5:
458; GFX9:       ; %bb.0:
459; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
460; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
461; GFX9-NEXT:    s_lshl_b32 s0, s0, 3
462; GFX9-NEXT:    s_lshr_b32 s1, s1, 5
463; GFX9-NEXT:    s_or_b32 s0, s0, s1
464; GFX9-NEXT:    ; return to shader part epilog
465;
466; GFX10-LABEL: s_fshr_i8_5:
467; GFX10:       ; %bb.0:
468; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
469; GFX10-NEXT:    s_lshl_b32 s0, s0, 3
470; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
471; GFX10-NEXT:    s_lshr_b32 s1, s1, 5
472; GFX10-NEXT:    s_or_b32 s0, s0, s1
473; GFX10-NEXT:    ; return to shader part epilog
474  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
475  ret i8 %result
476}
477
478define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
479; GFX6-LABEL: v_fshr_i8_5:
480; GFX6:       ; %bb.0:
481; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
482; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
483; GFX6-NEXT:    v_bfe_u32 v1, v1, 5, 3
484; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
485; GFX6-NEXT:    s_setpc_b64 s[30:31]
486;
487; GFX8-LABEL: v_fshr_i8_5:
488; GFX8:       ; %bb.0:
489; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
490; GFX8-NEXT:    v_mov_b32_e32 v2, 5
491; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 3, v0
492; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
493; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
494; GFX8-NEXT:    s_setpc_b64 s[30:31]
495;
496; GFX9-LABEL: v_fshr_i8_5:
497; GFX9:       ; %bb.0:
498; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
499; GFX9-NEXT:    v_mov_b32_e32 v2, 5
500; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 3, v0
501; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
502; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
503; GFX9-NEXT:    s_setpc_b64 s[30:31]
504;
505; GFX10-LABEL: v_fshr_i8_5:
506; GFX10:       ; %bb.0:
507; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
508; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
509; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
510; GFX10-NEXT:    v_lshlrev_b16 v0, 3, v0
511; GFX10-NEXT:    v_lshrrev_b16 v1, 5, v1
512; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
513; GFX10-NEXT:    s_setpc_b64 s[30:31]
514  %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
515  ret i8 %result
516}
517
518define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 inreg %amt.arg) {
519; GFX6-LABEL: s_fshr_v2i8:
520; GFX6:       ; %bb.0:
521; GFX6-NEXT:    s_lshr_b32 s3, s0, 8
522; GFX6-NEXT:    s_lshr_b32 s4, s2, 8
523; GFX6-NEXT:    s_and_b32 s5, s2, 7
524; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
525; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
526; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
527; GFX6-NEXT:    s_and_b32 s2, s1, 0xff
528; GFX6-NEXT:    s_lshr_b32 s2, s2, s5
529; GFX6-NEXT:    s_or_b32 s0, s0, s2
530; GFX6-NEXT:    s_and_b32 s2, s4, 7
531; GFX6-NEXT:    s_andn2_b32 s4, 7, s4
532; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
533; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x80008
534; GFX6-NEXT:    s_lshl_b32 s3, s3, s4
535; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
536; GFX6-NEXT:    s_or_b32 s1, s3, s1
537; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
538; GFX6-NEXT:    s_and_b32 s0, s0, 0xff
539; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
540; GFX6-NEXT:    s_or_b32 s0, s0, s1
541; GFX6-NEXT:    ; return to shader part epilog
542;
543; GFX8-LABEL: s_fshr_v2i8:
544; GFX8:       ; %bb.0:
545; GFX8-NEXT:    s_lshr_b32 s3, s0, 8
546; GFX8-NEXT:    s_lshr_b32 s4, s1, 8
547; GFX8-NEXT:    s_lshr_b32 s5, s2, 8
548; GFX8-NEXT:    s_and_b32 s6, s2, 7
549; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
550; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
551; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
552; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
553; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
554; GFX8-NEXT:    s_andn2_b32 s2, 7, s5
555; GFX8-NEXT:    s_lshl_b32 s3, s3, 1
556; GFX8-NEXT:    s_lshr_b32 s1, s1, s6
557; GFX8-NEXT:    s_lshl_b32 s2, s3, s2
558; GFX8-NEXT:    s_and_b32 s3, s4, 0xff
559; GFX8-NEXT:    s_or_b32 s0, s0, s1
560; GFX8-NEXT:    s_and_b32 s1, s5, 7
561; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
562; GFX8-NEXT:    s_lshr_b32 s1, s3, s1
563; GFX8-NEXT:    s_or_b32 s1, s2, s1
564; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
565; GFX8-NEXT:    s_bfe_u32 s2, 8, 0x100000
566; GFX8-NEXT:    s_and_b32 s0, s0, 0xff
567; GFX8-NEXT:    s_lshl_b32 s1, s1, s2
568; GFX8-NEXT:    s_or_b32 s0, s0, s1
569; GFX8-NEXT:    ; return to shader part epilog
570;
571; GFX9-LABEL: s_fshr_v2i8:
572; GFX9:       ; %bb.0:
573; GFX9-NEXT:    s_lshr_b32 s3, s0, 8
574; GFX9-NEXT:    s_lshr_b32 s4, s1, 8
575; GFX9-NEXT:    s_lshr_b32 s5, s2, 8
576; GFX9-NEXT:    s_and_b32 s6, s2, 7
577; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
578; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
579; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
580; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
581; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
582; GFX9-NEXT:    s_andn2_b32 s2, 7, s5
583; GFX9-NEXT:    s_lshl_b32 s3, s3, 1
584; GFX9-NEXT:    s_lshr_b32 s1, s1, s6
585; GFX9-NEXT:    s_lshl_b32 s2, s3, s2
586; GFX9-NEXT:    s_and_b32 s3, s4, 0xff
587; GFX9-NEXT:    s_or_b32 s0, s0, s1
588; GFX9-NEXT:    s_and_b32 s1, s5, 7
589; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
590; GFX9-NEXT:    s_lshr_b32 s1, s3, s1
591; GFX9-NEXT:    s_or_b32 s1, s2, s1
592; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
593; GFX9-NEXT:    s_bfe_u32 s2, 8, 0x100000
594; GFX9-NEXT:    s_and_b32 s0, s0, 0xff
595; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
596; GFX9-NEXT:    s_or_b32 s0, s0, s1
597; GFX9-NEXT:    ; return to shader part epilog
598;
599; GFX10-LABEL: s_fshr_v2i8:
600; GFX10:       ; %bb.0:
601; GFX10-NEXT:    s_lshr_b32 s4, s1, 8
602; GFX10-NEXT:    s_lshr_b32 s3, s0, 8
603; GFX10-NEXT:    s_lshr_b32 s5, s2, 8
604; GFX10-NEXT:    s_and_b32 s6, s2, 7
605; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
606; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
607; GFX10-NEXT:    s_and_b32 s4, s4, 0xff
608; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
609; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
610; GFX10-NEXT:    s_and_b32 s2, s5, 7
611; GFX10-NEXT:    s_andn2_b32 s5, 7, s5
612; GFX10-NEXT:    s_lshl_b32 s3, s3, 1
613; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
614; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
615; GFX10-NEXT:    s_lshl_b32 s3, s3, s5
616; GFX10-NEXT:    s_lshr_b32 s2, s4, s2
617; GFX10-NEXT:    s_lshr_b32 s1, s1, s6
618; GFX10-NEXT:    s_or_b32 s2, s3, s2
619; GFX10-NEXT:    s_or_b32 s0, s0, s1
620; GFX10-NEXT:    s_and_b32 s1, s2, 0xff
621; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
622; GFX10-NEXT:    s_and_b32 s0, s0, 0xff
623; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
624; GFX10-NEXT:    s_or_b32 s0, s0, s1
625; GFX10-NEXT:    ; return to shader part epilog
626  %lhs = bitcast i16 %lhs.arg to <2 x i8>
627  %rhs = bitcast i16 %rhs.arg to <2 x i8>
628  %amt = bitcast i16 %amt.arg to <2 x i8>
629  %result = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %lhs, <2 x i8> %rhs, <2 x i8> %amt)
630  %cast.result = bitcast <2 x i8> %result to i16
631  ret i16 %cast.result
632}
633
634define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
635; GFX6-LABEL: v_fshr_v2i8:
636; GFX6:       ; %bb.0:
637; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
638; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 8, v2
639; GFX6-NEXT:    v_and_b32_e32 v5, 7, v2
640; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
641; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
642; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
643; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
644; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
645; GFX6-NEXT:    v_and_b32_e32 v2, 0xff, v1
646; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v5, v2
647; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
648; GFX6-NEXT:    v_and_b32_e32 v2, 7, v4
649; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
650; GFX6-NEXT:    v_and_b32_e32 v4, 7, v4
651; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
652; GFX6-NEXT:    v_bfe_u32 v1, v1, 8, 8
653; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v4, v3
654; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
655; GFX6-NEXT:    v_or_b32_e32 v1, v3, v1
656; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
657; GFX6-NEXT:    v_and_b32_e32 v0, 0xff, v0
658; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
659; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
660; GFX6-NEXT:    s_setpc_b64 s[30:31]
661;
662; GFX8-LABEL: v_fshr_v2i8:
663; GFX8:       ; %bb.0:
664; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
665; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
666; GFX8-NEXT:    v_and_b32_e32 v6, 7, v2
667; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
668; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
669; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
670; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
671; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
672; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
673; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
674; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v5
675; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
676; GFX8-NEXT:    v_and_b32_e32 v1, 7, v5
677; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
678; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
679; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v2, v3
680; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
681; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
682; GFX8-NEXT:    v_and_b32_e32 v1, 0xff, v1
683; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
684; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
685; GFX8-NEXT:    s_setpc_b64 s[30:31]
686;
687; GFX9-LABEL: v_fshr_v2i8:
688; GFX9:       ; %bb.0:
689; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
690; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
691; GFX9-NEXT:    v_and_b32_e32 v6, 7, v2
692; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
693; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
694; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
695; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
696; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
697; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
698; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
699; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v5
700; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
701; GFX9-NEXT:    v_and_b32_e32 v1, 7, v5
702; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
703; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
704; GFX9-NEXT:    v_lshlrev_b16_e32 v2, v2, v3
705; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
706; GFX9-NEXT:    v_or_b32_e32 v1, v2, v1
707; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v1
708; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
709; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
710; GFX9-NEXT:    s_setpc_b64 s[30:31]
711;
712; GFX10-LABEL: v_fshr_v2i8:
713; GFX10:       ; %bb.0:
714; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
715; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
716; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v2
717; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 8, v0
718; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
719; GFX10-NEXT:    v_and_b32_e32 v7, 7, v2
720; GFX10-NEXT:    v_xor_b32_e32 v2, -1, v2
721; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v3
722; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
723; GFX10-NEXT:    v_lshlrev_b16 v4, 1, v4
724; GFX10-NEXT:    v_and_b32_e32 v5, 0xff, v5
725; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
726; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
727; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
728; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
729; GFX10-NEXT:    v_lshrrev_b16 v3, v3, v5
730; GFX10-NEXT:    s_movk_i32 s4, 0xff
731; GFX10-NEXT:    v_lshlrev_b16 v4, v6, v4
732; GFX10-NEXT:    v_lshrrev_b16 v1, v7, v1
733; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
734; GFX10-NEXT:    v_or_b32_e32 v2, v4, v3
735; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
736; GFX10-NEXT:    v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
737; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
738; GFX10-NEXT:    s_setpc_b64 s[30:31]
739  %lhs = bitcast i16 %lhs.arg to <2 x i8>
740  %rhs = bitcast i16 %rhs.arg to <2 x i8>
741  %amt = bitcast i16 %amt.arg to <2 x i8>
742  %result = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %lhs, <2 x i8> %rhs, <2 x i8> %amt)
743  %cast.result = bitcast <2 x i8> %result to i16
744  ret i16 %cast.result
745}
746
747define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 inreg %amt.arg) {
748; GFX6-LABEL: s_fshr_v4i8:
749; GFX6:       ; %bb.0:
750; GFX6-NEXT:    s_lshr_b32 s3, s0, 8
751; GFX6-NEXT:    s_lshr_b32 s4, s0, 16
752; GFX6-NEXT:    s_lshr_b32 s5, s0, 24
753; GFX6-NEXT:    s_lshr_b32 s7, s2, 8
754; GFX6-NEXT:    s_lshr_b32 s8, s2, 16
755; GFX6-NEXT:    s_lshr_b32 s9, s2, 24
756; GFX6-NEXT:    s_and_b32 s10, s2, 7
757; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
758; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
759; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
760; GFX6-NEXT:    s_and_b32 s2, s1, 0xff
761; GFX6-NEXT:    s_lshr_b32 s2, s2, s10
762; GFX6-NEXT:    s_or_b32 s0, s0, s2
763; GFX6-NEXT:    s_and_b32 s2, s7, 7
764; GFX6-NEXT:    s_andn2_b32 s7, 7, s7
765; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
766; GFX6-NEXT:    s_lshl_b32 s3, s3, s7
767; GFX6-NEXT:    s_bfe_u32 s7, s1, 0x80008
768; GFX6-NEXT:    s_lshr_b32 s2, s7, s2
769; GFX6-NEXT:    s_lshr_b32 s6, s1, 24
770; GFX6-NEXT:    s_or_b32 s2, s3, s2
771; GFX6-NEXT:    s_and_b32 s3, s8, 7
772; GFX6-NEXT:    s_andn2_b32 s7, 7, s8
773; GFX6-NEXT:    s_lshl_b32 s4, s4, 1
774; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x80010
775; GFX6-NEXT:    s_lshl_b32 s4, s4, s7
776; GFX6-NEXT:    s_lshr_b32 s1, s1, s3
777; GFX6-NEXT:    s_or_b32 s1, s4, s1
778; GFX6-NEXT:    s_and_b32 s3, s9, 7
779; GFX6-NEXT:    s_andn2_b32 s4, 7, s9
780; GFX6-NEXT:    s_lshl_b32 s5, s5, 1
781; GFX6-NEXT:    s_and_b32 s2, s2, 0xff
782; GFX6-NEXT:    s_lshl_b32 s4, s5, s4
783; GFX6-NEXT:    s_lshr_b32 s3, s6, s3
784; GFX6-NEXT:    s_and_b32 s0, s0, 0xff
785; GFX6-NEXT:    s_lshl_b32 s2, s2, 8
786; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
787; GFX6-NEXT:    s_or_b32 s3, s4, s3
788; GFX6-NEXT:    s_or_b32 s0, s0, s2
789; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
790; GFX6-NEXT:    s_or_b32 s0, s0, s1
791; GFX6-NEXT:    s_and_b32 s1, s3, 0xff
792; GFX6-NEXT:    s_lshl_b32 s1, s1, 24
793; GFX6-NEXT:    s_or_b32 s0, s0, s1
794; GFX6-NEXT:    ; return to shader part epilog
795;
796; GFX8-LABEL: s_fshr_v4i8:
797; GFX8:       ; %bb.0:
798; GFX8-NEXT:    s_lshr_b32 s3, s0, 8
799; GFX8-NEXT:    s_lshr_b32 s4, s0, 16
800; GFX8-NEXT:    s_lshr_b32 s5, s0, 24
801; GFX8-NEXT:    s_lshr_b32 s6, s1, 8
802; GFX8-NEXT:    s_lshr_b32 s7, s1, 16
803; GFX8-NEXT:    s_lshr_b32 s8, s1, 24
804; GFX8-NEXT:    s_lshr_b32 s9, s2, 8
805; GFX8-NEXT:    s_lshr_b32 s10, s2, 16
806; GFX8-NEXT:    s_lshr_b32 s11, s2, 24
807; GFX8-NEXT:    s_and_b32 s12, s2, 7
808; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
809; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
810; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
811; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
812; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
813; GFX8-NEXT:    s_andn2_b32 s2, 7, s9
814; GFX8-NEXT:    s_lshl_b32 s3, s3, 1
815; GFX8-NEXT:    s_lshr_b32 s1, s1, s12
816; GFX8-NEXT:    s_lshl_b32 s2, s3, s2
817; GFX8-NEXT:    s_and_b32 s3, s6, 0xff
818; GFX8-NEXT:    s_or_b32 s0, s0, s1
819; GFX8-NEXT:    s_and_b32 s1, s9, 7
820; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
821; GFX8-NEXT:    s_lshr_b32 s1, s3, s1
822; GFX8-NEXT:    s_andn2_b32 s3, 7, s10
823; GFX8-NEXT:    s_lshl_b32 s4, s4, 1
824; GFX8-NEXT:    s_lshl_b32 s3, s4, s3
825; GFX8-NEXT:    s_and_b32 s4, s7, 0xff
826; GFX8-NEXT:    s_or_b32 s1, s2, s1
827; GFX8-NEXT:    s_and_b32 s2, s10, 7
828; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
829; GFX8-NEXT:    s_lshr_b32 s2, s4, s2
830; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
831; GFX8-NEXT:    s_or_b32 s2, s3, s2
832; GFX8-NEXT:    s_and_b32 s3, s11, 7
833; GFX8-NEXT:    s_andn2_b32 s4, 7, s11
834; GFX8-NEXT:    s_lshl_b32 s5, s5, 1
835; GFX8-NEXT:    s_and_b32 s0, s0, 0xff
836; GFX8-NEXT:    s_lshl_b32 s1, s1, 8
837; GFX8-NEXT:    s_lshl_b32 s4, s5, s4
838; GFX8-NEXT:    s_lshr_b32 s3, s8, s3
839; GFX8-NEXT:    s_or_b32 s0, s0, s1
840; GFX8-NEXT:    s_and_b32 s1, s2, 0xff
841; GFX8-NEXT:    s_or_b32 s3, s4, s3
842; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
843; GFX8-NEXT:    s_or_b32 s0, s0, s1
844; GFX8-NEXT:    s_and_b32 s1, s3, 0xff
845; GFX8-NEXT:    s_lshl_b32 s1, s1, 24
846; GFX8-NEXT:    s_or_b32 s0, s0, s1
847; GFX8-NEXT:    ; return to shader part epilog
848;
849; GFX9-LABEL: s_fshr_v4i8:
850; GFX9:       ; %bb.0:
851; GFX9-NEXT:    s_lshr_b32 s3, s0, 8
852; GFX9-NEXT:    s_lshr_b32 s4, s0, 16
853; GFX9-NEXT:    s_lshr_b32 s5, s0, 24
854; GFX9-NEXT:    s_lshr_b32 s6, s1, 8
855; GFX9-NEXT:    s_lshr_b32 s7, s1, 16
856; GFX9-NEXT:    s_lshr_b32 s8, s1, 24
857; GFX9-NEXT:    s_lshr_b32 s9, s2, 8
858; GFX9-NEXT:    s_lshr_b32 s10, s2, 16
859; GFX9-NEXT:    s_lshr_b32 s11, s2, 24
860; GFX9-NEXT:    s_and_b32 s12, s2, 7
861; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
862; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
863; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
864; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
865; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
866; GFX9-NEXT:    s_andn2_b32 s2, 7, s9
867; GFX9-NEXT:    s_lshl_b32 s3, s3, 1
868; GFX9-NEXT:    s_lshr_b32 s1, s1, s12
869; GFX9-NEXT:    s_lshl_b32 s2, s3, s2
870; GFX9-NEXT:    s_and_b32 s3, s6, 0xff
871; GFX9-NEXT:    s_or_b32 s0, s0, s1
872; GFX9-NEXT:    s_and_b32 s1, s9, 7
873; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
874; GFX9-NEXT:    s_lshr_b32 s1, s3, s1
875; GFX9-NEXT:    s_andn2_b32 s3, 7, s10
876; GFX9-NEXT:    s_lshl_b32 s4, s4, 1
877; GFX9-NEXT:    s_lshl_b32 s3, s4, s3
878; GFX9-NEXT:    s_and_b32 s4, s7, 0xff
879; GFX9-NEXT:    s_or_b32 s1, s2, s1
880; GFX9-NEXT:    s_and_b32 s2, s10, 7
881; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
882; GFX9-NEXT:    s_lshr_b32 s2, s4, s2
883; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
884; GFX9-NEXT:    s_or_b32 s2, s3, s2
885; GFX9-NEXT:    s_and_b32 s3, s11, 7
886; GFX9-NEXT:    s_andn2_b32 s4, 7, s11
887; GFX9-NEXT:    s_lshl_b32 s5, s5, 1
888; GFX9-NEXT:    s_and_b32 s0, s0, 0xff
889; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
890; GFX9-NEXT:    s_lshl_b32 s4, s5, s4
891; GFX9-NEXT:    s_lshr_b32 s3, s8, s3
892; GFX9-NEXT:    s_or_b32 s0, s0, s1
893; GFX9-NEXT:    s_and_b32 s1, s2, 0xff
894; GFX9-NEXT:    s_or_b32 s3, s4, s3
895; GFX9-NEXT:    s_lshl_b32 s1, s1, 16
896; GFX9-NEXT:    s_or_b32 s0, s0, s1
897; GFX9-NEXT:    s_and_b32 s1, s3, 0xff
898; GFX9-NEXT:    s_lshl_b32 s1, s1, 24
899; GFX9-NEXT:    s_or_b32 s0, s0, s1
900; GFX9-NEXT:    ; return to shader part epilog
901;
902; GFX10-LABEL: s_fshr_v4i8:
903; GFX10:       ; %bb.0:
904; GFX10-NEXT:    s_lshr_b32 s6, s1, 8
905; GFX10-NEXT:    s_lshr_b32 s3, s0, 8
906; GFX10-NEXT:    s_lshr_b32 s4, s0, 16
907; GFX10-NEXT:    s_lshr_b32 s5, s0, 24
908; GFX10-NEXT:    s_lshr_b32 s7, s1, 16
909; GFX10-NEXT:    s_lshr_b32 s8, s1, 24
910; GFX10-NEXT:    s_lshr_b32 s9, s2, 8
911; GFX10-NEXT:    s_lshr_b32 s10, s2, 16
912; GFX10-NEXT:    s_lshr_b32 s11, s2, 24
913; GFX10-NEXT:    s_and_b32 s12, s2, 7
914; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
915; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
916; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
917; GFX10-NEXT:    s_and_b32 s6, s6, 0xff
918; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
919; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
920; GFX10-NEXT:    s_and_b32 s2, s9, 7
921; GFX10-NEXT:    s_andn2_b32 s9, 7, s9
922; GFX10-NEXT:    s_lshl_b32 s3, s3, 1
923; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
924; GFX10-NEXT:    s_lshr_b32 s1, s1, s12
925; GFX10-NEXT:    s_lshl_b32 s3, s3, s9
926; GFX10-NEXT:    s_lshr_b32 s2, s6, s2
927; GFX10-NEXT:    s_and_b32 s6, s7, 0xff
928; GFX10-NEXT:    s_or_b32 s0, s0, s1
929; GFX10-NEXT:    s_or_b32 s1, s3, s2
930; GFX10-NEXT:    s_and_b32 s2, s10, 7
931; GFX10-NEXT:    s_andn2_b32 s3, 7, s10
932; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
933; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
934; GFX10-NEXT:    s_lshl_b32 s3, s4, s3
935; GFX10-NEXT:    s_lshr_b32 s2, s6, s2
936; GFX10-NEXT:    s_andn2_b32 s4, 7, s11
937; GFX10-NEXT:    s_lshl_b32 s5, s5, 1
938; GFX10-NEXT:    s_and_b32 s6, s11, 7
939; GFX10-NEXT:    s_lshl_b32 s4, s5, s4
940; GFX10-NEXT:    s_lshr_b32 s5, s8, s6
941; GFX10-NEXT:    s_or_b32 s2, s3, s2
942; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
943; GFX10-NEXT:    s_or_b32 s3, s4, s5
944; GFX10-NEXT:    s_and_b32 s0, s0, 0xff
945; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
946; GFX10-NEXT:    s_and_b32 s2, s2, 0xff
947; GFX10-NEXT:    s_or_b32 s0, s0, s1
948; GFX10-NEXT:    s_lshl_b32 s1, s2, 16
949; GFX10-NEXT:    s_and_b32 s2, s3, 0xff
950; GFX10-NEXT:    s_or_b32 s0, s0, s1
951; GFX10-NEXT:    s_lshl_b32 s1, s2, 24
952; GFX10-NEXT:    s_or_b32 s0, s0, s1
953; GFX10-NEXT:    ; return to shader part epilog
954  %lhs = bitcast i32 %lhs.arg to <4 x i8>
955  %rhs = bitcast i32 %rhs.arg to <4 x i8>
956  %amt = bitcast i32 %amt.arg to <4 x i8>
957  %result = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %lhs, <4 x i8> %rhs, <4 x i8> %amt)
958  %cast.result = bitcast <4 x i8> %result to i32
959  ret i32 %cast.result
960}
961
962define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
963; GFX6-LABEL: v_fshr_v4i8:
964; GFX6:       ; %bb.0:
965; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
966; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 8, v2
967; GFX6-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
968; GFX6-NEXT:    v_lshrrev_b32_e32 v9, 24, v2
969; GFX6-NEXT:    v_and_b32_e32 v10, 7, v2
970; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
971; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
972; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
973; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
974; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
975; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
976; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
977; GFX6-NEXT:    v_and_b32_e32 v2, 0xff, v1
978; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v10, v2
979; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
980; GFX6-NEXT:    v_and_b32_e32 v2, 7, v7
981; GFX6-NEXT:    v_xor_b32_e32 v7, -1, v7
982; GFX6-NEXT:    v_and_b32_e32 v7, 7, v7
983; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
984; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v7, v3
985; GFX6-NEXT:    v_bfe_u32 v7, v1, 8, 8
986; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v7
987; GFX6-NEXT:    v_xor_b32_e32 v7, -1, v8
988; GFX6-NEXT:    v_lshrrev_b32_e32 v6, 24, v1
989; GFX6-NEXT:    v_or_b32_e32 v2, v3, v2
990; GFX6-NEXT:    v_and_b32_e32 v3, 7, v8
991; GFX6-NEXT:    v_and_b32_e32 v7, 7, v7
992; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v4
993; GFX6-NEXT:    v_bfe_u32 v1, v1, 16, 8
994; GFX6-NEXT:    v_lshlrev_b32_e32 v4, v7, v4
995; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v3, v1
996; GFX6-NEXT:    v_or_b32_e32 v1, v4, v1
997; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v9
998; GFX6-NEXT:    v_and_b32_e32 v3, 7, v9
999; GFX6-NEXT:    v_and_b32_e32 v4, 7, v4
1000; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 1, v5
1001; GFX6-NEXT:    v_and_b32_e32 v2, 0xff, v2
1002; GFX6-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
1003; GFX6-NEXT:    v_lshrrev_b32_e32 v3, v3, v6
1004; GFX6-NEXT:    v_and_b32_e32 v0, 0xff, v0
1005; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1006; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
1007; GFX6-NEXT:    v_or_b32_e32 v3, v4, v3
1008; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1009; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1010; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1011; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v3
1012; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
1013; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1014; GFX6-NEXT:    s_setpc_b64 s[30:31]
1015;
1016; GFX8-LABEL: v_fshr_v4i8:
1017; GFX8:       ; %bb.0:
1018; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1019; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1020; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1021; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 24, v2
1022; GFX8-NEXT:    v_and_b32_e32 v8, 7, v2
1023; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
1024; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
1025; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 1, v0
1026; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v2, v9
1027; GFX8-NEXT:    v_lshrrev_b16_sdwa v8, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1028; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1029; GFX8-NEXT:    v_or_b32_e32 v2, v2, v8
1030; GFX8-NEXT:    v_and_b32_e32 v8, 7, v5
1031; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
1032; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1033; GFX8-NEXT:    v_and_b32_e32 v5, 7, v5
1034; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
1035; GFX8-NEXT:    v_lshlrev_b16_e32 v3, v5, v3
1036; GFX8-NEXT:    v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1037; GFX8-NEXT:    v_or_b32_e32 v3, v3, v4
1038; GFX8-NEXT:    v_and_b32_e32 v4, 7, v6
1039; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v6
1040; GFX8-NEXT:    v_mov_b32_e32 v6, 1
1041; GFX8-NEXT:    v_mov_b32_e32 v9, 0xff
1042; GFX8-NEXT:    v_and_b32_e32 v5, 7, v5
1043; GFX8-NEXT:    v_lshlrev_b16_sdwa v8, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
1044; GFX8-NEXT:    v_lshlrev_b16_e32 v5, v5, v8
1045; GFX8-NEXT:    v_and_b32_sdwa v8, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1046; GFX8-NEXT:    v_lshrrev_b16_e32 v4, v4, v8
1047; GFX8-NEXT:    v_or_b32_e32 v4, v5, v4
1048; GFX8-NEXT:    v_and_b32_e32 v5, 7, v7
1049; GFX8-NEXT:    v_xor_b32_e32 v7, -1, v7
1050; GFX8-NEXT:    v_and_b32_e32 v7, 7, v7
1051; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1052; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v7, v0
1053; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1054; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1055; GFX8-NEXT:    v_mov_b32_e32 v1, 8
1056; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1057; GFX8-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1058; GFX8-NEXT:    v_and_b32_e32 v2, 0xff, v4
1059; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1060; GFX8-NEXT:    v_and_b32_e32 v0, 0xff, v0
1061; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
1062; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
1063; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
1064; GFX8-NEXT:    s_setpc_b64 s[30:31]
1065;
1066; GFX9-LABEL: v_fshr_v4i8:
1067; GFX9:       ; %bb.0:
1068; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1069; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1070; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1071; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v2
1072; GFX9-NEXT:    v_and_b32_e32 v8, 7, v2
1073; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
1074; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
1075; GFX9-NEXT:    v_lshlrev_b16_e32 v9, 1, v0
1076; GFX9-NEXT:    v_lshlrev_b16_e32 v2, v2, v9
1077; GFX9-NEXT:    v_lshrrev_b16_sdwa v8, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1078; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1079; GFX9-NEXT:    v_or_b32_e32 v2, v2, v8
1080; GFX9-NEXT:    v_and_b32_e32 v8, 7, v5
1081; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v5
1082; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1083; GFX9-NEXT:    v_and_b32_e32 v5, 7, v5
1084; GFX9-NEXT:    v_lshlrev_b16_e32 v3, 1, v3
1085; GFX9-NEXT:    v_lshlrev_b16_e32 v3, v5, v3
1086; GFX9-NEXT:    v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1087; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
1088; GFX9-NEXT:    v_and_b32_e32 v4, 7, v6
1089; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v6
1090; GFX9-NEXT:    v_mov_b32_e32 v6, 1
1091; GFX9-NEXT:    v_mov_b32_e32 v9, 0xff
1092; GFX9-NEXT:    v_and_b32_e32 v5, 7, v5
1093; GFX9-NEXT:    v_lshlrev_b16_sdwa v8, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
1094; GFX9-NEXT:    v_lshlrev_b16_e32 v5, v5, v8
1095; GFX9-NEXT:    v_and_b32_sdwa v8, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1096; GFX9-NEXT:    v_lshrrev_b16_e32 v4, v4, v8
1097; GFX9-NEXT:    v_or_b32_e32 v4, v5, v4
1098; GFX9-NEXT:    v_and_b32_e32 v5, 7, v7
1099; GFX9-NEXT:    v_xor_b32_e32 v7, -1, v7
1100; GFX9-NEXT:    v_and_b32_e32 v7, 7, v7
1101; GFX9-NEXT:    v_lshlrev_b16_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1102; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v7, v0
1103; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1104; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
1105; GFX9-NEXT:    v_mov_b32_e32 v1, 8
1106; GFX9-NEXT:    s_movk_i32 s4, 0xff
1107; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1108; GFX9-NEXT:    v_and_or_b32 v1, v2, s4, v1
1109; GFX9-NEXT:    v_and_b32_e32 v2, 0xff, v4
1110; GFX9-NEXT:    v_and_b32_e32 v0, 0xff, v0
1111; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1112; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
1113; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0
1114; GFX9-NEXT:    s_setpc_b64 s[30:31]
1115;
1116; GFX10-LABEL: v_fshr_v4i8:
1117; GFX10:       ; %bb.0:
1118; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1119; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1120; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1121; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1122; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v2
1123; GFX10-NEXT:    v_lshrrev_b32_e32 v11, 16, v2
1124; GFX10-NEXT:    v_lshrrev_b32_e32 v12, 24, v2
1125; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v5
1126; GFX10-NEXT:    v_lshlrev_b16 v3, 1, v3
1127; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
1128; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 24, v0
1129; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
1130; GFX10-NEXT:    v_and_b32_e32 v10, 7, v10
1131; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
1132; GFX10-NEXT:    v_and_b32_e32 v8, 7, v8
1133; GFX10-NEXT:    v_mov_b32_e32 v13, 0xff
1134; GFX10-NEXT:    v_xor_b32_e32 v14, -1, v12
1135; GFX10-NEXT:    v_lshlrev_b16 v3, v10, v3
1136; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v11
1137; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 24, v1
1138; GFX10-NEXT:    v_lshlrev_b16 v0, v8, v0
1139; GFX10-NEXT:    v_and_b32_e32 v8, 0xff, v1
1140; GFX10-NEXT:    v_and_b32_e32 v5, 7, v5
1141; GFX10-NEXT:    v_and_b32_e32 v7, 0xff, v7
1142; GFX10-NEXT:    v_and_b32_e32 v11, 7, v11
1143; GFX10-NEXT:    v_and_b32_e32 v10, 7, v10
1144; GFX10-NEXT:    v_lshlrev_b16 v4, 1, v4
1145; GFX10-NEXT:    v_and_b32_sdwa v1, v1, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1146; GFX10-NEXT:    v_and_b32_e32 v13, 7, v14
1147; GFX10-NEXT:    v_lshlrev_b16 v6, 1, v6
1148; GFX10-NEXT:    v_and_b32_e32 v12, 7, v12
1149; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
1150; GFX10-NEXT:    v_lshrrev_b16 v5, v5, v7
1151; GFX10-NEXT:    v_lshlrev_b16 v4, v10, v4
1152; GFX10-NEXT:    v_lshrrev_b16 v1, v11, v1
1153; GFX10-NEXT:    v_lshlrev_b16 v6, v13, v6
1154; GFX10-NEXT:    v_lshrrev_b16 v7, v12, v9
1155; GFX10-NEXT:    v_lshrrev_b16 v2, v2, v8
1156; GFX10-NEXT:    v_or_b32_e32 v3, v3, v5
1157; GFX10-NEXT:    v_mov_b32_e32 v5, 8
1158; GFX10-NEXT:    v_or_b32_e32 v1, v4, v1
1159; GFX10-NEXT:    v_or_b32_e32 v4, v6, v7
1160; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
1161; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1162; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
1163; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v4
1164; GFX10-NEXT:    v_and_or_b32 v0, v0, 0xff, v2
1165; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1166; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 24, v3
1167; GFX10-NEXT:    v_or3_b32 v0, v0, v1, v2
1168; GFX10-NEXT:    s_setpc_b64 s[30:31]
1169  %lhs = bitcast i32 %lhs.arg to <4 x i8>
1170  %rhs = bitcast i32 %rhs.arg to <4 x i8>
1171  %amt = bitcast i32 %amt.arg to <4 x i8>
1172  %result = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %lhs, <4 x i8> %rhs, <4 x i8> %amt)
1173  %cast.result = bitcast <4 x i8> %result to i32
1174  ret i32 %cast.result
1175}
1176
1177define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) {
1178; GFX6-LABEL: s_fshr_i24:
1179; GFX6:       ; %bb.0:
1180; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1181; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1182; GFX6-NEXT:    v_mov_b32_e32 v1, 0xffffffe8
1183; GFX6-NEXT:    s_and_b32 s2, s2, 0xffffff
1184; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
1185; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1186; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1187; GFX6-NEXT:    s_and_b32 s1, s1, 0xffffff
1188; GFX6-NEXT:    v_mul_lo_u32 v1, v1, v0
1189; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
1190; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1191; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
1192; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
1193; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1194; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 24, v0
1195; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1196; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1197; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 24, v0
1198; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1199; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1200; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 23, v0
1201; GFX6-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1202; GFX6-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1203; GFX6-NEXT:    v_lshl_b32_e32 v1, s0, v1
1204; GFX6-NEXT:    v_lshr_b32_e32 v0, s1, v0
1205; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
1206; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
1207; GFX6-NEXT:    ; return to shader part epilog
1208;
1209; GFX8-LABEL: s_fshr_i24:
1210; GFX8:       ; %bb.0:
1211; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1212; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1213; GFX8-NEXT:    v_mov_b32_e32 v1, 0xffffffe8
1214; GFX8-NEXT:    s_and_b32 s2, s2, 0xffffff
1215; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
1216; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1217; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
1218; GFX8-NEXT:    s_and_b32 s1, s1, 0xffffff
1219; GFX8-NEXT:    v_mul_lo_u32 v1, v1, v0
1220; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
1221; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
1222; GFX8-NEXT:    v_mul_hi_u32 v0, s2, v0
1223; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
1224; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
1225; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 24, v0
1226; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1227; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1228; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 24, v0
1229; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1230; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1231; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 23, v0
1232; GFX8-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1233; GFX8-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1234; GFX8-NEXT:    v_lshlrev_b32_e64 v1, v1, s0
1235; GFX8-NEXT:    v_lshrrev_b32_e64 v0, v0, s1
1236; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
1237; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
1238; GFX8-NEXT:    ; return to shader part epilog
1239;
1240; GFX9-LABEL: s_fshr_i24:
1241; GFX9:       ; %bb.0:
1242; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1243; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1244; GFX9-NEXT:    v_mov_b32_e32 v1, 0xffffffe8
1245; GFX9-NEXT:    s_and_b32 s2, s2, 0xffffff
1246; GFX9-NEXT:    s_and_b32 s1, s1, 0xffffff
1247; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1248; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1249; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
1250; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v0
1251; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1252; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
1253; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
1254; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 24
1255; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
1256; GFX9-NEXT:    v_subrev_u32_e32 v1, 24, v0
1257; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1258; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1259; GFX9-NEXT:    v_subrev_u32_e32 v1, 24, v0
1260; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1261; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1262; GFX9-NEXT:    v_sub_u32_e32 v1, 23, v0
1263; GFX9-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1264; GFX9-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1265; GFX9-NEXT:    v_lshrrev_b32_e64 v0, v0, s1
1266; GFX9-NEXT:    v_lshl_or_b32 v0, s0, v1, v0
1267; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
1268; GFX9-NEXT:    ; return to shader part epilog
1269;
1270; GFX10-LABEL: s_fshr_i24:
1271; GFX10:       ; %bb.0:
1272; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1273; GFX10-NEXT:    s_and_b32 s2, s2, 0xffffff
1274; GFX10-NEXT:    s_and_b32 s1, s1, 0xffffff
1275; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
1276; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1277; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1278; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1279; GFX10-NEXT:    v_mul_lo_u32 v1, 0xffffffe8, v0
1280; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
1281; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
1282; GFX10-NEXT:    v_mul_hi_u32 v0, s2, v0
1283; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 24
1284; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
1285; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 24, v0
1286; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1287; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
1288; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 24, v0
1289; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1290; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
1291; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 23, v0
1292; GFX10-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1293; GFX10-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1294; GFX10-NEXT:    v_lshrrev_b32_e64 v0, v0, s1
1295; GFX10-NEXT:    v_lshl_or_b32 v0, s0, v1, v0
1296; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
1297; GFX10-NEXT:    ; return to shader part epilog
1298  %result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt)
1299  ret i24 %result
1300}
1301
1302define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
1303; GFX6-LABEL: v_fshr_i24:
1304; GFX6:       ; %bb.0:
1305; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1306; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1307; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1308; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffffe8
1309; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1310; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1311; GFX6-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1312; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1313; GFX6-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1314; GFX6-NEXT:    v_mul_lo_u32 v4, v4, v3
1315; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
1316; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
1317; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
1318; GFX6-NEXT:    v_mul_lo_u32 v3, v3, 24
1319; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
1320; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v2
1321; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1322; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1323; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v2
1324; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1325; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1326; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v2
1327; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1328; GFX6-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
1329; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
1330; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1331; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1332; GFX6-NEXT:    s_setpc_b64 s[30:31]
1333;
1334; GFX8-LABEL: v_fshr_i24:
1335; GFX8:       ; %bb.0:
1336; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1337; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1338; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1339; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffffe8
1340; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1341; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1342; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1343; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
1344; GFX8-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1345; GFX8-NEXT:    v_mul_lo_u32 v4, v4, v3
1346; GFX8-NEXT:    v_mul_hi_u32 v4, v3, v4
1347; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v4
1348; GFX8-NEXT:    v_mul_hi_u32 v3, v2, v3
1349; GFX8-NEXT:    v_mul_lo_u32 v3, v3, 24
1350; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
1351; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v2
1352; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1353; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1354; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v2
1355; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1356; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1357; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v2
1358; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1359; GFX8-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
1360; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
1361; GFX8-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1362; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1363; GFX8-NEXT:    s_setpc_b64 s[30:31]
1364;
1365; GFX9-LABEL: v_fshr_i24:
1366; GFX9:       ; %bb.0:
1367; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1368; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1369; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1370; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffffffe8
1371; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1372; GFX9-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1373; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1374; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1375; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1376; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v3
1377; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
1378; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
1379; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
1380; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 24
1381; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
1382; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v2
1383; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1384; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1385; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v2
1386; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1387; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1388; GFX9-NEXT:    v_sub_u32_e32 v3, 23, v2
1389; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1390; GFX9-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
1391; GFX9-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1392; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v3, v1
1393; GFX9-NEXT:    s_setpc_b64 s[30:31]
1394;
1395; GFX10-LABEL: v_fshr_i24:
1396; GFX10:       ; %bb.0:
1397; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1398; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1399; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1400; GFX10-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1401; GFX10-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1402; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1403; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1404; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1405; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
1406; GFX10-NEXT:    v_mul_lo_u32 v4, 0xffffffe8, v3
1407; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
1408; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
1409; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
1410; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 24
1411; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
1412; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v2
1413; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v2
1414; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
1415; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v2
1416; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v2
1417; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
1418; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 23, v2
1419; GFX10-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1420; GFX10-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
1421; GFX10-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1422; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v3, v1
1423; GFX10-NEXT:    s_setpc_b64 s[30:31]
1424  %result = call i24 @llvm.fshr.i24(i24 %lhs, i24 %rhs, i24 %amt)
1425  ret i24 %result
1426}
1427
1428define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
1429; GFX6-LABEL: s_fshr_v2i24:
1430; GFX6:       ; %bb.0:
1431; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1432; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1433; GFX6-NEXT:    s_lshr_b32 s6, s0, 16
1434; GFX6-NEXT:    s_lshr_b32 s7, s0, 24
1435; GFX6-NEXT:    s_lshr_b32 s8, s1, 8
1436; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1437; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1438; GFX6-NEXT:    s_and_b32 s9, s0, 0xff
1439; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x80008
1440; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
1441; GFX6-NEXT:    s_lshl_b32 s0, s0, 8
1442; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
1443; GFX6-NEXT:    v_mov_b32_e32 v1, 0xffffffe8
1444; GFX6-NEXT:    s_or_b32 s0, s9, s0
1445; GFX6-NEXT:    s_or_b32 s1, s7, s1
1446; GFX6-NEXT:    s_and_b32 s7, s8, 0xff
1447; GFX6-NEXT:    s_lshr_b32 s8, s2, 16
1448; GFX6-NEXT:    s_lshr_b32 s9, s2, 24
1449; GFX6-NEXT:    s_and_b32 s11, s2, 0xff
1450; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x80008
1451; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v0
1452; GFX6-NEXT:    s_lshl_b32 s2, s2, 8
1453; GFX6-NEXT:    s_and_b32 s8, s8, 0xff
1454; GFX6-NEXT:    s_or_b32 s2, s11, s2
1455; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1456; GFX6-NEXT:    s_lshr_b32 s10, s3, 8
1457; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
1458; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1459; GFX6-NEXT:    s_and_b32 s3, s3, 0xff
1460; GFX6-NEXT:    s_or_b32 s2, s2, s8
1461; GFX6-NEXT:    s_lshl_b32 s3, s3, 8
1462; GFX6-NEXT:    s_and_b32 s8, s10, 0xff
1463; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
1464; GFX6-NEXT:    s_or_b32 s3, s9, s3
1465; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1466; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
1467; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1468; GFX6-NEXT:    s_or_b32 s3, s3, s8
1469; GFX6-NEXT:    s_lshr_b32 s8, s4, 16
1470; GFX6-NEXT:    s_lshr_b32 s9, s4, 24
1471; GFX6-NEXT:    s_and_b32 s11, s4, 0xff
1472; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x80008
1473; GFX6-NEXT:    s_lshl_b32 s4, s4, 8
1474; GFX6-NEXT:    s_and_b32 s8, s8, 0xff
1475; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1476; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, 24
1477; GFX6-NEXT:    s_or_b32 s4, s11, s4
1478; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1479; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
1480; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
1481; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1482; GFX6-NEXT:    s_or_b32 s4, s4, s8
1483; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1484; GFX6-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
1485; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
1486; GFX6-NEXT:    s_lshr_b32 s10, s5, 8
1487; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
1488; GFX6-NEXT:    s_and_b32 s5, s5, 0xff
1489; GFX6-NEXT:    v_mul_lo_u32 v1, v1, v2
1490; GFX6-NEXT:    s_lshl_b32 s5, s5, 8
1491; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1492; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v0
1493; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1494; GFX6-NEXT:    v_mul_hi_u32 v1, v2, v1
1495; GFX6-NEXT:    s_and_b32 s8, s10, 0xff
1496; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1497; GFX6-NEXT:    s_or_b32 s5, s9, s5
1498; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
1499; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v0
1500; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
1501; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
1502; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1503; GFX6-NEXT:    s_or_b32 s5, s5, s8
1504; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1505; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1506; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1507; GFX6-NEXT:    s_and_b32 s6, s6, 0xff
1508; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
1509; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1510; GFX6-NEXT:    v_mul_lo_u32 v1, v1, 24
1511; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v0
1512; GFX6-NEXT:    s_lshl_b32 s4, s6, 17
1513; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
1514; GFX6-NEXT:    s_or_b32 s0, s4, s0
1515; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v3
1516; GFX6-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1517; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
1518; GFX6-NEXT:    v_lshr_b32_e32 v0, s2, v0
1519; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
1520; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
1521; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
1522; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1523; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1524; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
1525; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1526; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
1527; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
1528; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1529; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v1
1530; GFX6-NEXT:    s_lshl_b32 s0, s7, 17
1531; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
1532; GFX6-NEXT:    s_or_b32 s0, s0, s1
1533; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1534; GFX6-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1535; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
1536; GFX6-NEXT:    v_lshr_b32_e32 v1, s3, v1
1537; GFX6-NEXT:    v_bfe_u32 v3, v0, 8, 8
1538; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
1539; GFX6-NEXT:    v_and_b32_e32 v2, 0xff, v0
1540; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 8, v3
1541; GFX6-NEXT:    v_bfe_u32 v0, v0, 16, 8
1542; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
1543; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1544; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
1545; GFX6-NEXT:    v_and_b32_e32 v2, 0xff, v1
1546; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
1547; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1548; GFX6-NEXT:    v_bfe_u32 v2, v1, 8, 8
1549; GFX6-NEXT:    v_bfe_u32 v1, v1, 16, 8
1550; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1551; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
1552; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
1553; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
1554; GFX6-NEXT:    ; return to shader part epilog
1555;
1556; GFX8-LABEL: s_fshr_v2i24:
1557; GFX8:       ; %bb.0:
1558; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1559; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1560; GFX8-NEXT:    s_lshr_b32 s9, s1, 8
1561; GFX8-NEXT:    s_bfe_u32 s10, 8, 0x100000
1562; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
1563; GFX8-NEXT:    s_lshr_b32 s6, s0, 8
1564; GFX8-NEXT:    s_lshr_b32 s8, s0, 24
1565; GFX8-NEXT:    s_lshl_b32 s1, s1, s10
1566; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1567; GFX8-NEXT:    s_and_b32 s6, s6, 0xff
1568; GFX8-NEXT:    s_or_b32 s1, s8, s1
1569; GFX8-NEXT:    s_lshr_b32 s8, s2, 8
1570; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
1571; GFX8-NEXT:    s_lshr_b32 s7, s0, 16
1572; GFX8-NEXT:    s_and_b32 s0, s0, 0xff
1573; GFX8-NEXT:    s_lshl_b32 s6, s6, s10
1574; GFX8-NEXT:    s_and_b32 s8, s8, 0xff
1575; GFX8-NEXT:    s_or_b32 s0, s0, s6
1576; GFX8-NEXT:    s_and_b32 s6, s7, 0xff
1577; GFX8-NEXT:    s_and_b32 s7, s9, 0xff
1578; GFX8-NEXT:    s_lshr_b32 s9, s2, 16
1579; GFX8-NEXT:    s_lshr_b32 s11, s2, 24
1580; GFX8-NEXT:    s_and_b32 s2, s2, 0xff
1581; GFX8-NEXT:    s_lshl_b32 s8, s8, s10
1582; GFX8-NEXT:    s_or_b32 s2, s2, s8
1583; GFX8-NEXT:    s_and_b32 s8, s9, 0xff
1584; GFX8-NEXT:    v_mov_b32_e32 v1, 0xffffffe8
1585; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1586; GFX8-NEXT:    v_mul_lo_u32 v2, v1, v0
1587; GFX8-NEXT:    s_lshr_b32 s12, s3, 8
1588; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
1589; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1590; GFX8-NEXT:    s_and_b32 s3, s3, 0xff
1591; GFX8-NEXT:    s_or_b32 s2, s2, s8
1592; GFX8-NEXT:    s_lshl_b32 s3, s3, s10
1593; GFX8-NEXT:    s_and_b32 s8, s12, 0xff
1594; GFX8-NEXT:    s_or_b32 s3, s11, s3
1595; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1596; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
1597; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1598; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v2
1599; GFX8-NEXT:    s_or_b32 s3, s3, s8
1600; GFX8-NEXT:    s_lshr_b32 s8, s4, 8
1601; GFX8-NEXT:    s_and_b32 s8, s8, 0xff
1602; GFX8-NEXT:    s_lshr_b32 s9, s4, 16
1603; GFX8-NEXT:    s_lshr_b32 s11, s4, 24
1604; GFX8-NEXT:    s_and_b32 s4, s4, 0xff
1605; GFX8-NEXT:    s_lshl_b32 s8, s8, s10
1606; GFX8-NEXT:    s_or_b32 s4, s4, s8
1607; GFX8-NEXT:    s_and_b32 s8, s9, 0xff
1608; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
1609; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v2, 24
1610; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1611; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
1612; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
1613; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1614; GFX8-NEXT:    s_or_b32 s4, s4, s8
1615; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
1616; GFX8-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
1617; GFX8-NEXT:    v_cvt_u32_f32_e32 v2, v2
1618; GFX8-NEXT:    s_lshr_b32 s12, s5, 8
1619; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
1620; GFX8-NEXT:    s_and_b32 s5, s5, 0xff
1621; GFX8-NEXT:    v_mul_lo_u32 v1, v1, v2
1622; GFX8-NEXT:    s_lshl_b32 s5, s5, s10
1623; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
1624; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v0
1625; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1626; GFX8-NEXT:    v_mul_hi_u32 v1, v2, v1
1627; GFX8-NEXT:    s_and_b32 s8, s12, 0xff
1628; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1629; GFX8-NEXT:    s_or_b32 s5, s11, s5
1630; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
1631; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v0
1632; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
1633; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
1634; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1635; GFX8-NEXT:    s_or_b32 s5, s5, s8
1636; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1637; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1
1638; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
1639; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
1640; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1641; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v0
1642; GFX8-NEXT:    v_mul_lo_u32 v1, v1, 24
1643; GFX8-NEXT:    s_lshl_b32 s4, s6, 17
1644; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
1645; GFX8-NEXT:    s_or_b32 s0, s4, s0
1646; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v3
1647; GFX8-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1648; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
1649; GFX8-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
1650; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
1651; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
1652; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
1653; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1654; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1655; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
1656; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1657; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
1658; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
1659; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1660; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v1
1661; GFX8-NEXT:    s_lshl_b32 s0, s7, 17
1662; GFX8-NEXT:    s_lshl_b32 s1, s1, 1
1663; GFX8-NEXT:    s_or_b32 s0, s0, s1
1664; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1665; GFX8-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1666; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
1667; GFX8-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
1668; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
1669; GFX8-NEXT:    v_mov_b32_e32 v2, 8
1670; GFX8-NEXT:    v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
1671; GFX8-NEXT:    v_mov_b32_e32 v4, 16
1672; GFX8-NEXT:    v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1673; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
1674; GFX8-NEXT:    v_or_b32_e32 v0, v3, v0
1675; GFX8-NEXT:    v_and_b32_e32 v3, 0xff, v1
1676; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
1677; GFX8-NEXT:    v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
1678; GFX8-NEXT:    v_or_b32_e32 v0, v0, v3
1679; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
1680; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
1681; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
1682; GFX8-NEXT:    ; return to shader part epilog
1683;
1684; GFX9-LABEL: s_fshr_v2i24:
1685; GFX9:       ; %bb.0:
1686; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1687; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1688; GFX9-NEXT:    v_mov_b32_e32 v1, 0xffffffe8
1689; GFX9-NEXT:    s_lshr_b32 s11, s1, 8
1690; GFX9-NEXT:    s_bfe_u32 s12, 8, 0x100000
1691; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1692; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1693; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
1694; GFX9-NEXT:    s_lshr_b32 s7, s0, 8
1695; GFX9-NEXT:    s_lshr_b32 s10, s0, 24
1696; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v0
1697; GFX9-NEXT:    s_lshl_b32 s1, s1, s12
1698; GFX9-NEXT:    s_and_b32 s7, s7, 0xff
1699; GFX9-NEXT:    s_or_b32 s1, s10, s1
1700; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2
1701; GFX9-NEXT:    s_lshr_b32 s10, s2, 8
1702; GFX9-NEXT:    s_lshr_b32 s9, s0, 16
1703; GFX9-NEXT:    s_and_b32 s0, s0, 0xff
1704; GFX9-NEXT:    s_lshl_b32 s7, s7, s12
1705; GFX9-NEXT:    s_and_b32 s10, s10, 0xff
1706; GFX9-NEXT:    s_or_b32 s0, s0, s7
1707; GFX9-NEXT:    s_and_b32 s7, s9, 0xff
1708; GFX9-NEXT:    s_and_b32 s9, s11, 0xff
1709; GFX9-NEXT:    s_lshr_b32 s11, s2, 16
1710; GFX9-NEXT:    s_lshr_b32 s13, s2, 24
1711; GFX9-NEXT:    s_and_b32 s2, s2, 0xff
1712; GFX9-NEXT:    s_lshl_b32 s10, s10, s12
1713; GFX9-NEXT:    s_or_b32 s2, s2, s10
1714; GFX9-NEXT:    s_and_b32 s10, s11, 0xff
1715; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2
1716; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, 24
1717; GFX9-NEXT:    s_bfe_u32 s10, s10, 0x100000
1718; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
1719; GFX9-NEXT:    s_lshr_b32 s14, s3, 8
1720; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
1721; GFX9-NEXT:    s_lshl_b32 s10, s10, 16
1722; GFX9-NEXT:    s_and_b32 s3, s3, 0xff
1723; GFX9-NEXT:    s_or_b32 s2, s2, s10
1724; GFX9-NEXT:    s_lshl_b32 s3, s3, s12
1725; GFX9-NEXT:    s_and_b32 s10, s14, 0xff
1726; GFX9-NEXT:    s_or_b32 s3, s13, s3
1727; GFX9-NEXT:    s_bfe_u32 s10, s10, 0x100000
1728; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
1729; GFX9-NEXT:    s_lshl_b32 s10, s10, 16
1730; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
1731; GFX9-NEXT:    s_or_b32 s3, s3, s10
1732; GFX9-NEXT:    s_lshr_b32 s10, s4, 8
1733; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
1734; GFX9-NEXT:    s_and_b32 s10, s10, 0xff
1735; GFX9-NEXT:    s_lshr_b32 s11, s4, 16
1736; GFX9-NEXT:    s_lshr_b32 s13, s4, 24
1737; GFX9-NEXT:    s_and_b32 s4, s4, 0xff
1738; GFX9-NEXT:    s_lshl_b32 s10, s10, s12
1739; GFX9-NEXT:    s_or_b32 s4, s4, s10
1740; GFX9-NEXT:    s_and_b32 s10, s11, 0xff
1741; GFX9-NEXT:    s_bfe_u32 s10, s10, 0x100000
1742; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
1743; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
1744; GFX9-NEXT:    s_lshl_b32 s10, s10, 16
1745; GFX9-NEXT:    s_or_b32 s4, s4, s10
1746; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1747; GFX9-NEXT:    s_lshr_b32 s14, s5, 8
1748; GFX9-NEXT:    s_and_b32 s5, s5, 0xff
1749; GFX9-NEXT:    v_mul_hi_u32 v1, v2, v1
1750; GFX9-NEXT:    s_lshl_b32 s5, s5, s12
1751; GFX9-NEXT:    s_and_b32 s10, s14, 0xff
1752; GFX9-NEXT:    s_or_b32 s5, s13, s5
1753; GFX9-NEXT:    s_bfe_u32 s10, s10, 0x100000
1754; GFX9-NEXT:    s_bfe_u32 s5, s5, 0x100000
1755; GFX9-NEXT:    s_lshl_b32 s10, s10, 16
1756; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 24
1757; GFX9-NEXT:    s_or_b32 s5, s5, s10
1758; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
1759; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1760; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1761; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v0
1762; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1763; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1764; GFX9-NEXT:    v_mul_lo_u32 v1, v1, 24
1765; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v0
1766; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1767; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
1768; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1769; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1770; GFX9-NEXT:    v_sub_u32_e32 v3, 23, v0
1771; GFX9-NEXT:    s_lshl_b32 s4, s7, 17
1772; GFX9-NEXT:    s_lshl_b32 s0, s0, 1
1773; GFX9-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1774; GFX9-NEXT:    s_or_b32 s0, s4, s0
1775; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v3
1776; GFX9-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
1777; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
1778; GFX9-NEXT:    v_lshl_or_b32 v0, s0, v2, v0
1779; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v1
1780; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1781; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1782; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v1
1783; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1784; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
1785; GFX9-NEXT:    s_bfe_u32 s9, s9, 0x100000
1786; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1787; GFX9-NEXT:    v_sub_u32_e32 v2, 23, v1
1788; GFX9-NEXT:    s_lshl_b32 s0, s9, 17
1789; GFX9-NEXT:    s_lshl_b32 s1, s1, 1
1790; GFX9-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1791; GFX9-NEXT:    s_or_b32 s0, s0, s1
1792; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1793; GFX9-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
1794; GFX9-NEXT:    s_mov_b32 s6, 8
1795; GFX9-NEXT:    v_lshl_or_b32 v1, s0, v2, v1
1796; GFX9-NEXT:    s_mov_b32 s8, 16
1797; GFX9-NEXT:    s_movk_i32 s0, 0xff
1798; GFX9-NEXT:    v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
1799; GFX9-NEXT:    v_and_b32_e32 v3, 0xff, v1
1800; GFX9-NEXT:    v_and_or_b32 v2, v0, s0, v2
1801; GFX9-NEXT:    v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
1802; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
1803; GFX9-NEXT:    v_or3_b32 v0, v2, v0, v3
1804; GFX9-NEXT:    v_bfe_u32 v2, v1, 8, 8
1805; GFX9-NEXT:    v_bfe_u32 v1, v1, 16, 8
1806; GFX9-NEXT:    v_lshl_or_b32 v1, v1, 8, v2
1807; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
1808; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
1809; GFX9-NEXT:    ; return to shader part epilog
1810;
1811; GFX10-LABEL: s_fshr_v2i24:
1812; GFX10:       ; %bb.0:
1813; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1814; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1815; GFX10-NEXT:    s_lshr_b32 s9, s1, 8
1816; GFX10-NEXT:    s_bfe_u32 s10, 8, 0x100000
1817; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
1818; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1819; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1820; GFX10-NEXT:    s_lshr_b32 s6, s0, 8
1821; GFX10-NEXT:    s_lshr_b32 s8, s0, 24
1822; GFX10-NEXT:    s_lshl_b32 s1, s1, s10
1823; GFX10-NEXT:    s_and_b32 s6, s6, 0xff
1824; GFX10-NEXT:    s_or_b32 s1, s8, s1
1825; GFX10-NEXT:    s_lshr_b32 s8, s4, 8
1826; GFX10-NEXT:    s_lshr_b32 s7, s0, 16
1827; GFX10-NEXT:    s_and_b32 s0, s0, 0xff
1828; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1829; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1830; GFX10-NEXT:    s_lshl_b32 s6, s6, s10
1831; GFX10-NEXT:    s_and_b32 s8, s8, 0xff
1832; GFX10-NEXT:    s_or_b32 s0, s0, s6
1833; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1834; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
1835; GFX10-NEXT:    s_and_b32 s6, s7, 0xff
1836; GFX10-NEXT:    s_and_b32 s7, s9, 0xff
1837; GFX10-NEXT:    s_lshr_b32 s9, s4, 16
1838; GFX10-NEXT:    v_mul_lo_u32 v2, 0xffffffe8, v0
1839; GFX10-NEXT:    v_mul_lo_u32 v3, 0xffffffe8, v1
1840; GFX10-NEXT:    s_lshr_b32 s11, s4, 24
1841; GFX10-NEXT:    s_and_b32 s4, s4, 0xff
1842; GFX10-NEXT:    s_lshl_b32 s8, s8, s10
1843; GFX10-NEXT:    s_lshr_b32 s12, s5, 8
1844; GFX10-NEXT:    s_or_b32 s4, s4, s8
1845; GFX10-NEXT:    s_and_b32 s8, s9, 0xff
1846; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2
1847; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v3
1848; GFX10-NEXT:    s_bfe_u32 s8, s8, 0x100000
1849; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
1850; GFX10-NEXT:    s_and_b32 s5, s5, 0xff
1851; GFX10-NEXT:    s_lshl_b32 s8, s8, 16
1852; GFX10-NEXT:    s_lshl_b32 s5, s5, s10
1853; GFX10-NEXT:    s_or_b32 s4, s4, s8
1854; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
1855; GFX10-NEXT:    s_and_b32 s8, s12, 0xff
1856; GFX10-NEXT:    s_or_b32 s5, s11, s5
1857; GFX10-NEXT:    s_bfe_u32 s8, s8, 0x100000
1858; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
1859; GFX10-NEXT:    v_mul_hi_u32 v0, s4, v0
1860; GFX10-NEXT:    s_bfe_u32 s5, s5, 0x100000
1861; GFX10-NEXT:    s_lshl_b32 s8, s8, 16
1862; GFX10-NEXT:    s_lshr_b32 s9, s2, 8
1863; GFX10-NEXT:    s_or_b32 s5, s5, s8
1864; GFX10-NEXT:    s_lshr_b32 s8, s2, 16
1865; GFX10-NEXT:    v_mul_hi_u32 v1, s5, v1
1866; GFX10-NEXT:    s_and_b32 s9, s9, 0xff
1867; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 24
1868; GFX10-NEXT:    s_lshr_b32 s11, s2, 24
1869; GFX10-NEXT:    s_lshr_b32 s12, s3, 8
1870; GFX10-NEXT:    s_and_b32 s2, s2, 0xff
1871; GFX10-NEXT:    s_lshl_b32 s9, s9, s10
1872; GFX10-NEXT:    s_and_b32 s8, s8, 0xff
1873; GFX10-NEXT:    v_mul_lo_u32 v1, v1, 24
1874; GFX10-NEXT:    s_and_b32 s3, s3, 0xff
1875; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s4, v0
1876; GFX10-NEXT:    s_or_b32 s2, s2, s9
1877; GFX10-NEXT:    s_bfe_u32 s4, s8, 0x100000
1878; GFX10-NEXT:    s_lshl_b32 s3, s3, s10
1879; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
1880; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v0
1881; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s5, v1
1882; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1883; GFX10-NEXT:    s_and_b32 s5, s12, 0xff
1884; GFX10-NEXT:    s_lshl_b32 s4, s4, 16
1885; GFX10-NEXT:    s_or_b32 s3, s11, s3
1886; GFX10-NEXT:    s_bfe_u32 s5, s5, 0x100000
1887; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
1888; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v1
1889; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v1
1890; GFX10-NEXT:    s_bfe_u32 s3, s3, 0x100000
1891; GFX10-NEXT:    s_lshl_b32 s5, s5, 16
1892; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v0
1893; GFX10-NEXT:    s_or_b32 s2, s2, s4
1894; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
1895; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1896; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
1897; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
1898; GFX10-NEXT:    s_or_b32 s3, s3, s5
1899; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v1
1900; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo
1901; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v1
1902; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
1903; GFX10-NEXT:    s_bfe_u32 s7, s7, 0x100000
1904; GFX10-NEXT:    s_lshl_b32 s4, s6, 17
1905; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 23, v0
1906; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
1907; GFX10-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1908; GFX10-NEXT:    s_lshl_b32 s0, s0, 1
1909; GFX10-NEXT:    s_lshl_b32 s1, s1, 1
1910; GFX10-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
1911; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 23, v1
1912; GFX10-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
1913; GFX10-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
1914; GFX10-NEXT:    s_or_b32 s0, s4, s0
1915; GFX10-NEXT:    s_lshl_b32 s2, s7, 17
1916; GFX10-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1917; GFX10-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
1918; GFX10-NEXT:    v_lshl_or_b32 v0, s0, v3, v0
1919; GFX10-NEXT:    s_or_b32 s0, s2, s1
1920; GFX10-NEXT:    v_lshl_or_b32 v1, s0, v2, v1
1921; GFX10-NEXT:    s_mov_b32 s0, 8
1922; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
1923; GFX10-NEXT:    s_mov_b32 s0, 16
1924; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1
1925; GFX10-NEXT:    v_bfe_u32 v4, v1, 8, 8
1926; GFX10-NEXT:    v_bfe_u32 v1, v1, 16, 8
1927; GFX10-NEXT:    v_and_or_b32 v2, v0, 0xff, v2
1928; GFX10-NEXT:    v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
1929; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
1930; GFX10-NEXT:    v_lshl_or_b32 v1, v1, 8, v4
1931; GFX10-NEXT:    v_or3_b32 v0, v2, v0, v3
1932; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
1933; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
1934; GFX10-NEXT:    ; return to shader part epilog
1935  %lhs = bitcast i48 %lhs.arg to <2 x i24>
1936  %rhs = bitcast i48 %rhs.arg to <2 x i24>
1937  %amt = bitcast i48 %amt.arg to <2 x i24>
1938  %result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
1939  %cast.result = bitcast <2 x i24> %result to i48
1940  ret i48 %cast.result
1941}
1942
1943define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
1944; GFX6-LABEL: v_fshr_v2i24:
1945; GFX6:       ; %bb.0:
1946; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1947; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
1948; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
1949; GFX6-NEXT:    v_mov_b32_e32 v7, 0xffffffe8
1950; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
1951; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v9, 24
1952; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
1953; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
1954; GFX6-NEXT:    v_and_b32_e32 v5, 0xffffff, v5
1955; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
1956; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1957; GFX6-NEXT:    v_mul_lo_u32 v8, v7, v6
1958; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
1959; GFX6-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
1960; GFX6-NEXT:    v_mul_hi_u32 v8, v6, v8
1961; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1962; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
1963; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v9
1964; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
1965; GFX6-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
1966; GFX6-NEXT:    v_cvt_u32_f32_e32 v8, v8
1967; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
1968; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
1969; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
1970; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
1971; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
1972; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
1973; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
1974; GFX6-NEXT:    v_mul_lo_u32 v6, v7, v8
1975; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, 23, v4
1976; GFX6-NEXT:    v_and_b32_e32 v7, 0xffffff, v7
1977; GFX6-NEXT:    v_mul_hi_u32 v6, v8, v6
1978; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
1979; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v7, v0
1980; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
1981; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1982; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
1983; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1984; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
1985; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
1986; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
1987; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1988; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1989; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
1990; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1991; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1992; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
1993; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
1994; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1995; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
1996; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
1997; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
1998; GFX6-NEXT:    s_setpc_b64 s[30:31]
1999;
2000; GFX8-LABEL: v_fshr_v2i24:
2001; GFX8:       ; %bb.0:
2002; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2003; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2004; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2005; GFX8-NEXT:    v_mov_b32_e32 v7, 0xffffffe8
2006; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2007; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v9, 24
2008; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2009; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
2010; GFX8-NEXT:    v_and_b32_e32 v5, 0xffffff, v5
2011; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2012; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
2013; GFX8-NEXT:    v_mul_lo_u32 v8, v7, v6
2014; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2015; GFX8-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
2016; GFX8-NEXT:    v_mul_hi_u32 v8, v6, v8
2017; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v8
2018; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
2019; GFX8-NEXT:    v_rcp_iflag_f32_e32 v8, v9
2020; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
2021; GFX8-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
2022; GFX8-NEXT:    v_cvt_u32_f32_e32 v8, v8
2023; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
2024; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
2025; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2026; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2027; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
2028; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2029; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2030; GFX8-NEXT:    v_mul_lo_u32 v6, v7, v8
2031; GFX8-NEXT:    v_sub_u32_e32 v7, vcc, 23, v4
2032; GFX8-NEXT:    v_and_b32_e32 v7, 0xffffff, v7
2033; GFX8-NEXT:    v_mul_hi_u32 v6, v8, v6
2034; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2035; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v7, v0
2036; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2037; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v8, v6
2038; GFX8-NEXT:    v_mul_hi_u32 v6, v5, v6
2039; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
2040; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
2041; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
2042; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
2043; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2044; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2045; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
2046; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2047; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2048; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
2049; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2050; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
2051; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
2052; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
2053; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
2054; GFX8-NEXT:    s_setpc_b64 s[30:31]
2055;
2056; GFX9-LABEL: v_fshr_v2i24:
2057; GFX9:       ; %bb.0:
2058; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2059; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2060; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2061; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v9, 24
2062; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v9
2063; GFX9-NEXT:    v_mov_b32_e32 v7, 0xffffffe8
2064; GFX9-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2065; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
2066; GFX9-NEXT:    v_mul_f32_e32 v9, 0x4f7ffffe, v9
2067; GFX9-NEXT:    v_cvt_u32_f32_e32 v9, v9
2068; GFX9-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2069; GFX9-NEXT:    v_mul_lo_u32 v8, v7, v6
2070; GFX9-NEXT:    v_and_b32_e32 v5, 0xffffff, v5
2071; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v9
2072; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
2073; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v8
2074; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2075; GFX9-NEXT:    v_mul_hi_u32 v7, v9, v7
2076; GFX9-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
2077; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
2078; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v6
2079; GFX9-NEXT:    v_add_u32_e32 v7, v9, v7
2080; GFX9-NEXT:    v_mul_hi_u32 v7, v5, v7
2081; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2082; GFX9-NEXT:    v_mul_lo_u32 v6, v6, 24
2083; GFX9-NEXT:    v_mul_lo_u32 v7, v7, 24
2084; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v6
2085; GFX9-NEXT:    v_subrev_u32_e32 v6, 24, v4
2086; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2087; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2088; GFX9-NEXT:    v_subrev_u32_e32 v6, 24, v4
2089; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2090; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2091; GFX9-NEXT:    v_sub_u32_e32 v6, 23, v4
2092; GFX9-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2093; GFX9-NEXT:    v_and_b32_e32 v6, 0xffffff, v6
2094; GFX9-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2095; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v6, v2
2096; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v7
2097; GFX9-NEXT:    v_subrev_u32_e32 v4, 24, v2
2098; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2099; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2100; GFX9-NEXT:    v_subrev_u32_e32 v4, 24, v2
2101; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2102; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2103; GFX9-NEXT:    v_sub_u32_e32 v4, 23, v2
2104; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
2105; GFX9-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2106; GFX9-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
2107; GFX9-NEXT:    v_lshl_or_b32 v1, v1, v4, v2
2108; GFX9-NEXT:    s_setpc_b64 s[30:31]
2109;
2110; GFX10-LABEL: v_fshr_v2i24:
2111; GFX10:       ; %bb.0:
2112; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2113; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2114; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2115; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v7, 24
2116; GFX10-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2117; GFX10-NEXT:    v_and_b32_e32 v5, 0xffffff, v5
2118; GFX10-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
2119; GFX10-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2120; GFX10-NEXT:    v_rcp_iflag_f32_e32 v7, v7
2121; GFX10-NEXT:    v_and_b32_e32 v3, 0xffffff, v3
2122; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2123; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
2124; GFX10-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2125; GFX10-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2126; GFX10-NEXT:    v_cvt_u32_f32_e32 v6, v6
2127; GFX10-NEXT:    v_cvt_u32_f32_e32 v7, v7
2128; GFX10-NEXT:    v_mul_lo_u32 v8, 0xffffffe8, v6
2129; GFX10-NEXT:    v_mul_lo_u32 v9, 0xffffffe8, v7
2130; GFX10-NEXT:    v_mul_hi_u32 v8, v6, v8
2131; GFX10-NEXT:    v_mul_hi_u32 v9, v7, v9
2132; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v8
2133; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v9
2134; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v6
2135; GFX10-NEXT:    v_mul_hi_u32 v7, v5, v7
2136; GFX10-NEXT:    v_mul_lo_u32 v6, v6, 24
2137; GFX10-NEXT:    v_mul_lo_u32 v7, v7, 24
2138; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v4, v6
2139; GFX10-NEXT:    v_sub_nc_u32_e32 v5, v5, v7
2140; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 24, v4
2141; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v4
2142; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 24, v5
2143; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
2144; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v5
2145; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 24, v4
2146; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
2147; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v4
2148; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 24, v5
2149; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
2150; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v5
2151; GFX10-NEXT:    v_sub_nc_u32_e32 v6, 23, v4
2152; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
2153; GFX10-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2154; GFX10-NEXT:    v_and_b32_e32 v6, 0xffffff, v6
2155; GFX10-NEXT:    v_sub_nc_u32_e32 v7, 23, v5
2156; GFX10-NEXT:    v_and_b32_e32 v5, 0xffffff, v5
2157; GFX10-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
2158; GFX10-NEXT:    v_and_b32_e32 v4, 0xffffff, v7
2159; GFX10-NEXT:    v_lshrrev_b32_e32 v3, v5, v3
2160; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v6, v2
2161; GFX10-NEXT:    v_lshl_or_b32 v1, v1, v4, v3
2162; GFX10-NEXT:    s_setpc_b64 s[30:31]
2163  %result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
2164  ret <2 x i24> %result
2165}
2166
2167define amdgpu_ps i32 @s_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
2168; GFX6-LABEL: s_fshr_i32:
2169; GFX6:       ; %bb.0:
2170; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2171; GFX6-NEXT:    v_mov_b32_e32 v1, s2
2172; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2173; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2174; GFX6-NEXT:    ; return to shader part epilog
2175;
2176; GFX8-LABEL: s_fshr_i32:
2177; GFX8:       ; %bb.0:
2178; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2179; GFX8-NEXT:    v_mov_b32_e32 v1, s2
2180; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2181; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2182; GFX8-NEXT:    ; return to shader part epilog
2183;
2184; GFX9-LABEL: s_fshr_i32:
2185; GFX9:       ; %bb.0:
2186; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2187; GFX9-NEXT:    v_mov_b32_e32 v1, s2
2188; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2189; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2190; GFX9-NEXT:    ; return to shader part epilog
2191;
2192; GFX10-LABEL: s_fshr_i32:
2193; GFX10:       ; %bb.0:
2194; GFX10-NEXT:    v_mov_b32_e32 v0, s2
2195; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, v0
2196; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2197; GFX10-NEXT:    ; return to shader part epilog
2198  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2199  ret i32 %result
2200}
2201
2202define amdgpu_ps i32 @s_fshr_i32_5(i32 inreg %lhs, i32 inreg %rhs) {
2203; GFX6-LABEL: s_fshr_i32_5:
2204; GFX6:       ; %bb.0:
2205; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2206; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 5
2207; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2208; GFX6-NEXT:    ; return to shader part epilog
2209;
2210; GFX8-LABEL: s_fshr_i32_5:
2211; GFX8:       ; %bb.0:
2212; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2213; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 5
2214; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2215; GFX8-NEXT:    ; return to shader part epilog
2216;
2217; GFX9-LABEL: s_fshr_i32_5:
2218; GFX9:       ; %bb.0:
2219; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2220; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 5
2221; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2222; GFX9-NEXT:    ; return to shader part epilog
2223;
2224; GFX10-LABEL: s_fshr_i32_5:
2225; GFX10:       ; %bb.0:
2226; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, 5
2227; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2228; GFX10-NEXT:    ; return to shader part epilog
2229  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 5)
2230  ret i32 %result
2231}
2232
2233define amdgpu_ps i32 @s_fshr_i32_8(i32 inreg %lhs, i32 inreg %rhs) {
2234; GFX6-LABEL: s_fshr_i32_8:
2235; GFX6:       ; %bb.0:
2236; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2237; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 8
2238; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2239; GFX6-NEXT:    ; return to shader part epilog
2240;
2241; GFX8-LABEL: s_fshr_i32_8:
2242; GFX8:       ; %bb.0:
2243; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2244; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 8
2245; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2246; GFX8-NEXT:    ; return to shader part epilog
2247;
2248; GFX9-LABEL: s_fshr_i32_8:
2249; GFX9:       ; %bb.0:
2250; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2251; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 8
2252; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2253; GFX9-NEXT:    ; return to shader part epilog
2254;
2255; GFX10-LABEL: s_fshr_i32_8:
2256; GFX10:       ; %bb.0:
2257; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, 8
2258; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2259; GFX10-NEXT:    ; return to shader part epilog
2260  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 8)
2261  ret i32 %result
2262}
2263
2264define i32 @v_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt) {
2265; GFX6-LABEL: v_fshr_i32:
2266; GFX6:       ; %bb.0:
2267; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2268; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2269; GFX6-NEXT:    s_setpc_b64 s[30:31]
2270;
2271; GFX8-LABEL: v_fshr_i32:
2272; GFX8:       ; %bb.0:
2273; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2274; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2275; GFX8-NEXT:    s_setpc_b64 s[30:31]
2276;
2277; GFX9-LABEL: v_fshr_i32:
2278; GFX9:       ; %bb.0:
2279; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2280; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2281; GFX9-NEXT:    s_setpc_b64 s[30:31]
2282;
2283; GFX10-LABEL: v_fshr_i32:
2284; GFX10:       ; %bb.0:
2285; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2286; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2287; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2288; GFX10-NEXT:    s_setpc_b64 s[30:31]
2289  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2290  ret i32 %result
2291}
2292
2293define i32 @v_fshr_i32_5(i32 %lhs, i32 %rhs) {
2294; GFX6-LABEL: v_fshr_i32_5:
2295; GFX6:       ; %bb.0:
2296; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2297; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2298; GFX6-NEXT:    s_setpc_b64 s[30:31]
2299;
2300; GFX8-LABEL: v_fshr_i32_5:
2301; GFX8:       ; %bb.0:
2302; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2303; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2304; GFX8-NEXT:    s_setpc_b64 s[30:31]
2305;
2306; GFX9-LABEL: v_fshr_i32_5:
2307; GFX9:       ; %bb.0:
2308; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2309; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2310; GFX9-NEXT:    s_setpc_b64 s[30:31]
2311;
2312; GFX10-LABEL: v_fshr_i32_5:
2313; GFX10:       ; %bb.0:
2314; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2315; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2316; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, 5
2317; GFX10-NEXT:    s_setpc_b64 s[30:31]
2318  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 5)
2319  ret i32 %result
2320}
2321
2322define i32 @v_fshr_i32_8(i32 %lhs, i32 %rhs) {
2323; GFX6-LABEL: v_fshr_i32_8:
2324; GFX6:       ; %bb.0:
2325; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2326; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2327; GFX6-NEXT:    s_setpc_b64 s[30:31]
2328;
2329; GFX8-LABEL: v_fshr_i32_8:
2330; GFX8:       ; %bb.0:
2331; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2332; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2333; GFX8-NEXT:    s_setpc_b64 s[30:31]
2334;
2335; GFX9-LABEL: v_fshr_i32_8:
2336; GFX9:       ; %bb.0:
2337; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2338; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2339; GFX9-NEXT:    s_setpc_b64 s[30:31]
2340;
2341; GFX10-LABEL: v_fshr_i32_8:
2342; GFX10:       ; %bb.0:
2343; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2344; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2345; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, 8
2346; GFX10-NEXT:    s_setpc_b64 s[30:31]
2347  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 8)
2348  ret i32 %result
2349}
2350
2351define amdgpu_ps float @v_fshr_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) {
2352; GFX6-LABEL: v_fshr_i32_ssv:
2353; GFX6:       ; %bb.0:
2354; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2355; GFX6-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2356; GFX6-NEXT:    ; return to shader part epilog
2357;
2358; GFX8-LABEL: v_fshr_i32_ssv:
2359; GFX8:       ; %bb.0:
2360; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2361; GFX8-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2362; GFX8-NEXT:    ; return to shader part epilog
2363;
2364; GFX9-LABEL: v_fshr_i32_ssv:
2365; GFX9:       ; %bb.0:
2366; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2367; GFX9-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2368; GFX9-NEXT:    ; return to shader part epilog
2369;
2370; GFX10-LABEL: v_fshr_i32_ssv:
2371; GFX10:       ; %bb.0:
2372; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, v0
2373; GFX10-NEXT:    ; return to shader part epilog
2374  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2375  %cast.result = bitcast i32 %result to float
2376  ret float %cast.result
2377}
2378
2379define amdgpu_ps float @v_fshr_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt) {
2380; GFX6-LABEL: v_fshr_i32_svs:
2381; GFX6:       ; %bb.0:
2382; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2383; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2384; GFX6-NEXT:    ; return to shader part epilog
2385;
2386; GFX8-LABEL: v_fshr_i32_svs:
2387; GFX8:       ; %bb.0:
2388; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2389; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2390; GFX8-NEXT:    ; return to shader part epilog
2391;
2392; GFX9-LABEL: v_fshr_i32_svs:
2393; GFX9:       ; %bb.0:
2394; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2395; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2396; GFX9-NEXT:    ; return to shader part epilog
2397;
2398; GFX10-LABEL: v_fshr_i32_svs:
2399; GFX10:       ; %bb.0:
2400; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
2401; GFX10-NEXT:    ; return to shader part epilog
2402  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2403  %cast.result = bitcast i32 %result to float
2404  ret float %cast.result
2405}
2406
2407define amdgpu_ps float @v_fshr_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
2408; GFX6-LABEL: v_fshr_i32_vss:
2409; GFX6:       ; %bb.0:
2410; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2411; GFX6-NEXT:    v_mov_b32_e32 v1, s2
2412; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2413; GFX6-NEXT:    ; return to shader part epilog
2414;
2415; GFX8-LABEL: v_fshr_i32_vss:
2416; GFX8:       ; %bb.0:
2417; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2418; GFX8-NEXT:    v_mov_b32_e32 v1, s2
2419; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2420; GFX8-NEXT:    ; return to shader part epilog
2421;
2422; GFX9-LABEL: v_fshr_i32_vss:
2423; GFX9:       ; %bb.0:
2424; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2425; GFX9-NEXT:    v_mov_b32_e32 v1, s2
2426; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2427; GFX9-NEXT:    ; return to shader part epilog
2428;
2429; GFX10-LABEL: v_fshr_i32_vss:
2430; GFX10:       ; %bb.0:
2431; GFX10-NEXT:    v_mov_b32_e32 v0, s2
2432; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, v0
2433; GFX10-NEXT:    ; return to shader part epilog
2434  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
2435  %cast.result = bitcast i32 %result to float
2436  ret float %cast.result
2437}
2438
2439define <2 x i32> @v_fshr_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
2440; GFX6-LABEL: v_fshr_v2i32:
2441; GFX6:       ; %bb.0:
2442; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2443; GFX6-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2444; GFX6-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2445; GFX6-NEXT:    s_setpc_b64 s[30:31]
2446;
2447; GFX8-LABEL: v_fshr_v2i32:
2448; GFX8:       ; %bb.0:
2449; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2450; GFX8-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2451; GFX8-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2452; GFX8-NEXT:    s_setpc_b64 s[30:31]
2453;
2454; GFX9-LABEL: v_fshr_v2i32:
2455; GFX9:       ; %bb.0:
2456; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2457; GFX9-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2458; GFX9-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2459; GFX9-NEXT:    s_setpc_b64 s[30:31]
2460;
2461; GFX10-LABEL: v_fshr_v2i32:
2462; GFX10:       ; %bb.0:
2463; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2464; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2465; GFX10-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2466; GFX10-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2467; GFX10-NEXT:    s_setpc_b64 s[30:31]
2468  %result = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt)
2469  ret <2 x i32> %result
2470}
2471
2472define <3 x i32> @v_fshr_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
2473; GFX6-LABEL: v_fshr_v3i32:
2474; GFX6:       ; %bb.0:
2475; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2476; GFX6-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2477; GFX6-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2478; GFX6-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2479; GFX6-NEXT:    s_setpc_b64 s[30:31]
2480;
2481; GFX8-LABEL: v_fshr_v3i32:
2482; GFX8:       ; %bb.0:
2483; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2484; GFX8-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2485; GFX8-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2486; GFX8-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2487; GFX8-NEXT:    s_setpc_b64 s[30:31]
2488;
2489; GFX9-LABEL: v_fshr_v3i32:
2490; GFX9:       ; %bb.0:
2491; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2492; GFX9-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2493; GFX9-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2494; GFX9-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2495; GFX9-NEXT:    s_setpc_b64 s[30:31]
2496;
2497; GFX10-LABEL: v_fshr_v3i32:
2498; GFX10:       ; %bb.0:
2499; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2500; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2501; GFX10-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2502; GFX10-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2503; GFX10-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2504; GFX10-NEXT:    s_setpc_b64 s[30:31]
2505  %result = call <3 x i32> @llvm.fshr.v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt)
2506  ret <3 x i32> %result
2507}
2508
2509define <4 x i32> @v_fshr_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
2510; GFX6-LABEL: v_fshr_v4i32:
2511; GFX6:       ; %bb.0:
2512; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2513; GFX6-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2514; GFX6-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2515; GFX6-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2516; GFX6-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2517; GFX6-NEXT:    s_setpc_b64 s[30:31]
2518;
2519; GFX8-LABEL: v_fshr_v4i32:
2520; GFX8:       ; %bb.0:
2521; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2522; GFX8-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2523; GFX8-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2524; GFX8-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2525; GFX8-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2526; GFX8-NEXT:    s_setpc_b64 s[30:31]
2527;
2528; GFX9-LABEL: v_fshr_v4i32:
2529; GFX9:       ; %bb.0:
2530; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2531; GFX9-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2532; GFX9-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2533; GFX9-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2534; GFX9-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2535; GFX9-NEXT:    s_setpc_b64 s[30:31]
2536;
2537; GFX10-LABEL: v_fshr_v4i32:
2538; GFX10:       ; %bb.0:
2539; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2540; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2541; GFX10-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2542; GFX10-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2543; GFX10-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2544; GFX10-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2545; GFX10-NEXT:    s_setpc_b64 s[30:31]
2546  %result = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt)
2547  ret <4 x i32> %result
2548}
2549
2550define amdgpu_ps i16 @s_fshr_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt) {
2551; GFX6-LABEL: s_fshr_i16:
2552; GFX6:       ; %bb.0:
2553; GFX6-NEXT:    s_and_b32 s3, s2, 15
2554; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
2555; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
2556; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
2557; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
2558; GFX6-NEXT:    s_bfe_u32 s2, s3, 0x100000
2559; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2560; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
2561; GFX6-NEXT:    s_or_b32 s0, s0, s1
2562; GFX6-NEXT:    ; return to shader part epilog
2563;
2564; GFX8-LABEL: s_fshr_i16:
2565; GFX8:       ; %bb.0:
2566; GFX8-NEXT:    s_and_b32 s3, s2, 15
2567; GFX8-NEXT:    s_andn2_b32 s2, 15, s2
2568; GFX8-NEXT:    s_bfe_u32 s4, 1, 0x100000
2569; GFX8-NEXT:    s_lshl_b32 s0, s0, s4
2570; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
2571; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2572; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2573; GFX8-NEXT:    s_bfe_u32 s2, s3, 0x100000
2574; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2575; GFX8-NEXT:    s_or_b32 s0, s0, s1
2576; GFX8-NEXT:    ; return to shader part epilog
2577;
2578; GFX9-LABEL: s_fshr_i16:
2579; GFX9:       ; %bb.0:
2580; GFX9-NEXT:    s_and_b32 s3, s2, 15
2581; GFX9-NEXT:    s_andn2_b32 s2, 15, s2
2582; GFX9-NEXT:    s_bfe_u32 s4, 1, 0x100000
2583; GFX9-NEXT:    s_lshl_b32 s0, s0, s4
2584; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
2585; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2586; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2587; GFX9-NEXT:    s_bfe_u32 s2, s3, 0x100000
2588; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2589; GFX9-NEXT:    s_or_b32 s0, s0, s1
2590; GFX9-NEXT:    ; return to shader part epilog
2591;
2592; GFX10-LABEL: s_fshr_i16:
2593; GFX10:       ; %bb.0:
2594; GFX10-NEXT:    s_and_b32 s3, s2, 15
2595; GFX10-NEXT:    s_bfe_u32 s4, 1, 0x100000
2596; GFX10-NEXT:    s_andn2_b32 s2, 15, s2
2597; GFX10-NEXT:    s_lshl_b32 s0, s0, s4
2598; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
2599; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2600; GFX10-NEXT:    s_bfe_u32 s3, s3, 0x100000
2601; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2602; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2603; GFX10-NEXT:    s_or_b32 s0, s0, s1
2604; GFX10-NEXT:    ; return to shader part epilog
2605  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2606  ret i16 %result
2607}
2608
2609define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
2610; GFX6-LABEL: s_fshr_i16_4:
2611; GFX6:       ; %bb.0:
2612; GFX6-NEXT:    s_lshl_b32 s0, s0, 12
2613; GFX6-NEXT:    s_bfe_u32 s1, s1, 0xc0004
2614; GFX6-NEXT:    s_or_b32 s0, s0, s1
2615; GFX6-NEXT:    ; return to shader part epilog
2616;
2617; GFX8-LABEL: s_fshr_i16_4:
2618; GFX8:       ; %bb.0:
2619; GFX8-NEXT:    s_bfe_u32 s2, 12, 0x100000
2620; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2621; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2622; GFX8-NEXT:    s_bfe_u32 s2, 4, 0x100000
2623; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2624; GFX8-NEXT:    s_or_b32 s0, s0, s1
2625; GFX8-NEXT:    ; return to shader part epilog
2626;
2627; GFX9-LABEL: s_fshr_i16_4:
2628; GFX9:       ; %bb.0:
2629; GFX9-NEXT:    s_bfe_u32 s2, 12, 0x100000
2630; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2631; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2632; GFX9-NEXT:    s_bfe_u32 s2, 4, 0x100000
2633; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2634; GFX9-NEXT:    s_or_b32 s0, s0, s1
2635; GFX9-NEXT:    ; return to shader part epilog
2636;
2637; GFX10-LABEL: s_fshr_i16_4:
2638; GFX10:       ; %bb.0:
2639; GFX10-NEXT:    s_bfe_u32 s2, 12, 0x100000
2640; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2641; GFX10-NEXT:    s_bfe_u32 s3, 4, 0x100000
2642; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2643; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2644; GFX10-NEXT:    s_or_b32 s0, s0, s1
2645; GFX10-NEXT:    ; return to shader part epilog
2646  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 4)
2647  ret i16 %result
2648}
2649
2650define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
2651; GFX6-LABEL: s_fshr_i16_5:
2652; GFX6:       ; %bb.0:
2653; GFX6-NEXT:    s_lshl_b32 s0, s0, 11
2654; GFX6-NEXT:    s_bfe_u32 s1, s1, 0xb0005
2655; GFX6-NEXT:    s_or_b32 s0, s0, s1
2656; GFX6-NEXT:    ; return to shader part epilog
2657;
2658; GFX8-LABEL: s_fshr_i16_5:
2659; GFX8:       ; %bb.0:
2660; GFX8-NEXT:    s_bfe_u32 s2, 11, 0x100000
2661; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2662; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2663; GFX8-NEXT:    s_bfe_u32 s2, 5, 0x100000
2664; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2665; GFX8-NEXT:    s_or_b32 s0, s0, s1
2666; GFX8-NEXT:    ; return to shader part epilog
2667;
2668; GFX9-LABEL: s_fshr_i16_5:
2669; GFX9:       ; %bb.0:
2670; GFX9-NEXT:    s_bfe_u32 s2, 11, 0x100000
2671; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2672; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2673; GFX9-NEXT:    s_bfe_u32 s2, 5, 0x100000
2674; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2675; GFX9-NEXT:    s_or_b32 s0, s0, s1
2676; GFX9-NEXT:    ; return to shader part epilog
2677;
2678; GFX10-LABEL: s_fshr_i16_5:
2679; GFX10:       ; %bb.0:
2680; GFX10-NEXT:    s_bfe_u32 s2, 11, 0x100000
2681; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2682; GFX10-NEXT:    s_bfe_u32 s3, 5, 0x100000
2683; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2684; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2685; GFX10-NEXT:    s_or_b32 s0, s0, s1
2686; GFX10-NEXT:    ; return to shader part epilog
2687  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 5)
2688  ret i16 %result
2689}
2690
2691define i16 @v_fshr_i16(i16 %lhs, i16 %rhs, i16 %amt) {
2692; GFX6-LABEL: v_fshr_i16:
2693; GFX6:       ; %bb.0:
2694; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2695; GFX6-NEXT:    v_and_b32_e32 v3, 15, v2
2696; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
2697; GFX6-NEXT:    v_and_b32_e32 v2, 15, v2
2698; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2699; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
2700; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
2701; GFX6-NEXT:    v_bfe_u32 v2, v3, 0, 16
2702; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2703; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
2704; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2705; GFX6-NEXT:    s_setpc_b64 s[30:31]
2706;
2707; GFX8-LABEL: v_fshr_i16:
2708; GFX8:       ; %bb.0:
2709; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2710; GFX8-NEXT:    v_and_b32_e32 v3, 15, v2
2711; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
2712; GFX8-NEXT:    v_and_b32_e32 v2, 15, v2
2713; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
2714; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
2715; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v3, v1
2716; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2717; GFX8-NEXT:    s_setpc_b64 s[30:31]
2718;
2719; GFX9-LABEL: v_fshr_i16:
2720; GFX9:       ; %bb.0:
2721; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2722; GFX9-NEXT:    v_and_b32_e32 v3, 15, v2
2723; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
2724; GFX9-NEXT:    v_and_b32_e32 v2, 15, v2
2725; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
2726; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
2727; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v3, v1
2728; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2729; GFX9-NEXT:    s_setpc_b64 s[30:31]
2730;
2731; GFX10-LABEL: v_fshr_i16:
2732; GFX10:       ; %bb.0:
2733; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2734; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2735; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
2736; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
2737; GFX10-NEXT:    v_and_b32_e32 v2, 15, v2
2738; GFX10-NEXT:    v_and_b32_e32 v3, 15, v3
2739; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
2740; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v0
2741; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2742; GFX10-NEXT:    s_setpc_b64 s[30:31]
2743  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2744  ret i16 %result
2745}
2746
2747define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
2748; GFX6-LABEL: v_fshr_i16_4:
2749; GFX6:       ; %bb.0:
2750; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2751; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 12, v0
2752; GFX6-NEXT:    v_bfe_u32 v1, v1, 4, 12
2753; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2754; GFX6-NEXT:    s_setpc_b64 s[30:31]
2755;
2756; GFX8-LABEL: v_fshr_i16_4:
2757; GFX8:       ; %bb.0:
2758; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2759; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 12, v0
2760; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 4, v1
2761; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2762; GFX8-NEXT:    s_setpc_b64 s[30:31]
2763;
2764; GFX9-LABEL: v_fshr_i16_4:
2765; GFX9:       ; %bb.0:
2766; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2767; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 12, v0
2768; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 4, v1
2769; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2770; GFX9-NEXT:    s_setpc_b64 s[30:31]
2771;
2772; GFX10-LABEL: v_fshr_i16_4:
2773; GFX10:       ; %bb.0:
2774; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2775; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2776; GFX10-NEXT:    v_lshlrev_b16 v0, 12, v0
2777; GFX10-NEXT:    v_lshrrev_b16 v1, 4, v1
2778; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2779; GFX10-NEXT:    s_setpc_b64 s[30:31]
2780  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 4)
2781  ret i16 %result
2782}
2783
2784define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
2785; GFX6-LABEL: v_fshr_i16_5:
2786; GFX6:       ; %bb.0:
2787; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2788; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 11, v0
2789; GFX6-NEXT:    v_bfe_u32 v1, v1, 5, 11
2790; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2791; GFX6-NEXT:    s_setpc_b64 s[30:31]
2792;
2793; GFX8-LABEL: v_fshr_i16_5:
2794; GFX8:       ; %bb.0:
2795; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2796; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 11, v0
2797; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 5, v1
2798; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2799; GFX8-NEXT:    s_setpc_b64 s[30:31]
2800;
2801; GFX9-LABEL: v_fshr_i16_5:
2802; GFX9:       ; %bb.0:
2803; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2804; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 11, v0
2805; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 5, v1
2806; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2807; GFX9-NEXT:    s_setpc_b64 s[30:31]
2808;
2809; GFX10-LABEL: v_fshr_i16_5:
2810; GFX10:       ; %bb.0:
2811; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2812; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2813; GFX10-NEXT:    v_lshlrev_b16 v0, 11, v0
2814; GFX10-NEXT:    v_lshrrev_b16 v1, 5, v1
2815; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2816; GFX10-NEXT:    s_setpc_b64 s[30:31]
2817  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 5)
2818  ret i16 %result
2819}
2820
2821define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt) {
2822; GFX6-LABEL: v_fshr_i16_ssv:
2823; GFX6:       ; %bb.0:
2824; GFX6-NEXT:    v_and_b32_e32 v1, 15, v0
2825; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
2826; GFX6-NEXT:    v_and_b32_e32 v0, 15, v0
2827; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
2828; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
2829; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0
2830; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
2831; GFX6-NEXT:    s_and_b32 s0, s1, 0xffff
2832; GFX6-NEXT:    v_lshr_b32_e32 v1, s0, v1
2833; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2834; GFX6-NEXT:    ; return to shader part epilog
2835;
2836; GFX8-LABEL: v_fshr_i16_ssv:
2837; GFX8:       ; %bb.0:
2838; GFX8-NEXT:    v_and_b32_e32 v1, 15, v0
2839; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
2840; GFX8-NEXT:    s_bfe_u32 s2, 1, 0x100000
2841; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
2842; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2843; GFX8-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
2844; GFX8-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
2845; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2846; GFX8-NEXT:    ; return to shader part epilog
2847;
2848; GFX9-LABEL: v_fshr_i16_ssv:
2849; GFX9:       ; %bb.0:
2850; GFX9-NEXT:    v_and_b32_e32 v1, 15, v0
2851; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
2852; GFX9-NEXT:    s_bfe_u32 s2, 1, 0x100000
2853; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
2854; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2855; GFX9-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
2856; GFX9-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
2857; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2858; GFX9-NEXT:    ; return to shader part epilog
2859;
2860; GFX10-LABEL: v_fshr_i16_ssv:
2861; GFX10:       ; %bb.0:
2862; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
2863; GFX10-NEXT:    v_and_b32_e32 v0, 15, v0
2864; GFX10-NEXT:    s_bfe_u32 s2, 1, 0x100000
2865; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2866; GFX10-NEXT:    v_and_b32_e32 v1, 15, v1
2867; GFX10-NEXT:    v_lshrrev_b16 v0, v0, s1
2868; GFX10-NEXT:    v_lshlrev_b16 v1, v1, s0
2869; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
2870; GFX10-NEXT:    ; return to shader part epilog
2871  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2872  %cast.result = bitcast i16 %result to half
2873  ret half %cast.result
2874}
2875
2876define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt) {
2877; GFX6-LABEL: v_fshr_i16_svs:
2878; GFX6:       ; %bb.0:
2879; GFX6-NEXT:    s_and_b32 s2, s1, 15
2880; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
2881; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
2882; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
2883; GFX6-NEXT:    s_lshl_b32 s0, s0, s1
2884; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
2885; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
2886; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s1, v0
2887; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
2888; GFX6-NEXT:    ; return to shader part epilog
2889;
2890; GFX8-LABEL: v_fshr_i16_svs:
2891; GFX8:       ; %bb.0:
2892; GFX8-NEXT:    s_and_b32 s2, s1, 15
2893; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
2894; GFX8-NEXT:    s_bfe_u32 s3, 1, 0x100000
2895; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
2896; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2897; GFX8-NEXT:    s_lshl_b32 s0, s0, s1
2898; GFX8-NEXT:    v_lshrrev_b16_e32 v0, s2, v0
2899; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
2900; GFX8-NEXT:    ; return to shader part epilog
2901;
2902; GFX9-LABEL: v_fshr_i16_svs:
2903; GFX9:       ; %bb.0:
2904; GFX9-NEXT:    s_and_b32 s2, s1, 15
2905; GFX9-NEXT:    s_andn2_b32 s1, 15, s1
2906; GFX9-NEXT:    s_bfe_u32 s3, 1, 0x100000
2907; GFX9-NEXT:    s_lshl_b32 s0, s0, s3
2908; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2909; GFX9-NEXT:    s_lshl_b32 s0, s0, s1
2910; GFX9-NEXT:    v_lshrrev_b16_e32 v0, s2, v0
2911; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
2912; GFX9-NEXT:    ; return to shader part epilog
2913;
2914; GFX10-LABEL: v_fshr_i16_svs:
2915; GFX10:       ; %bb.0:
2916; GFX10-NEXT:    s_and_b32 s2, s1, 15
2917; GFX10-NEXT:    s_bfe_u32 s3, 1, 0x100000
2918; GFX10-NEXT:    s_andn2_b32 s1, 15, s1
2919; GFX10-NEXT:    v_lshrrev_b16 v0, s2, v0
2920; GFX10-NEXT:    s_lshl_b32 s0, s0, s3
2921; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2922; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
2923; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
2924; GFX10-NEXT:    ; return to shader part epilog
2925  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2926  %cast.result = bitcast i16 %result to half
2927  ret half %cast.result
2928}
2929
2930define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt) {
2931; GFX6-LABEL: v_fshr_i16_vss:
2932; GFX6:       ; %bb.0:
2933; GFX6-NEXT:    s_and_b32 s2, s1, 15
2934; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
2935; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
2936; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
2937; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s1, v0
2938; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
2939; GFX6-NEXT:    s_and_b32 s0, s0, 0xffff
2940; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
2941; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
2942; GFX6-NEXT:    ; return to shader part epilog
2943;
2944; GFX8-LABEL: v_fshr_i16_vss:
2945; GFX8:       ; %bb.0:
2946; GFX8-NEXT:    s_and_b32 s2, s1, 15
2947; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
2948; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
2949; GFX8-NEXT:    v_lshlrev_b16_e32 v0, s1, v0
2950; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
2951; GFX8-NEXT:    s_bfe_u32 s1, s2, 0x100000
2952; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
2953; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
2954; GFX8-NEXT:    ; return to shader part epilog
2955;
2956; GFX9-LABEL: v_fshr_i16_vss:
2957; GFX9:       ; %bb.0:
2958; GFX9-NEXT:    s_and_b32 s2, s1, 15
2959; GFX9-NEXT:    s_andn2_b32 s1, 15, s1
2960; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
2961; GFX9-NEXT:    v_lshlrev_b16_e32 v0, s1, v0
2962; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
2963; GFX9-NEXT:    s_bfe_u32 s1, s2, 0x100000
2964; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
2965; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
2966; GFX9-NEXT:    ; return to shader part epilog
2967;
2968; GFX10-LABEL: v_fshr_i16_vss:
2969; GFX10:       ; %bb.0:
2970; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
2971; GFX10-NEXT:    s_andn2_b32 s2, 15, s1
2972; GFX10-NEXT:    s_and_b32 s1, s1, 15
2973; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
2974; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2975; GFX10-NEXT:    v_lshlrev_b16 v0, s2, v0
2976; GFX10-NEXT:    s_lshr_b32 s0, s0, s1
2977; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
2978; GFX10-NEXT:    ; return to shader part epilog
2979  %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
2980  %cast.result = bitcast i16 %result to half
2981  ret half %cast.result
2982}
2983
2984define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
2985; GFX6-LABEL: s_fshr_v2i16:
2986; GFX6:       ; %bb.0:
2987; GFX6-NEXT:    s_lshl_b32 s5, s5, 16
2988; GFX6-NEXT:    s_and_b32 s4, s4, 0xffff
2989; GFX6-NEXT:    s_or_b32 s4, s5, s4
2990; GFX6-NEXT:    s_bfe_u32 s5, 1, 0x100000
2991; GFX6-NEXT:    s_lshl_b32 s0, s0, s5
2992; GFX6-NEXT:    s_bfe_u32 s6, s2, 0xf0001
2993; GFX6-NEXT:    s_bfe_u32 s7, 14, 0x100000
2994; GFX6-NEXT:    s_lshl_b32 s1, s1, s5
2995; GFX6-NEXT:    s_bfe_u32 s5, s3, 0xf0001
2996; GFX6-NEXT:    s_lshr_b32 s6, s6, s7
2997; GFX6-NEXT:    s_lshr_b32 s5, s5, s7
2998; GFX6-NEXT:    s_xor_b32 s4, s4, -1
2999; GFX6-NEXT:    s_or_b32 s0, s0, s6
3000; GFX6-NEXT:    s_or_b32 s1, s1, s5
3001; GFX6-NEXT:    s_lshl_b32 s2, s2, 1
3002; GFX6-NEXT:    s_lshr_b32 s5, s4, 16
3003; GFX6-NEXT:    s_and_b32 s6, s4, 15
3004; GFX6-NEXT:    s_andn2_b32 s4, 15, s4
3005; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
3006; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf0001
3007; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3008; GFX6-NEXT:    s_lshl_b32 s0, s0, s6
3009; GFX6-NEXT:    s_lshr_b32 s2, s2, s4
3010; GFX6-NEXT:    s_or_b32 s0, s0, s2
3011; GFX6-NEXT:    s_and_b32 s2, s5, 15
3012; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
3013; GFX6-NEXT:    s_andn2_b32 s4, 15, s5
3014; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3015; GFX6-NEXT:    s_lshl_b32 s1, s1, s2
3016; GFX6-NEXT:    s_bfe_u32 s2, s3, 0xf0001
3017; GFX6-NEXT:    s_bfe_u32 s3, s4, 0x100000
3018; GFX6-NEXT:    s_lshr_b32 s2, s2, s3
3019; GFX6-NEXT:    s_or_b32 s1, s1, s2
3020; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3021; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3022; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
3023; GFX6-NEXT:    s_or_b32 s0, s0, s1
3024; GFX6-NEXT:    ; return to shader part epilog
3025;
3026; GFX8-LABEL: s_fshr_v2i16:
3027; GFX8:       ; %bb.0:
3028; GFX8-NEXT:    s_bfe_u32 s5, 1, 0x100000
3029; GFX8-NEXT:    s_bfe_u32 s6, s1, 0x100000
3030; GFX8-NEXT:    s_bfe_u32 s7, 15, 0x100000
3031; GFX8-NEXT:    s_lshr_b32 s3, s0, 16
3032; GFX8-NEXT:    s_lshr_b32 s4, s1, 16
3033; GFX8-NEXT:    s_lshl_b32 s0, s0, s5
3034; GFX8-NEXT:    s_lshr_b32 s6, s6, s7
3035; GFX8-NEXT:    s_or_b32 s0, s0, s6
3036; GFX8-NEXT:    s_lshl_b32 s3, s3, s5
3037; GFX8-NEXT:    s_lshr_b32 s6, s4, s7
3038; GFX8-NEXT:    s_lshl_b32 s1, s1, s5
3039; GFX8-NEXT:    s_xor_b32 s2, s2, -1
3040; GFX8-NEXT:    s_or_b32 s3, s3, s6
3041; GFX8-NEXT:    s_lshr_b32 s6, s2, 16
3042; GFX8-NEXT:    s_and_b32 s7, s2, 15
3043; GFX8-NEXT:    s_andn2_b32 s2, 15, s2
3044; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3045; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
3046; GFX8-NEXT:    s_lshr_b32 s1, s1, s5
3047; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3048; GFX8-NEXT:    s_lshl_b32 s0, s0, s7
3049; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
3050; GFX8-NEXT:    s_or_b32 s0, s0, s1
3051; GFX8-NEXT:    s_and_b32 s1, s6, 15
3052; GFX8-NEXT:    s_lshl_b32 s4, s4, s5
3053; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3054; GFX8-NEXT:    s_andn2_b32 s2, 15, s6
3055; GFX8-NEXT:    s_lshl_b32 s1, s3, s1
3056; GFX8-NEXT:    s_bfe_u32 s3, s4, 0x100000
3057; GFX8-NEXT:    s_lshr_b32 s3, s3, s5
3058; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3059; GFX8-NEXT:    s_lshr_b32 s2, s3, s2
3060; GFX8-NEXT:    s_or_b32 s1, s1, s2
3061; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3062; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3063; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
3064; GFX8-NEXT:    s_or_b32 s0, s0, s1
3065; GFX8-NEXT:    ; return to shader part epilog
3066;
3067; GFX9-LABEL: s_fshr_v2i16:
3068; GFX9:       ; %bb.0:
3069; GFX9-NEXT:    s_lshr_b32 s4, s0, 16
3070; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3071; GFX9-NEXT:    s_lshl_b32 s4, s4, 1
3072; GFX9-NEXT:    s_and_b32 s3, s2, 0xf000f
3073; GFX9-NEXT:    s_andn2_b32 s2, 0xf000f, s2
3074; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
3075; GFX9-NEXT:    s_lshr_b32 s4, s0, 16
3076; GFX9-NEXT:    s_lshr_b32 s5, s2, 16
3077; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
3078; GFX9-NEXT:    s_lshl_b32 s2, s4, s5
3079; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3080; GFX9-NEXT:    s_lshr_b32 s2, s1, 16
3081; GFX9-NEXT:    s_and_b32 s1, s1, 0xffff
3082; GFX9-NEXT:    s_lshr_b32 s4, s3, 16
3083; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
3084; GFX9-NEXT:    s_lshr_b32 s2, s2, s4
3085; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
3086; GFX9-NEXT:    s_or_b32 s0, s0, s1
3087; GFX9-NEXT:    ; return to shader part epilog
3088;
3089; GFX10-LABEL: s_fshr_v2i16:
3090; GFX10:       ; %bb.0:
3091; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3092; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3093; GFX10-NEXT:    s_lshl_b32 s3, s3, 1
3094; GFX10-NEXT:    s_and_b32 s4, s2, 0xf000f
3095; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
3096; GFX10-NEXT:    s_andn2_b32 s2, 0xf000f, s2
3097; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3098; GFX10-NEXT:    s_lshr_b32 s5, s2, 16
3099; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
3100; GFX10-NEXT:    s_lshl_b32 s2, s3, s5
3101; GFX10-NEXT:    s_lshr_b32 s3, s1, 16
3102; GFX10-NEXT:    s_and_b32 s1, s1, 0xffff
3103; GFX10-NEXT:    s_lshr_b32 s5, s4, 16
3104; GFX10-NEXT:    s_lshr_b32 s1, s1, s4
3105; GFX10-NEXT:    s_lshr_b32 s3, s3, s5
3106; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3107; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
3108; GFX10-NEXT:    s_or_b32 s0, s0, s1
3109; GFX10-NEXT:    ; return to shader part epilog
3110  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3111  %cast = bitcast <2 x i16> %result to i32
3112  ret i32 %cast
3113}
3114
3115define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
3116; GFX6-LABEL: v_fshr_v2i16:
3117; GFX6:       ; %bb.0:
3118; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3119; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
3120; GFX6-NEXT:    v_and_b32_e32 v4, 0xffff, v4
3121; GFX6-NEXT:    v_or_b32_e32 v4, v5, v4
3122; GFX6-NEXT:    s_bfe_u32 s4, 1, 0x100000
3123; GFX6-NEXT:    v_bfe_u32 v5, v2, 1, 15
3124; GFX6-NEXT:    s_bfe_u32 s5, 14, 0x100000
3125; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
3126; GFX6-NEXT:    v_lshrrev_b32_e32 v5, s5, v5
3127; GFX6-NEXT:    v_or_b32_e32 v0, v0, v5
3128; GFX6-NEXT:    v_bfe_u32 v5, v3, 1, 15
3129; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s4, v1
3130; GFX6-NEXT:    v_lshrrev_b32_e32 v5, s5, v5
3131; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
3132; GFX6-NEXT:    v_or_b32_e32 v1, v1, v5
3133; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
3134; GFX6-NEXT:    v_and_b32_e32 v6, 15, v4
3135; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
3136; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 1, v2
3137; GFX6-NEXT:    v_and_b32_e32 v4, 15, v4
3138; GFX6-NEXT:    v_bfe_u32 v6, v6, 0, 16
3139; GFX6-NEXT:    v_bfe_u32 v2, v2, 1, 15
3140; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
3141; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v6, v0
3142; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
3143; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3144; GFX6-NEXT:    v_and_b32_e32 v2, 15, v5
3145; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v5
3146; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 1, v3
3147; GFX6-NEXT:    v_and_b32_e32 v4, 15, v4
3148; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3149; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
3150; GFX6-NEXT:    v_bfe_u32 v2, v3, 1, 15
3151; GFX6-NEXT:    v_bfe_u32 v3, v4, 0, 16
3152; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
3153; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3154; GFX6-NEXT:    s_setpc_b64 s[30:31]
3155;
3156; GFX8-LABEL: v_fshr_v2i16:
3157; GFX8:       ; %bb.0:
3158; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3159; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v0
3160; GFX8-NEXT:    v_lshrrev_b16_e32 v4, 15, v1
3161; GFX8-NEXT:    v_or_b32_e32 v3, v3, v4
3162; GFX8-NEXT:    v_mov_b32_e32 v4, 1
3163; GFX8-NEXT:    v_mov_b32_e32 v5, 15
3164; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3165; GFX8-NEXT:    v_lshrrev_b16_sdwa v5, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3166; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
3167; GFX8-NEXT:    v_or_b32_e32 v0, v0, v5
3168; GFX8-NEXT:    v_lshlrev_b16_e32 v5, 1, v1
3169; GFX8-NEXT:    v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3170; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
3171; GFX8-NEXT:    v_and_b32_e32 v6, 15, v2
3172; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
3173; GFX8-NEXT:    v_and_b32_e32 v2, 15, v2
3174; GFX8-NEXT:    v_lshrrev_b16_e32 v5, 1, v5
3175; GFX8-NEXT:    v_lshlrev_b16_e32 v3, v6, v3
3176; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v2, v5
3177; GFX8-NEXT:    v_or_b32_e32 v2, v3, v2
3178; GFX8-NEXT:    v_and_b32_e32 v3, 15, v4
3179; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
3180; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
3181; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 1, v1
3182; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
3183; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v4, v1
3184; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
3185; GFX8-NEXT:    v_mov_b32_e32 v1, 16
3186; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3187; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3188; GFX8-NEXT:    s_setpc_b64 s[30:31]
3189;
3190; GFX9-LABEL: v_fshr_v2i16:
3191; GFX9:       ; %bb.0:
3192; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3193; GFX9-NEXT:    v_and_b32_e32 v3, 0xf000f, v2
3194; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
3195; GFX9-NEXT:    v_and_b32_e32 v2, 0xf000f, v2
3196; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3197; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
3198; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v3, v1
3199; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3200; GFX9-NEXT:    s_setpc_b64 s[30:31]
3201;
3202; GFX10-LABEL: v_fshr_v2i16:
3203; GFX10:       ; %bb.0:
3204; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3205; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3206; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
3207; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3208; GFX10-NEXT:    v_and_b32_e32 v2, 0xf000f, v2
3209; GFX10-NEXT:    v_and_b32_e32 v3, 0xf000f, v3
3210; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
3211; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v3, v0
3212; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3213; GFX10-NEXT:    s_setpc_b64 s[30:31]
3214  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3215  ret <2 x i16> %result
3216}
3217
3218define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
3219; GFX6-LABEL: v_fshr_v2i16_4_8:
3220; GFX6:       ; %bb.0:
3221; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3222; GFX6-NEXT:    s_bfe_u32 s4, 12, 0x100000
3223; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
3224; GFX6-NEXT:    v_bfe_u32 v2, v2, 1, 15
3225; GFX6-NEXT:    s_bfe_u32 s4, 3, 0x100000
3226; GFX6-NEXT:    v_lshrrev_b32_e32 v2, s4, v2
3227; GFX6-NEXT:    s_bfe_u32 s4, 8, 0x100000
3228; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3229; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s4, v1
3230; GFX6-NEXT:    v_bfe_u32 v2, v3, 1, 15
3231; GFX6-NEXT:    s_bfe_u32 s4, 7, 0x100000
3232; GFX6-NEXT:    v_lshrrev_b32_e32 v2, s4, v2
3233; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
3234; GFX6-NEXT:    s_setpc_b64 s[30:31]
3235;
3236; GFX8-LABEL: v_fshr_v2i16_4_8:
3237; GFX8:       ; %bb.0:
3238; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3239; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
3240; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 12, v0
3241; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 4, v1
3242; GFX8-NEXT:    v_or_b32_e32 v0, v0, v3
3243; GFX8-NEXT:    v_mov_b32_e32 v3, 8
3244; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 8, v2
3245; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3246; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
3247; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3248; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3249; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3250; GFX8-NEXT:    s_setpc_b64 s[30:31]
3251;
3252; GFX9-LABEL: v_fshr_v2i16_4_8:
3253; GFX9:       ; %bb.0:
3254; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3255; GFX9-NEXT:    v_mov_b32_e32 v2, 0x8000c
3256; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
3257; GFX9-NEXT:    v_mov_b32_e32 v2, 0x80004
3258; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
3259; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3260; GFX9-NEXT:    s_setpc_b64 s[30:31]
3261;
3262; GFX10-LABEL: v_fshr_v2i16_4_8:
3263; GFX10:       ; %bb.0:
3264; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3265; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3266; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 0x8000c, v0
3267; GFX10-NEXT:    v_pk_lshrrev_b16 v1, 0x80004, v1
3268; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3269; GFX10-NEXT:    s_setpc_b64 s[30:31]
3270  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> <i16 4, i16 8>)
3271  ret <2 x i16> %result
3272}
3273
3274define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> %amt) {
3275; GFX6-LABEL: v_fshr_v2i16_ssv:
3276; GFX6:       ; %bb.0:
3277; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3278; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
3279; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
3280; GFX6-NEXT:    s_bfe_u32 s4, 1, 0x100000
3281; GFX6-NEXT:    s_bfe_u32 s5, s2, 0xf0001
3282; GFX6-NEXT:    s_bfe_u32 s6, 14, 0x100000
3283; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
3284; GFX6-NEXT:    s_lshl_b32 s0, s0, s4
3285; GFX6-NEXT:    s_lshr_b32 s5, s5, s6
3286; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3287; GFX6-NEXT:    v_and_b32_e32 v2, 15, v0
3288; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
3289; GFX6-NEXT:    s_or_b32 s0, s0, s5
3290; GFX6-NEXT:    s_lshl_b32 s2, s2, 1
3291; GFX6-NEXT:    v_and_b32_e32 v0, 15, v0
3292; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3293; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
3294; GFX6-NEXT:    s_bfe_u32 s0, s2, 0xf0001
3295; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3296; GFX6-NEXT:    v_lshr_b32_e32 v0, s0, v0
3297; GFX6-NEXT:    s_lshl_b32 s1, s1, s4
3298; GFX6-NEXT:    s_bfe_u32 s4, s3, 0xf0001
3299; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
3300; GFX6-NEXT:    v_and_b32_e32 v2, 15, v1
3301; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1
3302; GFX6-NEXT:    s_lshr_b32 s4, s4, s6
3303; GFX6-NEXT:    s_lshl_b32 s3, s3, 1
3304; GFX6-NEXT:    v_and_b32_e32 v1, 15, v1
3305; GFX6-NEXT:    s_or_b32 s1, s1, s4
3306; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3307; GFX6-NEXT:    s_bfe_u32 s0, s3, 0xf0001
3308; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3309; GFX6-NEXT:    v_lshl_b32_e32 v2, s1, v2
3310; GFX6-NEXT:    v_lshr_b32_e32 v1, s0, v1
3311; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3312; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3313; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3314; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3315; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3316; GFX6-NEXT:    ; return to shader part epilog
3317;
3318; GFX8-LABEL: v_fshr_v2i16_ssv:
3319; GFX8:       ; %bb.0:
3320; GFX8-NEXT:    s_bfe_u32 s4, 1, 0x100000
3321; GFX8-NEXT:    s_bfe_u32 s5, s1, 0x100000
3322; GFX8-NEXT:    s_bfe_u32 s6, 15, 0x100000
3323; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3324; GFX8-NEXT:    s_lshl_b32 s0, s0, s4
3325; GFX8-NEXT:    s_lshr_b32 s5, s5, s6
3326; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
3327; GFX8-NEXT:    s_lshr_b32 s3, s1, 16
3328; GFX8-NEXT:    s_or_b32 s0, s0, s5
3329; GFX8-NEXT:    s_lshl_b32 s1, s1, s4
3330; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
3331; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3332; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
3333; GFX8-NEXT:    v_lshlrev_b16_e64 v2, v2, s0
3334; GFX8-NEXT:    s_bfe_u32 s0, s1, 0x100000
3335; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
3336; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3337; GFX8-NEXT:    s_lshr_b32 s5, s3, s6
3338; GFX8-NEXT:    s_lshl_b32 s3, s3, s4
3339; GFX8-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
3340; GFX8-NEXT:    s_lshl_b32 s2, s2, s4
3341; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
3342; GFX8-NEXT:    v_and_b32_e32 v2, 15, v1
3343; GFX8-NEXT:    v_xor_b32_e32 v1, -1, v1
3344; GFX8-NEXT:    s_bfe_u32 s0, s3, 0x100000
3345; GFX8-NEXT:    s_or_b32 s2, s2, s5
3346; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
3347; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3348; GFX8-NEXT:    v_lshlrev_b16_e64 v2, v2, s2
3349; GFX8-NEXT:    v_lshrrev_b16_e64 v1, v1, s0
3350; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
3351; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3352; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3353; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3354; GFX8-NEXT:    ; return to shader part epilog
3355;
3356; GFX9-LABEL: v_fshr_v2i16_ssv:
3357; GFX9:       ; %bb.0:
3358; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3359; GFX9-NEXT:    v_and_b32_e32 v1, 0xf000f, v0
3360; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
3361; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3362; GFX9-NEXT:    s_lshl_b32 s2, s2, 1
3363; GFX9-NEXT:    v_and_b32_e32 v0, 0xf000f, v0
3364; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3365; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v0, s0
3366; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v1, s1
3367; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3368; GFX9-NEXT:    ; return to shader part epilog
3369;
3370; GFX10-LABEL: v_fshr_v2i16_ssv:
3371; GFX10:       ; %bb.0:
3372; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
3373; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3374; GFX10-NEXT:    v_and_b32_e32 v0, 0xf000f, v0
3375; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3376; GFX10-NEXT:    s_lshl_b32 s2, s2, 1
3377; GFX10-NEXT:    v_and_b32_e32 v1, 0xf000f, v1
3378; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3379; GFX10-NEXT:    v_pk_lshrrev_b16 v0, v0, s1
3380; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v1, s0
3381; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
3382; GFX10-NEXT:    ; return to shader part epilog
3383  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3384  %cast = bitcast <2 x i16> %result to float
3385  ret float %cast
3386}
3387
3388define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <2 x i16> inreg %amt) {
3389; GFX6-LABEL: v_fshr_v2i16_svs:
3390; GFX6:       ; %bb.0:
3391; GFX6-NEXT:    s_lshl_b32 s3, s3, 16
3392; GFX6-NEXT:    s_and_b32 s2, s2, 0xffff
3393; GFX6-NEXT:    s_or_b32 s2, s3, s2
3394; GFX6-NEXT:    s_bfe_u32 s3, 1, 0x100000
3395; GFX6-NEXT:    v_bfe_u32 v2, v0, 1, 15
3396; GFX6-NEXT:    s_bfe_u32 s4, 14, 0x100000
3397; GFX6-NEXT:    s_lshl_b32 s0, s0, s3
3398; GFX6-NEXT:    v_lshrrev_b32_e32 v2, s4, v2
3399; GFX6-NEXT:    v_bfe_u32 v3, v1, 1, 15
3400; GFX6-NEXT:    v_or_b32_e32 v2, s0, v2
3401; GFX6-NEXT:    s_lshl_b32 s0, s1, s3
3402; GFX6-NEXT:    v_lshrrev_b32_e32 v3, s4, v3
3403; GFX6-NEXT:    v_or_b32_e32 v3, s0, v3
3404; GFX6-NEXT:    s_xor_b32 s0, s2, -1
3405; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
3406; GFX6-NEXT:    s_lshr_b32 s1, s0, 16
3407; GFX6-NEXT:    s_and_b32 s2, s0, 15
3408; GFX6-NEXT:    s_andn2_b32 s0, 15, s0
3409; GFX6-NEXT:    v_bfe_u32 v0, v0, 1, 15
3410; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3411; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3412; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s0, v0
3413; GFX6-NEXT:    s_and_b32 s0, s1, 15
3414; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
3415; GFX6-NEXT:    v_lshlrev_b32_e32 v2, s2, v2
3416; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3417; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3418; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
3419; GFX6-NEXT:    v_lshlrev_b32_e32 v2, s0, v3
3420; GFX6-NEXT:    v_bfe_u32 v1, v1, 1, 15
3421; GFX6-NEXT:    s_bfe_u32 s0, s1, 0x100000
3422; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s0, v1
3423; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3424; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3425; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3426; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3427; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3428; GFX6-NEXT:    ; return to shader part epilog
3429;
3430; GFX8-LABEL: v_fshr_v2i16_svs:
3431; GFX8:       ; %bb.0:
3432; GFX8-NEXT:    s_bfe_u32 s3, 1, 0x100000
3433; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3434; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
3435; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 15, v0
3436; GFX8-NEXT:    v_mov_b32_e32 v2, 15
3437; GFX8-NEXT:    v_or_b32_e32 v1, s0, v1
3438; GFX8-NEXT:    s_lshl_b32 s0, s2, s3
3439; GFX8-NEXT:    v_lshrrev_b16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3440; GFX8-NEXT:    v_or_b32_e32 v2, s0, v2
3441; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 1, v0
3442; GFX8-NEXT:    v_mov_b32_e32 v4, 1
3443; GFX8-NEXT:    s_xor_b32 s0, s1, -1
3444; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3445; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
3446; GFX8-NEXT:    s_and_b32 s2, s0, 15
3447; GFX8-NEXT:    s_andn2_b32 s0, 15, s0
3448; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 1, v3
3449; GFX8-NEXT:    v_lshrrev_b16_e32 v3, s0, v3
3450; GFX8-NEXT:    s_and_b32 s0, s1, 15
3451; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3452; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 1, v0
3453; GFX8-NEXT:    v_lshlrev_b16_e32 v2, s0, v2
3454; GFX8-NEXT:    v_lshrrev_b16_e32 v0, s1, v0
3455; GFX8-NEXT:    v_lshlrev_b16_e32 v1, s2, v1
3456; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
3457; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3458; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
3459; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3460; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3461; GFX8-NEXT:    ; return to shader part epilog
3462;
3463; GFX9-LABEL: v_fshr_v2i16_svs:
3464; GFX9:       ; %bb.0:
3465; GFX9-NEXT:    s_lshr_b32 s3, s0, 16
3466; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3467; GFX9-NEXT:    s_lshl_b32 s3, s3, 1
3468; GFX9-NEXT:    s_and_b32 s2, s1, 0xf000f
3469; GFX9-NEXT:    s_andn2_b32 s1, 0xf000f, s1
3470; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
3471; GFX9-NEXT:    s_lshr_b32 s3, s0, 16
3472; GFX9-NEXT:    s_lshr_b32 s4, s1, 16
3473; GFX9-NEXT:    s_lshl_b32 s0, s0, s1
3474; GFX9-NEXT:    s_lshl_b32 s1, s3, s4
3475; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3476; GFX9-NEXT:    v_pk_lshrrev_b16 v0, s2, v0
3477; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3478; GFX9-NEXT:    ; return to shader part epilog
3479;
3480; GFX10-LABEL: v_fshr_v2i16_svs:
3481; GFX10:       ; %bb.0:
3482; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3483; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3484; GFX10-NEXT:    s_lshl_b32 s2, s2, 1
3485; GFX10-NEXT:    s_and_b32 s3, s1, 0xf000f
3486; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3487; GFX10-NEXT:    s_andn2_b32 s1, 0xf000f, s1
3488; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3489; GFX10-NEXT:    s_lshr_b32 s4, s1, 16
3490; GFX10-NEXT:    v_pk_lshrrev_b16 v0, s3, v0
3491; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
3492; GFX10-NEXT:    s_lshl_b32 s1, s2, s4
3493; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3494; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3495; GFX10-NEXT:    ; return to shader part epilog
3496  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3497  %cast = bitcast <2 x i16> %result to float
3498  ret float %cast
3499}
3500
3501define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
3502; GFX6-LABEL: v_fshr_v2i16_vss:
3503; GFX6:       ; %bb.0:
3504; GFX6-NEXT:    s_lshl_b32 s3, s3, 16
3505; GFX6-NEXT:    s_and_b32 s2, s2, 0xffff
3506; GFX6-NEXT:    s_or_b32 s2, s3, s2
3507; GFX6-NEXT:    s_bfe_u32 s3, 1, 0x100000
3508; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s3, v0
3509; GFX6-NEXT:    s_bfe_u32 s4, s0, 0xf0001
3510; GFX6-NEXT:    s_bfe_u32 s5, 14, 0x100000
3511; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s3, v1
3512; GFX6-NEXT:    s_bfe_u32 s3, s1, 0xf0001
3513; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3514; GFX6-NEXT:    s_lshr_b32 s3, s3, s5
3515; GFX6-NEXT:    s_xor_b32 s2, s2, -1
3516; GFX6-NEXT:    v_or_b32_e32 v0, s4, v0
3517; GFX6-NEXT:    v_or_b32_e32 v1, s3, v1
3518; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
3519; GFX6-NEXT:    s_lshr_b32 s3, s2, 16
3520; GFX6-NEXT:    s_and_b32 s4, s2, 15
3521; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
3522; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3523; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf0001
3524; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3525; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
3526; GFX6-NEXT:    s_lshr_b32 s0, s0, s2
3527; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
3528; GFX6-NEXT:    s_and_b32 s0, s3, 15
3529; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
3530; GFX6-NEXT:    s_andn2_b32 s2, 15, s3
3531; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3532; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s0, v1
3533; GFX6-NEXT:    s_bfe_u32 s0, s1, 0xf0001
3534; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
3535; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
3536; GFX6-NEXT:    v_or_b32_e32 v1, s0, v1
3537; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3538; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3539; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3540; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3541; GFX6-NEXT:    ; return to shader part epilog
3542;
3543; GFX8-LABEL: v_fshr_v2i16_vss:
3544; GFX8:       ; %bb.0:
3545; GFX8-NEXT:    s_bfe_u32 s3, s0, 0x100000
3546; GFX8-NEXT:    s_bfe_u32 s4, 15, 0x100000
3547; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3548; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 1, v0
3549; GFX8-NEXT:    s_lshr_b32 s3, s3, s4
3550; GFX8-NEXT:    v_mov_b32_e32 v2, 1
3551; GFX8-NEXT:    v_or_b32_e32 v1, s3, v1
3552; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3553; GFX8-NEXT:    s_lshr_b32 s3, s2, s4
3554; GFX8-NEXT:    v_or_b32_e32 v0, s3, v0
3555; GFX8-NEXT:    s_bfe_u32 s3, 1, 0x100000
3556; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
3557; GFX8-NEXT:    s_xor_b32 s1, s1, -1
3558; GFX8-NEXT:    s_lshr_b32 s4, s1, 16
3559; GFX8-NEXT:    s_and_b32 s5, s1, 15
3560; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3561; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3562; GFX8-NEXT:    s_lshr_b32 s0, s0, s3
3563; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3564; GFX8-NEXT:    v_lshlrev_b16_e32 v1, s5, v1
3565; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3566; GFX8-NEXT:    s_lshl_b32 s2, s2, s3
3567; GFX8-NEXT:    v_or_b32_e32 v1, s0, v1
3568; GFX8-NEXT:    s_and_b32 s0, s4, 15
3569; GFX8-NEXT:    s_andn2_b32 s1, 15, s4
3570; GFX8-NEXT:    v_lshlrev_b16_e32 v0, s0, v0
3571; GFX8-NEXT:    s_bfe_u32 s0, s2, 0x100000
3572; GFX8-NEXT:    s_lshr_b32 s0, s0, s3
3573; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3574; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3575; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3576; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3577; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3578; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3579; GFX8-NEXT:    ; return to shader part epilog
3580;
3581; GFX9-LABEL: v_fshr_v2i16_vss:
3582; GFX9:       ; %bb.0:
3583; GFX9-NEXT:    s_and_b32 s2, s1, 0xf000f
3584; GFX9-NEXT:    s_andn2_b32 s1, 0xf000f, s1
3585; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3586; GFX9-NEXT:    v_pk_lshlrev_b16 v0, s1, v0
3587; GFX9-NEXT:    s_lshr_b32 s1, s0, 16
3588; GFX9-NEXT:    s_and_b32 s0, s0, 0xffff
3589; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
3590; GFX9-NEXT:    s_lshr_b32 s0, s0, s2
3591; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
3592; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3593; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3594; GFX9-NEXT:    ; return to shader part epilog
3595;
3596; GFX10-LABEL: v_fshr_v2i16_vss:
3597; GFX10:       ; %bb.0:
3598; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3599; GFX10-NEXT:    s_and_b32 s2, s1, 0xf000f
3600; GFX10-NEXT:    s_andn2_b32 s1, 0xf000f, s1
3601; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3602; GFX10-NEXT:    s_and_b32 s0, s0, 0xffff
3603; GFX10-NEXT:    s_lshr_b32 s4, s2, 16
3604; GFX10-NEXT:    v_pk_lshlrev_b16 v0, s1, v0
3605; GFX10-NEXT:    s_lshr_b32 s0, s0, s2
3606; GFX10-NEXT:    s_lshr_b32 s1, s3, s4
3607; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3608; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3609; GFX10-NEXT:    ; return to shader part epilog
3610  %result = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3611  %cast = bitcast <2 x i16> %result to float
3612  ret float %cast
3613}
3614
3615; ; FIXME
3616; define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <3 x i16> inreg %amt) {
3617;   %result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
3618;   %cast = bitcast <3 x i16> %result to i48
3619;   ret i48 %cast
3620; }
3621
3622; ; FIXME
3623; define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt) {
3624;   %result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
3625;   %cast.result = bitcast <3 x i16> %result to <3 x half>
3626;   ret <3 x half> %cast.result
3627; }
3628
3629define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs, <4 x i16> inreg %amt) {
3630; GFX6-LABEL: s_fshr_v4i16:
3631; GFX6:       ; %bb.0:
3632; GFX6-NEXT:    s_lshl_b32 s9, s9, 16
3633; GFX6-NEXT:    s_and_b32 s8, s8, 0xffff
3634; GFX6-NEXT:    s_or_b32 s8, s9, s8
3635; GFX6-NEXT:    s_lshl_b32 s9, s11, 16
3636; GFX6-NEXT:    s_and_b32 s10, s10, 0xffff
3637; GFX6-NEXT:    s_or_b32 s9, s9, s10
3638; GFX6-NEXT:    s_bfe_u32 s10, 1, 0x100000
3639; GFX6-NEXT:    s_bfe_u32 s11, s4, 0xf0001
3640; GFX6-NEXT:    s_bfe_u32 s12, 14, 0x100000
3641; GFX6-NEXT:    s_lshl_b32 s0, s0, s10
3642; GFX6-NEXT:    s_lshr_b32 s11, s11, s12
3643; GFX6-NEXT:    s_or_b32 s0, s0, s11
3644; GFX6-NEXT:    s_bfe_u32 s11, s5, 0xf0001
3645; GFX6-NEXT:    s_lshl_b32 s1, s1, s10
3646; GFX6-NEXT:    s_lshr_b32 s11, s11, s12
3647; GFX6-NEXT:    s_xor_b32 s8, s8, -1
3648; GFX6-NEXT:    s_or_b32 s1, s1, s11
3649; GFX6-NEXT:    s_lshl_b32 s4, s4, 1
3650; GFX6-NEXT:    s_lshr_b32 s11, s8, 16
3651; GFX6-NEXT:    s_and_b32 s13, s8, 15
3652; GFX6-NEXT:    s_andn2_b32 s8, 15, s8
3653; GFX6-NEXT:    s_bfe_u32 s13, s13, 0x100000
3654; GFX6-NEXT:    s_bfe_u32 s4, s4, 0xf0001
3655; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
3656; GFX6-NEXT:    s_lshl_b32 s0, s0, s13
3657; GFX6-NEXT:    s_lshr_b32 s4, s4, s8
3658; GFX6-NEXT:    s_or_b32 s0, s0, s4
3659; GFX6-NEXT:    s_and_b32 s4, s11, 15
3660; GFX6-NEXT:    s_lshl_b32 s5, s5, 1
3661; GFX6-NEXT:    s_andn2_b32 s8, 15, s11
3662; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3663; GFX6-NEXT:    s_lshl_b32 s1, s1, s4
3664; GFX6-NEXT:    s_bfe_u32 s4, s5, 0xf0001
3665; GFX6-NEXT:    s_bfe_u32 s5, s8, 0x100000
3666; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3667; GFX6-NEXT:    s_or_b32 s1, s1, s4
3668; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3669; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3670; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
3671; GFX6-NEXT:    s_or_b32 s0, s0, s1
3672; GFX6-NEXT:    s_lshl_b32 s1, s2, s10
3673; GFX6-NEXT:    s_bfe_u32 s2, s6, 0xf0001
3674; GFX6-NEXT:    s_lshr_b32 s2, s2, s12
3675; GFX6-NEXT:    s_or_b32 s1, s1, s2
3676; GFX6-NEXT:    s_lshl_b32 s2, s3, s10
3677; GFX6-NEXT:    s_bfe_u32 s3, s7, 0xf0001
3678; GFX6-NEXT:    s_lshr_b32 s3, s3, s12
3679; GFX6-NEXT:    s_xor_b32 s5, s9, -1
3680; GFX6-NEXT:    s_or_b32 s2, s2, s3
3681; GFX6-NEXT:    s_lshl_b32 s3, s6, 1
3682; GFX6-NEXT:    s_lshl_b32 s4, s7, 1
3683; GFX6-NEXT:    s_lshr_b32 s6, s5, 16
3684; GFX6-NEXT:    s_and_b32 s7, s5, 15
3685; GFX6-NEXT:    s_andn2_b32 s5, 15, s5
3686; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
3687; GFX6-NEXT:    s_bfe_u32 s3, s3, 0xf0001
3688; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
3689; GFX6-NEXT:    s_lshl_b32 s1, s1, s7
3690; GFX6-NEXT:    s_lshr_b32 s3, s3, s5
3691; GFX6-NEXT:    s_or_b32 s1, s1, s3
3692; GFX6-NEXT:    s_and_b32 s3, s6, 15
3693; GFX6-NEXT:    s_andn2_b32 s5, 15, s6
3694; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
3695; GFX6-NEXT:    s_lshl_b32 s2, s2, s3
3696; GFX6-NEXT:    s_bfe_u32 s3, s4, 0xf0001
3697; GFX6-NEXT:    s_bfe_u32 s4, s5, 0x100000
3698; GFX6-NEXT:    s_lshr_b32 s3, s3, s4
3699; GFX6-NEXT:    s_or_b32 s2, s2, s3
3700; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3701; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3702; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
3703; GFX6-NEXT:    s_or_b32 s1, s1, s2
3704; GFX6-NEXT:    ; return to shader part epilog
3705;
3706; GFX8-LABEL: s_fshr_v4i16:
3707; GFX8:       ; %bb.0:
3708; GFX8-NEXT:    s_bfe_u32 s8, 1, 0x100000
3709; GFX8-NEXT:    s_bfe_u32 s9, s2, 0x100000
3710; GFX8-NEXT:    s_bfe_u32 s10, 15, 0x100000
3711; GFX8-NEXT:    s_lshr_b32 s6, s0, 16
3712; GFX8-NEXT:    s_lshr_b32 s7, s2, 16
3713; GFX8-NEXT:    s_lshl_b32 s0, s0, s8
3714; GFX8-NEXT:    s_lshr_b32 s9, s9, s10
3715; GFX8-NEXT:    s_or_b32 s0, s0, s9
3716; GFX8-NEXT:    s_lshl_b32 s6, s6, s8
3717; GFX8-NEXT:    s_lshr_b32 s9, s7, s10
3718; GFX8-NEXT:    s_lshl_b32 s2, s2, s8
3719; GFX8-NEXT:    s_xor_b32 s4, s4, -1
3720; GFX8-NEXT:    s_or_b32 s6, s6, s9
3721; GFX8-NEXT:    s_lshr_b32 s9, s4, 16
3722; GFX8-NEXT:    s_and_b32 s11, s4, 15
3723; GFX8-NEXT:    s_andn2_b32 s4, 15, s4
3724; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3725; GFX8-NEXT:    s_bfe_u32 s11, s11, 0x100000
3726; GFX8-NEXT:    s_lshr_b32 s2, s2, s8
3727; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3728; GFX8-NEXT:    s_lshl_b32 s0, s0, s11
3729; GFX8-NEXT:    s_lshr_b32 s2, s2, s4
3730; GFX8-NEXT:    s_or_b32 s0, s0, s2
3731; GFX8-NEXT:    s_and_b32 s2, s9, 15
3732; GFX8-NEXT:    s_lshl_b32 s7, s7, s8
3733; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3734; GFX8-NEXT:    s_andn2_b32 s4, 15, s9
3735; GFX8-NEXT:    s_lshl_b32 s2, s6, s2
3736; GFX8-NEXT:    s_bfe_u32 s6, s7, 0x100000
3737; GFX8-NEXT:    s_lshr_b32 s6, s6, s8
3738; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3739; GFX8-NEXT:    s_lshr_b32 s4, s6, s4
3740; GFX8-NEXT:    s_or_b32 s2, s2, s4
3741; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3742; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3743; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
3744; GFX8-NEXT:    s_bfe_u32 s6, s3, 0x100000
3745; GFX8-NEXT:    s_or_b32 s0, s0, s2
3746; GFX8-NEXT:    s_lshr_b32 s2, s1, 16
3747; GFX8-NEXT:    s_lshr_b32 s4, s3, 16
3748; GFX8-NEXT:    s_lshl_b32 s1, s1, s8
3749; GFX8-NEXT:    s_lshr_b32 s6, s6, s10
3750; GFX8-NEXT:    s_or_b32 s1, s1, s6
3751; GFX8-NEXT:    s_lshl_b32 s2, s2, s8
3752; GFX8-NEXT:    s_lshr_b32 s6, s4, s10
3753; GFX8-NEXT:    s_lshl_b32 s3, s3, s8
3754; GFX8-NEXT:    s_xor_b32 s5, s5, -1
3755; GFX8-NEXT:    s_or_b32 s2, s2, s6
3756; GFX8-NEXT:    s_lshr_b32 s6, s5, 16
3757; GFX8-NEXT:    s_and_b32 s7, s5, 15
3758; GFX8-NEXT:    s_andn2_b32 s5, 15, s5
3759; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
3760; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
3761; GFX8-NEXT:    s_lshr_b32 s3, s3, s8
3762; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
3763; GFX8-NEXT:    s_lshl_b32 s1, s1, s7
3764; GFX8-NEXT:    s_lshr_b32 s3, s3, s5
3765; GFX8-NEXT:    s_or_b32 s1, s1, s3
3766; GFX8-NEXT:    s_and_b32 s3, s6, 15
3767; GFX8-NEXT:    s_lshl_b32 s4, s4, s8
3768; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
3769; GFX8-NEXT:    s_andn2_b32 s5, 15, s6
3770; GFX8-NEXT:    s_lshl_b32 s2, s2, s3
3771; GFX8-NEXT:    s_bfe_u32 s3, s4, 0x100000
3772; GFX8-NEXT:    s_lshr_b32 s3, s3, s8
3773; GFX8-NEXT:    s_bfe_u32 s4, s5, 0x100000
3774; GFX8-NEXT:    s_lshr_b32 s3, s3, s4
3775; GFX8-NEXT:    s_or_b32 s2, s2, s3
3776; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3777; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3778; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
3779; GFX8-NEXT:    s_or_b32 s1, s1, s2
3780; GFX8-NEXT:    ; return to shader part epilog
3781;
3782; GFX9-LABEL: s_fshr_v4i16:
3783; GFX9:       ; %bb.0:
3784; GFX9-NEXT:    s_lshr_b32 s7, s0, 16
3785; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x10001
3786; GFX9-NEXT:    s_lshl_b32 s7, s7, 1
3787; GFX9-NEXT:    s_and_b32 s6, s4, 0xf000f
3788; GFX9-NEXT:    s_andn2_b32 s4, 0xf000f, s4
3789; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s7
3790; GFX9-NEXT:    s_lshr_b32 s7, s0, 16
3791; GFX9-NEXT:    s_lshr_b32 s8, s4, 16
3792; GFX9-NEXT:    s_lshl_b32 s0, s0, s4
3793; GFX9-NEXT:    s_lshl_b32 s4, s7, s8
3794; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
3795; GFX9-NEXT:    s_lshr_b32 s4, s2, 16
3796; GFX9-NEXT:    s_and_b32 s2, s2, 0xffff
3797; GFX9-NEXT:    s_lshr_b32 s7, s6, 16
3798; GFX9-NEXT:    s_lshr_b32 s2, s2, s6
3799; GFX9-NEXT:    s_lshr_b32 s4, s4, s7
3800; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s4
3801; GFX9-NEXT:    s_or_b32 s0, s0, s2
3802; GFX9-NEXT:    s_and_b32 s2, s5, 0xf000f
3803; GFX9-NEXT:    s_andn2_b32 s4, 0xf000f, s5
3804; GFX9-NEXT:    s_lshr_b32 s5, s1, 16
3805; GFX9-NEXT:    s_lshl_b32 s1, s1, 0x10001
3806; GFX9-NEXT:    s_lshl_b32 s5, s5, 1
3807; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s5
3808; GFX9-NEXT:    s_lshr_b32 s5, s1, 16
3809; GFX9-NEXT:    s_lshr_b32 s6, s4, 16
3810; GFX9-NEXT:    s_lshl_b32 s1, s1, s4
3811; GFX9-NEXT:    s_lshl_b32 s4, s5, s6
3812; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
3813; GFX9-NEXT:    s_lshr_b32 s4, s3, 16
3814; GFX9-NEXT:    s_and_b32 s3, s3, 0xffff
3815; GFX9-NEXT:    s_lshr_b32 s5, s2, 16
3816; GFX9-NEXT:    s_lshr_b32 s2, s3, s2
3817; GFX9-NEXT:    s_lshr_b32 s3, s4, s5
3818; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
3819; GFX9-NEXT:    s_or_b32 s1, s1, s2
3820; GFX9-NEXT:    ; return to shader part epilog
3821;
3822; GFX10-LABEL: s_fshr_v4i16:
3823; GFX10:       ; %bb.0:
3824; GFX10-NEXT:    s_lshr_b32 s6, s0, 16
3825; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x10001
3826; GFX10-NEXT:    s_lshl_b32 s6, s6, 1
3827; GFX10-NEXT:    s_and_b32 s7, s4, 0xf000f
3828; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s6
3829; GFX10-NEXT:    s_andn2_b32 s4, 0xf000f, s4
3830; GFX10-NEXT:    s_lshr_b32 s6, s0, 16
3831; GFX10-NEXT:    s_lshr_b32 s8, s4, 16
3832; GFX10-NEXT:    s_lshl_b32 s0, s0, s4
3833; GFX10-NEXT:    s_lshl_b32 s4, s6, s8
3834; GFX10-NEXT:    s_lshr_b32 s6, s2, 16
3835; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s4
3836; GFX10-NEXT:    s_lshr_b32 s4, s1, 16
3837; GFX10-NEXT:    s_and_b32 s2, s2, 0xffff
3838; GFX10-NEXT:    s_lshr_b32 s8, s7, 16
3839; GFX10-NEXT:    s_lshl_b32 s1, s1, 0x10001
3840; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
3841; GFX10-NEXT:    s_lshr_b32 s2, s2, s7
3842; GFX10-NEXT:    s_lshr_b32 s6, s6, s8
3843; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
3844; GFX10-NEXT:    s_andn2_b32 s4, 0xf000f, s5
3845; GFX10-NEXT:    s_pack_ll_b32_b16 s2, s2, s6
3846; GFX10-NEXT:    s_and_b32 s6, s5, 0xf000f
3847; GFX10-NEXT:    s_lshr_b32 s5, s1, 16
3848; GFX10-NEXT:    s_lshr_b32 s7, s4, 16
3849; GFX10-NEXT:    s_lshl_b32 s1, s1, s4
3850; GFX10-NEXT:    s_lshl_b32 s4, s5, s7
3851; GFX10-NEXT:    s_lshr_b32 s5, s3, 16
3852; GFX10-NEXT:    s_and_b32 s3, s3, 0xffff
3853; GFX10-NEXT:    s_lshr_b32 s7, s6, 16
3854; GFX10-NEXT:    s_lshr_b32 s3, s3, s6
3855; GFX10-NEXT:    s_lshr_b32 s5, s5, s7
3856; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
3857; GFX10-NEXT:    s_pack_ll_b32_b16 s3, s3, s5
3858; GFX10-NEXT:    s_or_b32 s0, s0, s2
3859; GFX10-NEXT:    s_or_b32 s1, s1, s3
3860; GFX10-NEXT:    ; return to shader part epilog
3861  %result = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
3862  %cast.result = bitcast <4 x i16> %result to <2 x i32>
3863  ret <2 x i32> %cast.result
3864}
3865
3866define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt) {
3867; GFX6-LABEL: v_fshr_v4i16:
3868; GFX6:       ; %bb.0:
3869; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3870; GFX6-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
3871; GFX6-NEXT:    v_and_b32_e32 v8, 0xffff, v8
3872; GFX6-NEXT:    v_or_b32_e32 v8, v9, v8
3873; GFX6-NEXT:    v_lshlrev_b32_e32 v9, 16, v11
3874; GFX6-NEXT:    v_and_b32_e32 v10, 0xffff, v10
3875; GFX6-NEXT:    v_or_b32_e32 v9, v9, v10
3876; GFX6-NEXT:    s_bfe_u32 s4, 1, 0x100000
3877; GFX6-NEXT:    v_bfe_u32 v10, v4, 1, 15
3878; GFX6-NEXT:    s_bfe_u32 s5, 14, 0x100000
3879; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
3880; GFX6-NEXT:    v_lshrrev_b32_e32 v10, s5, v10
3881; GFX6-NEXT:    v_or_b32_e32 v0, v0, v10
3882; GFX6-NEXT:    v_bfe_u32 v10, v5, 1, 15
3883; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s4, v1
3884; GFX6-NEXT:    v_lshrrev_b32_e32 v10, s5, v10
3885; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
3886; GFX6-NEXT:    v_or_b32_e32 v1, v1, v10
3887; GFX6-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
3888; GFX6-NEXT:    v_and_b32_e32 v11, 15, v8
3889; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
3890; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v4
3891; GFX6-NEXT:    v_and_b32_e32 v8, 15, v8
3892; GFX6-NEXT:    v_bfe_u32 v11, v11, 0, 16
3893; GFX6-NEXT:    v_bfe_u32 v4, v4, 1, 15
3894; GFX6-NEXT:    v_bfe_u32 v8, v8, 0, 16
3895; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v11, v0
3896; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v8, v4
3897; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
3898; GFX6-NEXT:    v_and_b32_e32 v4, 15, v10
3899; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v10
3900; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 1, v5
3901; GFX6-NEXT:    v_and_b32_e32 v8, 15, v8
3902; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
3903; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
3904; GFX6-NEXT:    v_bfe_u32 v4, v5, 1, 15
3905; GFX6-NEXT:    v_bfe_u32 v5, v8, 0, 16
3906; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
3907; GFX6-NEXT:    v_or_b32_e32 v1, v1, v4
3908; GFX6-NEXT:    v_bfe_u32 v4, v6, 1, 15
3909; GFX6-NEXT:    v_lshlrev_b32_e32 v2, s4, v2
3910; GFX6-NEXT:    v_lshrrev_b32_e32 v4, s5, v4
3911; GFX6-NEXT:    v_or_b32_e32 v2, v2, v4
3912; GFX6-NEXT:    v_bfe_u32 v4, v7, 1, 15
3913; GFX6-NEXT:    v_lshlrev_b32_e32 v3, s4, v3
3914; GFX6-NEXT:    v_lshrrev_b32_e32 v4, s5, v4
3915; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
3916; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 1, v6
3917; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v9
3918; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 1, v7
3919; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
3920; GFX6-NEXT:    v_and_b32_e32 v8, 15, v6
3921; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v6
3922; GFX6-NEXT:    v_and_b32_e32 v6, 15, v6
3923; GFX6-NEXT:    v_bfe_u32 v8, v8, 0, 16
3924; GFX6-NEXT:    v_bfe_u32 v4, v4, 1, 15
3925; GFX6-NEXT:    v_bfe_u32 v6, v6, 0, 16
3926; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v8, v2
3927; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v6, v4
3928; GFX6-NEXT:    v_or_b32_e32 v2, v2, v4
3929; GFX6-NEXT:    v_and_b32_e32 v4, 15, v7
3930; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v7
3931; GFX6-NEXT:    v_and_b32_e32 v6, 15, v6
3932; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
3933; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v4, v3
3934; GFX6-NEXT:    v_bfe_u32 v4, v5, 1, 15
3935; GFX6-NEXT:    v_bfe_u32 v5, v6, 0, 16
3936; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
3937; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
3938; GFX6-NEXT:    s_setpc_b64 s[30:31]
3939;
3940; GFX8-LABEL: v_fshr_v4i16:
3941; GFX8:       ; %bb.0:
3942; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3943; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 1, v0
3944; GFX8-NEXT:    v_lshrrev_b16_e32 v7, 15, v2
3945; GFX8-NEXT:    v_or_b32_e32 v6, v6, v7
3946; GFX8-NEXT:    v_mov_b32_e32 v7, 1
3947; GFX8-NEXT:    v_mov_b32_e32 v8, 15
3948; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3949; GFX8-NEXT:    v_lshrrev_b16_sdwa v9, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3950; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
3951; GFX8-NEXT:    v_or_b32_e32 v0, v0, v9
3952; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 1, v2
3953; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3954; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
3955; GFX8-NEXT:    v_and_b32_e32 v10, 15, v4
3956; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
3957; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
3958; GFX8-NEXT:    v_lshrrev_b16_e32 v9, 1, v9
3959; GFX8-NEXT:    v_lshlrev_b16_e32 v6, v10, v6
3960; GFX8-NEXT:    v_lshrrev_b16_e32 v4, v4, v9
3961; GFX8-NEXT:    v_or_b32_e32 v4, v6, v4
3962; GFX8-NEXT:    v_and_b32_e32 v6, 15, v7
3963; GFX8-NEXT:    v_xor_b32_e32 v7, -1, v7
3964; GFX8-NEXT:    v_and_b32_e32 v7, 15, v7
3965; GFX8-NEXT:    v_lshrrev_b16_e32 v2, 1, v2
3966; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v6, v0
3967; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v7, v2
3968; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
3969; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3970; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3971; GFX8-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3972; GFX8-NEXT:    v_lshlrev_b16_e32 v4, 1, v1
3973; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 15, v3
3974; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
3975; GFX8-NEXT:    v_mov_b32_e32 v6, 1
3976; GFX8-NEXT:    v_lshlrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3977; GFX8-NEXT:    v_lshrrev_b16_sdwa v7, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3978; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
3979; GFX8-NEXT:    v_or_b32_e32 v1, v1, v7
3980; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 1, v3
3981; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3982; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
3983; GFX8-NEXT:    v_and_b32_e32 v8, 15, v5
3984; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
3985; GFX8-NEXT:    v_and_b32_e32 v5, 15, v5
3986; GFX8-NEXT:    v_lshrrev_b16_e32 v7, 1, v7
3987; GFX8-NEXT:    v_lshlrev_b16_e32 v4, v8, v4
3988; GFX8-NEXT:    v_lshrrev_b16_e32 v5, v5, v7
3989; GFX8-NEXT:    v_or_b32_e32 v4, v4, v5
3990; GFX8-NEXT:    v_and_b32_e32 v5, 15, v6
3991; GFX8-NEXT:    v_xor_b32_e32 v6, -1, v6
3992; GFX8-NEXT:    v_and_b32_e32 v6, 15, v6
3993; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 1, v3
3994; GFX8-NEXT:    v_lshlrev_b16_e32 v1, v5, v1
3995; GFX8-NEXT:    v_lshrrev_b16_e32 v3, v6, v3
3996; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
3997; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3998; GFX8-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3999; GFX8-NEXT:    s_setpc_b64 s[30:31]
4000;
4001; GFX9-LABEL: v_fshr_v4i16:
4002; GFX9:       ; %bb.0:
4003; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4004; GFX9-NEXT:    v_and_b32_e32 v6, 0xf000f, v4
4005; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
4006; GFX9-NEXT:    v_and_b32_e32 v4, 0xf000f, v4
4007; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
4008; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v4, v0
4009; GFX9-NEXT:    v_pk_lshrrev_b16 v2, v6, v2
4010; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v5
4011; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4012; GFX9-NEXT:    v_and_b32_e32 v2, 0xf000f, v5
4013; GFX9-NEXT:    v_and_b32_e32 v4, 0xf000f, v4
4014; GFX9-NEXT:    v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
4015; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v4, v1
4016; GFX9-NEXT:    v_pk_lshrrev_b16 v2, v2, v3
4017; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
4018; GFX9-NEXT:    s_setpc_b64 s[30:31]
4019;
4020; GFX10-LABEL: v_fshr_v4i16:
4021; GFX10:       ; %bb.0:
4022; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4023; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4024; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v4
4025; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v5
4026; GFX10-NEXT:    v_and_b32_e32 v4, 0xf000f, v4
4027; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
4028; GFX10-NEXT:    v_and_b32_e32 v5, 0xf000f, v5
4029; GFX10-NEXT:    v_and_b32_e32 v6, 0xf000f, v6
4030; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
4031; GFX10-NEXT:    v_and_b32_e32 v7, 0xf000f, v7
4032; GFX10-NEXT:    v_pk_lshrrev_b16 v2, v4, v2
4033; GFX10-NEXT:    v_pk_lshrrev_b16 v3, v5, v3
4034; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v6, v0
4035; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v7, v1
4036; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4037; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4038; GFX10-NEXT:    s_setpc_b64 s[30:31]
4039  %result = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
4040  %cast.result = bitcast <4 x i16> %result to <4 x half>
4041  ret <4 x half> %cast.result
4042}
4043
4044define amdgpu_ps i64 @s_fshr_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt) {
4045; GFX6-LABEL: s_fshr_i64:
4046; GFX6:       ; %bb.0:
4047; GFX6-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4048; GFX6-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4049; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4050; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4051; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], s6
4052; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4053; GFX6-NEXT:    ; return to shader part epilog
4054;
4055; GFX8-LABEL: s_fshr_i64:
4056; GFX8:       ; %bb.0:
4057; GFX8-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4058; GFX8-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4059; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4060; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4061; GFX8-NEXT:    s_lshr_b64 s[2:3], s[2:3], s6
4062; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4063; GFX8-NEXT:    ; return to shader part epilog
4064;
4065; GFX9-LABEL: s_fshr_i64:
4066; GFX9:       ; %bb.0:
4067; GFX9-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4068; GFX9-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4069; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4070; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4071; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s6
4072; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4073; GFX9-NEXT:    ; return to shader part epilog
4074;
4075; GFX10-LABEL: s_fshr_i64:
4076; GFX10:       ; %bb.0:
4077; GFX10-NEXT:    s_andn2_b64 s[6:7], 63, s[4:5]
4078; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4079; GFX10-NEXT:    s_and_b64 s[4:5], s[4:5], 63
4080; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s6
4081; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s4
4082; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4083; GFX10-NEXT:    ; return to shader part epilog
4084  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4085  ret i64 %result
4086}
4087
4088define amdgpu_ps i64 @s_fshr_i64_5(i64 inreg %lhs, i64 inreg %rhs) {
4089; GCN-LABEL: s_fshr_i64_5:
4090; GCN:       ; %bb.0:
4091; GCN-NEXT:    s_lshl_b32 s1, s0, 27
4092; GCN-NEXT:    s_mov_b32 s0, 0
4093; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], 5
4094; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4095; GCN-NEXT:    ; return to shader part epilog
4096  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5)
4097  ret i64 %result
4098}
4099
4100define amdgpu_ps i64 @s_fshr_i64_32(i64 inreg %lhs, i64 inreg %rhs) {
4101; GCN-LABEL: s_fshr_i64_32:
4102; GCN:       ; %bb.0:
4103; GCN-NEXT:    s_mov_b32 s1, s0
4104; GCN-NEXT:    s_mov_b32 s0, 0
4105; GCN-NEXT:    s_mov_b32 s2, s3
4106; GCN-NEXT:    s_mov_b32 s3, s0
4107; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4108; GCN-NEXT:    ; return to shader part epilog
4109  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 32)
4110  ret i64 %result
4111}
4112
4113define amdgpu_ps i64 @s_fshr_i64_48(i64 inreg %lhs, i64 inreg %rhs) {
4114; GCN-LABEL: s_fshr_i64_48:
4115; GCN:       ; %bb.0:
4116; GCN-NEXT:    s_lshl_b64 s[0:1], s[0:1], 16
4117; GCN-NEXT:    s_lshr_b32 s2, s3, 16
4118; GCN-NEXT:    s_mov_b32 s3, 0
4119; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4120; GCN-NEXT:    ; return to shader part epilog
4121  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 48)
4122  ret i64 %result
4123}
4124
4125define i64 @v_fshr_i64(i64 %lhs, i64 %rhs, i64 %amt) {
4126; GFX6-LABEL: v_fshr_i64:
4127; GFX6:       ; %bb.0:
4128; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4129; GFX6-NEXT:    v_and_b32_e32 v5, 63, v4
4130; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
4131; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
4132; GFX6-NEXT:    v_and_b32_e32 v4, 63, v4
4133; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
4134; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], v5
4135; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4136; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
4137; GFX6-NEXT:    s_setpc_b64 s[30:31]
4138;
4139; GFX8-LABEL: v_fshr_i64:
4140; GFX8:       ; %bb.0:
4141; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4142; GFX8-NEXT:    v_and_b32_e32 v5, 63, v4
4143; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
4144; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4145; GFX8-NEXT:    v_and_b32_e32 v4, 63, v4
4146; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
4147; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
4148; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4149; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4150; GFX8-NEXT:    s_setpc_b64 s[30:31]
4151;
4152; GFX9-LABEL: v_fshr_i64:
4153; GFX9:       ; %bb.0:
4154; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4155; GFX9-NEXT:    v_and_b32_e32 v5, 63, v4
4156; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
4157; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4158; GFX9-NEXT:    v_and_b32_e32 v4, 63, v4
4159; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
4160; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
4161; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4162; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
4163; GFX9-NEXT:    s_setpc_b64 s[30:31]
4164;
4165; GFX10-LABEL: v_fshr_i64:
4166; GFX10:       ; %bb.0:
4167; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4168; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4169; GFX10-NEXT:    v_xor_b32_e32 v5, -1, v4
4170; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4171; GFX10-NEXT:    v_and_b32_e32 v4, 63, v4
4172; GFX10-NEXT:    v_and_b32_e32 v5, 63, v5
4173; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]
4174; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v5, v[0:1]
4175; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4176; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4177; GFX10-NEXT:    s_setpc_b64 s[30:31]
4178  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4179  ret i64 %result
4180}
4181
4182define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
4183; GFX6-LABEL: v_fshr_i64_5:
4184; GFX6:       ; %bb.0:
4185; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4186; GFX6-NEXT:    v_mov_b32_e32 v4, v0
4187; GFX6-NEXT:    v_lshr_b64 v[0:1], v[2:3], 5
4188; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4189; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
4190; GFX6-NEXT:    s_setpc_b64 s[30:31]
4191;
4192; GFX8-LABEL: v_fshr_i64_5:
4193; GFX8:       ; %bb.0:
4194; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4195; GFX8-NEXT:    v_mov_b32_e32 v4, v0
4196; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 5, v[2:3]
4197; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4198; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
4199; GFX8-NEXT:    s_setpc_b64 s[30:31]
4200;
4201; GFX9-LABEL: v_fshr_i64_5:
4202; GFX9:       ; %bb.0:
4203; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4204; GFX9-NEXT:    v_mov_b32_e32 v4, v0
4205; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 5, v[2:3]
4206; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4207; GFX9-NEXT:    v_or_b32_e32 v1, v2, v1
4208; GFX9-NEXT:    s_setpc_b64 s[30:31]
4209;
4210; GFX10-LABEL: v_fshr_i64_5:
4211; GFX10:       ; %bb.0:
4212; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4213; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4214; GFX10-NEXT:    v_mov_b32_e32 v4, v0
4215; GFX10-NEXT:    v_lshrrev_b64 v[0:1], 5, v[2:3]
4216; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 27, v4
4217; GFX10-NEXT:    v_or_b32_e32 v1, v2, v1
4218; GFX10-NEXT:    s_setpc_b64 s[30:31]
4219  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5)
4220  ret i64 %result
4221}
4222
4223define i64 @v_fshr_i64_32(i64 %lhs, i64 %rhs) {
4224; GFX6-LABEL: v_fshr_i64_32:
4225; GFX6:       ; %bb.0:
4226; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4227; GFX6-NEXT:    v_mov_b32_e32 v1, v0
4228; GFX6-NEXT:    v_mov_b32_e32 v0, v3
4229; GFX6-NEXT:    s_setpc_b64 s[30:31]
4230;
4231; GFX8-LABEL: v_fshr_i64_32:
4232; GFX8:       ; %bb.0:
4233; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4234; GFX8-NEXT:    v_mov_b32_e32 v1, v0
4235; GFX8-NEXT:    v_mov_b32_e32 v0, v3
4236; GFX8-NEXT:    s_setpc_b64 s[30:31]
4237;
4238; GFX9-LABEL: v_fshr_i64_32:
4239; GFX9:       ; %bb.0:
4240; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4241; GFX9-NEXT:    v_mov_b32_e32 v1, v0
4242; GFX9-NEXT:    v_mov_b32_e32 v0, v3
4243; GFX9-NEXT:    s_setpc_b64 s[30:31]
4244;
4245; GFX10-LABEL: v_fshr_i64_32:
4246; GFX10:       ; %bb.0:
4247; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4248; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4249; GFX10-NEXT:    v_mov_b32_e32 v1, v0
4250; GFX10-NEXT:    v_mov_b32_e32 v0, v3
4251; GFX10-NEXT:    s_setpc_b64 s[30:31]
4252  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 32)
4253  ret i64 %result
4254}
4255
4256define i64 @v_fshr_i64_48(i64 %lhs, i64 %rhs) {
4257; GFX6-LABEL: v_fshr_i64_48:
4258; GFX6:       ; %bb.0:
4259; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4260; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 16
4261; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
4262; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4263; GFX6-NEXT:    s_setpc_b64 s[30:31]
4264;
4265; GFX8-LABEL: v_fshr_i64_48:
4266; GFX8:       ; %bb.0:
4267; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4268; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]
4269; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4270; GFX8-NEXT:    s_setpc_b64 s[30:31]
4271;
4272; GFX9-LABEL: v_fshr_i64_48:
4273; GFX9:       ; %bb.0:
4274; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4275; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]
4276; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4277; GFX9-NEXT:    s_setpc_b64 s[30:31]
4278;
4279; GFX10-LABEL: v_fshr_i64_48:
4280; GFX10:       ; %bb.0:
4281; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4282; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4283; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]
4284; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4285; GFX10-NEXT:    s_setpc_b64 s[30:31]
4286  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 48)
4287  ret i64 %result
4288}
4289
4290define amdgpu_ps <2 x float> @v_fshr_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64 %amt) {
4291; GFX6-LABEL: v_fshr_i64_ssv:
4292; GFX6:       ; %bb.0:
4293; GFX6-NEXT:    v_and_b32_e32 v2, 63, v0
4294; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
4295; GFX6-NEXT:    v_and_b32_e32 v0, 63, v0
4296; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4297; GFX6-NEXT:    v_lshl_b64 v[0:1], s[0:1], v0
4298; GFX6-NEXT:    v_lshr_b64 v[2:3], s[2:3], v2
4299; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4300; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
4301; GFX6-NEXT:    ; return to shader part epilog
4302;
4303; GFX8-LABEL: v_fshr_i64_ssv:
4304; GFX8:       ; %bb.0:
4305; GFX8-NEXT:    v_and_b32_e32 v2, 63, v0
4306; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
4307; GFX8-NEXT:    v_and_b32_e32 v0, 63, v0
4308; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4309; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v0, s[0:1]
4310; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v2, s[2:3]
4311; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4312; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4313; GFX8-NEXT:    ; return to shader part epilog
4314;
4315; GFX9-LABEL: v_fshr_i64_ssv:
4316; GFX9:       ; %bb.0:
4317; GFX9-NEXT:    v_and_b32_e32 v2, 63, v0
4318; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
4319; GFX9-NEXT:    v_and_b32_e32 v0, 63, v0
4320; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4321; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v0, s[0:1]
4322; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v2, s[2:3]
4323; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4324; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
4325; GFX9-NEXT:    ; return to shader part epilog
4326;
4327; GFX10-LABEL: v_fshr_i64_ssv:
4328; GFX10:       ; %bb.0:
4329; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
4330; GFX10-NEXT:    v_and_b32_e32 v0, 63, v0
4331; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4332; GFX10-NEXT:    v_and_b32_e32 v2, 63, v1
4333; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v0, s[2:3]
4334; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v2, s[0:1]
4335; GFX10-NEXT:    v_or_b32_e32 v0, v2, v0
4336; GFX10-NEXT:    v_or_b32_e32 v1, v3, v1
4337; GFX10-NEXT:    ; return to shader part epilog
4338  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4339  %cast = bitcast i64 %result to <2 x float>
4340  ret <2 x float> %cast
4341}
4342
4343define amdgpu_ps <2 x float> @v_fshr_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg %amt) {
4344; GFX6-LABEL: v_fshr_i64_svs:
4345; GFX6:       ; %bb.0:
4346; GFX6-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4347; GFX6-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4348; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4349; GFX6-NEXT:    v_lshr_b64 v[0:1], v[0:1], s4
4350; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4351; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
4352; GFX6-NEXT:    v_or_b32_e32 v1, s1, v1
4353; GFX6-NEXT:    ; return to shader part epilog
4354;
4355; GFX8-LABEL: v_fshr_i64_svs:
4356; GFX8:       ; %bb.0:
4357; GFX8-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4358; GFX8-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4359; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4360; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4361; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4362; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
4363; GFX8-NEXT:    v_or_b32_e32 v1, s1, v1
4364; GFX8-NEXT:    ; return to shader part epilog
4365;
4366; GFX9-LABEL: v_fshr_i64_svs:
4367; GFX9:       ; %bb.0:
4368; GFX9-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4369; GFX9-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4370; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4371; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4372; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4373; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
4374; GFX9-NEXT:    v_or_b32_e32 v1, s1, v1
4375; GFX9-NEXT:    ; return to shader part epilog
4376;
4377; GFX10-LABEL: v_fshr_i64_svs:
4378; GFX10:       ; %bb.0:
4379; GFX10-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4380; GFX10-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4381; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4382; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4383; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4384; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
4385; GFX10-NEXT:    v_or_b32_e32 v1, s1, v1
4386; GFX10-NEXT:    ; return to shader part epilog
4387  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4388  %cast = bitcast i64 %result to <2 x float>
4389  ret <2 x float> %cast
4390}
4391
4392define amdgpu_ps <2 x float> @v_fshr_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg %amt) {
4393; GFX6-LABEL: v_fshr_i64_vss:
4394; GFX6:       ; %bb.0:
4395; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
4396; GFX6-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4397; GFX6-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4398; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s2
4399; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
4400; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
4401; GFX6-NEXT:    v_or_b32_e32 v1, s1, v1
4402; GFX6-NEXT:    ; return to shader part epilog
4403;
4404; GFX8-LABEL: v_fshr_i64_vss:
4405; GFX8:       ; %bb.0:
4406; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4407; GFX8-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4408; GFX8-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4409; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s2, v[0:1]
4410; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
4411; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
4412; GFX8-NEXT:    v_or_b32_e32 v1, s1, v1
4413; GFX8-NEXT:    ; return to shader part epilog
4414;
4415; GFX9-LABEL: v_fshr_i64_vss:
4416; GFX9:       ; %bb.0:
4417; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4418; GFX9-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4419; GFX9-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4420; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s2, v[0:1]
4421; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s4
4422; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
4423; GFX9-NEXT:    v_or_b32_e32 v1, s1, v1
4424; GFX9-NEXT:    ; return to shader part epilog
4425;
4426; GFX10-LABEL: v_fshr_i64_vss:
4427; GFX10:       ; %bb.0:
4428; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4429; GFX10-NEXT:    s_andn2_b64 s[4:5], 63, s[2:3]
4430; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], 63
4431; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
4432; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
4433; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
4434; GFX10-NEXT:    v_or_b32_e32 v1, s1, v1
4435; GFX10-NEXT:    ; return to shader part epilog
4436  %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 %amt)
4437  %cast = bitcast i64 %result to <2 x float>
4438  ret <2 x float> %cast
4439}
4440
4441define amdgpu_ps <2 x i64> @s_fshr_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs, <2 x i64> inreg %amt) {
4442; GFX6-LABEL: s_fshr_v2i64:
4443; GFX6:       ; %bb.0:
4444; GFX6-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4445; GFX6-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4446; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4447; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
4448; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], s12
4449; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4450; GFX6-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4451; GFX6-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4452; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4453; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4454; GFX6-NEXT:    s_lshr_b64 s[4:5], s[6:7], s4
4455; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4456; GFX6-NEXT:    ; return to shader part epilog
4457;
4458; GFX8-LABEL: s_fshr_v2i64:
4459; GFX8:       ; %bb.0:
4460; GFX8-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4461; GFX8-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4462; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4463; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
4464; GFX8-NEXT:    s_lshr_b64 s[4:5], s[4:5], s12
4465; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4466; GFX8-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4467; GFX8-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4468; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4469; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4470; GFX8-NEXT:    s_lshr_b64 s[4:5], s[6:7], s4
4471; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4472; GFX8-NEXT:    ; return to shader part epilog
4473;
4474; GFX9-LABEL: s_fshr_v2i64:
4475; GFX9:       ; %bb.0:
4476; GFX9-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4477; GFX9-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4478; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4479; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s8
4480; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s12
4481; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4482; GFX9-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4483; GFX9-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4484; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4485; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4486; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], s4
4487; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4488; GFX9-NEXT:    ; return to shader part epilog
4489;
4490; GFX10-LABEL: s_fshr_v2i64:
4491; GFX10:       ; %bb.0:
4492; GFX10-NEXT:    s_andn2_b64 s[12:13], 63, s[8:9]
4493; GFX10-NEXT:    s_and_b64 s[8:9], s[8:9], 63
4494; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4495; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4496; GFX10-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4497; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4498; GFX10-NEXT:    s_and_b64 s[10:11], s[10:11], 63
4499; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s12
4500; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4501; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s10
4502; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4503; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
4504; GFX10-NEXT:    ; return to shader part epilog
4505  %result = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
4506  ret <2 x i64> %result
4507}
4508
4509define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
4510; GFX6-LABEL: v_fshr_v2i64:
4511; GFX6:       ; %bb.0:
4512; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4513; GFX6-NEXT:    v_and_b32_e32 v9, 63, v8
4514; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4515; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
4516; GFX6-NEXT:    v_and_b32_e32 v8, 63, v8
4517; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v8
4518; GFX6-NEXT:    v_lshr_b64 v[4:5], v[4:5], v9
4519; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v10
4520; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
4521; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
4522; GFX6-NEXT:    v_and_b32_e32 v4, 63, v10
4523; GFX6-NEXT:    v_and_b32_e32 v8, 63, v8
4524; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], v8
4525; GFX6-NEXT:    v_lshr_b64 v[6:7], v[6:7], v4
4526; GFX6-NEXT:    v_or_b32_e32 v1, v1, v5
4527; GFX6-NEXT:    v_or_b32_e32 v2, v2, v6
4528; GFX6-NEXT:    v_or_b32_e32 v3, v3, v7
4529; GFX6-NEXT:    s_setpc_b64 s[30:31]
4530;
4531; GFX8-LABEL: v_fshr_v2i64:
4532; GFX8:       ; %bb.0:
4533; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4534; GFX8-NEXT:    v_and_b32_e32 v9, 63, v8
4535; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
4536; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4537; GFX8-NEXT:    v_and_b32_e32 v8, 63, v8
4538; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
4539; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
4540; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v10
4541; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4542; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
4543; GFX8-NEXT:    v_and_b32_e32 v4, 63, v10
4544; GFX8-NEXT:    v_and_b32_e32 v8, 63, v8
4545; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v8, v[2:3]
4546; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v4, v[6:7]
4547; GFX8-NEXT:    v_or_b32_e32 v1, v1, v5
4548; GFX8-NEXT:    v_or_b32_e32 v2, v2, v6
4549; GFX8-NEXT:    v_or_b32_e32 v3, v3, v7
4550; GFX8-NEXT:    s_setpc_b64 s[30:31]
4551;
4552; GFX9-LABEL: v_fshr_v2i64:
4553; GFX9:       ; %bb.0:
4554; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4555; GFX9-NEXT:    v_and_b32_e32 v9, 63, v8
4556; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
4557; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4558; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
4559; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
4560; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
4561; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v10
4562; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4563; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
4564; GFX9-NEXT:    v_and_b32_e32 v4, 63, v10
4565; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
4566; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v8, v[2:3]
4567; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v4, v[6:7]
4568; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
4569; GFX9-NEXT:    v_or_b32_e32 v2, v2, v6
4570; GFX9-NEXT:    v_or_b32_e32 v3, v3, v7
4571; GFX9-NEXT:    s_setpc_b64 s[30:31]
4572;
4573; GFX10-LABEL: v_fshr_v2i64:
4574; GFX10:       ; %bb.0:
4575; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4576; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4577; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v8
4578; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v10
4579; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4580; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4581; GFX10-NEXT:    v_and_b32_e32 v8, 63, v8
4582; GFX10-NEXT:    v_and_b32_e32 v9, 63, v9
4583; GFX10-NEXT:    v_and_b32_e32 v11, 63, v11
4584; GFX10-NEXT:    v_and_b32_e32 v10, 63, v10
4585; GFX10-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]
4586; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v9, v[0:1]
4587; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v11, v[2:3]
4588; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v10, v[6:7]
4589; GFX10-NEXT:    v_or_b32_e32 v0, v0, v4
4590; GFX10-NEXT:    v_or_b32_e32 v1, v1, v5
4591; GFX10-NEXT:    v_or_b32_e32 v2, v2, v6
4592; GFX10-NEXT:    v_or_b32_e32 v3, v3, v7
4593; GFX10-NEXT:    s_setpc_b64 s[30:31]
4594  %result = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
4595  ret <2 x i64> %result
4596}
4597
4598define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg %amt) {
4599; GFX6-LABEL: s_fshr_i128:
4600; GFX6:       ; %bb.0:
4601; GFX6-NEXT:    s_movk_i32 s10, 0x7f
4602; GFX6-NEXT:    s_mov_b32 s11, 0
4603; GFX6-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4604; GFX6-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4605; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4606; GFX6-NEXT:    s_lshr_b32 s10, s1, 31
4607; GFX6-NEXT:    s_lshl_b64 s[14:15], s[0:1], 1
4608; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[10:11]
4609; GFX6-NEXT:    s_sub_i32 s13, s8, 64
4610; GFX6-NEXT:    s_sub_i32 s9, 64, s8
4611; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
4612; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4613; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
4614; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
4615; GFX6-NEXT:    s_lshl_b64 s[2:3], s[14:15], s8
4616; GFX6-NEXT:    s_lshr_b64 s[10:11], s[14:15], s9
4617; GFX6-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
4618; GFX6-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
4619; GFX6-NEXT:    s_lshl_b64 s[10:11], s[14:15], s13
4620; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4621; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
4622; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
4623; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
4624; GFX6-NEXT:    s_cselect_b64 s[8:9], s[0:1], s[8:9]
4625; GFX6-NEXT:    s_sub_i32 s14, s12, 64
4626; GFX6-NEXT:    s_sub_i32 s13, 64, s12
4627; GFX6-NEXT:    s_cmp_lt_u32 s12, 64
4628; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
4629; GFX6-NEXT:    s_cmp_eq_u32 s12, 0
4630; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4631; GFX6-NEXT:    s_lshr_b64 s[0:1], s[6:7], s12
4632; GFX6-NEXT:    s_lshr_b64 s[10:11], s[4:5], s12
4633; GFX6-NEXT:    s_lshl_b64 s[12:13], s[6:7], s13
4634; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
4635; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
4636; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
4637; GFX6-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
4638; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4639; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4640; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
4641; GFX6-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
4642; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
4643; GFX6-NEXT:    s_or_b64 s[2:3], s[8:9], s[6:7]
4644; GFX6-NEXT:    ; return to shader part epilog
4645;
4646; GFX8-LABEL: s_fshr_i128:
4647; GFX8:       ; %bb.0:
4648; GFX8-NEXT:    s_movk_i32 s10, 0x7f
4649; GFX8-NEXT:    s_mov_b32 s11, 0
4650; GFX8-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4651; GFX8-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4652; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4653; GFX8-NEXT:    s_lshr_b32 s10, s1, 31
4654; GFX8-NEXT:    s_lshl_b64 s[14:15], s[0:1], 1
4655; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[10:11]
4656; GFX8-NEXT:    s_sub_i32 s13, s8, 64
4657; GFX8-NEXT:    s_sub_i32 s9, 64, s8
4658; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
4659; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4660; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
4661; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
4662; GFX8-NEXT:    s_lshl_b64 s[2:3], s[14:15], s8
4663; GFX8-NEXT:    s_lshr_b64 s[10:11], s[14:15], s9
4664; GFX8-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
4665; GFX8-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
4666; GFX8-NEXT:    s_lshl_b64 s[10:11], s[14:15], s13
4667; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4668; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
4669; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
4670; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
4671; GFX8-NEXT:    s_cselect_b64 s[8:9], s[0:1], s[8:9]
4672; GFX8-NEXT:    s_sub_i32 s14, s12, 64
4673; GFX8-NEXT:    s_sub_i32 s13, 64, s12
4674; GFX8-NEXT:    s_cmp_lt_u32 s12, 64
4675; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
4676; GFX8-NEXT:    s_cmp_eq_u32 s12, 0
4677; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4678; GFX8-NEXT:    s_lshr_b64 s[0:1], s[6:7], s12
4679; GFX8-NEXT:    s_lshr_b64 s[10:11], s[4:5], s12
4680; GFX8-NEXT:    s_lshl_b64 s[12:13], s[6:7], s13
4681; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
4682; GFX8-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
4683; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
4684; GFX8-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
4685; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4686; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4687; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
4688; GFX8-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
4689; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
4690; GFX8-NEXT:    s_or_b64 s[2:3], s[8:9], s[6:7]
4691; GFX8-NEXT:    ; return to shader part epilog
4692;
4693; GFX9-LABEL: s_fshr_i128:
4694; GFX9:       ; %bb.0:
4695; GFX9-NEXT:    s_movk_i32 s10, 0x7f
4696; GFX9-NEXT:    s_mov_b32 s11, 0
4697; GFX9-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4698; GFX9-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4699; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4700; GFX9-NEXT:    s_lshr_b32 s10, s1, 31
4701; GFX9-NEXT:    s_lshl_b64 s[14:15], s[0:1], 1
4702; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[10:11]
4703; GFX9-NEXT:    s_sub_i32 s13, s8, 64
4704; GFX9-NEXT:    s_sub_i32 s9, 64, s8
4705; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
4706; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
4707; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
4708; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
4709; GFX9-NEXT:    s_lshl_b64 s[2:3], s[14:15], s8
4710; GFX9-NEXT:    s_lshr_b64 s[10:11], s[14:15], s9
4711; GFX9-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
4712; GFX9-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
4713; GFX9-NEXT:    s_lshl_b64 s[10:11], s[14:15], s13
4714; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
4715; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
4716; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
4717; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
4718; GFX9-NEXT:    s_cselect_b64 s[8:9], s[0:1], s[8:9]
4719; GFX9-NEXT:    s_sub_i32 s14, s12, 64
4720; GFX9-NEXT:    s_sub_i32 s13, 64, s12
4721; GFX9-NEXT:    s_cmp_lt_u32 s12, 64
4722; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
4723; GFX9-NEXT:    s_cmp_eq_u32 s12, 0
4724; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
4725; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], s12
4726; GFX9-NEXT:    s_lshr_b64 s[10:11], s[4:5], s12
4727; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], s13
4728; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
4729; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
4730; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
4731; GFX9-NEXT:    s_cselect_b64 s[6:7], s[10:11], s[6:7]
4732; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
4733; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4734; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
4735; GFX9-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
4736; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
4737; GFX9-NEXT:    s_or_b64 s[2:3], s[8:9], s[6:7]
4738; GFX9-NEXT:    ; return to shader part epilog
4739;
4740; GFX10-LABEL: s_fshr_i128:
4741; GFX10:       ; %bb.0:
4742; GFX10-NEXT:    s_movk_i32 s10, 0x7f
4743; GFX10-NEXT:    s_mov_b32 s11, 0
4744; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4745; GFX10-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4746; GFX10-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4747; GFX10-NEXT:    s_lshr_b32 s10, s1, 31
4748; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
4749; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[10:11]
4750; GFX10-NEXT:    s_sub_i32 s13, s8, 64
4751; GFX10-NEXT:    s_sub_i32 s9, 64, s8
4752; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
4753; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
4754; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
4755; GFX10-NEXT:    s_cselect_b32 s17, 1, 0
4756; GFX10-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
4757; GFX10-NEXT:    s_lshl_b64 s[14:15], s[2:3], s8
4758; GFX10-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
4759; GFX10-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
4760; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s13
4761; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
4762; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
4763; GFX10-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
4764; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
4765; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
4766; GFX10-NEXT:    s_sub_i32 s14, s12, 64
4767; GFX10-NEXT:    s_sub_i32 s10, 64, s12
4768; GFX10-NEXT:    s_cmp_lt_u32 s12, 64
4769; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
4770; GFX10-NEXT:    s_cmp_eq_u32 s12, 0
4771; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
4772; GFX10-NEXT:    s_lshr_b64 s[0:1], s[4:5], s12
4773; GFX10-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
4774; GFX10-NEXT:    s_lshr_b64 s[12:13], s[6:7], s12
4775; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
4776; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
4777; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
4778; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
4779; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
4780; GFX10-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
4781; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
4782; GFX10-NEXT:    s_cselect_b64 s[4:5], s[12:13], 0
4783; GFX10-NEXT:    s_or_b64 s[0:1], s[8:9], s[0:1]
4784; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4785; GFX10-NEXT:    ; return to shader part epilog
4786  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
4787  ret i128 %result
4788}
4789
4790define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
4791; GFX6-LABEL: v_fshr_i128:
4792; GFX6:       ; %bb.0:
4793; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4794; GFX6-NEXT:    v_and_b32_e32 v14, 0x7f, v8
4795; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4796; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
4797; GFX6-NEXT:    v_and_b32_e32 v15, 0x7f, v8
4798; GFX6-NEXT:    v_lshl_b64 v[8:9], v[0:1], 1
4799; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 31, v1
4800; GFX6-NEXT:    v_or_b32_e32 v2, v2, v0
4801; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, 64, v15
4802; GFX6-NEXT:    v_lshr_b64 v[0:1], v[8:9], v0
4803; GFX6-NEXT:    v_lshl_b64 v[10:11], v[2:3], v15
4804; GFX6-NEXT:    v_subrev_i32_e32 v16, vcc, 64, v15
4805; GFX6-NEXT:    v_lshl_b64 v[12:13], v[8:9], v15
4806; GFX6-NEXT:    v_or_b32_e32 v10, v0, v10
4807; GFX6-NEXT:    v_or_b32_e32 v11, v1, v11
4808; GFX6-NEXT:    v_lshl_b64 v[0:1], v[8:9], v16
4809; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
4810; GFX6-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
4811; GFX6-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
4812; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
4813; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
4814; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v15
4815; GFX6-NEXT:    v_cndmask_b32_e32 v10, v0, v2, vcc
4816; GFX6-NEXT:    v_cndmask_b32_e32 v11, v1, v3, vcc
4817; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v14
4818; GFX6-NEXT:    v_lshr_b64 v[0:1], v[4:5], v14
4819; GFX6-NEXT:    v_lshl_b64 v[2:3], v[6:7], v2
4820; GFX6-NEXT:    v_subrev_i32_e32 v15, vcc, 64, v14
4821; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
4822; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
4823; GFX6-NEXT:    v_lshr_b64 v[0:1], v[6:7], v15
4824; GFX6-NEXT:    v_lshr_b64 v[8:9], v[6:7], v14
4825; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
4826; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
4827; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
4828; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v14
4829; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[4:5]
4830; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[4:5]
4831; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
4832; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
4833; GFX6-NEXT:    v_or_b32_e32 v0, v12, v0
4834; GFX6-NEXT:    v_or_b32_e32 v1, v13, v1
4835; GFX6-NEXT:    v_or_b32_e32 v2, v10, v2
4836; GFX6-NEXT:    v_or_b32_e32 v3, v11, v3
4837; GFX6-NEXT:    s_setpc_b64 s[30:31]
4838;
4839; GFX8-LABEL: v_fshr_i128:
4840; GFX8:       ; %bb.0:
4841; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4842; GFX8-NEXT:    v_and_b32_e32 v14, 0x7f, v8
4843; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
4844; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4845; GFX8-NEXT:    v_and_b32_e32 v15, 0x7f, v8
4846; GFX8-NEXT:    v_lshlrev_b64 v[8:9], 1, v[0:1]
4847; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 31, v1
4848; GFX8-NEXT:    v_or_b32_e32 v2, v2, v0
4849; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, 64, v15
4850; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v0, v[8:9]
4851; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v15, v[2:3]
4852; GFX8-NEXT:    v_subrev_u32_e32 v16, vcc, 64, v15
4853; GFX8-NEXT:    v_lshlrev_b64 v[12:13], v15, v[8:9]
4854; GFX8-NEXT:    v_or_b32_e32 v10, v0, v10
4855; GFX8-NEXT:    v_or_b32_e32 v11, v1, v11
4856; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v16, v[8:9]
4857; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
4858; GFX8-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
4859; GFX8-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
4860; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
4861; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
4862; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v15
4863; GFX8-NEXT:    v_cndmask_b32_e32 v10, v0, v2, vcc
4864; GFX8-NEXT:    v_cndmask_b32_e32 v11, v1, v3, vcc
4865; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v14
4866; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v14, v[4:5]
4867; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, v[6:7]
4868; GFX8-NEXT:    v_subrev_u32_e32 v15, vcc, 64, v14
4869; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
4870; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
4871; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v15, v[6:7]
4872; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v14, v[6:7]
4873; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
4874; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
4875; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
4876; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v14
4877; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[4:5]
4878; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[4:5]
4879; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
4880; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
4881; GFX8-NEXT:    v_or_b32_e32 v0, v12, v0
4882; GFX8-NEXT:    v_or_b32_e32 v1, v13, v1
4883; GFX8-NEXT:    v_or_b32_e32 v2, v10, v2
4884; GFX8-NEXT:    v_or_b32_e32 v3, v11, v3
4885; GFX8-NEXT:    s_setpc_b64 s[30:31]
4886;
4887; GFX9-LABEL: v_fshr_i128:
4888; GFX9:       ; %bb.0:
4889; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4890; GFX9-NEXT:    v_and_b32_e32 v14, 0x7f, v8
4891; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
4892; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4893; GFX9-NEXT:    v_and_b32_e32 v15, 0x7f, v8
4894; GFX9-NEXT:    v_lshlrev_b64 v[8:9], 1, v[0:1]
4895; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 31, v1
4896; GFX9-NEXT:    v_or_b32_e32 v2, v2, v0
4897; GFX9-NEXT:    v_sub_u32_e32 v0, 64, v15
4898; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v0, v[8:9]
4899; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v15, v[2:3]
4900; GFX9-NEXT:    v_subrev_u32_e32 v16, 64, v15
4901; GFX9-NEXT:    v_lshlrev_b64 v[12:13], v15, v[8:9]
4902; GFX9-NEXT:    v_or_b32_e32 v10, v0, v10
4903; GFX9-NEXT:    v_or_b32_e32 v11, v1, v11
4904; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v16, v[8:9]
4905; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
4906; GFX9-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
4907; GFX9-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
4908; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
4909; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
4910; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v15
4911; GFX9-NEXT:    v_cndmask_b32_e32 v10, v0, v2, vcc
4912; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v14
4913; GFX9-NEXT:    v_cndmask_b32_e32 v11, v1, v3, vcc
4914; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v14, v[4:5]
4915; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, v[6:7]
4916; GFX9-NEXT:    v_subrev_u32_e32 v15, 64, v14
4917; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
4918; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
4919; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v15, v[6:7]
4920; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v14, v[6:7]
4921; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
4922; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
4923; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
4924; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v14
4925; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[4:5]
4926; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[4:5]
4927; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
4928; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
4929; GFX9-NEXT:    v_or_b32_e32 v0, v12, v0
4930; GFX9-NEXT:    v_or_b32_e32 v1, v13, v1
4931; GFX9-NEXT:    v_or_b32_e32 v2, v10, v2
4932; GFX9-NEXT:    v_or_b32_e32 v3, v11, v3
4933; GFX9-NEXT:    s_setpc_b64 s[30:31]
4934;
4935; GFX10-LABEL: v_fshr_i128:
4936; GFX10:       ; %bb.0:
4937; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4938; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4939; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v8
4940; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
4941; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 31, v1
4942; GFX10-NEXT:    v_and_b32_e32 v19, 0x7f, v8
4943; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
4944; GFX10-NEXT:    v_and_b32_e32 v18, 0x7f, v9
4945; GFX10-NEXT:    v_or_b32_e32 v2, v2, v10
4946; GFX10-NEXT:    v_sub_nc_u32_e32 v16, 64, v19
4947; GFX10-NEXT:    v_subrev_nc_u32_e32 v21, 64, v19
4948; GFX10-NEXT:    v_sub_nc_u32_e32 v10, 64, v18
4949; GFX10-NEXT:    v_subrev_nc_u32_e32 v20, 64, v18
4950; GFX10-NEXT:    v_lshlrev_b64 v[8:9], v18, v[2:3]
4951; GFX10-NEXT:    v_lshrrev_b64 v[12:13], v19, v[4:5]
4952; GFX10-NEXT:    v_lshlrev_b64 v[16:17], v16, v[6:7]
4953; GFX10-NEXT:    v_lshrrev_b64 v[10:11], v10, v[0:1]
4954; GFX10-NEXT:    v_lshlrev_b64 v[14:15], v18, v[0:1]
4955; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v20, v[0:1]
4956; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v18
4957; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v19
4958; GFX10-NEXT:    v_or_b32_e32 v12, v12, v16
4959; GFX10-NEXT:    v_or_b32_e32 v10, v10, v8
4960; GFX10-NEXT:    v_or_b32_e32 v11, v11, v9
4961; GFX10-NEXT:    v_lshrrev_b64 v[8:9], v21, v[6:7]
4962; GFX10-NEXT:    v_or_b32_e32 v13, v13, v17
4963; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v19
4964; GFX10-NEXT:    v_cndmask_b32_e32 v10, v0, v10, vcc_lo
4965; GFX10-NEXT:    v_cndmask_b32_e32 v11, v1, v11, vcc_lo
4966; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v19, v[6:7]
4967; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v12, s4
4968; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v18
4969; GFX10-NEXT:    v_cndmask_b32_e64 v6, v9, v13, s4
4970; GFX10-NEXT:    v_cndmask_b32_e32 v14, 0, v14, vcc_lo
4971; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0, v15, vcc_lo
4972; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s5
4973; GFX10-NEXT:    v_cndmask_b32_e64 v2, v10, v2, s6
4974; GFX10-NEXT:    v_cndmask_b32_e64 v3, v11, v3, s6
4975; GFX10-NEXT:    v_cndmask_b32_e64 v5, v6, v5, s5
4976; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, v0, s4
4977; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, v1, s4
4978; GFX10-NEXT:    v_or_b32_e32 v0, v14, v4
4979; GFX10-NEXT:    v_or_b32_e32 v1, v7, v5
4980; GFX10-NEXT:    v_or_b32_e32 v2, v2, v6
4981; GFX10-NEXT:    v_or_b32_e32 v3, v3, v8
4982; GFX10-NEXT:    s_setpc_b64 s[30:31]
4983  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
4984  ret i128 %result
4985}
4986
4987define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
4988; GFX6-LABEL: v_fshr_i128_ssv:
4989; GFX6:       ; %bb.0:
4990; GFX6-NEXT:    v_and_b32_e32 v6, 0x7f, v0
4991; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
4992; GFX6-NEXT:    s_mov_b32 s9, 0
4993; GFX6-NEXT:    v_and_b32_e32 v7, 0x7f, v0
4994; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
4995; GFX6-NEXT:    s_lshr_b32 s8, s1, 31
4996; GFX6-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
4997; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
4998; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, 64, v7
4999; GFX6-NEXT:    v_lshr_b64 v[0:1], s[10:11], v0
5000; GFX6-NEXT:    v_lshl_b64 v[2:3], s[0:1], v7
5001; GFX6-NEXT:    v_subrev_i32_e32 v8, vcc, 64, v7
5002; GFX6-NEXT:    v_lshl_b64 v[4:5], s[10:11], v7
5003; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5004; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5005; GFX6-NEXT:    v_lshl_b64 v[0:1], s[10:11], v8
5006; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5007; GFX6-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5008; GFX6-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5009; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5010; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5011; GFX6-NEXT:    v_mov_b32_e32 v2, s0
5012; GFX6-NEXT:    v_mov_b32_e32 v3, s1
5013; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
5014; GFX6-NEXT:    v_cndmask_b32_e32 v7, v0, v2, vcc
5015; GFX6-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5016; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v6
5017; GFX6-NEXT:    v_lshr_b64 v[0:1], s[4:5], v6
5018; GFX6-NEXT:    v_lshl_b64 v[2:3], s[6:7], v2
5019; GFX6-NEXT:    v_subrev_i32_e32 v11, vcc, 64, v6
5020; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5021; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5022; GFX6-NEXT:    v_lshr_b64 v[0:1], s[6:7], v11
5023; GFX6-NEXT:    v_lshr_b64 v[4:5], s[6:7], v6
5024; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5025; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5026; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5027; GFX6-NEXT:    v_mov_b32_e32 v2, s4
5028; GFX6-NEXT:    v_mov_b32_e32 v3, s5
5029; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
5030; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5031; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5032; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5033; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5034; GFX6-NEXT:    v_or_b32_e32 v0, v8, v0
5035; GFX6-NEXT:    v_or_b32_e32 v1, v9, v1
5036; GFX6-NEXT:    v_or_b32_e32 v2, v7, v2
5037; GFX6-NEXT:    v_or_b32_e32 v3, v10, v3
5038; GFX6-NEXT:    ; return to shader part epilog
5039;
5040; GFX8-LABEL: v_fshr_i128_ssv:
5041; GFX8:       ; %bb.0:
5042; GFX8-NEXT:    v_and_b32_e32 v6, 0x7f, v0
5043; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
5044; GFX8-NEXT:    s_mov_b32 s9, 0
5045; GFX8-NEXT:    v_and_b32_e32 v7, 0x7f, v0
5046; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5047; GFX8-NEXT:    s_lshr_b32 s8, s1, 31
5048; GFX8-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
5049; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
5050; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, 64, v7
5051; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v0, s[10:11]
5052; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v7, s[0:1]
5053; GFX8-NEXT:    v_subrev_u32_e32 v8, vcc, 64, v7
5054; GFX8-NEXT:    v_lshlrev_b64 v[4:5], v7, s[10:11]
5055; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5056; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5057; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v8, s[10:11]
5058; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5059; GFX8-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5060; GFX8-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5061; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5062; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5063; GFX8-NEXT:    v_mov_b32_e32 v2, s0
5064; GFX8-NEXT:    v_mov_b32_e32 v3, s1
5065; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
5066; GFX8-NEXT:    v_cndmask_b32_e32 v7, v0, v2, vcc
5067; GFX8-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5068; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v6
5069; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v6, s[4:5]
5070; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, s[6:7]
5071; GFX8-NEXT:    v_subrev_u32_e32 v11, vcc, 64, v6
5072; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5073; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5074; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v11, s[6:7]
5075; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v6, s[6:7]
5076; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5077; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5078; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5079; GFX8-NEXT:    v_mov_b32_e32 v2, s4
5080; GFX8-NEXT:    v_mov_b32_e32 v3, s5
5081; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
5082; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5083; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5084; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5085; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5086; GFX8-NEXT:    v_or_b32_e32 v0, v8, v0
5087; GFX8-NEXT:    v_or_b32_e32 v1, v9, v1
5088; GFX8-NEXT:    v_or_b32_e32 v2, v7, v2
5089; GFX8-NEXT:    v_or_b32_e32 v3, v10, v3
5090; GFX8-NEXT:    ; return to shader part epilog
5091;
5092; GFX9-LABEL: v_fshr_i128_ssv:
5093; GFX9:       ; %bb.0:
5094; GFX9-NEXT:    v_and_b32_e32 v6, 0x7f, v0
5095; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
5096; GFX9-NEXT:    s_mov_b32 s9, 0
5097; GFX9-NEXT:    v_and_b32_e32 v7, 0x7f, v0
5098; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5099; GFX9-NEXT:    s_lshr_b32 s8, s1, 31
5100; GFX9-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
5101; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
5102; GFX9-NEXT:    v_sub_u32_e32 v0, 64, v7
5103; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v0, s[10:11]
5104; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v7, s[0:1]
5105; GFX9-NEXT:    v_subrev_u32_e32 v8, 64, v7
5106; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v7, s[10:11]
5107; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5108; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5109; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, s[10:11]
5110; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5111; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5112; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5113; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5114; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5115; GFX9-NEXT:    v_mov_b32_e32 v2, s0
5116; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v7
5117; GFX9-NEXT:    v_mov_b32_e32 v3, s1
5118; GFX9-NEXT:    v_cndmask_b32_e32 v7, v0, v2, vcc
5119; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v6
5120; GFX9-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5121; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v6, s[4:5]
5122; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, s[6:7]
5123; GFX9-NEXT:    v_subrev_u32_e32 v11, 64, v6
5124; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5125; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5126; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v11, s[6:7]
5127; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v6, s[6:7]
5128; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5129; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5130; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5131; GFX9-NEXT:    v_mov_b32_e32 v2, s4
5132; GFX9-NEXT:    v_mov_b32_e32 v3, s5
5133; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
5134; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5135; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5136; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5137; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5138; GFX9-NEXT:    v_or_b32_e32 v0, v8, v0
5139; GFX9-NEXT:    v_or_b32_e32 v1, v9, v1
5140; GFX9-NEXT:    v_or_b32_e32 v2, v7, v2
5141; GFX9-NEXT:    v_or_b32_e32 v3, v10, v3
5142; GFX9-NEXT:    ; return to shader part epilog
5143;
5144; GFX10-LABEL: v_fshr_i128_ssv:
5145; GFX10:       ; %bb.0:
5146; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
5147; GFX10-NEXT:    v_and_b32_e32 v13, 0x7f, v0
5148; GFX10-NEXT:    s_mov_b32 s9, 0
5149; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5150; GFX10-NEXT:    s_lshr_b32 s8, s1, 31
5151; GFX10-NEXT:    v_and_b32_e32 v12, 0x7f, v1
5152; GFX10-NEXT:    v_sub_nc_u32_e32 v8, 64, v13
5153; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
5154; GFX10-NEXT:    s_or_b64 s[8:9], s[2:3], s[8:9]
5155; GFX10-NEXT:    v_subrev_nc_u32_e32 v14, 64, v13
5156; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 64, v12
5157; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v12, s[8:9]
5158; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 64, v12
5159; GFX10-NEXT:    v_lshrrev_b64 v[4:5], v13, s[4:5]
5160; GFX10-NEXT:    v_lshlrev_b64 v[8:9], v8, s[6:7]
5161; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v2, s[0:1]
5162; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v12
5163; GFX10-NEXT:    v_lshlrev_b64 v[10:11], v10, s[0:1]
5164; GFX10-NEXT:    v_lshlrev_b64 v[6:7], v12, s[0:1]
5165; GFX10-NEXT:    v_cmp_gt_u32_e64 s0, 64, v13
5166; GFX10-NEXT:    v_or_b32_e32 v4, v4, v8
5167; GFX10-NEXT:    v_or_b32_e32 v2, v2, v0
5168; GFX10-NEXT:    v_or_b32_e32 v3, v3, v1
5169; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v14, s[6:7]
5170; GFX10-NEXT:    v_or_b32_e32 v5, v5, v9
5171; GFX10-NEXT:    v_cmp_eq_u32_e64 s1, 0, v13
5172; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc_lo
5173; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v3, vcc_lo
5174; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v13, s[6:7]
5175; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s0
5176; GFX10-NEXT:    v_cmp_eq_u32_e64 s2, 0, v12
5177; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s0
5178; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc_lo
5179; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0, v7, vcc_lo
5180; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s4, s1
5181; GFX10-NEXT:    v_cndmask_b32_e64 v5, v8, s8, s2
5182; GFX10-NEXT:    v_cndmask_b32_e64 v7, v10, s9, s2
5183; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s5, s1
5184; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5185; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5186; GFX10-NEXT:    v_or_b32_e32 v0, v6, v0
5187; GFX10-NEXT:    v_or_b32_e32 v1, v4, v1
5188; GFX10-NEXT:    v_or_b32_e32 v2, v5, v2
5189; GFX10-NEXT:    v_or_b32_e32 v3, v7, v3
5190; GFX10-NEXT:    ; return to shader part epilog
5191  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5192  %cast.result = bitcast i128 %result to <4 x float>
5193  ret <4 x float> %cast.result
5194}
5195
5196define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 inreg %amt) {
5197; GFX6-LABEL: v_fshr_i128_svs:
5198; GFX6:       ; %bb.0:
5199; GFX6-NEXT:    s_movk_i32 s6, 0x7f
5200; GFX6-NEXT:    s_mov_b32 s7, 0
5201; GFX6-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5202; GFX6-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5203; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5204; GFX6-NEXT:    s_lshr_b32 s6, s1, 31
5205; GFX6-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
5206; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[6:7]
5207; GFX6-NEXT:    s_sub_i32 s9, s4, 64
5208; GFX6-NEXT:    s_sub_i32 s5, 64, s4
5209; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
5210; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5211; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
5212; GFX6-NEXT:    s_cselect_b32 s13, 1, 0
5213; GFX6-NEXT:    s_lshl_b64 s[2:3], s[10:11], s4
5214; GFX6-NEXT:    s_lshr_b64 s[6:7], s[10:11], s5
5215; GFX6-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5216; GFX6-NEXT:    s_or_b64 s[4:5], s[6:7], s[4:5]
5217; GFX6-NEXT:    s_lshl_b64 s[6:7], s[10:11], s9
5218; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5219; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5220; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5221; GFX6-NEXT:    s_cmp_lg_u32 s13, 0
5222; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
5223; GFX6-NEXT:    s_sub_i32 s4, s8, 64
5224; GFX6-NEXT:    s_sub_i32 s5, 64, s8
5225; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5226; GFX6-NEXT:    s_cselect_b32 s6, 1, 0
5227; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5228; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], s8
5229; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], s5
5230; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5231; GFX6-NEXT:    v_lshr_b64 v[8:9], v[2:3], s8
5232; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], s4
5233; GFX6-NEXT:    s_and_b32 s4, 1, s6
5234; GFX6-NEXT:    v_or_b32_e32 v4, v4, v6
5235; GFX6-NEXT:    v_or_b32_e32 v5, v5, v7
5236; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5237; GFX6-NEXT:    s_and_b32 s4, 1, s7
5238; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5239; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5240; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5241; GFX6-NEXT:    s_and_b32 s4, 1, s6
5242; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5243; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5244; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5245; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5246; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5247; GFX6-NEXT:    v_or_b32_e32 v0, s2, v0
5248; GFX6-NEXT:    v_or_b32_e32 v1, s3, v1
5249; GFX6-NEXT:    v_or_b32_e32 v2, s0, v2
5250; GFX6-NEXT:    v_or_b32_e32 v3, s1, v3
5251; GFX6-NEXT:    ; return to shader part epilog
5252;
5253; GFX8-LABEL: v_fshr_i128_svs:
5254; GFX8:       ; %bb.0:
5255; GFX8-NEXT:    s_movk_i32 s6, 0x7f
5256; GFX8-NEXT:    s_mov_b32 s7, 0
5257; GFX8-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5258; GFX8-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5259; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5260; GFX8-NEXT:    s_lshr_b32 s6, s1, 31
5261; GFX8-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
5262; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[6:7]
5263; GFX8-NEXT:    s_sub_i32 s9, s4, 64
5264; GFX8-NEXT:    s_sub_i32 s5, 64, s4
5265; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
5266; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5267; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
5268; GFX8-NEXT:    s_cselect_b32 s13, 1, 0
5269; GFX8-NEXT:    s_lshl_b64 s[2:3], s[10:11], s4
5270; GFX8-NEXT:    s_lshr_b64 s[6:7], s[10:11], s5
5271; GFX8-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5272; GFX8-NEXT:    s_or_b64 s[4:5], s[6:7], s[4:5]
5273; GFX8-NEXT:    s_lshl_b64 s[6:7], s[10:11], s9
5274; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5275; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5276; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5277; GFX8-NEXT:    s_cmp_lg_u32 s13, 0
5278; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
5279; GFX8-NEXT:    s_sub_i32 s4, s8, 64
5280; GFX8-NEXT:    s_sub_i32 s5, 64, s8
5281; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
5282; GFX8-NEXT:    s_cselect_b32 s6, 1, 0
5283; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
5284; GFX8-NEXT:    v_lshrrev_b64 v[4:5], s8, v[0:1]
5285; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s5, v[2:3]
5286; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5287; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s8, v[2:3]
5288; GFX8-NEXT:    v_lshrrev_b64 v[2:3], s4, v[2:3]
5289; GFX8-NEXT:    s_and_b32 s4, 1, s6
5290; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
5291; GFX8-NEXT:    v_or_b32_e32 v5, v5, v7
5292; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5293; GFX8-NEXT:    s_and_b32 s4, 1, s7
5294; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5295; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5296; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5297; GFX8-NEXT:    s_and_b32 s4, 1, s6
5298; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5299; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5300; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5301; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5302; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5303; GFX8-NEXT:    v_or_b32_e32 v0, s2, v0
5304; GFX8-NEXT:    v_or_b32_e32 v1, s3, v1
5305; GFX8-NEXT:    v_or_b32_e32 v2, s0, v2
5306; GFX8-NEXT:    v_or_b32_e32 v3, s1, v3
5307; GFX8-NEXT:    ; return to shader part epilog
5308;
5309; GFX9-LABEL: v_fshr_i128_svs:
5310; GFX9:       ; %bb.0:
5311; GFX9-NEXT:    s_movk_i32 s6, 0x7f
5312; GFX9-NEXT:    s_mov_b32 s7, 0
5313; GFX9-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5314; GFX9-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5315; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5316; GFX9-NEXT:    s_lshr_b32 s6, s1, 31
5317; GFX9-NEXT:    s_lshl_b64 s[10:11], s[0:1], 1
5318; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[6:7]
5319; GFX9-NEXT:    s_sub_i32 s9, s4, 64
5320; GFX9-NEXT:    s_sub_i32 s5, 64, s4
5321; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
5322; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5323; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
5324; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
5325; GFX9-NEXT:    s_lshl_b64 s[2:3], s[10:11], s4
5326; GFX9-NEXT:    s_lshr_b64 s[6:7], s[10:11], s5
5327; GFX9-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5328; GFX9-NEXT:    s_or_b64 s[4:5], s[6:7], s[4:5]
5329; GFX9-NEXT:    s_lshl_b64 s[6:7], s[10:11], s9
5330; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5331; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5332; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
5333; GFX9-NEXT:    s_cmp_lg_u32 s13, 0
5334; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
5335; GFX9-NEXT:    s_sub_i32 s4, s8, 64
5336; GFX9-NEXT:    s_sub_i32 s5, 64, s8
5337; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
5338; GFX9-NEXT:    s_cselect_b32 s6, 1, 0
5339; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
5340; GFX9-NEXT:    v_lshrrev_b64 v[4:5], s8, v[0:1]
5341; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s5, v[2:3]
5342; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
5343; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s8, v[2:3]
5344; GFX9-NEXT:    v_lshrrev_b64 v[2:3], s4, v[2:3]
5345; GFX9-NEXT:    s_and_b32 s4, 1, s6
5346; GFX9-NEXT:    v_or_b32_e32 v4, v4, v6
5347; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
5348; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5349; GFX9-NEXT:    s_and_b32 s4, 1, s7
5350; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5351; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5352; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5353; GFX9-NEXT:    s_and_b32 s4, 1, s6
5354; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5355; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5356; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5357; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5358; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5359; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
5360; GFX9-NEXT:    v_or_b32_e32 v1, s3, v1
5361; GFX9-NEXT:    v_or_b32_e32 v2, s0, v2
5362; GFX9-NEXT:    v_or_b32_e32 v3, s1, v3
5363; GFX9-NEXT:    ; return to shader part epilog
5364;
5365; GFX10-LABEL: v_fshr_i128_svs:
5366; GFX10:       ; %bb.0:
5367; GFX10-NEXT:    s_movk_i32 s6, 0x7f
5368; GFX10-NEXT:    s_mov_b32 s7, 0
5369; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5370; GFX10-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5371; GFX10-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5372; GFX10-NEXT:    s_lshr_b32 s6, s1, 31
5373; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
5374; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
5375; GFX10-NEXT:    s_sub_i32 s9, s4, 64
5376; GFX10-NEXT:    s_sub_i32 s5, 64, s4
5377; GFX10-NEXT:    s_cmp_lt_u32 s4, 64
5378; GFX10-NEXT:    v_lshrrev_b64 v[4:5], s8, v[0:1]
5379; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
5380; GFX10-NEXT:    s_cmp_eq_u32 s4, 0
5381; GFX10-NEXT:    s_cselect_b32 s13, 1, 0
5382; GFX10-NEXT:    s_lshr_b64 s[6:7], s[0:1], s5
5383; GFX10-NEXT:    s_lshl_b64 s[10:11], s[2:3], s4
5384; GFX10-NEXT:    s_lshl_b64 s[4:5], s[0:1], s4
5385; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
5386; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
5387; GFX10-NEXT:    s_cmp_lg_u32 s12, 0
5388; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], 0
5389; GFX10-NEXT:    s_cselect_b64 s[0:1], s[6:7], s[0:1]
5390; GFX10-NEXT:    s_cmp_lg_u32 s13, 0
5391; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
5392; GFX10-NEXT:    s_sub_i32 s0, 64, s8
5393; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s0, v[2:3]
5394; GFX10-NEXT:    s_sub_i32 s0, s8, 64
5395; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
5396; GFX10-NEXT:    v_lshrrev_b64 v[8:9], s0, v[2:3]
5397; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
5398; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
5399; GFX10-NEXT:    v_or_b32_e32 v4, v4, v6
5400; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
5401; GFX10-NEXT:    s_and_b32 s0, 1, s1
5402; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
5403; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
5404; GFX10-NEXT:    s_and_b32 s0, 1, s6
5405; GFX10-NEXT:    s_and_b32 s1, 1, s1
5406; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s8, v[2:3]
5407; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc_lo
5408; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo
5409; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
5410; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
5411; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
5412; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
5413; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5414; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5415; GFX10-NEXT:    v_or_b32_e32 v0, s4, v0
5416; GFX10-NEXT:    v_or_b32_e32 v1, s5, v1
5417; GFX10-NEXT:    v_or_b32_e32 v2, s2, v2
5418; GFX10-NEXT:    v_or_b32_e32 v3, s3, v3
5419; GFX10-NEXT:    ; return to shader part epilog
5420  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5421  %cast.result = bitcast i128 %result to <4 x float>
5422  ret <4 x float> %cast.result
5423}
5424
5425define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 inreg %amt) {
5426; GFX6-LABEL: v_fshr_i128_vss:
5427; GFX6:       ; %bb.0:
5428; GFX6-NEXT:    s_mov_b64 s[6:7], 0x7f
5429; GFX6-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5430; GFX6-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5431; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
5432; GFX6-NEXT:    s_sub_i32 s5, s4, 64
5433; GFX6-NEXT:    s_sub_i32 s6, 64, s4
5434; GFX6-NEXT:    v_lshl_b64 v[4:5], v[0:1], 1
5435; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 31, v1
5436; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
5437; GFX6-NEXT:    v_or_b32_e32 v2, v2, v0
5438; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5439; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
5440; GFX6-NEXT:    s_cselect_b32 s9, 1, 0
5441; GFX6-NEXT:    v_lshr_b64 v[0:1], v[4:5], s6
5442; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], s4
5443; GFX6-NEXT:    v_lshl_b64 v[8:9], v[4:5], s4
5444; GFX6-NEXT:    s_and_b32 s4, 1, s7
5445; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5446; GFX6-NEXT:    s_and_b32 s4, 1, s9
5447; GFX6-NEXT:    s_sub_i32 s10, s8, 64
5448; GFX6-NEXT:    s_sub_i32 s9, 64, s8
5449; GFX6-NEXT:    v_or_b32_e32 v6, v0, v6
5450; GFX6-NEXT:    v_or_b32_e32 v7, v1, v7
5451; GFX6-NEXT:    v_lshl_b64 v[0:1], v[4:5], s5
5452; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5453; GFX6-NEXT:    s_cselect_b32 s11, 1, 0
5454; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5455; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
5456; GFX6-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
5457; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
5458; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
5459; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5460; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5461; GFX6-NEXT:    s_lshr_b64 s[4:5], s[2:3], s8
5462; GFX6-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
5463; GFX6-NEXT:    s_lshl_b64 s[8:9], s[2:3], s9
5464; GFX6-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
5465; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5466; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5467; GFX6-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
5468; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5469; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5470; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5471; GFX6-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
5472; GFX6-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
5473; GFX6-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
5474; GFX6-NEXT:    v_or_b32_e32 v0, s0, v4
5475; GFX6-NEXT:    v_or_b32_e32 v1, s1, v5
5476; GFX6-NEXT:    v_or_b32_e32 v2, s2, v2
5477; GFX6-NEXT:    v_or_b32_e32 v3, s3, v3
5478; GFX6-NEXT:    ; return to shader part epilog
5479;
5480; GFX8-LABEL: v_fshr_i128_vss:
5481; GFX8:       ; %bb.0:
5482; GFX8-NEXT:    s_mov_b64 s[6:7], 0x7f
5483; GFX8-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5484; GFX8-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5485; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
5486; GFX8-NEXT:    s_sub_i32 s5, s4, 64
5487; GFX8-NEXT:    s_sub_i32 s6, 64, s4
5488; GFX8-NEXT:    v_lshlrev_b64 v[4:5], 1, v[0:1]
5489; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 31, v1
5490; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
5491; GFX8-NEXT:    v_or_b32_e32 v2, v2, v0
5492; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5493; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
5494; GFX8-NEXT:    s_cselect_b32 s9, 1, 0
5495; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s6, v[4:5]
5496; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s4, v[2:3]
5497; GFX8-NEXT:    v_lshlrev_b64 v[8:9], s4, v[4:5]
5498; GFX8-NEXT:    s_and_b32 s4, 1, s7
5499; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5500; GFX8-NEXT:    s_and_b32 s4, 1, s9
5501; GFX8-NEXT:    s_sub_i32 s10, s8, 64
5502; GFX8-NEXT:    s_sub_i32 s9, 64, s8
5503; GFX8-NEXT:    v_or_b32_e32 v6, v0, v6
5504; GFX8-NEXT:    v_or_b32_e32 v7, v1, v7
5505; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s5, v[4:5]
5506; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
5507; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
5508; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
5509; GFX8-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
5510; GFX8-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
5511; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
5512; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
5513; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5514; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5515; GFX8-NEXT:    s_lshr_b64 s[4:5], s[2:3], s8
5516; GFX8-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
5517; GFX8-NEXT:    s_lshl_b64 s[8:9], s[2:3], s9
5518; GFX8-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
5519; GFX8-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5520; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
5521; GFX8-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
5522; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5523; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5524; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
5525; GFX8-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
5526; GFX8-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
5527; GFX8-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
5528; GFX8-NEXT:    v_or_b32_e32 v0, s0, v4
5529; GFX8-NEXT:    v_or_b32_e32 v1, s1, v5
5530; GFX8-NEXT:    v_or_b32_e32 v2, s2, v2
5531; GFX8-NEXT:    v_or_b32_e32 v3, s3, v3
5532; GFX8-NEXT:    ; return to shader part epilog
5533;
5534; GFX9-LABEL: v_fshr_i128_vss:
5535; GFX9:       ; %bb.0:
5536; GFX9-NEXT:    s_mov_b64 s[6:7], 0x7f
5537; GFX9-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5538; GFX9-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5539; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
5540; GFX9-NEXT:    s_sub_i32 s5, s4, 64
5541; GFX9-NEXT:    s_sub_i32 s6, 64, s4
5542; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 1, v[0:1]
5543; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 31, v1
5544; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
5545; GFX9-NEXT:    v_or_b32_e32 v2, v2, v0
5546; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
5547; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
5548; GFX9-NEXT:    s_cselect_b32 s9, 1, 0
5549; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s6, v[4:5]
5550; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s4, v[2:3]
5551; GFX9-NEXT:    v_lshlrev_b64 v[8:9], s4, v[4:5]
5552; GFX9-NEXT:    s_and_b32 s4, 1, s7
5553; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5554; GFX9-NEXT:    s_and_b32 s4, 1, s9
5555; GFX9-NEXT:    s_sub_i32 s10, s8, 64
5556; GFX9-NEXT:    s_sub_i32 s9, 64, s8
5557; GFX9-NEXT:    v_or_b32_e32 v6, v0, v6
5558; GFX9-NEXT:    v_or_b32_e32 v7, v1, v7
5559; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s5, v[4:5]
5560; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
5561; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
5562; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
5563; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
5564; GFX9-NEXT:    v_cndmask_b32_e32 v5, 0, v9, vcc
5565; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
5566; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
5567; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5568; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5569; GFX9-NEXT:    s_lshr_b64 s[4:5], s[2:3], s8
5570; GFX9-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
5571; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s9
5572; GFX9-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
5573; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5574; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
5575; GFX9-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
5576; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5577; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5578; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
5579; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
5580; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
5581; GFX9-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
5582; GFX9-NEXT:    v_or_b32_e32 v0, s0, v4
5583; GFX9-NEXT:    v_or_b32_e32 v1, s1, v5
5584; GFX9-NEXT:    v_or_b32_e32 v2, s2, v2
5585; GFX9-NEXT:    v_or_b32_e32 v3, s3, v3
5586; GFX9-NEXT:    ; return to shader part epilog
5587;
5588; GFX10-LABEL: v_fshr_i128_vss:
5589; GFX10:       ; %bb.0:
5590; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
5591; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 31, v1
5592; GFX10-NEXT:    s_mov_b64 s[6:7], 0x7f
5593; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
5594; GFX10-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5595; GFX10-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5596; GFX10-NEXT:    v_or_b32_e32 v2, v2, v4
5597; GFX10-NEXT:    s_sub_i32 s6, 64, s4
5598; GFX10-NEXT:    s_sub_i32 s5, s4, 64
5599; GFX10-NEXT:    s_cmp_lt_u32 s4, 64
5600; GFX10-NEXT:    v_lshrrev_b64 v[4:5], s6, v[0:1]
5601; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s4, v[2:3]
5602; GFX10-NEXT:    s_cselect_b32 s7, 1, 0
5603; GFX10-NEXT:    s_cmp_eq_u32 s4, 0
5604; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s4, v[0:1]
5605; GFX10-NEXT:    s_cselect_b32 s9, 1, 0
5606; GFX10-NEXT:    s_and_b32 s4, 1, s7
5607; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
5608; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
5609; GFX10-NEXT:    v_or_b32_e32 v4, v4, v6
5610; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
5611; GFX10-NEXT:    s_and_b32 s4, 1, s9
5612; GFX10-NEXT:    s_sub_i32 s10, s8, 64
5613; GFX10-NEXT:    s_sub_i32 s6, 64, s8
5614; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
5615; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc_lo
5616; GFX10-NEXT:    s_cselect_b32 s11, 1, 0
5617; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
5618; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc_lo
5619; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
5620; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
5621; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
5622; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
5623; GFX10-NEXT:    s_lshr_b64 s[4:5], s[0:1], s8
5624; GFX10-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
5625; GFX10-NEXT:    s_lshr_b64 s[8:9], s[2:3], s8
5626; GFX10-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
5627; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5628; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
5629; GFX10-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
5630; GFX10-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5631; GFX10-NEXT:    s_cmp_lg_u32 s12, 0
5632; GFX10-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc_lo
5633; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5634; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
5635; GFX10-NEXT:    v_or_b32_e32 v0, s0, v6
5636; GFX10-NEXT:    s_cselect_b64 s[2:3], s[8:9], 0
5637; GFX10-NEXT:    v_or_b32_e32 v1, s1, v7
5638; GFX10-NEXT:    v_or_b32_e32 v2, s2, v2
5639; GFX10-NEXT:    v_or_b32_e32 v3, s3, v3
5640; GFX10-NEXT:    ; return to shader part epilog
5641  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
5642  %cast.result = bitcast i128 %result to <4 x float>
5643  ret <4 x float> %cast.result
5644}
5645
5646define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
5647; GFX6-LABEL: s_fshr_i128_65:
5648; GFX6:       ; %bb.0:
5649; GFX6-NEXT:    s_mov_b32 s4, 0
5650; GFX6-NEXT:    s_lshl_b32 s5, s0, 31
5651; GFX6-NEXT:    s_lshl_b32 s3, s2, 31
5652; GFX6-NEXT:    s_mov_b32 s2, s4
5653; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
5654; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[0:1]
5655; GFX6-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
5656; GFX6-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
5657; GFX6-NEXT:    ; return to shader part epilog
5658;
5659; GFX8-LABEL: s_fshr_i128_65:
5660; GFX8:       ; %bb.0:
5661; GFX8-NEXT:    s_mov_b32 s4, 0
5662; GFX8-NEXT:    s_lshl_b32 s5, s0, 31
5663; GFX8-NEXT:    s_lshl_b32 s3, s2, 31
5664; GFX8-NEXT:    s_mov_b32 s2, s4
5665; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
5666; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[0:1]
5667; GFX8-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
5668; GFX8-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
5669; GFX8-NEXT:    ; return to shader part epilog
5670;
5671; GFX9-LABEL: s_fshr_i128_65:
5672; GFX9:       ; %bb.0:
5673; GFX9-NEXT:    s_mov_b32 s4, 0
5674; GFX9-NEXT:    s_lshl_b32 s5, s0, 31
5675; GFX9-NEXT:    s_lshl_b32 s3, s2, 31
5676; GFX9-NEXT:    s_mov_b32 s2, s4
5677; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
5678; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[0:1]
5679; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
5680; GFX9-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]
5681; GFX9-NEXT:    ; return to shader part epilog
5682;
5683; GFX10-LABEL: s_fshr_i128_65:
5684; GFX10:       ; %bb.0:
5685; GFX10-NEXT:    s_mov_b32 s4, 0
5686; GFX10-NEXT:    s_lshl_b32 s5, s0, 31
5687; GFX10-NEXT:    s_lshl_b32 s3, s2, 31
5688; GFX10-NEXT:    s_mov_b32 s2, s4
5689; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], 1
5690; GFX10-NEXT:    s_lshr_b64 s[8:9], s[0:1], 1
5691; GFX10-NEXT:    s_or_b64 s[0:1], s[4:5], s[6:7]
5692; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
5693; GFX10-NEXT:    ; return to shader part epilog
5694  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
5695  ret i128 %result
5696}
5697
5698define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
5699; GFX6-LABEL: v_fshr_i128_65:
5700; GFX6:       ; %bb.0:
5701; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5702; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 31, v0
5703; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 31, v2
5704; GFX6-NEXT:    v_lshr_b64 v[2:3], v[0:1], 1
5705; GFX6-NEXT:    v_lshr_b64 v[0:1], v[6:7], 1
5706; GFX6-NEXT:    v_or_b32_e32 v3, v5, v3
5707; GFX6-NEXT:    v_or_b32_e32 v1, v4, v1
5708; GFX6-NEXT:    s_setpc_b64 s[30:31]
5709;
5710; GFX8-LABEL: v_fshr_i128_65:
5711; GFX8:       ; %bb.0:
5712; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5713; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 31, v0
5714; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 31, v2
5715; GFX8-NEXT:    v_lshrrev_b64 v[2:3], 1, v[0:1]
5716; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 1, v[6:7]
5717; GFX8-NEXT:    v_or_b32_e32 v3, v5, v3
5718; GFX8-NEXT:    v_or_b32_e32 v1, v4, v1
5719; GFX8-NEXT:    s_setpc_b64 s[30:31]
5720;
5721; GFX9-LABEL: v_fshr_i128_65:
5722; GFX9:       ; %bb.0:
5723; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5724; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 31, v0
5725; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 31, v2
5726; GFX9-NEXT:    v_lshrrev_b64 v[2:3], 1, v[0:1]
5727; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 1, v[6:7]
5728; GFX9-NEXT:    v_or_b32_e32 v3, v5, v3
5729; GFX9-NEXT:    v_or_b32_e32 v1, v4, v1
5730; GFX9-NEXT:    s_setpc_b64 s[30:31]
5731;
5732; GFX10-LABEL: v_fshr_i128_65:
5733; GFX10:       ; %bb.0:
5734; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5735; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
5736; GFX10-NEXT:    v_mov_b32_e32 v8, v2
5737; GFX10-NEXT:    v_lshrrev_b64 v[4:5], 1, v[6:7]
5738; GFX10-NEXT:    v_lshrrev_b64 v[2:3], 1, v[0:1]
5739; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 31, v0
5740; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 31, v8
5741; GFX10-NEXT:    v_or_b32_e32 v1, v9, v5
5742; GFX10-NEXT:    v_or_b32_e32 v3, v0, v3
5743; GFX10-NEXT:    v_mov_b32_e32 v0, v4
5744; GFX10-NEXT:    s_setpc_b64 s[30:31]
5745  %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
5746  ret i128 %result
5747}
5748
5749define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
5750; GFX6-LABEL: s_fshr_v2i128:
5751; GFX6:       ; %bb.0:
5752; GFX6-NEXT:    s_movk_i32 s18, 0x7f
5753; GFX6-NEXT:    s_mov_b32 s19, 0
5754; GFX6-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
5755; GFX6-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
5756; GFX6-NEXT:    s_lshl_b64 s[24:25], s[0:1], 1
5757; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5758; GFX6-NEXT:    s_lshr_b32 s0, s1, 31
5759; GFX6-NEXT:    s_mov_b32 s1, s19
5760; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
5761; GFX6-NEXT:    s_sub_i32 s23, s16, 64
5762; GFX6-NEXT:    s_sub_i32 s17, 64, s16
5763; GFX6-NEXT:    s_cmp_lt_u32 s16, 64
5764; GFX6-NEXT:    s_cselect_b32 s28, 1, 0
5765; GFX6-NEXT:    s_cmp_eq_u32 s16, 0
5766; GFX6-NEXT:    s_cselect_b32 s29, 1, 0
5767; GFX6-NEXT:    s_lshl_b64 s[2:3], s[24:25], s16
5768; GFX6-NEXT:    s_lshr_b64 s[26:27], s[24:25], s17
5769; GFX6-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
5770; GFX6-NEXT:    s_or_b64 s[16:17], s[26:27], s[16:17]
5771; GFX6-NEXT:    s_lshl_b64 s[24:25], s[24:25], s23
5772; GFX6-NEXT:    s_cmp_lg_u32 s28, 0
5773; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5774; GFX6-NEXT:    s_cselect_b64 s[16:17], s[16:17], s[24:25]
5775; GFX6-NEXT:    s_cmp_lg_u32 s29, 0
5776; GFX6-NEXT:    s_cselect_b64 s[16:17], s[0:1], s[16:17]
5777; GFX6-NEXT:    s_sub_i32 s26, s22, 64
5778; GFX6-NEXT:    s_sub_i32 s24, 64, s22
5779; GFX6-NEXT:    s_cmp_lt_u32 s22, 64
5780; GFX6-NEXT:    s_cselect_b32 s27, 1, 0
5781; GFX6-NEXT:    s_cmp_eq_u32 s22, 0
5782; GFX6-NEXT:    s_cselect_b32 s28, 1, 0
5783; GFX6-NEXT:    s_lshr_b64 s[0:1], s[10:11], s22
5784; GFX6-NEXT:    s_lshr_b64 s[22:23], s[8:9], s22
5785; GFX6-NEXT:    s_lshl_b64 s[24:25], s[10:11], s24
5786; GFX6-NEXT:    s_or_b64 s[22:23], s[22:23], s[24:25]
5787; GFX6-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
5788; GFX6-NEXT:    s_cmp_lg_u32 s27, 0
5789; GFX6-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
5790; GFX6-NEXT:    s_cmp_lg_u32 s28, 0
5791; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
5792; GFX6-NEXT:    s_cmp_lg_u32 s27, 0
5793; GFX6-NEXT:    s_cselect_b64 s[10:11], s[0:1], 0
5794; GFX6-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
5795; GFX6-NEXT:    s_or_b64 s[2:3], s[16:17], s[10:11]
5796; GFX6-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
5797; GFX6-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
5798; GFX6-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
5799; GFX6-NEXT:    s_lshr_b32 s18, s5, 31
5800; GFX6-NEXT:    s_lshl_b64 s[16:17], s[4:5], 1
5801; GFX6-NEXT:    s_or_b64 s[4:5], s[6:7], s[18:19]
5802; GFX6-NEXT:    s_sub_i32 s9, s10, 64
5803; GFX6-NEXT:    s_sub_i32 s11, 64, s10
5804; GFX6-NEXT:    s_cmp_lt_u32 s10, 64
5805; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
5806; GFX6-NEXT:    s_cmp_eq_u32 s10, 0
5807; GFX6-NEXT:    s_cselect_b32 s21, 1, 0
5808; GFX6-NEXT:    s_lshl_b64 s[6:7], s[16:17], s10
5809; GFX6-NEXT:    s_lshr_b64 s[18:19], s[16:17], s11
5810; GFX6-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
5811; GFX6-NEXT:    s_or_b64 s[10:11], s[18:19], s[10:11]
5812; GFX6-NEXT:    s_lshl_b64 s[16:17], s[16:17], s9
5813; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
5814; GFX6-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5815; GFX6-NEXT:    s_cselect_b64 s[10:11], s[10:11], s[16:17]
5816; GFX6-NEXT:    s_cmp_lg_u32 s21, 0
5817; GFX6-NEXT:    s_cselect_b64 s[10:11], s[4:5], s[10:11]
5818; GFX6-NEXT:    s_sub_i32 s18, s8, 64
5819; GFX6-NEXT:    s_sub_i32 s16, 64, s8
5820; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5821; GFX6-NEXT:    s_cselect_b32 s19, 1, 0
5822; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5823; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
5824; GFX6-NEXT:    s_lshr_b64 s[4:5], s[14:15], s8
5825; GFX6-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8
5826; GFX6-NEXT:    s_lshl_b64 s[16:17], s[14:15], s16
5827; GFX6-NEXT:    s_or_b64 s[8:9], s[8:9], s[16:17]
5828; GFX6-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
5829; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
5830; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
5831; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
5832; GFX6-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
5833; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
5834; GFX6-NEXT:    s_cselect_b64 s[12:13], s[4:5], 0
5835; GFX6-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
5836; GFX6-NEXT:    s_or_b64 s[6:7], s[10:11], s[12:13]
5837; GFX6-NEXT:    ; return to shader part epilog
5838;
5839; GFX8-LABEL: s_fshr_v2i128:
5840; GFX8:       ; %bb.0:
5841; GFX8-NEXT:    s_movk_i32 s18, 0x7f
5842; GFX8-NEXT:    s_mov_b32 s19, 0
5843; GFX8-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
5844; GFX8-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
5845; GFX8-NEXT:    s_lshl_b64 s[24:25], s[0:1], 1
5846; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5847; GFX8-NEXT:    s_lshr_b32 s0, s1, 31
5848; GFX8-NEXT:    s_mov_b32 s1, s19
5849; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
5850; GFX8-NEXT:    s_sub_i32 s23, s16, 64
5851; GFX8-NEXT:    s_sub_i32 s17, 64, s16
5852; GFX8-NEXT:    s_cmp_lt_u32 s16, 64
5853; GFX8-NEXT:    s_cselect_b32 s28, 1, 0
5854; GFX8-NEXT:    s_cmp_eq_u32 s16, 0
5855; GFX8-NEXT:    s_cselect_b32 s29, 1, 0
5856; GFX8-NEXT:    s_lshl_b64 s[2:3], s[24:25], s16
5857; GFX8-NEXT:    s_lshr_b64 s[26:27], s[24:25], s17
5858; GFX8-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
5859; GFX8-NEXT:    s_or_b64 s[16:17], s[26:27], s[16:17]
5860; GFX8-NEXT:    s_lshl_b64 s[24:25], s[24:25], s23
5861; GFX8-NEXT:    s_cmp_lg_u32 s28, 0
5862; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5863; GFX8-NEXT:    s_cselect_b64 s[16:17], s[16:17], s[24:25]
5864; GFX8-NEXT:    s_cmp_lg_u32 s29, 0
5865; GFX8-NEXT:    s_cselect_b64 s[16:17], s[0:1], s[16:17]
5866; GFX8-NEXT:    s_sub_i32 s26, s22, 64
5867; GFX8-NEXT:    s_sub_i32 s24, 64, s22
5868; GFX8-NEXT:    s_cmp_lt_u32 s22, 64
5869; GFX8-NEXT:    s_cselect_b32 s27, 1, 0
5870; GFX8-NEXT:    s_cmp_eq_u32 s22, 0
5871; GFX8-NEXT:    s_cselect_b32 s28, 1, 0
5872; GFX8-NEXT:    s_lshr_b64 s[0:1], s[10:11], s22
5873; GFX8-NEXT:    s_lshr_b64 s[22:23], s[8:9], s22
5874; GFX8-NEXT:    s_lshl_b64 s[24:25], s[10:11], s24
5875; GFX8-NEXT:    s_or_b64 s[22:23], s[22:23], s[24:25]
5876; GFX8-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
5877; GFX8-NEXT:    s_cmp_lg_u32 s27, 0
5878; GFX8-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
5879; GFX8-NEXT:    s_cmp_lg_u32 s28, 0
5880; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
5881; GFX8-NEXT:    s_cmp_lg_u32 s27, 0
5882; GFX8-NEXT:    s_cselect_b64 s[10:11], s[0:1], 0
5883; GFX8-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
5884; GFX8-NEXT:    s_or_b64 s[2:3], s[16:17], s[10:11]
5885; GFX8-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
5886; GFX8-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
5887; GFX8-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
5888; GFX8-NEXT:    s_lshr_b32 s18, s5, 31
5889; GFX8-NEXT:    s_lshl_b64 s[16:17], s[4:5], 1
5890; GFX8-NEXT:    s_or_b64 s[4:5], s[6:7], s[18:19]
5891; GFX8-NEXT:    s_sub_i32 s9, s10, 64
5892; GFX8-NEXT:    s_sub_i32 s11, 64, s10
5893; GFX8-NEXT:    s_cmp_lt_u32 s10, 64
5894; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
5895; GFX8-NEXT:    s_cmp_eq_u32 s10, 0
5896; GFX8-NEXT:    s_cselect_b32 s21, 1, 0
5897; GFX8-NEXT:    s_lshl_b64 s[6:7], s[16:17], s10
5898; GFX8-NEXT:    s_lshr_b64 s[18:19], s[16:17], s11
5899; GFX8-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
5900; GFX8-NEXT:    s_or_b64 s[10:11], s[18:19], s[10:11]
5901; GFX8-NEXT:    s_lshl_b64 s[16:17], s[16:17], s9
5902; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
5903; GFX8-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5904; GFX8-NEXT:    s_cselect_b64 s[10:11], s[10:11], s[16:17]
5905; GFX8-NEXT:    s_cmp_lg_u32 s21, 0
5906; GFX8-NEXT:    s_cselect_b64 s[10:11], s[4:5], s[10:11]
5907; GFX8-NEXT:    s_sub_i32 s18, s8, 64
5908; GFX8-NEXT:    s_sub_i32 s16, 64, s8
5909; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
5910; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
5911; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
5912; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
5913; GFX8-NEXT:    s_lshr_b64 s[4:5], s[14:15], s8
5914; GFX8-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8
5915; GFX8-NEXT:    s_lshl_b64 s[16:17], s[14:15], s16
5916; GFX8-NEXT:    s_or_b64 s[8:9], s[8:9], s[16:17]
5917; GFX8-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
5918; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
5919; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
5920; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
5921; GFX8-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
5922; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
5923; GFX8-NEXT:    s_cselect_b64 s[12:13], s[4:5], 0
5924; GFX8-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
5925; GFX8-NEXT:    s_or_b64 s[6:7], s[10:11], s[12:13]
5926; GFX8-NEXT:    ; return to shader part epilog
5927;
5928; GFX9-LABEL: s_fshr_v2i128:
5929; GFX9:       ; %bb.0:
5930; GFX9-NEXT:    s_movk_i32 s18, 0x7f
5931; GFX9-NEXT:    s_mov_b32 s19, 0
5932; GFX9-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
5933; GFX9-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
5934; GFX9-NEXT:    s_lshl_b64 s[24:25], s[0:1], 1
5935; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
5936; GFX9-NEXT:    s_lshr_b32 s0, s1, 31
5937; GFX9-NEXT:    s_mov_b32 s1, s19
5938; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
5939; GFX9-NEXT:    s_sub_i32 s23, s16, 64
5940; GFX9-NEXT:    s_sub_i32 s17, 64, s16
5941; GFX9-NEXT:    s_cmp_lt_u32 s16, 64
5942; GFX9-NEXT:    s_cselect_b32 s28, 1, 0
5943; GFX9-NEXT:    s_cmp_eq_u32 s16, 0
5944; GFX9-NEXT:    s_cselect_b32 s29, 1, 0
5945; GFX9-NEXT:    s_lshl_b64 s[2:3], s[24:25], s16
5946; GFX9-NEXT:    s_lshr_b64 s[26:27], s[24:25], s17
5947; GFX9-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
5948; GFX9-NEXT:    s_or_b64 s[16:17], s[26:27], s[16:17]
5949; GFX9-NEXT:    s_lshl_b64 s[24:25], s[24:25], s23
5950; GFX9-NEXT:    s_cmp_lg_u32 s28, 0
5951; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], 0
5952; GFX9-NEXT:    s_cselect_b64 s[16:17], s[16:17], s[24:25]
5953; GFX9-NEXT:    s_cmp_lg_u32 s29, 0
5954; GFX9-NEXT:    s_cselect_b64 s[16:17], s[0:1], s[16:17]
5955; GFX9-NEXT:    s_sub_i32 s26, s22, 64
5956; GFX9-NEXT:    s_sub_i32 s24, 64, s22
5957; GFX9-NEXT:    s_cmp_lt_u32 s22, 64
5958; GFX9-NEXT:    s_cselect_b32 s27, 1, 0
5959; GFX9-NEXT:    s_cmp_eq_u32 s22, 0
5960; GFX9-NEXT:    s_cselect_b32 s28, 1, 0
5961; GFX9-NEXT:    s_lshr_b64 s[0:1], s[10:11], s22
5962; GFX9-NEXT:    s_lshr_b64 s[22:23], s[8:9], s22
5963; GFX9-NEXT:    s_lshl_b64 s[24:25], s[10:11], s24
5964; GFX9-NEXT:    s_or_b64 s[22:23], s[22:23], s[24:25]
5965; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
5966; GFX9-NEXT:    s_cmp_lg_u32 s27, 0
5967; GFX9-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
5968; GFX9-NEXT:    s_cmp_lg_u32 s28, 0
5969; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
5970; GFX9-NEXT:    s_cmp_lg_u32 s27, 0
5971; GFX9-NEXT:    s_cselect_b64 s[10:11], s[0:1], 0
5972; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[8:9]
5973; GFX9-NEXT:    s_or_b64 s[2:3], s[16:17], s[10:11]
5974; GFX9-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
5975; GFX9-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
5976; GFX9-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
5977; GFX9-NEXT:    s_lshr_b32 s18, s5, 31
5978; GFX9-NEXT:    s_lshl_b64 s[16:17], s[4:5], 1
5979; GFX9-NEXT:    s_or_b64 s[4:5], s[6:7], s[18:19]
5980; GFX9-NEXT:    s_sub_i32 s9, s10, 64
5981; GFX9-NEXT:    s_sub_i32 s11, 64, s10
5982; GFX9-NEXT:    s_cmp_lt_u32 s10, 64
5983; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
5984; GFX9-NEXT:    s_cmp_eq_u32 s10, 0
5985; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
5986; GFX9-NEXT:    s_lshl_b64 s[6:7], s[16:17], s10
5987; GFX9-NEXT:    s_lshr_b64 s[18:19], s[16:17], s11
5988; GFX9-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
5989; GFX9-NEXT:    s_or_b64 s[10:11], s[18:19], s[10:11]
5990; GFX9-NEXT:    s_lshl_b64 s[16:17], s[16:17], s9
5991; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
5992; GFX9-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5993; GFX9-NEXT:    s_cselect_b64 s[10:11], s[10:11], s[16:17]
5994; GFX9-NEXT:    s_cmp_lg_u32 s21, 0
5995; GFX9-NEXT:    s_cselect_b64 s[10:11], s[4:5], s[10:11]
5996; GFX9-NEXT:    s_sub_i32 s18, s8, 64
5997; GFX9-NEXT:    s_sub_i32 s16, 64, s8
5998; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
5999; GFX9-NEXT:    s_cselect_b32 s19, 1, 0
6000; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
6001; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
6002; GFX9-NEXT:    s_lshr_b64 s[4:5], s[14:15], s8
6003; GFX9-NEXT:    s_lshr_b64 s[8:9], s[12:13], s8
6004; GFX9-NEXT:    s_lshl_b64 s[16:17], s[14:15], s16
6005; GFX9-NEXT:    s_or_b64 s[8:9], s[8:9], s[16:17]
6006; GFX9-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
6007; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
6008; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6009; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
6010; GFX9-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6011; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
6012; GFX9-NEXT:    s_cselect_b64 s[12:13], s[4:5], 0
6013; GFX9-NEXT:    s_or_b64 s[4:5], s[6:7], s[8:9]
6014; GFX9-NEXT:    s_or_b64 s[6:7], s[10:11], s[12:13]
6015; GFX9-NEXT:    ; return to shader part epilog
6016;
6017; GFX10-LABEL: s_fshr_v2i128:
6018; GFX10:       ; %bb.0:
6019; GFX10-NEXT:    s_movk_i32 s18, 0x7f
6020; GFX10-NEXT:    s_mov_b32 s19, 0
6021; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], 1
6022; GFX10-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6023; GFX10-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6024; GFX10-NEXT:    s_lshr_b32 s24, s1, 31
6025; GFX10-NEXT:    s_mov_b32 s25, s19
6026; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], 1
6027; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[24:25]
6028; GFX10-NEXT:    s_sub_i32 s23, s16, 64
6029; GFX10-NEXT:    s_sub_i32 s17, 64, s16
6030; GFX10-NEXT:    s_cmp_lt_u32 s16, 64
6031; GFX10-NEXT:    s_cselect_b32 s28, 1, 0
6032; GFX10-NEXT:    s_cmp_eq_u32 s16, 0
6033; GFX10-NEXT:    s_cselect_b32 s29, 1, 0
6034; GFX10-NEXT:    s_lshr_b64 s[24:25], s[0:1], s17
6035; GFX10-NEXT:    s_lshl_b64 s[26:27], s[2:3], s16
6036; GFX10-NEXT:    s_lshl_b64 s[16:17], s[0:1], s16
6037; GFX10-NEXT:    s_or_b64 s[24:25], s[24:25], s[26:27]
6038; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s23
6039; GFX10-NEXT:    s_cmp_lg_u32 s28, 0
6040; GFX10-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6041; GFX10-NEXT:    s_cselect_b64 s[0:1], s[24:25], s[0:1]
6042; GFX10-NEXT:    s_cmp_lg_u32 s29, 0
6043; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6044; GFX10-NEXT:    s_sub_i32 s26, s22, 64
6045; GFX10-NEXT:    s_sub_i32 s23, 64, s22
6046; GFX10-NEXT:    s_cmp_lt_u32 s22, 64
6047; GFX10-NEXT:    s_cselect_b32 s27, 1, 0
6048; GFX10-NEXT:    s_cmp_eq_u32 s22, 0
6049; GFX10-NEXT:    s_cselect_b32 s28, 1, 0
6050; GFX10-NEXT:    s_lshr_b64 s[0:1], s[8:9], s22
6051; GFX10-NEXT:    s_lshl_b64 s[24:25], s[10:11], s23
6052; GFX10-NEXT:    s_lshr_b64 s[22:23], s[10:11], s22
6053; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[24:25]
6054; GFX10-NEXT:    s_lshr_b64 s[10:11], s[10:11], s26
6055; GFX10-NEXT:    s_cmp_lg_u32 s27, 0
6056; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[10:11]
6057; GFX10-NEXT:    s_cmp_lg_u32 s28, 0
6058; GFX10-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6059; GFX10-NEXT:    s_cmp_lg_u32 s27, 0
6060; GFX10-NEXT:    s_cselect_b64 s[8:9], s[22:23], 0
6061; GFX10-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6062; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
6063; GFX10-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6064; GFX10-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
6065; GFX10-NEXT:    s_lshr_b32 s18, s5, 31
6066; GFX10-NEXT:    s_or_b64 s[0:1], s[16:17], s[0:1]
6067; GFX10-NEXT:    s_lshl_b64 s[4:5], s[4:5], 1
6068; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[18:19]
6069; GFX10-NEXT:    s_sub_i32 s9, s10, 64
6070; GFX10-NEXT:    s_sub_i32 s11, 64, s10
6071; GFX10-NEXT:    s_cmp_lt_u32 s10, 64
6072; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
6073; GFX10-NEXT:    s_cmp_eq_u32 s10, 0
6074; GFX10-NEXT:    s_cselect_b32 s21, 1, 0
6075; GFX10-NEXT:    s_lshr_b64 s[16:17], s[4:5], s11
6076; GFX10-NEXT:    s_lshl_b64 s[18:19], s[6:7], s10
6077; GFX10-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
6078; GFX10-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
6079; GFX10-NEXT:    s_lshl_b64 s[4:5], s[4:5], s9
6080; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
6081; GFX10-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
6082; GFX10-NEXT:    s_cselect_b64 s[4:5], s[16:17], s[4:5]
6083; GFX10-NEXT:    s_cmp_lg_u32 s21, 0
6084; GFX10-NEXT:    s_cselect_b64 s[6:7], s[6:7], s[4:5]
6085; GFX10-NEXT:    s_sub_i32 s18, s8, 64
6086; GFX10-NEXT:    s_sub_i32 s9, 64, s8
6087; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
6088; GFX10-NEXT:    s_cselect_b32 s19, 1, 0
6089; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
6090; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
6091; GFX10-NEXT:    s_lshr_b64 s[4:5], s[12:13], s8
6092; GFX10-NEXT:    s_lshl_b64 s[16:17], s[14:15], s9
6093; GFX10-NEXT:    s_lshr_b64 s[8:9], s[14:15], s8
6094; GFX10-NEXT:    s_or_b64 s[4:5], s[4:5], s[16:17]
6095; GFX10-NEXT:    s_lshr_b64 s[14:15], s[14:15], s18
6096; GFX10-NEXT:    s_cmp_lg_u32 s19, 0
6097; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[14:15]
6098; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
6099; GFX10-NEXT:    s_cselect_b64 s[4:5], s[12:13], s[4:5]
6100; GFX10-NEXT:    s_cmp_lg_u32 s19, 0
6101; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
6102; GFX10-NEXT:    s_or_b64 s[4:5], s[10:11], s[4:5]
6103; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6104; GFX10-NEXT:    ; return to shader part epilog
6105  %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
6106  ret <2 x i128> %result
6107}
6108
6109define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) {
6110; GFX6-LABEL: v_fshr_v2i128:
6111; GFX6:       ; %bb.0:
6112; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6113; GFX6-NEXT:    v_xor_b32_e32 v17, -1, v16
6114; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
6115; GFX6-NEXT:    v_and_b32_e32 v23, 0x7f, v17
6116; GFX6-NEXT:    v_lshrrev_b32_e32 v17, 31, v1
6117; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
6118; GFX6-NEXT:    v_or_b32_e32 v2, v2, v17
6119; GFX6-NEXT:    v_sub_i32_e32 v17, vcc, 64, v23
6120; GFX6-NEXT:    v_lshr_b64 v[17:18], v[0:1], v17
6121; GFX6-NEXT:    v_lshl_b64 v[21:22], v[2:3], v23
6122; GFX6-NEXT:    v_and_b32_e32 v24, 0x7f, v16
6123; GFX6-NEXT:    v_sub_i32_e32 v16, vcc, 64, v24
6124; GFX6-NEXT:    v_or_b32_e32 v21, v17, v21
6125; GFX6-NEXT:    v_or_b32_e32 v22, v18, v22
6126; GFX6-NEXT:    v_lshl_b64 v[16:17], v[10:11], v16
6127; GFX6-NEXT:    v_lshr_b64 v[18:19], v[8:9], v24
6128; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
6129; GFX6-NEXT:    v_or_b32_e32 v18, v18, v16
6130; GFX6-NEXT:    v_subrev_i32_e32 v16, vcc, 64, v23
6131; GFX6-NEXT:    v_or_b32_e32 v19, v19, v17
6132; GFX6-NEXT:    v_lshl_b64 v[16:17], v[0:1], v16
6133; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v23
6134; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
6135; GFX6-NEXT:    v_cndmask_b32_e32 v25, 0, v0, vcc
6136; GFX6-NEXT:    v_cndmask_b32_e32 v0, v16, v21, vcc
6137; GFX6-NEXT:    v_cndmask_b32_e32 v16, v17, v22, vcc
6138; GFX6-NEXT:    v_cndmask_b32_e64 v17, v0, v2, s[4:5]
6139; GFX6-NEXT:    v_cndmask_b32_e64 v16, v16, v3, s[4:5]
6140; GFX6-NEXT:    v_subrev_i32_e64 v0, s[4:5], 64, v24
6141; GFX6-NEXT:    v_lshr_b64 v[2:3], v[10:11], v0
6142; GFX6-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v24
6143; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v18, s[4:5]
6144; GFX6-NEXT:    v_cndmask_b32_e32 v18, 0, v1, vcc
6145; GFX6-NEXT:    v_lshr_b64 v[0:1], v[10:11], v24
6146; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v24
6147; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v19, s[4:5]
6148; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
6149; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, v0, s[4:5]
6150; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
6151; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, v1, s[4:5]
6152; GFX6-NEXT:    v_or_b32_e32 v0, v25, v2
6153; GFX6-NEXT:    v_or_b32_e32 v2, v17, v8
6154; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v20
6155; GFX6-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
6156; GFX6-NEXT:    v_or_b32_e32 v1, v18, v3
6157; GFX6-NEXT:    v_or_b32_e32 v3, v16, v9
6158; GFX6-NEXT:    v_and_b32_e32 v17, 0x7f, v8
6159; GFX6-NEXT:    v_lshl_b64 v[8:9], v[4:5], 1
6160; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 31, v5
6161; GFX6-NEXT:    v_or_b32_e32 v6, v6, v4
6162; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 64, v17
6163; GFX6-NEXT:    v_lshr_b64 v[4:5], v[8:9], v4
6164; GFX6-NEXT:    v_lshl_b64 v[10:11], v[6:7], v17
6165; GFX6-NEXT:    v_subrev_i32_e32 v18, vcc, 64, v17
6166; GFX6-NEXT:    v_or_b32_e32 v10, v4, v10
6167; GFX6-NEXT:    v_or_b32_e32 v11, v5, v11
6168; GFX6-NEXT:    v_lshl_b64 v[4:5], v[8:9], v17
6169; GFX6-NEXT:    v_lshl_b64 v[8:9], v[8:9], v18
6170; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
6171; GFX6-NEXT:    v_and_b32_e32 v16, 0x7f, v20
6172; GFX6-NEXT:    v_cndmask_b32_e32 v18, 0, v4, vcc
6173; GFX6-NEXT:    v_cndmask_b32_e32 v19, 0, v5, vcc
6174; GFX6-NEXT:    v_cndmask_b32_e32 v4, v8, v10, vcc
6175; GFX6-NEXT:    v_cndmask_b32_e32 v5, v9, v11, vcc
6176; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v17
6177; GFX6-NEXT:    v_cndmask_b32_e32 v8, v4, v6, vcc
6178; GFX6-NEXT:    v_cndmask_b32_e32 v9, v5, v7, vcc
6179; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 64, v16
6180; GFX6-NEXT:    v_lshr_b64 v[4:5], v[12:13], v16
6181; GFX6-NEXT:    v_lshl_b64 v[6:7], v[14:15], v6
6182; GFX6-NEXT:    v_subrev_i32_e32 v10, vcc, 64, v16
6183; GFX6-NEXT:    v_or_b32_e32 v11, v4, v6
6184; GFX6-NEXT:    v_or_b32_e32 v17, v5, v7
6185; GFX6-NEXT:    v_lshr_b64 v[6:7], v[14:15], v10
6186; GFX6-NEXT:    v_lshr_b64 v[4:5], v[14:15], v16
6187; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
6188; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
6189; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v17, vcc
6190; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v16
6191; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
6192; GFX6-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
6193; GFX6-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
6194; GFX6-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
6195; GFX6-NEXT:    v_or_b32_e32 v4, v18, v6
6196; GFX6-NEXT:    v_or_b32_e32 v5, v19, v7
6197; GFX6-NEXT:    v_or_b32_e32 v6, v8, v10
6198; GFX6-NEXT:    v_or_b32_e32 v7, v9, v11
6199; GFX6-NEXT:    s_setpc_b64 s[30:31]
6200;
6201; GFX8-LABEL: v_fshr_v2i128:
6202; GFX8:       ; %bb.0:
6203; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6204; GFX8-NEXT:    v_xor_b32_e32 v17, -1, v16
6205; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
6206; GFX8-NEXT:    v_and_b32_e32 v23, 0x7f, v17
6207; GFX8-NEXT:    v_lshrrev_b32_e32 v17, 31, v1
6208; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
6209; GFX8-NEXT:    v_or_b32_e32 v2, v2, v17
6210; GFX8-NEXT:    v_sub_u32_e32 v17, vcc, 64, v23
6211; GFX8-NEXT:    v_lshrrev_b64 v[17:18], v17, v[0:1]
6212; GFX8-NEXT:    v_lshlrev_b64 v[21:22], v23, v[2:3]
6213; GFX8-NEXT:    v_and_b32_e32 v24, 0x7f, v16
6214; GFX8-NEXT:    v_sub_u32_e32 v16, vcc, 64, v24
6215; GFX8-NEXT:    v_or_b32_e32 v21, v17, v21
6216; GFX8-NEXT:    v_or_b32_e32 v22, v18, v22
6217; GFX8-NEXT:    v_lshlrev_b64 v[16:17], v16, v[10:11]
6218; GFX8-NEXT:    v_lshrrev_b64 v[18:19], v24, v[8:9]
6219; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
6220; GFX8-NEXT:    v_or_b32_e32 v18, v18, v16
6221; GFX8-NEXT:    v_subrev_u32_e32 v16, vcc, 64, v23
6222; GFX8-NEXT:    v_or_b32_e32 v19, v19, v17
6223; GFX8-NEXT:    v_lshlrev_b64 v[16:17], v16, v[0:1]
6224; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v23, v[0:1]
6225; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
6226; GFX8-NEXT:    v_cndmask_b32_e32 v25, 0, v0, vcc
6227; GFX8-NEXT:    v_cndmask_b32_e32 v0, v16, v21, vcc
6228; GFX8-NEXT:    v_cndmask_b32_e32 v16, v17, v22, vcc
6229; GFX8-NEXT:    v_cndmask_b32_e64 v17, v0, v2, s[4:5]
6230; GFX8-NEXT:    v_cndmask_b32_e64 v16, v16, v3, s[4:5]
6231; GFX8-NEXT:    v_subrev_u32_e64 v0, s[4:5], 64, v24
6232; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v0, v[10:11]
6233; GFX8-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v24
6234; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, v18, s[4:5]
6235; GFX8-NEXT:    v_cndmask_b32_e32 v18, 0, v1, vcc
6236; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v24, v[10:11]
6237; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v24
6238; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, v19, s[4:5]
6239; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
6240; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, v0, s[4:5]
6241; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
6242; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, v1, s[4:5]
6243; GFX8-NEXT:    v_or_b32_e32 v0, v25, v2
6244; GFX8-NEXT:    v_or_b32_e32 v2, v17, v8
6245; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v20
6246; GFX8-NEXT:    v_lshlrev_b64 v[6:7], 1, v[6:7]
6247; GFX8-NEXT:    v_or_b32_e32 v1, v18, v3
6248; GFX8-NEXT:    v_or_b32_e32 v3, v16, v9
6249; GFX8-NEXT:    v_and_b32_e32 v17, 0x7f, v8
6250; GFX8-NEXT:    v_lshlrev_b64 v[8:9], 1, v[4:5]
6251; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 31, v5
6252; GFX8-NEXT:    v_or_b32_e32 v6, v6, v4
6253; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 64, v17
6254; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v4, v[8:9]
6255; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v17, v[6:7]
6256; GFX8-NEXT:    v_subrev_u32_e32 v18, vcc, 64, v17
6257; GFX8-NEXT:    v_or_b32_e32 v10, v4, v10
6258; GFX8-NEXT:    v_or_b32_e32 v11, v5, v11
6259; GFX8-NEXT:    v_lshlrev_b64 v[4:5], v17, v[8:9]
6260; GFX8-NEXT:    v_lshlrev_b64 v[8:9], v18, v[8:9]
6261; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
6262; GFX8-NEXT:    v_and_b32_e32 v16, 0x7f, v20
6263; GFX8-NEXT:    v_cndmask_b32_e32 v18, 0, v4, vcc
6264; GFX8-NEXT:    v_cndmask_b32_e32 v19, 0, v5, vcc
6265; GFX8-NEXT:    v_cndmask_b32_e32 v4, v8, v10, vcc
6266; GFX8-NEXT:    v_cndmask_b32_e32 v5, v9, v11, vcc
6267; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v17
6268; GFX8-NEXT:    v_cndmask_b32_e32 v8, v4, v6, vcc
6269; GFX8-NEXT:    v_cndmask_b32_e32 v9, v5, v7, vcc
6270; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 64, v16
6271; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v16, v[12:13]
6272; GFX8-NEXT:    v_lshlrev_b64 v[6:7], v6, v[14:15]
6273; GFX8-NEXT:    v_subrev_u32_e32 v10, vcc, 64, v16
6274; GFX8-NEXT:    v_or_b32_e32 v11, v4, v6
6275; GFX8-NEXT:    v_or_b32_e32 v17, v5, v7
6276; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v10, v[14:15]
6277; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v16, v[14:15]
6278; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
6279; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
6280; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v17, vcc
6281; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v16
6282; GFX8-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
6283; GFX8-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
6284; GFX8-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
6285; GFX8-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
6286; GFX8-NEXT:    v_or_b32_e32 v4, v18, v6
6287; GFX8-NEXT:    v_or_b32_e32 v5, v19, v7
6288; GFX8-NEXT:    v_or_b32_e32 v6, v8, v10
6289; GFX8-NEXT:    v_or_b32_e32 v7, v9, v11
6290; GFX8-NEXT:    s_setpc_b64 s[30:31]
6291;
6292; GFX9-LABEL: v_fshr_v2i128:
6293; GFX9:       ; %bb.0:
6294; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6295; GFX9-NEXT:    v_xor_b32_e32 v17, -1, v16
6296; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
6297; GFX9-NEXT:    v_and_b32_e32 v23, 0x7f, v17
6298; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 31, v1
6299; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
6300; GFX9-NEXT:    v_or_b32_e32 v2, v2, v17
6301; GFX9-NEXT:    v_sub_u32_e32 v17, 64, v23
6302; GFX9-NEXT:    v_lshrrev_b64 v[17:18], v17, v[0:1]
6303; GFX9-NEXT:    v_lshlrev_b64 v[21:22], v23, v[2:3]
6304; GFX9-NEXT:    v_and_b32_e32 v24, 0x7f, v16
6305; GFX9-NEXT:    v_sub_u32_e32 v16, 64, v24
6306; GFX9-NEXT:    v_or_b32_e32 v21, v17, v21
6307; GFX9-NEXT:    v_or_b32_e32 v22, v18, v22
6308; GFX9-NEXT:    v_lshlrev_b64 v[16:17], v16, v[10:11]
6309; GFX9-NEXT:    v_lshrrev_b64 v[18:19], v24, v[8:9]
6310; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
6311; GFX9-NEXT:    v_or_b32_e32 v18, v18, v16
6312; GFX9-NEXT:    v_subrev_u32_e32 v16, 64, v23
6313; GFX9-NEXT:    v_or_b32_e32 v19, v19, v17
6314; GFX9-NEXT:    v_lshlrev_b64 v[16:17], v16, v[0:1]
6315; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v23, v[0:1]
6316; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
6317; GFX9-NEXT:    v_cndmask_b32_e32 v25, 0, v0, vcc
6318; GFX9-NEXT:    v_cndmask_b32_e32 v0, v16, v21, vcc
6319; GFX9-NEXT:    v_cndmask_b32_e32 v16, v17, v22, vcc
6320; GFX9-NEXT:    v_cndmask_b32_e64 v17, v0, v2, s[4:5]
6321; GFX9-NEXT:    v_subrev_u32_e32 v0, 64, v24
6322; GFX9-NEXT:    v_cndmask_b32_e64 v16, v16, v3, s[4:5]
6323; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v0, v[10:11]
6324; GFX9-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v24
6325; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, v18, s[4:5]
6326; GFX9-NEXT:    v_cndmask_b32_e32 v18, 0, v1, vcc
6327; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v24, v[10:11]
6328; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v24
6329; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v19, s[4:5]
6330; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
6331; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, v0, s[4:5]
6332; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
6333; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, v1, s[4:5]
6334; GFX9-NEXT:    v_or_b32_e32 v0, v25, v2
6335; GFX9-NEXT:    v_or_b32_e32 v2, v17, v8
6336; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v20
6337; GFX9-NEXT:    v_lshlrev_b64 v[6:7], 1, v[6:7]
6338; GFX9-NEXT:    v_or_b32_e32 v1, v18, v3
6339; GFX9-NEXT:    v_or_b32_e32 v3, v16, v9
6340; GFX9-NEXT:    v_and_b32_e32 v17, 0x7f, v8
6341; GFX9-NEXT:    v_lshlrev_b64 v[8:9], 1, v[4:5]
6342; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 31, v5
6343; GFX9-NEXT:    v_or_b32_e32 v6, v6, v4
6344; GFX9-NEXT:    v_sub_u32_e32 v4, 64, v17
6345; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v4, v[8:9]
6346; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v17, v[6:7]
6347; GFX9-NEXT:    v_subrev_u32_e32 v18, 64, v17
6348; GFX9-NEXT:    v_or_b32_e32 v10, v4, v10
6349; GFX9-NEXT:    v_or_b32_e32 v11, v5, v11
6350; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v17, v[8:9]
6351; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v18, v[8:9]
6352; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
6353; GFX9-NEXT:    v_and_b32_e32 v16, 0x7f, v20
6354; GFX9-NEXT:    v_cndmask_b32_e32 v18, 0, v4, vcc
6355; GFX9-NEXT:    v_cndmask_b32_e32 v19, 0, v5, vcc
6356; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v10, vcc
6357; GFX9-NEXT:    v_cndmask_b32_e32 v5, v9, v11, vcc
6358; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v17
6359; GFX9-NEXT:    v_cndmask_b32_e32 v8, v4, v6, vcc
6360; GFX9-NEXT:    v_sub_u32_e32 v6, 64, v16
6361; GFX9-NEXT:    v_cndmask_b32_e32 v9, v5, v7, vcc
6362; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v16, v[12:13]
6363; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v6, v[14:15]
6364; GFX9-NEXT:    v_subrev_u32_e32 v10, 64, v16
6365; GFX9-NEXT:    v_or_b32_e32 v11, v4, v6
6366; GFX9-NEXT:    v_or_b32_e32 v17, v5, v7
6367; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v10, v[14:15]
6368; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v16, v[14:15]
6369; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
6370; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v11, vcc
6371; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v17, vcc
6372; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v16
6373; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
6374; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
6375; GFX9-NEXT:    v_cndmask_b32_e32 v10, 0, v4, vcc
6376; GFX9-NEXT:    v_cndmask_b32_e32 v11, 0, v5, vcc
6377; GFX9-NEXT:    v_or_b32_e32 v4, v18, v6
6378; GFX9-NEXT:    v_or_b32_e32 v5, v19, v7
6379; GFX9-NEXT:    v_or_b32_e32 v6, v8, v10
6380; GFX9-NEXT:    v_or_b32_e32 v7, v9, v11
6381; GFX9-NEXT:    s_setpc_b64 s[30:31]
6382;
6383; GFX10-LABEL: v_fshr_v2i128:
6384; GFX10:       ; %bb.0:
6385; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6386; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
6387; GFX10-NEXT:    v_xor_b32_e32 v17, -1, v16
6388; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
6389; GFX10-NEXT:    v_and_b32_e32 v26, 0x7f, v16
6390; GFX10-NEXT:    v_lshlrev_b64 v[6:7], 1, v[6:7]
6391; GFX10-NEXT:    v_and_b32_e32 v25, 0x7f, v17
6392; GFX10-NEXT:    v_lshrrev_b32_e32 v17, 31, v1
6393; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
6394; GFX10-NEXT:    v_subrev_nc_u32_e32 v27, 64, v26
6395; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v26
6396; GFX10-NEXT:    v_sub_nc_u32_e32 v18, 64, v25
6397; GFX10-NEXT:    v_or_b32_e32 v2, v2, v17
6398; GFX10-NEXT:    v_subrev_nc_u32_e32 v19, 64, v25
6399; GFX10-NEXT:    v_lshlrev_b64 v[23:24], v25, v[0:1]
6400; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v25
6401; GFX10-NEXT:    v_lshrrev_b64 v[17:18], v18, v[0:1]
6402; GFX10-NEXT:    v_lshlrev_b64 v[21:22], v25, v[2:3]
6403; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v19, v[0:1]
6404; GFX10-NEXT:    v_cndmask_b32_e32 v23, 0, v23, vcc_lo
6405; GFX10-NEXT:    v_cndmask_b32_e32 v24, 0, v24, vcc_lo
6406; GFX10-NEXT:    v_or_b32_e32 v22, v18, v22
6407; GFX10-NEXT:    v_sub_nc_u32_e32 v18, 64, v26
6408; GFX10-NEXT:    v_or_b32_e32 v21, v17, v21
6409; GFX10-NEXT:    v_lshrrev_b64 v[16:17], v26, v[8:9]
6410; GFX10-NEXT:    v_cndmask_b32_e32 v22, v1, v22, vcc_lo
6411; GFX10-NEXT:    v_lshlrev_b64 v[18:19], v18, v[10:11]
6412; GFX10-NEXT:    v_cndmask_b32_e32 v21, v0, v21, vcc_lo
6413; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v27, v[10:11]
6414; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v25
6415; GFX10-NEXT:    v_or_b32_e32 v16, v16, v18
6416; GFX10-NEXT:    v_or_b32_e32 v17, v17, v19
6417; GFX10-NEXT:    v_cndmask_b32_e32 v18, v21, v2, vcc_lo
6418; GFX10-NEXT:    v_cndmask_b32_e32 v22, v22, v3, vcc_lo
6419; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v26
6420; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v16, s4
6421; GFX10-NEXT:    v_xor_b32_e32 v16, -1, v20
6422; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v17, s4
6423; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v26, v[10:11]
6424; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo
6425; GFX10-NEXT:    v_and_b32_e32 v25, 0x7f, v16
6426; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 31, v5
6427; GFX10-NEXT:    v_lshlrev_b64 v[4:5], 1, v[4:5]
6428; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo
6429; GFX10-NEXT:    v_or_b32_e32 v0, v23, v0
6430; GFX10-NEXT:    v_sub_nc_u32_e32 v9, 64, v25
6431; GFX10-NEXT:    v_or_b32_e32 v6, v6, v8
6432; GFX10-NEXT:    v_and_b32_e32 v23, 0x7f, v20
6433; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s4
6434; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, v3, s4
6435; GFX10-NEXT:    v_lshrrev_b64 v[8:9], v9, v[4:5]
6436; GFX10-NEXT:    v_lshlrev_b64 v[10:11], v25, v[6:7]
6437; GFX10-NEXT:    v_sub_nc_u32_e32 v20, 64, v23
6438; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 64, v25
6439; GFX10-NEXT:    v_or_b32_e32 v2, v18, v2
6440; GFX10-NEXT:    v_lshlrev_b64 v[16:17], v25, v[4:5]
6441; GFX10-NEXT:    v_lshrrev_b64 v[18:19], v23, v[12:13]
6442; GFX10-NEXT:    v_or_b32_e32 v10, v8, v10
6443; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, 64, v23
6444; GFX10-NEXT:    v_lshlrev_b64 v[20:21], v20, v[14:15]
6445; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v25
6446; GFX10-NEXT:    v_lshlrev_b64 v[3:4], v3, v[4:5]
6447; GFX10-NEXT:    v_or_b32_e32 v5, v9, v11
6448; GFX10-NEXT:    v_lshrrev_b64 v[8:9], v8, v[14:15]
6449; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v23
6450; GFX10-NEXT:    v_cndmask_b32_e32 v11, 0, v16, vcc_lo
6451; GFX10-NEXT:    v_or_b32_e32 v16, v18, v20
6452; GFX10-NEXT:    v_or_b32_e32 v18, v19, v21
6453; GFX10-NEXT:    v_cndmask_b32_e32 v10, v3, v10, vcc_lo
6454; GFX10-NEXT:    v_cndmask_b32_e32 v5, v4, v5, vcc_lo
6455; GFX10-NEXT:    v_lshrrev_b64 v[3:4], v23, v[14:15]
6456; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v16, s4
6457; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v23
6458; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v25
6459; GFX10-NEXT:    v_cndmask_b32_e64 v9, v9, v18, s4
6460; GFX10-NEXT:    v_cndmask_b32_e32 v14, 0, v17, vcc_lo
6461; GFX10-NEXT:    v_or_b32_e32 v1, v24, v1
6462; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v6, s6
6463; GFX10-NEXT:    v_cndmask_b32_e64 v7, v5, v7, s6
6464; GFX10-NEXT:    v_cndmask_b32_e64 v5, v8, v12, s5
6465; GFX10-NEXT:    v_cndmask_b32_e64 v8, v9, v13, s5
6466; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, v3, s4
6467; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, v4, s4
6468; GFX10-NEXT:    v_or_b32_e32 v3, v22, v26
6469; GFX10-NEXT:    v_or_b32_e32 v4, v11, v5
6470; GFX10-NEXT:    v_or_b32_e32 v5, v14, v8
6471; GFX10-NEXT:    v_or_b32_e32 v6, v6, v9
6472; GFX10-NEXT:    v_or_b32_e32 v7, v7, v10
6473; GFX10-NEXT:    s_setpc_b64 s[30:31]
6474  %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
6475  ret <2 x i128> %result
6476}
6477
6478declare i7 @llvm.fshr.i7(i7, i7, i7) #0
6479declare i8 @llvm.fshr.i8(i8, i8, i8) #0
6480declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0
6481declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>) #0
6482
6483declare i16 @llvm.fshr.i16(i16, i16, i16) #0
6484declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>) #0
6485declare <3 x i16> @llvm.fshr.v3i16(<3 x i16>, <3 x i16>, <3 x i16>) #0
6486declare <4 x i16> @llvm.fshr.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) #0
6487declare <5 x i16> @llvm.fshr.v5i16(<5 x i16>, <5 x i16>, <5 x i16>) #0
6488declare <6 x i16> @llvm.fshr.v6i16(<6 x i16>, <6 x i16>, <6 x i16>) #0
6489declare <8 x i16> @llvm.fshr.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) #0
6490
6491declare i24 @llvm.fshr.i24(i24, i24, i24) #0
6492declare <2 x i24> @llvm.fshr.v2i24(<2 x i24>, <2 x i24>, <2 x i24>) #0
6493
6494declare i32 @llvm.fshr.i32(i32, i32, i32) #0
6495declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) #0
6496declare <3 x i32> @llvm.fshr.v3i32(<3 x i32>, <3 x i32>, <3 x i32>) #0
6497declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #0
6498declare <5 x i32> @llvm.fshr.v5i32(<5 x i32>, <5 x i32>, <5 x i32>) #0
6499declare <16 x i32> @llvm.fshr.v16i32(<16 x i32>, <16 x i32>, <16 x i32>) #0
6500
6501declare i48 @llvm.fshr.i48(i48, i48, i48) #0
6502
6503declare i64 @llvm.fshr.i64(i64, i64, i64) #0
6504declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) #0
6505
6506declare i128 @llvm.fshr.i128(i128, i128, i128) #0
6507declare <2 x i128> @llvm.fshr.v2i128(<2 x i128>, <2 x i128>, <2 x i128>) #0
6508
6509attributes #0 = { nounwind readnone speculatable willreturn }
6510