1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
6
7define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
8; GFX6-LABEL: s_fshl_i7:
9; GFX6:       ; %bb.0:
10; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
11; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
12; GFX6-NEXT:    s_sub_i32 s3, 0, 7
13; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
14; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
15; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
16; GFX6-NEXT:    s_movk_i32 s3, 0x7f
17; GFX6-NEXT:    s_and_b32 s2, s2, s3
18; GFX6-NEXT:    s_and_b32 s1, s1, s3
19; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
20; GFX6-NEXT:    s_lshr_b32 s1, s1, 1
21; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
22; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
23; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 7
24; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
25; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 7, v0
26; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
27; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
28; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 7, v0
29; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
30; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
31; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 6, v0
32; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
33; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
34; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0
35; GFX6-NEXT:    v_lshr_b32_e32 v1, s1, v1
36; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
37; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
38; GFX6-NEXT:    ; return to shader part epilog
39;
40; GFX8-LABEL: s_fshl_i7:
41; GFX8:       ; %bb.0:
42; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
43; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
44; GFX8-NEXT:    s_sub_i32 s3, 0, 7
45; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
46; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
47; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
48; GFX8-NEXT:    s_movk_i32 s3, 0x7f
49; GFX8-NEXT:    s_and_b32 s2, s2, s3
50; GFX8-NEXT:    s_and_b32 s1, s1, s3
51; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
52; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
53; GFX8-NEXT:    s_lshr_b32 s1, s1, 1
54; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
55; GFX8-NEXT:    v_mul_hi_u32 v0, s2, v0
56; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 7
57; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
58; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 7, v0
59; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
60; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
61; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 7, v0
62; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
63; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
64; GFX8-NEXT:    v_sub_u16_e32 v1, 6, v0
65; GFX8-NEXT:    v_and_b32_e32 v0, s3, v0
66; GFX8-NEXT:    v_and_b32_e32 v1, s3, v1
67; GFX8-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
68; GFX8-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
69; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
70; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
71; GFX8-NEXT:    ; return to shader part epilog
72;
73; GFX9-LABEL: s_fshl_i7:
74; GFX9:       ; %bb.0:
75; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
76; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
77; GFX9-NEXT:    s_sub_i32 s3, 0, 7
78; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
79; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
80; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
81; GFX9-NEXT:    s_movk_i32 s3, 0x7f
82; GFX9-NEXT:    s_and_b32 s2, s2, s3
83; GFX9-NEXT:    s_and_b32 s1, s1, s3
84; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
85; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
86; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
87; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
88; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
89; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 7
90; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
91; GFX9-NEXT:    v_subrev_u32_e32 v1, 7, v0
92; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
93; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
94; GFX9-NEXT:    v_subrev_u32_e32 v1, 7, v0
95; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v0
96; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
97; GFX9-NEXT:    v_sub_u16_e32 v1, 6, v0
98; GFX9-NEXT:    v_and_b32_e32 v0, s3, v0
99; GFX9-NEXT:    v_and_b32_e32 v1, s3, v1
100; GFX9-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
101; GFX9-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
102; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
103; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
104; GFX9-NEXT:    ; return to shader part epilog
105;
106; GFX10-LABEL: s_fshl_i7:
107; GFX10:       ; %bb.0:
108; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 7
109; GFX10-NEXT:    s_sub_i32 s3, 0, 7
110; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
111; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
112; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
113; GFX10-NEXT:    v_mul_lo_u32 v1, s3, v0
114; GFX10-NEXT:    s_movk_i32 s3, 0x7f
115; GFX10-NEXT:    s_and_b32 s2, s2, s3
116; GFX10-NEXT:    s_and_b32 s1, s1, s3
117; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
118; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
119; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
120; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
121; GFX10-NEXT:    v_mul_hi_u32 v0, s2, v0
122; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 7
123; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
124; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
125; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
126; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
127; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
128; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
129; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
130; GFX10-NEXT:    v_sub_nc_u16 v1, 6, v0
131; GFX10-NEXT:    v_and_b32_e32 v0, s3, v0
132; GFX10-NEXT:    v_and_b32_e32 v1, s3, v1
133; GFX10-NEXT:    v_lshlrev_b16 v0, v0, s0
134; GFX10-NEXT:    v_lshrrev_b16 v1, v1, s1
135; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
136; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
137; GFX10-NEXT:    ; return to shader part epilog
138  %result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
139  ret i7 %result
140}
141
142define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
143; GFX6-LABEL: v_fshl_i7:
144; GFX6:       ; %bb.0:
145; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
146; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
147; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
148; GFX6-NEXT:    s_sub_i32 s4, 0, 7
149; GFX6-NEXT:    v_and_b32_e32 v2, 0x7f, v2
150; GFX6-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
151; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
152; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
153; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
154; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
155; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
156; GFX6-NEXT:    v_mov_b32_e32 v4, 0x7f
157; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
158; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
159; GFX6-NEXT:    v_mul_lo_u32 v3, v3, 7
160; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
161; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 7, v2
162; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
163; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
164; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 7, v2
165; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
166; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
167; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 6, v2
168; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
169; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
170; GFX6-NEXT:    v_and_b32_e32 v2, v3, v4
171; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
172; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
173; GFX6-NEXT:    s_setpc_b64 s[30:31]
174;
175; GFX8-LABEL: v_fshl_i7:
176; GFX8:       ; %bb.0:
177; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
178; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
179; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
180; GFX8-NEXT:    s_sub_i32 s4, 0, 7
181; GFX8-NEXT:    v_and_b32_e32 v2, 0x7f, v2
182; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
183; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
184; GFX8-NEXT:    v_mul_lo_u32 v4, s4, v3
185; GFX8-NEXT:    v_mul_hi_u32 v4, v3, v4
186; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v4
187; GFX8-NEXT:    v_mul_hi_u32 v3, v2, v3
188; GFX8-NEXT:    v_mov_b32_e32 v4, 0x7f
189; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
190; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 1, v1
191; GFX8-NEXT:    v_mul_lo_u32 v3, v3, 7
192; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
193; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 7, v2
194; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
195; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
196; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 7, v2
197; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
198; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
199; GFX8-NEXT:    v_sub_u16_e32 v3, 6, v2
200; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
201; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
202; GFX8-NEXT:    v_and_b32_e32 v2, v3, v4
203; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
204; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
205; GFX8-NEXT:    s_setpc_b64 s[30:31]
206;
207; GFX9-LABEL: v_fshl_i7:
208; GFX9:       ; %bb.0:
209; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
210; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
211; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
212; GFX9-NEXT:    s_sub_i32 s4, 0, 7
213; GFX9-NEXT:    v_and_b32_e32 v2, 0x7f, v2
214; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
215; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
216; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v3
217; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
218; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
219; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
220; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7f
221; GFX9-NEXT:    v_and_b32_e32 v1, v1, v4
222; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 1, v1
223; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 7
224; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
225; GFX9-NEXT:    v_subrev_u32_e32 v3, 7, v2
226; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
227; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
228; GFX9-NEXT:    v_subrev_u32_e32 v3, 7, v2
229; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 7, v2
230; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
231; GFX9-NEXT:    v_sub_u16_e32 v3, 6, v2
232; GFX9-NEXT:    v_and_b32_e32 v2, v2, v4
233; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v2, v0
234; GFX9-NEXT:    v_and_b32_e32 v2, v3, v4
235; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
236; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
237; GFX9-NEXT:    s_setpc_b64 s[30:31]
238;
239; GFX10-LABEL: v_fshl_i7:
240; GFX10:       ; %bb.0:
241; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
242; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
243; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
244; GFX10-NEXT:    s_sub_i32 s4, 0, 7
245; GFX10-NEXT:    v_and_b32_e32 v2, 0x7f, v2
246; GFX10-NEXT:    v_and_b32_e32 v1, 0x7f, v1
247; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
248; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
249; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
250; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
251; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v3
252; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
253; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
254; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
255; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 7
256; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
257; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
258; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
259; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
260; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
261; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
262; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
263; GFX10-NEXT:    v_mov_b32_e32 v3, 0x7f
264; GFX10-NEXT:    v_sub_nc_u16 v4, 6, v2
265; GFX10-NEXT:    v_and_b32_e32 v2, v2, v3
266; GFX10-NEXT:    v_and_b32_e32 v3, v4, v3
267; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
268; GFX10-NEXT:    v_lshrrev_b16 v1, v3, v1
269; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
270; GFX10-NEXT:    s_setpc_b64 s[30:31]
271  %result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
272  ret i7 %result
273}
274
275define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
276; GFX6-LABEL: s_fshl_i8:
277; GFX6:       ; %bb.0:
278; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
279; GFX6-NEXT:    s_and_b32 s3, s2, 7
280; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
281; GFX6-NEXT:    s_lshr_b32 s1, s1, 1
282; GFX6-NEXT:    s_lshl_b32 s0, s0, s3
283; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
284; GFX6-NEXT:    s_or_b32 s0, s0, s1
285; GFX6-NEXT:    ; return to shader part epilog
286;
287; GFX8-LABEL: s_fshl_i8:
288; GFX8:       ; %bb.0:
289; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
290; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
291; GFX8-NEXT:    s_and_b32 s3, s2, 7
292; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
293; GFX8-NEXT:    s_lshr_b32 s1, s1, 1
294; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
295; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
296; GFX8-NEXT:    s_or_b32 s0, s0, s1
297; GFX8-NEXT:    ; return to shader part epilog
298;
299; GFX9-LABEL: s_fshl_i8:
300; GFX9:       ; %bb.0:
301; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
302; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
303; GFX9-NEXT:    s_and_b32 s3, s2, 7
304; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
305; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
306; GFX9-NEXT:    s_lshl_b32 s0, s0, s3
307; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
308; GFX9-NEXT:    s_or_b32 s0, s0, s1
309; GFX9-NEXT:    ; return to shader part epilog
310;
311; GFX10-LABEL: s_fshl_i8:
312; GFX10:       ; %bb.0:
313; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
314; GFX10-NEXT:    s_and_b32 s3, s2, 7
315; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
316; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
317; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
318; GFX10-NEXT:    s_lshl_b32 s0, s0, s3
319; GFX10-NEXT:    s_lshr_b32 s1, s1, s2
320; GFX10-NEXT:    s_or_b32 s0, s0, s1
321; GFX10-NEXT:    ; return to shader part epilog
322  %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 %amt)
323  ret i8 %result
324}
325
326define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
327; GFX6-LABEL: v_fshl_i8:
328; GFX6:       ; %bb.0:
329; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
330; GFX6-NEXT:    v_and_b32_e32 v3, 7, v2
331; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
332; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
333; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
334; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
335; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
336; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
337; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
338; GFX6-NEXT:    s_setpc_b64 s[30:31]
339;
340; GFX8-LABEL: v_fshl_i8:
341; GFX8:       ; %bb.0:
342; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
343; GFX8-NEXT:    v_and_b32_e32 v3, 7, v2
344; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
345; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
346; GFX8-NEXT:    v_mov_b32_e32 v3, 1
347; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
348; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
349; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
350; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
351; GFX8-NEXT:    s_setpc_b64 s[30:31]
352;
353; GFX9-LABEL: v_fshl_i8:
354; GFX9:       ; %bb.0:
355; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
356; GFX9-NEXT:    v_and_b32_e32 v3, 7, v2
357; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
358; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
359; GFX9-NEXT:    v_mov_b32_e32 v3, 1
360; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
361; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
362; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
363; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
364; GFX9-NEXT:    s_setpc_b64 s[30:31]
365;
366; GFX10-LABEL: v_fshl_i8:
367; GFX10:       ; %bb.0:
368; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
369; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
370; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
371; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
372; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
373; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
374; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
375; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
376; GFX10-NEXT:    v_lshrrev_b16 v1, v3, v1
377; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
378; GFX10-NEXT:    s_setpc_b64 s[30:31]
379  %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 %amt)
380  ret i8 %result
381}
382
383define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
384; GFX6-LABEL: s_fshl_i8_4:
385; GFX6:       ; %bb.0:
386; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
387; GFX6-NEXT:    s_lshl_b32 s0, s0, 4
388; GFX6-NEXT:    s_lshr_b32 s1, s1, 4
389; GFX6-NEXT:    s_or_b32 s0, s0, s1
390; GFX6-NEXT:    ; return to shader part epilog
391;
392; GFX8-LABEL: s_fshl_i8_4:
393; GFX8:       ; %bb.0:
394; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
395; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
396; GFX8-NEXT:    s_lshl_b32 s0, s0, 4
397; GFX8-NEXT:    s_lshr_b32 s1, s1, 4
398; GFX8-NEXT:    s_or_b32 s0, s0, s1
399; GFX8-NEXT:    ; return to shader part epilog
400;
401; GFX9-LABEL: s_fshl_i8_4:
402; GFX9:       ; %bb.0:
403; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
404; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
405; GFX9-NEXT:    s_lshl_b32 s0, s0, 4
406; GFX9-NEXT:    s_lshr_b32 s1, s1, 4
407; GFX9-NEXT:    s_or_b32 s0, s0, s1
408; GFX9-NEXT:    ; return to shader part epilog
409;
410; GFX10-LABEL: s_fshl_i8_4:
411; GFX10:       ; %bb.0:
412; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
413; GFX10-NEXT:    s_lshl_b32 s0, s0, 4
414; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
415; GFX10-NEXT:    s_lshr_b32 s1, s1, 4
416; GFX10-NEXT:    s_or_b32 s0, s0, s1
417; GFX10-NEXT:    ; return to shader part epilog
418  %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 4)
419  ret i8 %result
420}
421
422define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
423; GFX6-LABEL: v_fshl_i8_4:
424; GFX6:       ; %bb.0:
425; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
426; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
427; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
428; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 4, v1
429; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
430; GFX6-NEXT:    s_setpc_b64 s[30:31]
431;
432; GFX8-LABEL: v_fshl_i8_4:
433; GFX8:       ; %bb.0:
434; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
435; GFX8-NEXT:    v_mov_b32_e32 v2, 4
436; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
437; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
438; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
439; GFX8-NEXT:    s_setpc_b64 s[30:31]
440;
441; GFX9-LABEL: v_fshl_i8_4:
442; GFX9:       ; %bb.0:
443; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
444; GFX9-NEXT:    s_mov_b32 s4, 4
445; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
446; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
447; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
448; GFX9-NEXT:    s_setpc_b64 s[30:31]
449;
450; GFX10-LABEL: v_fshl_i8_4:
451; GFX10:       ; %bb.0:
452; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
453; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
454; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
455; GFX10-NEXT:    v_lshlrev_b16 v0, 4, v0
456; GFX10-NEXT:    v_lshrrev_b16 v1, 4, v1
457; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
458; GFX10-NEXT:    s_setpc_b64 s[30:31]
459  %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 4)
460  ret i8 %result
461}
462
463define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
464; GFX6-LABEL: s_fshl_i8_5:
465; GFX6:       ; %bb.0:
466; GFX6-NEXT:    s_and_b32 s1, s1, 0xff
467; GFX6-NEXT:    s_lshl_b32 s0, s0, 5
468; GFX6-NEXT:    s_lshr_b32 s1, s1, 3
469; GFX6-NEXT:    s_or_b32 s0, s0, s1
470; GFX6-NEXT:    ; return to shader part epilog
471;
472; GFX8-LABEL: s_fshl_i8_5:
473; GFX8:       ; %bb.0:
474; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
475; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
476; GFX8-NEXT:    s_lshl_b32 s0, s0, 5
477; GFX8-NEXT:    s_lshr_b32 s1, s1, 3
478; GFX8-NEXT:    s_or_b32 s0, s0, s1
479; GFX8-NEXT:    ; return to shader part epilog
480;
481; GFX9-LABEL: s_fshl_i8_5:
482; GFX9:       ; %bb.0:
483; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
484; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
485; GFX9-NEXT:    s_lshl_b32 s0, s0, 5
486; GFX9-NEXT:    s_lshr_b32 s1, s1, 3
487; GFX9-NEXT:    s_or_b32 s0, s0, s1
488; GFX9-NEXT:    ; return to shader part epilog
489;
490; GFX10-LABEL: s_fshl_i8_5:
491; GFX10:       ; %bb.0:
492; GFX10-NEXT:    s_and_b32 s1, s1, 0xff
493; GFX10-NEXT:    s_lshl_b32 s0, s0, 5
494; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
495; GFX10-NEXT:    s_lshr_b32 s1, s1, 3
496; GFX10-NEXT:    s_or_b32 s0, s0, s1
497; GFX10-NEXT:    ; return to shader part epilog
498  %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 5)
499  ret i8 %result
500}
501
502define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) {
503; GFX6-LABEL: v_fshl_i8_5:
504; GFX6:       ; %bb.0:
505; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
506; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
507; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 5, v0
508; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 3, v1
509; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
510; GFX6-NEXT:    s_setpc_b64 s[30:31]
511;
512; GFX8-LABEL: v_fshl_i8_5:
513; GFX8:       ; %bb.0:
514; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
515; GFX8-NEXT:    v_mov_b32_e32 v2, 3
516; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 5, v0
517; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
518; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
519; GFX8-NEXT:    s_setpc_b64 s[30:31]
520;
521; GFX9-LABEL: v_fshl_i8_5:
522; GFX9:       ; %bb.0:
523; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
524; GFX9-NEXT:    v_mov_b32_e32 v2, 3
525; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 5, v0
526; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
527; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
528; GFX9-NEXT:    s_setpc_b64 s[30:31]
529;
530; GFX10-LABEL: v_fshl_i8_5:
531; GFX10:       ; %bb.0:
532; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
533; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
534; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
535; GFX10-NEXT:    v_lshlrev_b16 v0, 5, v0
536; GFX10-NEXT:    v_lshrrev_b16 v1, 3, v1
537; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
538; GFX10-NEXT:    s_setpc_b64 s[30:31]
539  %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 5)
540  ret i8 %result
541}
542
543define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 inreg %amt.arg) {
544; GFX6-LABEL: s_fshl_v2i8:
545; GFX6:       ; %bb.0:
546; GFX6-NEXT:    s_and_b32 s5, s2, 7
547; GFX6-NEXT:    s_movk_i32 s6, 0xff
548; GFX6-NEXT:    s_lshr_b32 s3, s0, 8
549; GFX6-NEXT:    s_lshl_b32 s0, s0, s5
550; GFX6-NEXT:    s_and_b32 s5, s1, s6
551; GFX6-NEXT:    s_lshr_b32 s4, s2, 8
552; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
553; GFX6-NEXT:    s_lshr_b32 s5, s5, 1
554; GFX6-NEXT:    s_lshr_b32 s1, s1, 9
555; GFX6-NEXT:    s_lshr_b32 s2, s5, s2
556; GFX6-NEXT:    s_or_b32 s0, s0, s2
557; GFX6-NEXT:    s_and_b32 s2, s4, 7
558; GFX6-NEXT:    s_andn2_b32 s4, 7, s4
559; GFX6-NEXT:    s_and_b32 s1, s1, 0x7f
560; GFX6-NEXT:    s_lshl_b32 s2, s3, s2
561; GFX6-NEXT:    s_lshr_b32 s1, s1, s4
562; GFX6-NEXT:    s_or_b32 s1, s2, s1
563; GFX6-NEXT:    s_and_b32 s1, s1, s6
564; GFX6-NEXT:    s_and_b32 s0, s0, s6
565; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
566; GFX6-NEXT:    s_or_b32 s0, s0, s1
567; GFX6-NEXT:    ; return to shader part epilog
568;
569; GFX8-LABEL: s_fshl_v2i8:
570; GFX8:       ; %bb.0:
571; GFX8-NEXT:    s_and_b32 s6, s2, 7
572; GFX8-NEXT:    s_lshr_b32 s3, s0, 8
573; GFX8-NEXT:    s_lshl_b32 s0, s0, s6
574; GFX8-NEXT:    s_movk_i32 s6, 0xff
575; GFX8-NEXT:    s_lshr_b32 s4, s1, 8
576; GFX8-NEXT:    s_and_b32 s1, s1, s6
577; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
578; GFX8-NEXT:    s_lshr_b32 s5, s2, 8
579; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
580; GFX8-NEXT:    s_lshr_b32 s1, s1, 1
581; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
582; GFX8-NEXT:    s_or_b32 s0, s0, s1
583; GFX8-NEXT:    s_and_b32 s1, s5, 7
584; GFX8-NEXT:    s_lshl_b32 s1, s3, s1
585; GFX8-NEXT:    s_and_b32 s3, s4, s6
586; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
587; GFX8-NEXT:    s_andn2_b32 s2, 7, s5
588; GFX8-NEXT:    s_lshr_b32 s3, s3, 1
589; GFX8-NEXT:    s_lshr_b32 s2, s3, s2
590; GFX8-NEXT:    s_or_b32 s1, s1, s2
591; GFX8-NEXT:    s_and_b32 s1, s1, s6
592; GFX8-NEXT:    s_bfe_u32 s2, 8, 0x100000
593; GFX8-NEXT:    s_and_b32 s0, s0, s6
594; GFX8-NEXT:    s_lshl_b32 s1, s1, s2
595; GFX8-NEXT:    s_or_b32 s0, s0, s1
596; GFX8-NEXT:    ; return to shader part epilog
597;
598; GFX9-LABEL: s_fshl_v2i8:
599; GFX9:       ; %bb.0:
600; GFX9-NEXT:    s_and_b32 s6, s2, 7
601; GFX9-NEXT:    s_lshr_b32 s3, s0, 8
602; GFX9-NEXT:    s_lshl_b32 s0, s0, s6
603; GFX9-NEXT:    s_movk_i32 s6, 0xff
604; GFX9-NEXT:    s_lshr_b32 s4, s1, 8
605; GFX9-NEXT:    s_and_b32 s1, s1, s6
606; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
607; GFX9-NEXT:    s_lshr_b32 s5, s2, 8
608; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
609; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
610; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
611; GFX9-NEXT:    s_or_b32 s0, s0, s1
612; GFX9-NEXT:    s_and_b32 s1, s5, 7
613; GFX9-NEXT:    s_lshl_b32 s1, s3, s1
614; GFX9-NEXT:    s_and_b32 s3, s4, s6
615; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
616; GFX9-NEXT:    s_andn2_b32 s2, 7, s5
617; GFX9-NEXT:    s_lshr_b32 s3, s3, 1
618; GFX9-NEXT:    s_lshr_b32 s2, s3, s2
619; GFX9-NEXT:    s_or_b32 s1, s1, s2
620; GFX9-NEXT:    s_and_b32 s1, s1, s6
621; GFX9-NEXT:    s_bfe_u32 s2, 8, 0x100000
622; GFX9-NEXT:    s_and_b32 s0, s0, s6
623; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
624; GFX9-NEXT:    s_or_b32 s0, s0, s1
625; GFX9-NEXT:    ; return to shader part epilog
626;
627; GFX10-LABEL: s_fshl_v2i8:
628; GFX10:       ; %bb.0:
629; GFX10-NEXT:    s_lshr_b32 s4, s1, 8
630; GFX10-NEXT:    s_movk_i32 s6, 0xff
631; GFX10-NEXT:    s_lshr_b32 s5, s2, 8
632; GFX10-NEXT:    s_and_b32 s4, s4, s6
633; GFX10-NEXT:    s_and_b32 s1, s1, s6
634; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
635; GFX10-NEXT:    s_and_b32 s7, s2, 7
636; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
637; GFX10-NEXT:    s_lshr_b32 s3, s0, 8
638; GFX10-NEXT:    s_lshl_b32 s0, s0, s7
639; GFX10-NEXT:    s_and_b32 s7, s5, 7
640; GFX10-NEXT:    s_andn2_b32 s5, 7, s5
641; GFX10-NEXT:    s_lshr_b32 s4, s4, 1
642; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
643; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
644; GFX10-NEXT:    s_lshl_b32 s3, s3, s7
645; GFX10-NEXT:    s_lshr_b32 s4, s4, s5
646; GFX10-NEXT:    s_lshr_b32 s1, s1, s2
647; GFX10-NEXT:    s_or_b32 s2, s3, s4
648; GFX10-NEXT:    s_or_b32 s0, s0, s1
649; GFX10-NEXT:    s_and_b32 s1, s2, s6
650; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
651; GFX10-NEXT:    s_and_b32 s0, s0, s6
652; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
653; GFX10-NEXT:    s_or_b32 s0, s0, s1
654; GFX10-NEXT:    ; return to shader part epilog
655  %lhs = bitcast i16 %lhs.arg to <2 x i8>
656  %rhs = bitcast i16 %rhs.arg to <2 x i8>
657  %amt = bitcast i16 %amt.arg to <2 x i8>
658  %result = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %lhs, <2 x i8> %rhs, <2 x i8> %amt)
659  %cast.result = bitcast <2 x i8> %result to i16
660  ret i16 %cast.result
661}
662
663define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
664; GFX6-LABEL: v_fshl_v2i8:
665; GFX6:       ; %bb.0:
666; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
667; GFX6-NEXT:    v_and_b32_e32 v6, 0xff, v1
668; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 8, v2
669; GFX6-NEXT:    v_and_b32_e32 v5, 7, v2
670; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
671; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
672; GFX6-NEXT:    v_lshrrev_b32_e32 v6, 1, v6
673; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
674; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v5, v0
675; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v6
676; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 9, v1
677; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
678; GFX6-NEXT:    v_and_b32_e32 v2, 7, v4
679; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
680; GFX6-NEXT:    v_and_b32_e32 v4, 7, v4
681; GFX6-NEXT:    v_and_b32_e32 v1, 0x7f, v1
682; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v2, v3
683; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v4, v1
684; GFX6-NEXT:    v_mov_b32_e32 v5, 0xff
685; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
686; GFX6-NEXT:    v_and_b32_e32 v1, v1, v5
687; GFX6-NEXT:    v_and_b32_e32 v0, v0, v5
688; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
689; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
690; GFX6-NEXT:    s_setpc_b64 s[30:31]
691;
692; GFX8-LABEL: v_fshl_v2i8:
693; GFX8:       ; %bb.0:
694; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
695; GFX8-NEXT:    v_and_b32_e32 v6, 7, v2
696; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
697; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
698; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
699; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v6, v0
700; GFX8-NEXT:    v_mov_b32_e32 v6, 1
701; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
702; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
703; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
704; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
705; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v5
706; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
707; GFX8-NEXT:    v_and_b32_e32 v1, 7, v5
708; GFX8-NEXT:    v_lshlrev_b16_e32 v1, v1, v3
709; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
710; GFX8-NEXT:    v_lshrrev_b16_sdwa v3, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
711; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v2, v3
712; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
713; GFX8-NEXT:    v_and_b32_e32 v1, 0xff, v1
714; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
715; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
716; GFX8-NEXT:    s_setpc_b64 s[30:31]
717;
718; GFX9-LABEL: v_fshl_v2i8:
719; GFX9:       ; %bb.0:
720; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
721; GFX9-NEXT:    v_and_b32_e32 v6, 7, v2
722; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
723; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
724; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
725; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v6, v0
726; GFX9-NEXT:    v_mov_b32_e32 v6, 1
727; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
728; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
729; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
730; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
731; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v5
732; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
733; GFX9-NEXT:    v_and_b32_e32 v1, 7, v5
734; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v1, v3
735; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
736; GFX9-NEXT:    v_lshrrev_b16_sdwa v3, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
737; GFX9-NEXT:    v_lshrrev_b16_e32 v2, v2, v3
738; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
739; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v1
740; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
741; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
742; GFX9-NEXT:    s_setpc_b64 s[30:31]
743;
744; GFX10-LABEL: v_fshl_v2i8:
745; GFX10:       ; %bb.0:
746; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
747; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
748; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v2
749; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
750; GFX10-NEXT:    s_movk_i32 s4, 0xff
751; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v2
752; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
753; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v3
754; GFX10-NEXT:    v_and_b32_e32 v4, s4, v4
755; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
756; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
757; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
758; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
759; GFX10-NEXT:    v_lshrrev_b16 v4, 1, v4
760; GFX10-NEXT:    v_and_b32_e32 v7, 7, v7
761; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
762; GFX10-NEXT:    v_lshlrev_b16 v3, v3, v5
763; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
764; GFX10-NEXT:    v_lshrrev_b16 v4, v6, v4
765; GFX10-NEXT:    v_lshrrev_b16 v1, v7, v1
766; GFX10-NEXT:    v_or_b32_e32 v2, v3, v4
767; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
768; GFX10-NEXT:    v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
769; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
770; GFX10-NEXT:    s_setpc_b64 s[30:31]
771  %lhs = bitcast i16 %lhs.arg to <2 x i8>
772  %rhs = bitcast i16 %rhs.arg to <2 x i8>
773  %amt = bitcast i16 %amt.arg to <2 x i8>
774  %result = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %lhs, <2 x i8> %rhs, <2 x i8> %amt)
775  %cast.result = bitcast <2 x i8> %result to i16
776  ret i16 %cast.result
777}
778
779define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 inreg %amt.arg) {
780; GFX6-LABEL: s_fshl_v4i8:
781; GFX6:       ; %bb.0:
782; GFX6-NEXT:    s_and_b32 s9, s2, 7
783; GFX6-NEXT:    s_movk_i32 s10, 0xff
784; GFX6-NEXT:    s_lshr_b32 s3, s0, 8
785; GFX6-NEXT:    s_lshr_b32 s4, s0, 16
786; GFX6-NEXT:    s_lshr_b32 s5, s0, 24
787; GFX6-NEXT:    s_lshl_b32 s0, s0, s9
788; GFX6-NEXT:    s_and_b32 s9, s1, s10
789; GFX6-NEXT:    s_lshr_b32 s6, s2, 8
790; GFX6-NEXT:    s_lshr_b32 s7, s2, 16
791; GFX6-NEXT:    s_lshr_b32 s8, s2, 24
792; GFX6-NEXT:    s_andn2_b32 s2, 7, s2
793; GFX6-NEXT:    s_lshr_b32 s9, s9, 1
794; GFX6-NEXT:    s_lshr_b32 s2, s9, s2
795; GFX6-NEXT:    s_or_b32 s0, s0, s2
796; GFX6-NEXT:    s_and_b32 s2, s6, 7
797; GFX6-NEXT:    s_lshl_b32 s2, s3, s2
798; GFX6-NEXT:    s_lshr_b32 s3, s1, 9
799; GFX6-NEXT:    s_movk_i32 s9, 0x7f
800; GFX6-NEXT:    s_andn2_b32 s6, 7, s6
801; GFX6-NEXT:    s_and_b32 s3, s3, s9
802; GFX6-NEXT:    s_lshr_b32 s3, s3, s6
803; GFX6-NEXT:    s_or_b32 s2, s2, s3
804; GFX6-NEXT:    s_and_b32 s3, s7, 7
805; GFX6-NEXT:    s_lshl_b32 s3, s4, s3
806; GFX6-NEXT:    s_lshr_b32 s4, s1, 17
807; GFX6-NEXT:    s_andn2_b32 s6, 7, s7
808; GFX6-NEXT:    s_and_b32 s4, s4, s9
809; GFX6-NEXT:    s_lshr_b32 s4, s4, s6
810; GFX6-NEXT:    s_and_b32 s2, s2, s10
811; GFX6-NEXT:    s_or_b32 s3, s3, s4
812; GFX6-NEXT:    s_and_b32 s4, s8, 7
813; GFX6-NEXT:    s_andn2_b32 s6, 7, s8
814; GFX6-NEXT:    s_lshr_b32 s1, s1, 25
815; GFX6-NEXT:    s_lshl_b32 s4, s5, s4
816; GFX6-NEXT:    s_lshr_b32 s1, s1, s6
817; GFX6-NEXT:    s_and_b32 s0, s0, s10
818; GFX6-NEXT:    s_lshl_b32 s2, s2, 8
819; GFX6-NEXT:    s_or_b32 s1, s4, s1
820; GFX6-NEXT:    s_or_b32 s0, s0, s2
821; GFX6-NEXT:    s_and_b32 s2, s3, s10
822; GFX6-NEXT:    s_and_b32 s1, s1, s10
823; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
824; GFX6-NEXT:    s_or_b32 s0, s0, s2
825; GFX6-NEXT:    s_lshl_b32 s1, s1, 24
826; GFX6-NEXT:    s_or_b32 s0, s0, s1
827; GFX6-NEXT:    ; return to shader part epilog
828;
829; GFX8-LABEL: s_fshl_v4i8:
830; GFX8:       ; %bb.0:
831; GFX8-NEXT:    s_movk_i32 s13, 0xff
832; GFX8-NEXT:    s_lshr_b32 s6, s1, 8
833; GFX8-NEXT:    s_lshr_b32 s7, s1, 16
834; GFX8-NEXT:    s_lshr_b32 s8, s1, 24
835; GFX8-NEXT:    s_and_b32 s1, s1, s13
836; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
837; GFX8-NEXT:    s_lshr_b32 s9, s2, 8
838; GFX8-NEXT:    s_lshr_b32 s10, s2, 16
839; GFX8-NEXT:    s_lshr_b32 s11, s2, 24
840; GFX8-NEXT:    s_and_b32 s12, s2, 7
841; GFX8-NEXT:    s_andn2_b32 s2, 7, s2
842; GFX8-NEXT:    s_lshr_b32 s1, s1, 1
843; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
844; GFX8-NEXT:    s_lshr_b32 s3, s0, 8
845; GFX8-NEXT:    s_lshr_b32 s4, s0, 16
846; GFX8-NEXT:    s_lshr_b32 s5, s0, 24
847; GFX8-NEXT:    s_lshl_b32 s0, s0, s12
848; GFX8-NEXT:    s_or_b32 s0, s0, s1
849; GFX8-NEXT:    s_and_b32 s1, s9, 7
850; GFX8-NEXT:    s_lshl_b32 s1, s3, s1
851; GFX8-NEXT:    s_and_b32 s3, s6, s13
852; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
853; GFX8-NEXT:    s_andn2_b32 s2, 7, s9
854; GFX8-NEXT:    s_lshr_b32 s3, s3, 1
855; GFX8-NEXT:    s_lshr_b32 s2, s3, s2
856; GFX8-NEXT:    s_or_b32 s1, s1, s2
857; GFX8-NEXT:    s_and_b32 s2, s10, 7
858; GFX8-NEXT:    s_lshl_b32 s2, s4, s2
859; GFX8-NEXT:    s_and_b32 s4, s7, s13
860; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
861; GFX8-NEXT:    s_andn2_b32 s3, 7, s10
862; GFX8-NEXT:    s_lshr_b32 s4, s4, 1
863; GFX8-NEXT:    s_lshr_b32 s3, s4, s3
864; GFX8-NEXT:    s_and_b32 s1, s1, s13
865; GFX8-NEXT:    s_or_b32 s2, s2, s3
866; GFX8-NEXT:    s_and_b32 s3, s11, 7
867; GFX8-NEXT:    s_lshl_b32 s3, s5, s3
868; GFX8-NEXT:    s_andn2_b32 s4, 7, s11
869; GFX8-NEXT:    s_lshr_b32 s5, s8, 1
870; GFX8-NEXT:    s_and_b32 s0, s0, s13
871; GFX8-NEXT:    s_lshl_b32 s1, s1, 8
872; GFX8-NEXT:    s_lshr_b32 s4, s5, s4
873; GFX8-NEXT:    s_or_b32 s0, s0, s1
874; GFX8-NEXT:    s_and_b32 s1, s2, s13
875; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
876; GFX8-NEXT:    s_or_b32 s3, s3, s4
877; GFX8-NEXT:    s_or_b32 s0, s0, s1
878; GFX8-NEXT:    s_and_b32 s1, s3, s13
879; GFX8-NEXT:    s_lshl_b32 s1, s1, 24
880; GFX8-NEXT:    s_or_b32 s0, s0, s1
881; GFX8-NEXT:    ; return to shader part epilog
882;
883; GFX9-LABEL: s_fshl_v4i8:
884; GFX9:       ; %bb.0:
885; GFX9-NEXT:    s_movk_i32 s13, 0xff
886; GFX9-NEXT:    s_lshr_b32 s6, s1, 8
887; GFX9-NEXT:    s_lshr_b32 s7, s1, 16
888; GFX9-NEXT:    s_lshr_b32 s8, s1, 24
889; GFX9-NEXT:    s_and_b32 s1, s1, s13
890; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
891; GFX9-NEXT:    s_lshr_b32 s9, s2, 8
892; GFX9-NEXT:    s_lshr_b32 s10, s2, 16
893; GFX9-NEXT:    s_lshr_b32 s11, s2, 24
894; GFX9-NEXT:    s_and_b32 s12, s2, 7
895; GFX9-NEXT:    s_andn2_b32 s2, 7, s2
896; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
897; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
898; GFX9-NEXT:    s_lshr_b32 s3, s0, 8
899; GFX9-NEXT:    s_lshr_b32 s4, s0, 16
900; GFX9-NEXT:    s_lshr_b32 s5, s0, 24
901; GFX9-NEXT:    s_lshl_b32 s0, s0, s12
902; GFX9-NEXT:    s_or_b32 s0, s0, s1
903; GFX9-NEXT:    s_and_b32 s1, s9, 7
904; GFX9-NEXT:    s_lshl_b32 s1, s3, s1
905; GFX9-NEXT:    s_and_b32 s3, s6, s13
906; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
907; GFX9-NEXT:    s_andn2_b32 s2, 7, s9
908; GFX9-NEXT:    s_lshr_b32 s3, s3, 1
909; GFX9-NEXT:    s_lshr_b32 s2, s3, s2
910; GFX9-NEXT:    s_or_b32 s1, s1, s2
911; GFX9-NEXT:    s_and_b32 s2, s10, 7
912; GFX9-NEXT:    s_lshl_b32 s2, s4, s2
913; GFX9-NEXT:    s_and_b32 s4, s7, s13
914; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
915; GFX9-NEXT:    s_andn2_b32 s3, 7, s10
916; GFX9-NEXT:    s_lshr_b32 s4, s4, 1
917; GFX9-NEXT:    s_lshr_b32 s3, s4, s3
918; GFX9-NEXT:    s_and_b32 s1, s1, s13
919; GFX9-NEXT:    s_or_b32 s2, s2, s3
920; GFX9-NEXT:    s_and_b32 s3, s11, 7
921; GFX9-NEXT:    s_lshl_b32 s3, s5, s3
922; GFX9-NEXT:    s_andn2_b32 s4, 7, s11
923; GFX9-NEXT:    s_lshr_b32 s5, s8, 1
924; GFX9-NEXT:    s_and_b32 s0, s0, s13
925; GFX9-NEXT:    s_lshl_b32 s1, s1, 8
926; GFX9-NEXT:    s_lshr_b32 s4, s5, s4
927; GFX9-NEXT:    s_or_b32 s0, s0, s1
928; GFX9-NEXT:    s_and_b32 s1, s2, s13
929; GFX9-NEXT:    s_lshl_b32 s1, s1, 16
930; GFX9-NEXT:    s_or_b32 s3, s3, s4
931; GFX9-NEXT:    s_or_b32 s0, s0, s1
932; GFX9-NEXT:    s_and_b32 s1, s3, s13
933; GFX9-NEXT:    s_lshl_b32 s1, s1, 24
934; GFX9-NEXT:    s_or_b32 s0, s0, s1
935; GFX9-NEXT:    ; return to shader part epilog
936;
937; GFX10-LABEL: s_fshl_v4i8:
938; GFX10:       ; %bb.0:
939; GFX10-NEXT:    s_movk_i32 s11, 0xff
940; GFX10-NEXT:    s_lshr_b32 s6, s1, 8
941; GFX10-NEXT:    s_lshr_b32 s7, s1, 16
942; GFX10-NEXT:    s_lshr_b32 s8, s1, 24
943; GFX10-NEXT:    s_and_b32 s1, s1, s11
944; GFX10-NEXT:    s_lshr_b32 s9, s2, 8
945; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
946; GFX10-NEXT:    s_lshr_b32 s10, s2, 16
947; GFX10-NEXT:    s_lshr_b32 s12, s2, 24
948; GFX10-NEXT:    s_and_b32 s13, s2, 7
949; GFX10-NEXT:    s_andn2_b32 s2, 7, s2
950; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
951; GFX10-NEXT:    s_lshr_b32 s3, s0, 8
952; GFX10-NEXT:    s_lshr_b32 s1, s1, s2
953; GFX10-NEXT:    s_and_b32 s2, s6, s11
954; GFX10-NEXT:    s_and_b32 s6, s9, 7
955; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
956; GFX10-NEXT:    s_andn2_b32 s9, 7, s9
957; GFX10-NEXT:    s_lshr_b32 s2, s2, 1
958; GFX10-NEXT:    s_lshl_b32 s3, s3, s6
959; GFX10-NEXT:    s_lshr_b32 s4, s0, 16
960; GFX10-NEXT:    s_lshr_b32 s5, s0, 24
961; GFX10-NEXT:    s_lshl_b32 s0, s0, s13
962; GFX10-NEXT:    s_lshr_b32 s2, s2, s9
963; GFX10-NEXT:    s_or_b32 s0, s0, s1
964; GFX10-NEXT:    s_or_b32 s1, s3, s2
965; GFX10-NEXT:    s_and_b32 s2, s7, s11
966; GFX10-NEXT:    s_and_b32 s3, s10, 7
967; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
968; GFX10-NEXT:    s_andn2_b32 s6, 7, s10
969; GFX10-NEXT:    s_lshr_b32 s2, s2, 1
970; GFX10-NEXT:    s_lshl_b32 s3, s4, s3
971; GFX10-NEXT:    s_lshr_b32 s2, s2, s6
972; GFX10-NEXT:    s_and_b32 s4, s12, 7
973; GFX10-NEXT:    s_andn2_b32 s6, 7, s12
974; GFX10-NEXT:    s_lshr_b32 s7, s8, 1
975; GFX10-NEXT:    s_or_b32 s2, s3, s2
976; GFX10-NEXT:    s_and_b32 s1, s1, s11
977; GFX10-NEXT:    s_lshl_b32 s4, s5, s4
978; GFX10-NEXT:    s_lshr_b32 s5, s7, s6
979; GFX10-NEXT:    s_and_b32 s0, s0, s11
980; GFX10-NEXT:    s_lshl_b32 s1, s1, 8
981; GFX10-NEXT:    s_or_b32 s3, s4, s5
982; GFX10-NEXT:    s_and_b32 s2, s2, s11
983; GFX10-NEXT:    s_or_b32 s0, s0, s1
984; GFX10-NEXT:    s_lshl_b32 s1, s2, 16
985; GFX10-NEXT:    s_and_b32 s2, s3, s11
986; GFX10-NEXT:    s_or_b32 s0, s0, s1
987; GFX10-NEXT:    s_lshl_b32 s1, s2, 24
988; GFX10-NEXT:    s_or_b32 s0, s0, s1
989; GFX10-NEXT:    ; return to shader part epilog
990  %lhs = bitcast i32 %lhs.arg to <4 x i8>
991  %rhs = bitcast i32 %rhs.arg to <4 x i8>
992  %amt = bitcast i32 %amt.arg to <4 x i8>
993  %result = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %lhs, <4 x i8> %rhs, <4 x i8> %amt)
994  %cast.result = bitcast <4 x i8> %result to i32
995  ret i32 %cast.result
996}
997
998define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
999; GFX6-LABEL: v_fshl_v4i8:
1000; GFX6:       ; %bb.0:
1001; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1002; GFX6-NEXT:    v_and_b32_e32 v10, 0xff, v1
1003; GFX6-NEXT:    v_lshrrev_b32_e32 v6, 8, v2
1004; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
1005; GFX6-NEXT:    v_lshrrev_b32_e32 v8, 24, v2
1006; GFX6-NEXT:    v_and_b32_e32 v9, 7, v2
1007; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
1008; GFX6-NEXT:    v_and_b32_e32 v2, 7, v2
1009; GFX6-NEXT:    v_lshrrev_b32_e32 v10, 1, v10
1010; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1011; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
1012; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
1013; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
1014; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v10
1015; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1016; GFX6-NEXT:    v_and_b32_e32 v2, 7, v6
1017; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v6
1018; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v2, v3
1019; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 9, v1
1020; GFX6-NEXT:    s_movk_i32 s4, 0x7f
1021; GFX6-NEXT:    v_and_b32_e32 v6, 7, v6
1022; GFX6-NEXT:    v_and_b32_e32 v3, s4, v3
1023; GFX6-NEXT:    v_lshrrev_b32_e32 v3, v6, v3
1024; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
1025; GFX6-NEXT:    v_and_b32_e32 v3, 7, v7
1026; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v7
1027; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v3, v4
1028; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 17, v1
1029; GFX6-NEXT:    v_and_b32_e32 v6, 7, v6
1030; GFX6-NEXT:    v_and_b32_e32 v4, s4, v4
1031; GFX6-NEXT:    v_mov_b32_e32 v9, 0xff
1032; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v6, v4
1033; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v8
1034; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
1035; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
1036; GFX6-NEXT:    v_and_b32_e32 v4, 7, v8
1037; GFX6-NEXT:    v_and_b32_e32 v6, 7, v6
1038; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 25, v1
1039; GFX6-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
1040; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v6, v1
1041; GFX6-NEXT:    v_and_b32_e32 v0, v0, v9
1042; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1043; GFX6-NEXT:    v_or_b32_e32 v1, v4, v1
1044; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1045; GFX6-NEXT:    v_and_b32_e32 v2, v3, v9
1046; GFX6-NEXT:    v_and_b32_e32 v1, v1, v9
1047; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1048; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1049; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
1050; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1051; GFX6-NEXT:    s_setpc_b64 s[30:31]
1052;
1053; GFX8-LABEL: v_fshl_v4i8:
1054; GFX8:       ; %bb.0:
1055; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1056; GFX8-NEXT:    v_and_b32_e32 v8, 7, v2
1057; GFX8-NEXT:    v_mov_b32_e32 v10, 1
1058; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1059; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1060; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 24, v2
1061; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
1062; GFX8-NEXT:    v_and_b32_e32 v2, 7, v2
1063; GFX8-NEXT:    v_lshrrev_b16_sdwa v11, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1064; GFX8-NEXT:    v_lshlrev_b16_e32 v8, v8, v0
1065; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v2, v11
1066; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1067; GFX8-NEXT:    v_or_b32_e32 v2, v8, v2
1068; GFX8-NEXT:    v_and_b32_e32 v8, 7, v5
1069; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
1070; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1071; GFX8-NEXT:    v_and_b32_e32 v5, 7, v5
1072; GFX8-NEXT:    v_lshrrev_b16_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1073; GFX8-NEXT:    v_lshrrev_b16_e32 v4, v5, v4
1074; GFX8-NEXT:    v_lshlrev_b16_e32 v3, v8, v3
1075; GFX8-NEXT:    v_mov_b32_e32 v9, 0xff
1076; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v6
1077; GFX8-NEXT:    v_or_b32_e32 v3, v3, v4
1078; GFX8-NEXT:    v_and_b32_e32 v4, 7, v6
1079; GFX8-NEXT:    v_and_b32_sdwa v6, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1080; GFX8-NEXT:    v_and_b32_e32 v5, 7, v5
1081; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 1, v6
1082; GFX8-NEXT:    v_lshrrev_b16_e32 v5, v5, v6
1083; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
1084; GFX8-NEXT:    v_xor_b32_e32 v6, -1, v7
1085; GFX8-NEXT:    v_or_b32_e32 v4, v4, v5
1086; GFX8-NEXT:    v_and_b32_e32 v5, 7, v7
1087; GFX8-NEXT:    v_and_b32_e32 v6, 7, v6
1088; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1089; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1090; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v6, v1
1091; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1092; GFX8-NEXT:    v_mov_b32_e32 v1, 8
1093; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1094; GFX8-NEXT:    s_movk_i32 s4, 0xff
1095; GFX8-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1096; GFX8-NEXT:    v_and_b32_e32 v2, s4, v4
1097; GFX8-NEXT:    v_and_b32_e32 v0, s4, v0
1098; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1099; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
1100; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
1101; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
1102; GFX8-NEXT:    s_setpc_b64 s[30:31]
1103;
1104; GFX9-LABEL: v_fshl_v4i8:
1105; GFX9:       ; %bb.0:
1106; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1107; GFX9-NEXT:    v_and_b32_e32 v8, 7, v2
1108; GFX9-NEXT:    v_mov_b32_e32 v10, 1
1109; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 8, v2
1110; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1111; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 24, v2
1112; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
1113; GFX9-NEXT:    v_and_b32_e32 v2, 7, v2
1114; GFX9-NEXT:    v_lshrrev_b16_sdwa v11, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1115; GFX9-NEXT:    v_lshlrev_b16_e32 v8, v8, v0
1116; GFX9-NEXT:    v_lshrrev_b16_e32 v2, v2, v11
1117; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1118; GFX9-NEXT:    v_or_b32_e32 v2, v8, v2
1119; GFX9-NEXT:    v_and_b32_e32 v8, 7, v5
1120; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v5
1121; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1122; GFX9-NEXT:    v_and_b32_e32 v5, 7, v5
1123; GFX9-NEXT:    v_lshrrev_b16_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1124; GFX9-NEXT:    v_lshrrev_b16_e32 v4, v5, v4
1125; GFX9-NEXT:    v_lshlrev_b16_e32 v3, v8, v3
1126; GFX9-NEXT:    v_mov_b32_e32 v9, 0xff
1127; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v6
1128; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
1129; GFX9-NEXT:    v_and_b32_e32 v4, 7, v6
1130; GFX9-NEXT:    v_and_b32_sdwa v6, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1131; GFX9-NEXT:    v_and_b32_e32 v5, 7, v5
1132; GFX9-NEXT:    v_lshrrev_b16_e32 v6, 1, v6
1133; GFX9-NEXT:    v_lshrrev_b16_e32 v5, v5, v6
1134; GFX9-NEXT:    v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
1135; GFX9-NEXT:    v_xor_b32_e32 v6, -1, v7
1136; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
1137; GFX9-NEXT:    v_and_b32_e32 v5, 7, v7
1138; GFX9-NEXT:    v_and_b32_e32 v6, 7, v6
1139; GFX9-NEXT:    v_lshrrev_b16_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1140; GFX9-NEXT:    v_lshlrev_b16_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
1141; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v6, v1
1142; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
1143; GFX9-NEXT:    v_mov_b32_e32 v1, 8
1144; GFX9-NEXT:    s_movk_i32 s4, 0xff
1145; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1146; GFX9-NEXT:    v_and_b32_e32 v0, s4, v0
1147; GFX9-NEXT:    v_and_or_b32 v1, v2, s4, v1
1148; GFX9-NEXT:    v_and_b32_e32 v2, s4, v4
1149; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1150; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
1151; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0
1152; GFX9-NEXT:    s_setpc_b64 s[30:31]
1153;
1154; GFX10-LABEL: v_fshl_v4i8:
1155; GFX10:       ; %bb.0:
1156; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1157; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1158; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 8, v2
1159; GFX10-NEXT:    v_and_b32_e32 v11, 7, v2
1160; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v2
1161; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 16, v2
1162; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1163; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
1164; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
1165; GFX10-NEXT:    v_lshlrev_b16 v0, v11, v0
1166; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v8
1167; GFX10-NEXT:    v_and_b32_e32 v8, 7, v8
1168; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
1169; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 24, v2
1170; GFX10-NEXT:    v_mov_b32_e32 v13, 0xff
1171; GFX10-NEXT:    s_movk_i32 s4, 0xff
1172; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
1173; GFX10-NEXT:    v_and_b32_e32 v12, s4, v1
1174; GFX10-NEXT:    v_and_b32_e32 v6, s4, v6
1175; GFX10-NEXT:    v_and_b32_sdwa v1, v1, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1176; GFX10-NEXT:    v_xor_b32_e32 v13, -1, v2
1177; GFX10-NEXT:    v_lshlrev_b16 v3, v8, v3
1178; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v9
1179; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
1180; GFX10-NEXT:    v_and_b32_e32 v9, 7, v9
1181; GFX10-NEXT:    v_and_b32_e32 v11, 7, v11
1182; GFX10-NEXT:    v_lshrrev_b16 v6, 1, v6
1183; GFX10-NEXT:    v_and_b32_e32 v8, 7, v8
1184; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
1185; GFX10-NEXT:    v_and_b32_e32 v13, 7, v13
1186; GFX10-NEXT:    v_lshrrev_b16 v7, 1, v7
1187; GFX10-NEXT:    v_lshrrev_b16 v6, v11, v6
1188; GFX10-NEXT:    v_lshlrev_b16 v2, v2, v5
1189; GFX10-NEXT:    v_and_b32_e32 v10, 7, v10
1190; GFX10-NEXT:    v_lshrrev_b16 v12, 1, v12
1191; GFX10-NEXT:    v_lshrrev_b16 v5, v13, v7
1192; GFX10-NEXT:    v_lshlrev_b16 v4, v9, v4
1193; GFX10-NEXT:    v_lshrrev_b16 v1, v8, v1
1194; GFX10-NEXT:    v_or_b32_e32 v3, v3, v6
1195; GFX10-NEXT:    v_lshrrev_b16 v7, v10, v12
1196; GFX10-NEXT:    v_or_b32_e32 v2, v2, v5
1197; GFX10-NEXT:    v_mov_b32_e32 v6, 8
1198; GFX10-NEXT:    v_or_b32_e32 v1, v4, v1
1199; GFX10-NEXT:    v_or_b32_e32 v0, v0, v7
1200; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
1201; GFX10-NEXT:    v_lshlrev_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1202; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
1203; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
1204; GFX10-NEXT:    v_and_or_b32 v0, v0, s4, v3
1205; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1206; GFX10-NEXT:    v_or3_b32 v0, v0, v1, v2
1207; GFX10-NEXT:    s_setpc_b64 s[30:31]
1208  %lhs = bitcast i32 %lhs.arg to <4 x i8>
1209  %rhs = bitcast i32 %rhs.arg to <4 x i8>
1210  %amt = bitcast i32 %amt.arg to <4 x i8>
1211  %result = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %lhs, <4 x i8> %rhs, <4 x i8> %amt)
1212  %cast.result = bitcast <4 x i8> %result to i32
1213  ret i32 %cast.result
1214}
1215
1216define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) {
1217; GFX6-LABEL: s_fshl_i24:
1218; GFX6:       ; %bb.0:
1219; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1220; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1221; GFX6-NEXT:    s_sub_i32 s3, 0, 24
1222; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1223; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1224; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
1225; GFX6-NEXT:    s_mov_b32 s3, 0xffffff
1226; GFX6-NEXT:    s_and_b32 s2, s2, s3
1227; GFX6-NEXT:    s_and_b32 s1, s1, s3
1228; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
1229; GFX6-NEXT:    s_lshr_b32 s1, s1, 1
1230; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1231; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
1232; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
1233; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1234; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 24, v0
1235; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1236; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1237; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, 24, v0
1238; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1239; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1240; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 23, v0
1241; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
1242; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
1243; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0
1244; GFX6-NEXT:    v_lshr_b32_e32 v1, s1, v1
1245; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1246; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
1247; GFX6-NEXT:    ; return to shader part epilog
1248;
1249; GFX8-LABEL: s_fshl_i24:
1250; GFX8:       ; %bb.0:
1251; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1252; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1253; GFX8-NEXT:    s_sub_i32 s3, 0, 24
1254; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1255; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
1256; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
1257; GFX8-NEXT:    s_mov_b32 s3, 0xffffff
1258; GFX8-NEXT:    s_and_b32 s2, s2, s3
1259; GFX8-NEXT:    s_and_b32 s1, s1, s3
1260; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
1261; GFX8-NEXT:    s_lshr_b32 s1, s1, 1
1262; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
1263; GFX8-NEXT:    v_mul_hi_u32 v0, s2, v0
1264; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
1265; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
1266; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 24, v0
1267; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1268; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1269; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, 24, v0
1270; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1271; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1272; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 23, v0
1273; GFX8-NEXT:    v_and_b32_e32 v0, s3, v0
1274; GFX8-NEXT:    v_and_b32_e32 v1, s3, v1
1275; GFX8-NEXT:    v_lshlrev_b32_e64 v0, v0, s0
1276; GFX8-NEXT:    v_lshrrev_b32_e64 v1, v1, s1
1277; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1278; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
1279; GFX8-NEXT:    ; return to shader part epilog
1280;
1281; GFX9-LABEL: s_fshl_i24:
1282; GFX9:       ; %bb.0:
1283; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1284; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1285; GFX9-NEXT:    s_sub_i32 s3, 0, 24
1286; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1287; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1288; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
1289; GFX9-NEXT:    s_mov_b32 s3, 0xffffff
1290; GFX9-NEXT:    s_and_b32 s2, s2, s3
1291; GFX9-NEXT:    s_and_b32 s1, s1, s3
1292; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1293; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
1294; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
1295; GFX9-NEXT:    v_mul_hi_u32 v0, s2, v0
1296; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 24
1297; GFX9-NEXT:    v_sub_u32_e32 v0, s2, v0
1298; GFX9-NEXT:    v_subrev_u32_e32 v1, 24, v0
1299; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1300; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1301; GFX9-NEXT:    v_subrev_u32_e32 v1, 24, v0
1302; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1303; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1304; GFX9-NEXT:    v_sub_u32_e32 v1, 23, v0
1305; GFX9-NEXT:    v_and_b32_e32 v1, s3, v1
1306; GFX9-NEXT:    v_and_b32_e32 v0, s3, v0
1307; GFX9-NEXT:    v_lshrrev_b32_e64 v1, v1, s1
1308; GFX9-NEXT:    v_lshl_or_b32 v0, s0, v0, v1
1309; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
1310; GFX9-NEXT:    ; return to shader part epilog
1311;
1312; GFX10-LABEL: s_fshl_i24:
1313; GFX10:       ; %bb.0:
1314; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1315; GFX10-NEXT:    s_sub_i32 s3, 0, 24
1316; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1317; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1318; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1319; GFX10-NEXT:    v_mul_lo_u32 v1, s3, v0
1320; GFX10-NEXT:    s_mov_b32 s3, 0xffffff
1321; GFX10-NEXT:    s_and_b32 s2, s2, s3
1322; GFX10-NEXT:    s_and_b32 s1, s1, s3
1323; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
1324; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
1325; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
1326; GFX10-NEXT:    v_mul_hi_u32 v0, s2, v0
1327; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 24
1328; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
1329; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 24, v0
1330; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1331; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
1332; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 24, v0
1333; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1334; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
1335; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 23, v0
1336; GFX10-NEXT:    v_and_b32_e32 v0, s3, v0
1337; GFX10-NEXT:    v_and_b32_e32 v1, s3, v1
1338; GFX10-NEXT:    v_lshrrev_b32_e64 v1, v1, s1
1339; GFX10-NEXT:    v_lshl_or_b32 v0, s0, v0, v1
1340; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
1341; GFX10-NEXT:    ; return to shader part epilog
1342  %result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt)
1343  ret i24 %result
1344}
1345
1346define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
1347; GFX6-LABEL: v_fshl_i24:
1348; GFX6:       ; %bb.0:
1349; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1350; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1351; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1352; GFX6-NEXT:    s_sub_i32 s4, 0, 24
1353; GFX6-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1354; GFX6-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1355; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
1356; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
1357; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
1358; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
1359; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
1360; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffff
1361; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
1362; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
1363; GFX6-NEXT:    v_mul_lo_u32 v3, v3, 24
1364; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
1365; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v2
1366; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1367; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1368; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v2
1369; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1370; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1371; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v2
1372; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
1373; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
1374; GFX6-NEXT:    v_and_b32_e32 v2, v3, v4
1375; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1376; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1377; GFX6-NEXT:    s_setpc_b64 s[30:31]
1378;
1379; GFX8-LABEL: v_fshl_i24:
1380; GFX8:       ; %bb.0:
1381; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1382; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1383; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1384; GFX8-NEXT:    s_sub_i32 s4, 0, 24
1385; GFX8-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1386; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1387; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
1388; GFX8-NEXT:    v_mul_lo_u32 v4, s4, v3
1389; GFX8-NEXT:    v_mul_hi_u32 v4, v3, v4
1390; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v4
1391; GFX8-NEXT:    v_mul_hi_u32 v3, v2, v3
1392; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffff
1393; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
1394; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
1395; GFX8-NEXT:    v_mul_lo_u32 v3, v3, 24
1396; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
1397; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v2
1398; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1399; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1400; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, 24, v2
1401; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1402; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1403; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v2
1404; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
1405; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
1406; GFX8-NEXT:    v_and_b32_e32 v2, v3, v4
1407; GFX8-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
1408; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
1409; GFX8-NEXT:    s_setpc_b64 s[30:31]
1410;
1411; GFX9-LABEL: v_fshl_i24:
1412; GFX9:       ; %bb.0:
1413; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1414; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1415; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1416; GFX9-NEXT:    s_sub_i32 s4, 0, 24
1417; GFX9-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1418; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1419; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
1420; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v3
1421; GFX9-NEXT:    v_mul_hi_u32 v4, v3, v4
1422; GFX9-NEXT:    v_add_u32_e32 v3, v3, v4
1423; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3
1424; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffffff
1425; GFX9-NEXT:    v_and_b32_e32 v1, v1, v4
1426; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
1427; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 24
1428; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
1429; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v2
1430; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1431; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1432; GFX9-NEXT:    v_subrev_u32_e32 v3, 24, v2
1433; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
1434; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
1435; GFX9-NEXT:    v_sub_u32_e32 v3, 23, v2
1436; GFX9-NEXT:    v_and_b32_e32 v3, v3, v4
1437; GFX9-NEXT:    v_and_b32_e32 v2, v2, v4
1438; GFX9-NEXT:    v_lshrrev_b32_e32 v1, v3, v1
1439; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v2, v1
1440; GFX9-NEXT:    s_setpc_b64 s[30:31]
1441;
1442; GFX10-LABEL: v_fshl_i24:
1443; GFX10:       ; %bb.0:
1444; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1445; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1446; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 24
1447; GFX10-NEXT:    s_sub_i32 s4, 0, 24
1448; GFX10-NEXT:    v_and_b32_e32 v2, 0xffffff, v2
1449; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
1450; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
1451; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
1452; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v3
1453; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
1454; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
1455; GFX10-NEXT:    v_mov_b32_e32 v4, 0xffffff
1456; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
1457; GFX10-NEXT:    v_and_b32_e32 v1, v1, v4
1458; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
1459; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 24
1460; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
1461; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v2
1462; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v2
1463; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
1464; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v2
1465; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v2
1466; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
1467; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 23, v2
1468; GFX10-NEXT:    v_and_b32_e32 v2, v2, v4
1469; GFX10-NEXT:    v_and_b32_e32 v3, v3, v4
1470; GFX10-NEXT:    v_lshrrev_b32_e32 v1, v3, v1
1471; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v2, v1
1472; GFX10-NEXT:    s_setpc_b64 s[30:31]
1473  %result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt)
1474  ret i24 %result
1475}
1476
1477define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
1478; GFX6-LABEL: s_fshl_v2i24:
1479; GFX6:       ; %bb.0:
1480; GFX6-NEXT:    s_lshr_b32 s6, s0, 8
1481; GFX6-NEXT:    s_movk_i32 s10, 0xff
1482; GFX6-NEXT:    s_and_b32 s6, s6, s10
1483; GFX6-NEXT:    s_lshr_b32 s7, s0, 16
1484; GFX6-NEXT:    s_lshr_b32 s8, s0, 24
1485; GFX6-NEXT:    s_and_b32 s0, s0, s10
1486; GFX6-NEXT:    s_lshl_b32 s6, s6, 8
1487; GFX6-NEXT:    s_or_b32 s0, s0, s6
1488; GFX6-NEXT:    s_and_b32 s6, s7, s10
1489; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1490; GFX6-NEXT:    s_lshr_b32 s9, s1, 8
1491; GFX6-NEXT:    s_and_b32 s1, s1, s10
1492; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
1493; GFX6-NEXT:    s_lshl_b32 s6, s6, 16
1494; GFX6-NEXT:    s_lshl_b32 s1, s1, 8
1495; GFX6-NEXT:    s_or_b32 s0, s0, s6
1496; GFX6-NEXT:    s_and_b32 s6, s9, s10
1497; GFX6-NEXT:    s_or_b32 s1, s8, s1
1498; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1499; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
1500; GFX6-NEXT:    s_lshl_b32 s6, s6, 16
1501; GFX6-NEXT:    s_or_b32 s1, s1, s6
1502; GFX6-NEXT:    s_lshr_b32 s6, s2, 8
1503; GFX6-NEXT:    s_and_b32 s6, s6, s10
1504; GFX6-NEXT:    s_lshr_b32 s7, s2, 16
1505; GFX6-NEXT:    s_lshr_b32 s8, s2, 24
1506; GFX6-NEXT:    s_and_b32 s2, s2, s10
1507; GFX6-NEXT:    s_lshl_b32 s6, s6, 8
1508; GFX6-NEXT:    s_or_b32 s2, s2, s6
1509; GFX6-NEXT:    s_and_b32 s6, s7, s10
1510; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1511; GFX6-NEXT:    s_lshr_b32 s9, s3, 8
1512; GFX6-NEXT:    s_and_b32 s3, s3, s10
1513; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
1514; GFX6-NEXT:    s_lshl_b32 s6, s6, 16
1515; GFX6-NEXT:    s_lshl_b32 s3, s3, 8
1516; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1517; GFX6-NEXT:    s_or_b32 s2, s2, s6
1518; GFX6-NEXT:    s_and_b32 s6, s9, s10
1519; GFX6-NEXT:    s_or_b32 s3, s8, s3
1520; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1521; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1522; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
1523; GFX6-NEXT:    s_lshl_b32 s6, s6, 16
1524; GFX6-NEXT:    s_or_b32 s3, s3, s6
1525; GFX6-NEXT:    s_lshr_b32 s6, s4, 8
1526; GFX6-NEXT:    s_and_b32 s6, s6, s10
1527; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1528; GFX6-NEXT:    s_lshr_b32 s7, s4, 16
1529; GFX6-NEXT:    s_lshr_b32 s8, s4, 24
1530; GFX6-NEXT:    s_and_b32 s4, s4, s10
1531; GFX6-NEXT:    s_lshl_b32 s6, s6, 8
1532; GFX6-NEXT:    s_or_b32 s4, s4, s6
1533; GFX6-NEXT:    s_and_b32 s6, s7, s10
1534; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
1535; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
1536; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
1537; GFX6-NEXT:    s_lshl_b32 s6, s6, 16
1538; GFX6-NEXT:    s_or_b32 s4, s4, s6
1539; GFX6-NEXT:    s_sub_i32 s6, 0, 24
1540; GFX6-NEXT:    v_mul_lo_u32 v1, s6, v0
1541; GFX6-NEXT:    s_lshr_b32 s9, s5, 8
1542; GFX6-NEXT:    s_and_b32 s5, s5, s10
1543; GFX6-NEXT:    s_lshl_b32 s5, s5, 8
1544; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
1545; GFX6-NEXT:    s_and_b32 s7, s9, s10
1546; GFX6-NEXT:    s_or_b32 s5, s8, s5
1547; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
1548; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1549; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1550; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1551; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
1552; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
1553; GFX6-NEXT:    s_lshl_b32 s7, s7, 16
1554; GFX6-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1555; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
1556; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
1557; GFX6-NEXT:    s_or_b32 s5, s5, s7
1558; GFX6-NEXT:    s_mov_b32 s7, 0xffffff
1559; GFX6-NEXT:    v_mul_lo_u32 v3, s6, v1
1560; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1561; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1562; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1563; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
1564; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1565; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1566; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1567; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1568; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1569; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
1570; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v0
1571; GFX6-NEXT:    v_and_b32_e32 v0, s7, v0
1572; GFX6-NEXT:    v_lshl_b32_e32 v0, s0, v0
1573; GFX6-NEXT:    v_mul_lo_u32 v1, v1, 24
1574; GFX6-NEXT:    s_lshr_b32 s0, s2, 1
1575; GFX6-NEXT:    v_and_b32_e32 v2, s7, v2
1576; GFX6-NEXT:    v_lshr_b32_e32 v2, s0, v2
1577; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
1578; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1579; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
1580; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1581; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1582; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
1583; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1584; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1585; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffff
1586; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v1
1587; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
1588; GFX6-NEXT:    s_lshr_b32 s0, s3, 1
1589; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
1590; GFX6-NEXT:    v_lshl_b32_e32 v1, s1, v1
1591; GFX6-NEXT:    v_lshr_b32_e32 v2, s0, v2
1592; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
1593; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
1594; GFX6-NEXT:    v_and_b32_e32 v2, s10, v2
1595; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
1596; GFX6-NEXT:    v_and_b32_e32 v0, s10, v0
1597; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1598; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1599; GFX6-NEXT:    v_and_b32_e32 v2, s10, v3
1600; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
1601; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
1602; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
1603; GFX6-NEXT:    v_and_b32_e32 v1, s10, v1
1604; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
1605; GFX6-NEXT:    v_and_b32_e32 v2, s10, v5
1606; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
1607; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
1608; GFX6-NEXT:    v_and_b32_e32 v1, s10, v4
1609; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1610; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
1611; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
1612; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
1613; GFX6-NEXT:    ; return to shader part epilog
1614;
1615; GFX8-LABEL: s_fshl_v2i24:
1616; GFX8:       ; %bb.0:
1617; GFX8-NEXT:    s_lshr_b32 s6, s0, 8
1618; GFX8-NEXT:    s_movk_i32 s10, 0xff
1619; GFX8-NEXT:    s_and_b32 s6, s6, s10
1620; GFX8-NEXT:    s_bfe_u32 s11, 8, 0x100000
1621; GFX8-NEXT:    s_lshr_b32 s7, s0, 16
1622; GFX8-NEXT:    s_lshr_b32 s8, s0, 24
1623; GFX8-NEXT:    s_and_b32 s0, s0, s10
1624; GFX8-NEXT:    s_lshl_b32 s6, s6, s11
1625; GFX8-NEXT:    s_or_b32 s0, s0, s6
1626; GFX8-NEXT:    s_and_b32 s6, s7, s10
1627; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1628; GFX8-NEXT:    s_lshr_b32 s9, s1, 8
1629; GFX8-NEXT:    s_and_b32 s1, s1, s10
1630; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
1631; GFX8-NEXT:    s_lshl_b32 s6, s6, 16
1632; GFX8-NEXT:    s_lshl_b32 s1, s1, s11
1633; GFX8-NEXT:    s_or_b32 s0, s0, s6
1634; GFX8-NEXT:    s_and_b32 s6, s9, s10
1635; GFX8-NEXT:    s_or_b32 s1, s8, s1
1636; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1637; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
1638; GFX8-NEXT:    s_lshl_b32 s6, s6, 16
1639; GFX8-NEXT:    s_or_b32 s1, s1, s6
1640; GFX8-NEXT:    s_lshr_b32 s6, s2, 8
1641; GFX8-NEXT:    s_and_b32 s6, s6, s10
1642; GFX8-NEXT:    s_lshr_b32 s7, s2, 16
1643; GFX8-NEXT:    s_lshr_b32 s8, s2, 24
1644; GFX8-NEXT:    s_and_b32 s2, s2, s10
1645; GFX8-NEXT:    s_lshl_b32 s6, s6, s11
1646; GFX8-NEXT:    s_or_b32 s2, s2, s6
1647; GFX8-NEXT:    s_and_b32 s6, s7, s10
1648; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1649; GFX8-NEXT:    s_lshr_b32 s9, s3, 8
1650; GFX8-NEXT:    s_and_b32 s3, s3, s10
1651; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
1652; GFX8-NEXT:    s_lshl_b32 s6, s6, 16
1653; GFX8-NEXT:    s_lshl_b32 s3, s3, s11
1654; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1655; GFX8-NEXT:    s_or_b32 s2, s2, s6
1656; GFX8-NEXT:    s_and_b32 s6, s9, s10
1657; GFX8-NEXT:    s_or_b32 s3, s8, s3
1658; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1659; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1660; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
1661; GFX8-NEXT:    s_lshl_b32 s6, s6, 16
1662; GFX8-NEXT:    s_or_b32 s3, s3, s6
1663; GFX8-NEXT:    s_lshr_b32 s6, s4, 8
1664; GFX8-NEXT:    s_and_b32 s6, s6, s10
1665; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1666; GFX8-NEXT:    s_lshr_b32 s7, s4, 16
1667; GFX8-NEXT:    s_lshr_b32 s8, s4, 24
1668; GFX8-NEXT:    s_and_b32 s4, s4, s10
1669; GFX8-NEXT:    s_lshl_b32 s6, s6, s11
1670; GFX8-NEXT:    s_or_b32 s4, s4, s6
1671; GFX8-NEXT:    s_and_b32 s6, s7, s10
1672; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
1673; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
1674; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
1675; GFX8-NEXT:    s_lshl_b32 s6, s6, 16
1676; GFX8-NEXT:    s_or_b32 s4, s4, s6
1677; GFX8-NEXT:    s_sub_i32 s6, 0, 24
1678; GFX8-NEXT:    v_mul_lo_u32 v1, s6, v0
1679; GFX8-NEXT:    s_lshr_b32 s9, s5, 8
1680; GFX8-NEXT:    s_and_b32 s5, s5, s10
1681; GFX8-NEXT:    s_lshl_b32 s5, s5, s11
1682; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
1683; GFX8-NEXT:    s_and_b32 s7, s9, s10
1684; GFX8-NEXT:    s_or_b32 s5, s8, s5
1685; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
1686; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
1687; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1688; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1689; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
1690; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
1691; GFX8-NEXT:    s_lshl_b32 s7, s7, 16
1692; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1693; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
1694; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
1695; GFX8-NEXT:    s_or_b32 s5, s5, s7
1696; GFX8-NEXT:    s_mov_b32 s7, 0xffffff
1697; GFX8-NEXT:    v_mul_lo_u32 v3, s6, v1
1698; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
1699; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
1700; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1701; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
1702; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1703; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
1704; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1705; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1706; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
1707; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
1708; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v0
1709; GFX8-NEXT:    v_and_b32_e32 v0, s7, v0
1710; GFX8-NEXT:    v_lshlrev_b32_e64 v0, v0, s0
1711; GFX8-NEXT:    v_mul_lo_u32 v1, v1, 24
1712; GFX8-NEXT:    s_lshr_b32 s0, s2, 1
1713; GFX8-NEXT:    v_and_b32_e32 v2, s7, v2
1714; GFX8-NEXT:    v_lshrrev_b32_e64 v2, v2, s0
1715; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
1716; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
1717; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
1718; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1719; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1720; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
1721; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1722; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1723; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffff
1724; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v1
1725; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
1726; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
1727; GFX8-NEXT:    s_lshr_b32 s0, s3, 1
1728; GFX8-NEXT:    v_lshlrev_b32_e64 v1, v1, s1
1729; GFX8-NEXT:    v_lshrrev_b32_e64 v2, v2, s0
1730; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
1731; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
1732; GFX8-NEXT:    v_mov_b32_e32 v4, 8
1733; GFX8-NEXT:    v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1734; GFX8-NEXT:    v_mov_b32_e32 v4, s10
1735; GFX8-NEXT:    v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1736; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1737; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
1738; GFX8-NEXT:    v_and_b32_e32 v2, s10, v1
1739; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
1740; GFX8-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1741; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1742; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
1743; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
1744; GFX8-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
1745; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
1746; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
1747; GFX8-NEXT:    ; return to shader part epilog
1748;
1749; GFX9-LABEL: s_fshl_v2i24:
1750; GFX9:       ; %bb.0:
1751; GFX9-NEXT:    s_lshr_b32 s7, s0, 8
1752; GFX9-NEXT:    s_movk_i32 s11, 0xff
1753; GFX9-NEXT:    s_and_b32 s7, s7, s11
1754; GFX9-NEXT:    s_bfe_u32 s12, 8, 0x100000
1755; GFX9-NEXT:    s_lshr_b32 s8, s0, 16
1756; GFX9-NEXT:    s_lshr_b32 s9, s0, 24
1757; GFX9-NEXT:    s_and_b32 s0, s0, s11
1758; GFX9-NEXT:    s_lshl_b32 s7, s7, s12
1759; GFX9-NEXT:    s_or_b32 s0, s0, s7
1760; GFX9-NEXT:    s_and_b32 s7, s8, s11
1761; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1762; GFX9-NEXT:    s_lshr_b32 s10, s1, 8
1763; GFX9-NEXT:    s_and_b32 s1, s1, s11
1764; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
1765; GFX9-NEXT:    s_lshl_b32 s7, s7, 16
1766; GFX9-NEXT:    s_lshl_b32 s1, s1, s12
1767; GFX9-NEXT:    s_or_b32 s0, s0, s7
1768; GFX9-NEXT:    s_and_b32 s7, s10, s11
1769; GFX9-NEXT:    s_or_b32 s1, s9, s1
1770; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1771; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
1772; GFX9-NEXT:    s_lshl_b32 s7, s7, 16
1773; GFX9-NEXT:    s_or_b32 s1, s1, s7
1774; GFX9-NEXT:    s_lshr_b32 s7, s2, 8
1775; GFX9-NEXT:    s_and_b32 s7, s7, s11
1776; GFX9-NEXT:    s_lshr_b32 s8, s2, 16
1777; GFX9-NEXT:    s_lshr_b32 s9, s2, 24
1778; GFX9-NEXT:    s_and_b32 s2, s2, s11
1779; GFX9-NEXT:    s_lshl_b32 s7, s7, s12
1780; GFX9-NEXT:    s_or_b32 s2, s2, s7
1781; GFX9-NEXT:    s_and_b32 s7, s8, s11
1782; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1783; GFX9-NEXT:    s_lshr_b32 s10, s3, 8
1784; GFX9-NEXT:    s_and_b32 s3, s3, s11
1785; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
1786; GFX9-NEXT:    s_lshl_b32 s7, s7, 16
1787; GFX9-NEXT:    s_or_b32 s2, s2, s7
1788; GFX9-NEXT:    s_and_b32 s7, s10, s11
1789; GFX9-NEXT:    s_lshl_b32 s3, s3, s12
1790; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1791; GFX9-NEXT:    s_or_b32 s3, s9, s3
1792; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1793; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1794; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
1795; GFX9-NEXT:    s_lshl_b32 s7, s7, 16
1796; GFX9-NEXT:    s_or_b32 s3, s3, s7
1797; GFX9-NEXT:    s_lshr_b32 s7, s4, 8
1798; GFX9-NEXT:    s_and_b32 s7, s7, s11
1799; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1800; GFX9-NEXT:    s_lshr_b32 s8, s4, 16
1801; GFX9-NEXT:    s_lshr_b32 s9, s4, 24
1802; GFX9-NEXT:    s_and_b32 s4, s4, s11
1803; GFX9-NEXT:    s_lshl_b32 s7, s7, s12
1804; GFX9-NEXT:    s_or_b32 s4, s4, s7
1805; GFX9-NEXT:    s_and_b32 s7, s8, s11
1806; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
1807; GFX9-NEXT:    s_bfe_u32 s7, s7, 0x100000
1808; GFX9-NEXT:    s_bfe_u32 s4, s4, 0x100000
1809; GFX9-NEXT:    s_lshl_b32 s7, s7, 16
1810; GFX9-NEXT:    s_or_b32 s4, s4, s7
1811; GFX9-NEXT:    s_sub_i32 s7, 0, 24
1812; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v0
1813; GFX9-NEXT:    s_lshr_b32 s10, s5, 8
1814; GFX9-NEXT:    s_and_b32 s5, s5, s11
1815; GFX9-NEXT:    s_lshl_b32 s5, s5, s12
1816; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
1817; GFX9-NEXT:    s_and_b32 s8, s10, s11
1818; GFX9-NEXT:    s_or_b32 s5, s9, s5
1819; GFX9-NEXT:    s_bfe_u32 s8, s8, 0x100000
1820; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
1821; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1822; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1823; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0
1824; GFX9-NEXT:    s_bfe_u32 s5, s5, 0x100000
1825; GFX9-NEXT:    s_lshl_b32 s8, s8, 16
1826; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1827; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
1828; GFX9-NEXT:    v_mul_lo_u32 v0, v0, 24
1829; GFX9-NEXT:    s_or_b32 s5, s5, s8
1830; GFX9-NEXT:    s_mov_b32 s8, 0xffffff
1831; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v1
1832; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
1833; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v0
1834; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1835; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
1836; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1837; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v0
1838; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
1839; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
1840; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1
1841; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1842; GFX9-NEXT:    v_sub_u32_e32 v2, 23, v0
1843; GFX9-NEXT:    s_lshr_b32 s2, s2, 1
1844; GFX9-NEXT:    v_mul_lo_u32 v1, v1, 24
1845; GFX9-NEXT:    v_and_b32_e32 v2, s8, v2
1846; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
1847; GFX9-NEXT:    v_lshrrev_b32_e64 v2, v2, s2
1848; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v1
1849; GFX9-NEXT:    v_lshl_or_b32 v0, s0, v0, v2
1850; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v1
1851; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1852; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1853; GFX9-NEXT:    v_subrev_u32_e32 v2, 24, v1
1854; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
1855; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1856; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffffff
1857; GFX9-NEXT:    v_sub_u32_e32 v2, 23, v1
1858; GFX9-NEXT:    s_lshr_b32 s0, s3, 1
1859; GFX9-NEXT:    v_and_b32_e32 v2, v2, v3
1860; GFX9-NEXT:    v_and_b32_e32 v1, v1, v3
1861; GFX9-NEXT:    v_lshrrev_b32_e64 v2, v2, s0
1862; GFX9-NEXT:    v_lshl_or_b32 v1, s1, v1, v2
1863; GFX9-NEXT:    s_mov_b32 s6, 8
1864; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
1865; GFX9-NEXT:    v_lshlrev_b32_sdwa v2, s6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1866; GFX9-NEXT:    v_and_b32_e32 v4, s11, v1
1867; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
1868; GFX9-NEXT:    v_and_b32_sdwa v1, v1, s11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1869; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
1870; GFX9-NEXT:    v_and_or_b32 v2, v0, s11, v2
1871; GFX9-NEXT:    v_and_b32_sdwa v0, v0, s11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1872; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 24, v4
1873; GFX9-NEXT:    v_or3_b32 v0, v2, v0, v4
1874; GFX9-NEXT:    v_and_or_b32 v1, v3, s11, v1
1875; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
1876; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
1877; GFX9-NEXT:    ; return to shader part epilog
1878;
1879; GFX10-LABEL: s_fshl_v2i24:
1880; GFX10:       ; %bb.0:
1881; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, 24
1882; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
1883; GFX10-NEXT:    s_movk_i32 s8, 0xff
1884; GFX10-NEXT:    s_lshr_b32 s11, s1, 8
1885; GFX10-NEXT:    s_bfe_u32 s10, 8, 0x100000
1886; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1887; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1888; GFX10-NEXT:    s_and_b32 s1, s1, s8
1889; GFX10-NEXT:    s_lshr_b32 s9, s0, 24
1890; GFX10-NEXT:    s_lshl_b32 s1, s1, s10
1891; GFX10-NEXT:    s_lshr_b32 s6, s0, 8
1892; GFX10-NEXT:    s_or_b32 s1, s9, s1
1893; GFX10-NEXT:    s_sub_i32 s9, 0, 24
1894; GFX10-NEXT:    s_and_b32 s6, s6, s8
1895; GFX10-NEXT:    s_lshr_b32 s7, s0, 16
1896; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
1897; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
1898; GFX10-NEXT:    s_and_b32 s0, s0, s8
1899; GFX10-NEXT:    s_lshl_b32 s6, s6, s10
1900; GFX10-NEXT:    s_lshr_b32 s12, s4, 24
1901; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
1902; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1
1903; GFX10-NEXT:    s_or_b32 s0, s0, s6
1904; GFX10-NEXT:    s_and_b32 s6, s7, s8
1905; GFX10-NEXT:    s_lshr_b32 s7, s4, 8
1906; GFX10-NEXT:    v_mul_lo_u32 v2, s9, v0
1907; GFX10-NEXT:    v_mul_lo_u32 v3, s9, v1
1908; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
1909; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
1910; GFX10-NEXT:    s_lshl_b32 s6, s6, 16
1911; GFX10-NEXT:    s_and_b32 s7, s7, s8
1912; GFX10-NEXT:    s_or_b32 s0, s0, s6
1913; GFX10-NEXT:    s_and_b32 s6, s11, s8
1914; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2
1915; GFX10-NEXT:    s_lshr_b32 s11, s4, 16
1916; GFX10-NEXT:    s_and_b32 s4, s4, s8
1917; GFX10-NEXT:    s_lshl_b32 s7, s7, s10
1918; GFX10-NEXT:    s_and_b32 s9, s11, s8
1919; GFX10-NEXT:    s_or_b32 s4, s4, s7
1920; GFX10-NEXT:    s_bfe_u32 s7, s9, 0x100000
1921; GFX10-NEXT:    s_lshr_b32 s13, s5, 8
1922; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
1923; GFX10-NEXT:    v_mul_hi_u32 v2, v1, v3
1924; GFX10-NEXT:    s_and_b32 s5, s5, s8
1925; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
1926; GFX10-NEXT:    s_lshl_b32 s7, s7, 16
1927; GFX10-NEXT:    s_lshl_b32 s5, s5, s10
1928; GFX10-NEXT:    s_or_b32 s4, s4, s7
1929; GFX10-NEXT:    s_and_b32 s7, s13, s8
1930; GFX10-NEXT:    s_or_b32 s5, s12, s5
1931; GFX10-NEXT:    s_bfe_u32 s7, s7, 0x100000
1932; GFX10-NEXT:    v_mul_hi_u32 v0, s4, v0
1933; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v2
1934; GFX10-NEXT:    s_bfe_u32 s5, s5, 0x100000
1935; GFX10-NEXT:    s_lshl_b32 s7, s7, 16
1936; GFX10-NEXT:    s_lshr_b32 s9, s2, 16
1937; GFX10-NEXT:    s_or_b32 s5, s5, s7
1938; GFX10-NEXT:    s_lshr_b32 s7, s2, 8
1939; GFX10-NEXT:    v_mul_hi_u32 v1, s5, v1
1940; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 24
1941; GFX10-NEXT:    s_lshr_b32 s11, s2, 24
1942; GFX10-NEXT:    s_and_b32 s2, s2, s8
1943; GFX10-NEXT:    s_lshr_b32 s12, s3, 8
1944; GFX10-NEXT:    s_and_b32 s3, s3, s8
1945; GFX10-NEXT:    s_bfe_u32 s6, s6, 0x100000
1946; GFX10-NEXT:    s_lshl_b32 s3, s3, s10
1947; GFX10-NEXT:    v_mul_lo_u32 v1, v1, 24
1948; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s4, v0
1949; GFX10-NEXT:    s_and_b32 s4, s7, s8
1950; GFX10-NEXT:    s_and_b32 s7, s9, s8
1951; GFX10-NEXT:    s_lshl_b32 s4, s4, s10
1952; GFX10-NEXT:    s_or_b32 s3, s11, s3
1953; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v0
1954; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1955; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s5, v1
1956; GFX10-NEXT:    s_or_b32 s2, s2, s4
1957; GFX10-NEXT:    s_bfe_u32 s4, s7, 0x100000
1958; GFX10-NEXT:    s_mov_b32 s5, 0xffffff
1959; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
1960; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v1
1961; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v1
1962; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
1963; GFX10-NEXT:    s_lshl_b32 s4, s4, 16
1964; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 24, v0
1965; GFX10-NEXT:    s_or_b32 s2, s2, s4
1966; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
1967; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v0
1968; GFX10-NEXT:    s_and_b32 s4, s12, s8
1969; GFX10-NEXT:    s_lshr_b32 s2, s2, 1
1970; GFX10-NEXT:    s_bfe_u32 s4, s4, 0x100000
1971; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, 24, v1
1972; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo
1973; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v1
1974; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
1975; GFX10-NEXT:    s_lshl_b32 s6, s6, 16
1976; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 23, v0
1977; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
1978; GFX10-NEXT:    v_and_b32_e32 v0, s5, v0
1979; GFX10-NEXT:    v_and_b32_e32 v2, s5, v3
1980; GFX10-NEXT:    v_mov_b32_e32 v3, 0xffffff
1981; GFX10-NEXT:    v_sub_nc_u32_e32 v4, 23, v1
1982; GFX10-NEXT:    v_lshrrev_b32_e64 v2, v2, s2
1983; GFX10-NEXT:    s_bfe_u32 s2, s3, 0x100000
1984; GFX10-NEXT:    s_lshl_b32 s3, s4, 16
1985; GFX10-NEXT:    v_and_b32_e32 v4, v4, v3
1986; GFX10-NEXT:    s_or_b32 s2, s2, s3
1987; GFX10-NEXT:    v_lshl_or_b32 v0, s0, v0, v2
1988; GFX10-NEXT:    s_lshr_b32 s0, s2, 1
1989; GFX10-NEXT:    v_and_b32_e32 v1, v1, v3
1990; GFX10-NEXT:    v_lshrrev_b32_e64 v2, v4, s0
1991; GFX10-NEXT:    s_or_b32 s0, s1, s6
1992; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
1993; GFX10-NEXT:    v_lshl_or_b32 v1, s0, v1, v2
1994; GFX10-NEXT:    s_mov_b32 s0, 8
1995; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, s0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1996; GFX10-NEXT:    v_and_b32_e32 v3, s8, v1
1997; GFX10-NEXT:    v_and_b32_sdwa v4, v1, s8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1998; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
1999; GFX10-NEXT:    v_and_or_b32 v2, v0, s8, v2
2000; GFX10-NEXT:    v_and_b32_sdwa v0, v0, s8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
2001; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
2002; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 8, v4
2003; GFX10-NEXT:    v_or3_b32 v0, v2, v0, v3
2004; GFX10-NEXT:    v_and_or_b32 v1, v1, s8, v4
2005; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2006; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
2007; GFX10-NEXT:    ; return to shader part epilog
2008  %lhs = bitcast i48 %lhs.arg to <2 x i24>
2009  %rhs = bitcast i48 %rhs.arg to <2 x i24>
2010  %amt = bitcast i48 %amt.arg to <2 x i24>
2011  %result = call <2 x i24> @llvm.fshl.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
2012  %cast.result = bitcast <2 x i24> %result to i48
2013  ret i48 %cast.result
2014}
2015
2016define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
2017; GFX6-LABEL: v_fshl_v2i24:
2018; GFX6:       ; %bb.0:
2019; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2020; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2021; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2022; GFX6-NEXT:    s_sub_i32 s4, 0, 24
2023; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2024; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
2025; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2026; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
2027; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v6
2028; GFX6-NEXT:    v_mul_hi_u32 v7, v6, v7
2029; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
2030; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
2031; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v8
2032; GFX6-NEXT:    v_mov_b32_e32 v8, 0xffffff
2033; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
2034; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
2035; GFX6-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2036; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
2037; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2038; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
2039; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
2040; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2041; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2042; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
2043; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2044; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2045; GFX6-NEXT:    v_mul_lo_u32 v6, s4, v7
2046; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 23, v4
2047; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
2048; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v4, v0
2049; GFX6-NEXT:    v_mul_hi_u32 v6, v7, v6
2050; GFX6-NEXT:    v_and_b32_e32 v4, v5, v8
2051; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v6
2052; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
2053; GFX6-NEXT:    v_and_b32_e32 v6, v9, v8
2054; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
2055; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
2056; GFX6-NEXT:    v_mul_lo_u32 v5, v5, 24
2057; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v4, v5
2058; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
2059; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2060; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2061; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
2062; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2063; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2064; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
2065; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
2066; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
2067; GFX6-NEXT:    v_and_b32_e32 v2, v3, v8
2068; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2069; GFX6-NEXT:    v_and_b32_e32 v3, v4, v8
2070; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
2071; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
2072; GFX6-NEXT:    s_setpc_b64 s[30:31]
2073;
2074; GFX8-LABEL: v_fshl_v2i24:
2075; GFX8:       ; %bb.0:
2076; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2077; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2078; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2079; GFX8-NEXT:    s_sub_i32 s4, 0, 24
2080; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2081; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
2082; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2083; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
2084; GFX8-NEXT:    v_mul_lo_u32 v7, s4, v6
2085; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7
2086; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v7
2087; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
2088; GFX8-NEXT:    v_rcp_iflag_f32_e32 v7, v8
2089; GFX8-NEXT:    v_mov_b32_e32 v8, 0xffffff
2090; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
2091; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
2092; GFX8-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2093; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v7
2094; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2095; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
2096; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
2097; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2098; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2099; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
2100; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2101; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2102; GFX8-NEXT:    v_mul_lo_u32 v6, s4, v7
2103; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, 23, v4
2104; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
2105; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v4, v0
2106; GFX8-NEXT:    v_mul_hi_u32 v6, v7, v6
2107; GFX8-NEXT:    v_and_b32_e32 v4, v5, v8
2108; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v7, v6
2109; GFX8-NEXT:    v_mul_hi_u32 v5, v4, v5
2110; GFX8-NEXT:    v_and_b32_e32 v6, v9, v8
2111; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
2112; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
2113; GFX8-NEXT:    v_mul_lo_u32 v5, v5, 24
2114; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v4, v5
2115; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
2116; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2117; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2118; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
2119; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2120; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2121; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
2122; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
2123; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
2124; GFX8-NEXT:    v_and_b32_e32 v2, v3, v8
2125; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2126; GFX8-NEXT:    v_and_b32_e32 v3, v4, v8
2127; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
2128; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
2129; GFX8-NEXT:    s_setpc_b64 s[30:31]
2130;
2131; GFX9-LABEL: v_fshl_v2i24:
2132; GFX9:       ; %bb.0:
2133; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2134; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2135; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2136; GFX9-NEXT:    s_sub_i32 s4, 0, 24
2137; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
2138; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v8
2139; GFX9-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2140; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
2141; GFX9-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2142; GFX9-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
2143; GFX9-NEXT:    v_mov_b32_e32 v9, 0xffffff
2144; GFX9-NEXT:    v_mul_lo_u32 v7, s4, v6
2145; GFX9-NEXT:    v_and_b32_e32 v5, v5, v9
2146; GFX9-NEXT:    v_and_b32_e32 v2, v2, v9
2147; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2148; GFX9-NEXT:    v_mul_hi_u32 v7, v6, v7
2149; GFX9-NEXT:    v_and_b32_e32 v3, v3, v9
2150; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
2151; GFX9-NEXT:    v_add_u32_e32 v6, v6, v7
2152; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v8
2153; GFX9-NEXT:    v_mul_hi_u32 v6, v4, v6
2154; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v7
2155; GFX9-NEXT:    v_mul_lo_u32 v6, v6, 24
2156; GFX9-NEXT:    v_mul_hi_u32 v8, v7, v8
2157; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v6
2158; GFX9-NEXT:    v_subrev_u32_e32 v6, 24, v4
2159; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2160; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
2161; GFX9-NEXT:    v_mul_hi_u32 v7, v5, v7
2162; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2163; GFX9-NEXT:    v_subrev_u32_e32 v6, 24, v4
2164; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
2165; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
2166; GFX9-NEXT:    v_mul_lo_u32 v7, v7, 24
2167; GFX9-NEXT:    v_sub_u32_e32 v6, 23, v4
2168; GFX9-NEXT:    v_and_b32_e32 v6, v6, v9
2169; GFX9-NEXT:    v_and_b32_e32 v4, v4, v9
2170; GFX9-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
2171; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v4, v2
2172; GFX9-NEXT:    v_sub_u32_e32 v2, v5, v7
2173; GFX9-NEXT:    v_subrev_u32_e32 v4, 24, v2
2174; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2175; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2176; GFX9-NEXT:    v_subrev_u32_e32 v4, 24, v2
2177; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
2178; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
2179; GFX9-NEXT:    v_sub_u32_e32 v4, 23, v2
2180; GFX9-NEXT:    v_and_b32_e32 v4, v4, v9
2181; GFX9-NEXT:    v_and_b32_e32 v2, v2, v9
2182; GFX9-NEXT:    v_lshrrev_b32_e32 v3, v4, v3
2183; GFX9-NEXT:    v_lshl_or_b32 v1, v1, v2, v3
2184; GFX9-NEXT:    s_setpc_b64 s[30:31]
2185;
2186; GFX10-LABEL: v_fshl_v2i24:
2187; GFX10:       ; %bb.0:
2188; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2189; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2190; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
2191; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v7, 24
2192; GFX10-NEXT:    s_sub_i32 s4, 0, 24
2193; GFX10-NEXT:    v_mov_b32_e32 v10, 0xffffff
2194; GFX10-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
2195; GFX10-NEXT:    v_rcp_iflag_f32_e32 v6, v6
2196; GFX10-NEXT:    v_rcp_iflag_f32_e32 v7, v7
2197; GFX10-NEXT:    v_and_b32_e32 v5, v5, v10
2198; GFX10-NEXT:    v_and_b32_e32 v2, v2, v10
2199; GFX10-NEXT:    v_and_b32_e32 v3, v3, v10
2200; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2201; GFX10-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
2202; GFX10-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
2203; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
2204; GFX10-NEXT:    v_cvt_u32_f32_e32 v6, v6
2205; GFX10-NEXT:    v_cvt_u32_f32_e32 v7, v7
2206; GFX10-NEXT:    v_mul_lo_u32 v8, s4, v6
2207; GFX10-NEXT:    v_mul_lo_u32 v9, s4, v7
2208; GFX10-NEXT:    v_mul_hi_u32 v8, v6, v8
2209; GFX10-NEXT:    v_mul_hi_u32 v9, v7, v9
2210; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v8
2211; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v9
2212; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v6
2213; GFX10-NEXT:    v_mul_hi_u32 v7, v5, v7
2214; GFX10-NEXT:    v_mul_lo_u32 v6, v6, 24
2215; GFX10-NEXT:    v_mul_lo_u32 v7, v7, 24
2216; GFX10-NEXT:    v_sub_nc_u32_e32 v4, v4, v6
2217; GFX10-NEXT:    v_sub_nc_u32_e32 v5, v5, v7
2218; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 24, v4
2219; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v4
2220; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 24, v5
2221; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
2222; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v5
2223; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, 24, v4
2224; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
2225; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v4
2226; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, 24, v5
2227; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
2228; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 24, v5
2229; GFX10-NEXT:    v_sub_nc_u32_e32 v6, 23, v4
2230; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
2231; GFX10-NEXT:    v_and_b32_e32 v4, v4, v10
2232; GFX10-NEXT:    v_and_b32_e32 v6, v6, v10
2233; GFX10-NEXT:    v_sub_nc_u32_e32 v7, 23, v5
2234; GFX10-NEXT:    v_and_b32_e32 v5, v5, v10
2235; GFX10-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
2236; GFX10-NEXT:    v_and_b32_e32 v7, v7, v10
2237; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v4, v2
2238; GFX10-NEXT:    v_lshrrev_b32_e32 v3, v7, v3
2239; GFX10-NEXT:    v_lshl_or_b32 v1, v1, v5, v3
2240; GFX10-NEXT:    s_setpc_b64 s[30:31]
2241  %result = call <2 x i24> @llvm.fshl.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
2242  ret <2 x i24> %result
2243}
2244
2245define amdgpu_ps i32 @s_fshl_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
2246; GFX6-LABEL: s_fshl_i32:
2247; GFX6:       ; %bb.0:
2248; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2249; GFX6-NEXT:    s_not_b32 s1, s2
2250; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2251; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
2252; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2253; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2254; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2255; GFX6-NEXT:    ; return to shader part epilog
2256;
2257; GFX8-LABEL: s_fshl_i32:
2258; GFX8:       ; %bb.0:
2259; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2260; GFX8-NEXT:    s_not_b32 s1, s2
2261; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2262; GFX8-NEXT:    s_lshr_b32 s0, s0, 1
2263; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2264; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2265; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2266; GFX8-NEXT:    ; return to shader part epilog
2267;
2268; GFX9-LABEL: s_fshl_i32:
2269; GFX9:       ; %bb.0:
2270; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2271; GFX9-NEXT:    s_not_b32 s1, s2
2272; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2273; GFX9-NEXT:    s_lshr_b32 s0, s0, 1
2274; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2275; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2276; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2277; GFX9-NEXT:    ; return to shader part epilog
2278;
2279; GFX10-LABEL: s_fshl_i32:
2280; GFX10:       ; %bb.0:
2281; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, 1
2282; GFX10-NEXT:    s_lshr_b32 s0, s0, 1
2283; GFX10-NEXT:    s_not_b32 s1, s2
2284; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
2285; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2286; GFX10-NEXT:    ; return to shader part epilog
2287  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
2288  ret i32 %result
2289}
2290
2291define amdgpu_ps i32 @s_fshl_i32_5(i32 inreg %lhs, i32 inreg %rhs) {
2292; GFX6-LABEL: s_fshl_i32_5:
2293; GFX6:       ; %bb.0:
2294; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2295; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, -5
2296; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2297; GFX6-NEXT:    ; return to shader part epilog
2298;
2299; GFX8-LABEL: s_fshl_i32_5:
2300; GFX8:       ; %bb.0:
2301; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2302; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, -5
2303; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2304; GFX8-NEXT:    ; return to shader part epilog
2305;
2306; GFX9-LABEL: s_fshl_i32_5:
2307; GFX9:       ; %bb.0:
2308; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2309; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, -5
2310; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2311; GFX9-NEXT:    ; return to shader part epilog
2312;
2313; GFX10-LABEL: s_fshl_i32_5:
2314; GFX10:       ; %bb.0:
2315; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, -5
2316; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2317; GFX10-NEXT:    ; return to shader part epilog
2318  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5)
2319  ret i32 %result
2320}
2321
2322define amdgpu_ps i32 @s_fshl_i32_8(i32 inreg %lhs, i32 inreg %rhs) {
2323; GFX6-LABEL: s_fshl_i32_8:
2324; GFX6:       ; %bb.0:
2325; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2326; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, -8
2327; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
2328; GFX6-NEXT:    ; return to shader part epilog
2329;
2330; GFX8-LABEL: s_fshl_i32_8:
2331; GFX8:       ; %bb.0:
2332; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2333; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, -8
2334; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
2335; GFX8-NEXT:    ; return to shader part epilog
2336;
2337; GFX9-LABEL: s_fshl_i32_8:
2338; GFX9:       ; %bb.0:
2339; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2340; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, -8
2341; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
2342; GFX9-NEXT:    ; return to shader part epilog
2343;
2344; GFX10-LABEL: s_fshl_i32_8:
2345; GFX10:       ; %bb.0:
2346; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, -8
2347; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
2348; GFX10-NEXT:    ; return to shader part epilog
2349  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8)
2350  ret i32 %result
2351}
2352
2353define i32 @v_fshl_i32(i32 %lhs, i32 %rhs, i32 %amt) {
2354; GFX6-LABEL: v_fshl_i32:
2355; GFX6:       ; %bb.0:
2356; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2357; GFX6-NEXT:    v_alignbit_b32 v1, v0, v1, 1
2358; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2359; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
2360; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2361; GFX6-NEXT:    s_setpc_b64 s[30:31]
2362;
2363; GFX8-LABEL: v_fshl_i32:
2364; GFX8:       ; %bb.0:
2365; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2366; GFX8-NEXT:    v_alignbit_b32 v1, v0, v1, 1
2367; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2368; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
2369; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2370; GFX8-NEXT:    s_setpc_b64 s[30:31]
2371;
2372; GFX9-LABEL: v_fshl_i32:
2373; GFX9:       ; %bb.0:
2374; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2375; GFX9-NEXT:    v_alignbit_b32 v1, v0, v1, 1
2376; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2377; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
2378; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2379; GFX9-NEXT:    s_setpc_b64 s[30:31]
2380;
2381; GFX10-LABEL: v_fshl_i32:
2382; GFX10:       ; %bb.0:
2383; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2384; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2385; GFX10-NEXT:    v_alignbit_b32 v1, v0, v1, 1
2386; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2387; GFX10-NEXT:    v_xor_b32_e32 v2, -1, v2
2388; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, v2
2389; GFX10-NEXT:    s_setpc_b64 s[30:31]
2390  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
2391  ret i32 %result
2392}
2393
2394define i32 @v_fshl_i32_5(i32 %lhs, i32 %rhs) {
2395; GFX6-LABEL: v_fshl_i32_5:
2396; GFX6:       ; %bb.0:
2397; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2398; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, -5
2399; GFX6-NEXT:    s_setpc_b64 s[30:31]
2400;
2401; GFX8-LABEL: v_fshl_i32_5:
2402; GFX8:       ; %bb.0:
2403; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2404; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, -5
2405; GFX8-NEXT:    s_setpc_b64 s[30:31]
2406;
2407; GFX9-LABEL: v_fshl_i32_5:
2408; GFX9:       ; %bb.0:
2409; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2410; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, -5
2411; GFX9-NEXT:    s_setpc_b64 s[30:31]
2412;
2413; GFX10-LABEL: v_fshl_i32_5:
2414; GFX10:       ; %bb.0:
2415; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2416; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2417; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, -5
2418; GFX10-NEXT:    s_setpc_b64 s[30:31]
2419  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5)
2420  ret i32 %result
2421}
2422
2423define i32 @v_fshl_i32_8(i32 %lhs, i32 %rhs) {
2424; GFX6-LABEL: v_fshl_i32_8:
2425; GFX6:       ; %bb.0:
2426; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2427; GFX6-NEXT:    v_alignbit_b32 v0, v0, v1, -8
2428; GFX6-NEXT:    s_setpc_b64 s[30:31]
2429;
2430; GFX8-LABEL: v_fshl_i32_8:
2431; GFX8:       ; %bb.0:
2432; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2433; GFX8-NEXT:    v_alignbit_b32 v0, v0, v1, -8
2434; GFX8-NEXT:    s_setpc_b64 s[30:31]
2435;
2436; GFX9-LABEL: v_fshl_i32_8:
2437; GFX9:       ; %bb.0:
2438; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2439; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, -8
2440; GFX9-NEXT:    s_setpc_b64 s[30:31]
2441;
2442; GFX10-LABEL: v_fshl_i32_8:
2443; GFX10:       ; %bb.0:
2444; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2445; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2446; GFX10-NEXT:    v_alignbit_b32 v0, v0, v1, -8
2447; GFX10-NEXT:    s_setpc_b64 s[30:31]
2448  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8)
2449  ret i32 %result
2450}
2451
2452define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) {
2453; GFX6-LABEL: v_fshl_i32_ssv:
2454; GFX6:       ; %bb.0:
2455; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2456; GFX6-NEXT:    v_alignbit_b32 v1, s0, v1, 1
2457; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
2458; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
2459; GFX6-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2460; GFX6-NEXT:    ; return to shader part epilog
2461;
2462; GFX8-LABEL: v_fshl_i32_ssv:
2463; GFX8:       ; %bb.0:
2464; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2465; GFX8-NEXT:    v_alignbit_b32 v1, s0, v1, 1
2466; GFX8-NEXT:    s_lshr_b32 s0, s0, 1
2467; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
2468; GFX8-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2469; GFX8-NEXT:    ; return to shader part epilog
2470;
2471; GFX9-LABEL: v_fshl_i32_ssv:
2472; GFX9:       ; %bb.0:
2473; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2474; GFX9-NEXT:    v_alignbit_b32 v1, s0, v1, 1
2475; GFX9-NEXT:    s_lshr_b32 s0, s0, 1
2476; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
2477; GFX9-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2478; GFX9-NEXT:    ; return to shader part epilog
2479;
2480; GFX10-LABEL: v_fshl_i32_ssv:
2481; GFX10:       ; %bb.0:
2482; GFX10-NEXT:    v_alignbit_b32 v1, s0, s1, 1
2483; GFX10-NEXT:    v_xor_b32_e32 v0, -1, v0
2484; GFX10-NEXT:    s_lshr_b32 s0, s0, 1
2485; GFX10-NEXT:    v_alignbit_b32 v0, s0, v1, v0
2486; GFX10-NEXT:    ; return to shader part epilog
2487  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
2488  %cast.result = bitcast i32 %result to float
2489  ret float %cast.result
2490}
2491
2492define amdgpu_ps float @v_fshl_i32_svs(i32 inreg %lhs, i32 %rhs, i32 inreg %amt) {
2493; GFX6-LABEL: v_fshl_i32_svs:
2494; GFX6:       ; %bb.0:
2495; GFX6-NEXT:    s_not_b32 s1, s1
2496; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2497; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
2498; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2499; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2500; GFX6-NEXT:    ; return to shader part epilog
2501;
2502; GFX8-LABEL: v_fshl_i32_svs:
2503; GFX8:       ; %bb.0:
2504; GFX8-NEXT:    s_not_b32 s1, s1
2505; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2506; GFX8-NEXT:    s_lshr_b32 s0, s0, 1
2507; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2508; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2509; GFX8-NEXT:    ; return to shader part epilog
2510;
2511; GFX9-LABEL: v_fshl_i32_svs:
2512; GFX9:       ; %bb.0:
2513; GFX9-NEXT:    s_not_b32 s1, s1
2514; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2515; GFX9-NEXT:    s_lshr_b32 s0, s0, 1
2516; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2517; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2518; GFX9-NEXT:    ; return to shader part epilog
2519;
2520; GFX10-LABEL: v_fshl_i32_svs:
2521; GFX10:       ; %bb.0:
2522; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2523; GFX10-NEXT:    s_lshr_b32 s0, s0, 1
2524; GFX10-NEXT:    s_not_b32 s1, s1
2525; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
2526; GFX10-NEXT:    ; return to shader part epilog
2527  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
2528  %cast.result = bitcast i32 %result to float
2529  ret float %cast.result
2530}
2531
2532define amdgpu_ps float @v_fshl_i32_vss(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
2533; GFX6-LABEL: v_fshl_i32_vss:
2534; GFX6:       ; %bb.0:
2535; GFX6-NEXT:    v_mov_b32_e32 v0, s1
2536; GFX6-NEXT:    s_not_b32 s1, s2
2537; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2538; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
2539; GFX6-NEXT:    v_mov_b32_e32 v1, s1
2540; GFX6-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2541; GFX6-NEXT:    ; return to shader part epilog
2542;
2543; GFX8-LABEL: v_fshl_i32_vss:
2544; GFX8:       ; %bb.0:
2545; GFX8-NEXT:    v_mov_b32_e32 v0, s1
2546; GFX8-NEXT:    s_not_b32 s1, s2
2547; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2548; GFX8-NEXT:    s_lshr_b32 s0, s0, 1
2549; GFX8-NEXT:    v_mov_b32_e32 v1, s1
2550; GFX8-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2551; GFX8-NEXT:    ; return to shader part epilog
2552;
2553; GFX9-LABEL: v_fshl_i32_vss:
2554; GFX9:       ; %bb.0:
2555; GFX9-NEXT:    v_mov_b32_e32 v0, s1
2556; GFX9-NEXT:    s_not_b32 s1, s2
2557; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, 1
2558; GFX9-NEXT:    s_lshr_b32 s0, s0, 1
2559; GFX9-NEXT:    v_mov_b32_e32 v1, s1
2560; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
2561; GFX9-NEXT:    ; return to shader part epilog
2562;
2563; GFX10-LABEL: v_fshl_i32_vss:
2564; GFX10:       ; %bb.0:
2565; GFX10-NEXT:    v_alignbit_b32 v0, s0, s1, 1
2566; GFX10-NEXT:    s_lshr_b32 s0, s0, 1
2567; GFX10-NEXT:    s_not_b32 s1, s2
2568; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
2569; GFX10-NEXT:    ; return to shader part epilog
2570  %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
2571  %cast.result = bitcast i32 %result to float
2572  ret float %cast.result
2573}
2574
2575define <2 x i32> @v_fshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt) {
2576; GFX6-LABEL: v_fshl_v2i32:
2577; GFX6:       ; %bb.0:
2578; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2579; GFX6-NEXT:    v_alignbit_b32 v2, v0, v2, 1
2580; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2581; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
2582; GFX6-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2583; GFX6-NEXT:    v_alignbit_b32 v2, v1, v3, 1
2584; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2585; GFX6-NEXT:    v_xor_b32_e32 v3, -1, v5
2586; GFX6-NEXT:    v_alignbit_b32 v1, v1, v2, v3
2587; GFX6-NEXT:    s_setpc_b64 s[30:31]
2588;
2589; GFX8-LABEL: v_fshl_v2i32:
2590; GFX8:       ; %bb.0:
2591; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2592; GFX8-NEXT:    v_alignbit_b32 v2, v0, v2, 1
2593; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2594; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
2595; GFX8-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2596; GFX8-NEXT:    v_alignbit_b32 v2, v1, v3, 1
2597; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2598; GFX8-NEXT:    v_xor_b32_e32 v3, -1, v5
2599; GFX8-NEXT:    v_alignbit_b32 v1, v1, v2, v3
2600; GFX8-NEXT:    s_setpc_b64 s[30:31]
2601;
2602; GFX9-LABEL: v_fshl_v2i32:
2603; GFX9:       ; %bb.0:
2604; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2605; GFX9-NEXT:    v_alignbit_b32 v2, v0, v2, 1
2606; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2607; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
2608; GFX9-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2609; GFX9-NEXT:    v_alignbit_b32 v2, v1, v3, 1
2610; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2611; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v5
2612; GFX9-NEXT:    v_alignbit_b32 v1, v1, v2, v3
2613; GFX9-NEXT:    s_setpc_b64 s[30:31]
2614;
2615; GFX10-LABEL: v_fshl_v2i32:
2616; GFX10:       ; %bb.0:
2617; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2618; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2619; GFX10-NEXT:    v_alignbit_b32 v2, v0, v2, 1
2620; GFX10-NEXT:    v_alignbit_b32 v3, v1, v3, 1
2621; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2622; GFX10-NEXT:    v_xor_b32_e32 v4, -1, v4
2623; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2624; GFX10-NEXT:    v_xor_b32_e32 v5, -1, v5
2625; GFX10-NEXT:    v_alignbit_b32 v0, v0, v2, v4
2626; GFX10-NEXT:    v_alignbit_b32 v1, v1, v3, v5
2627; GFX10-NEXT:    s_setpc_b64 s[30:31]
2628  %result = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %lhs, <2 x i32> %rhs, <2 x i32> %amt)
2629  ret <2 x i32> %result
2630}
2631
2632define <3 x i32> @v_fshl_v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt) {
2633; GFX6-LABEL: v_fshl_v3i32:
2634; GFX6:       ; %bb.0:
2635; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2636; GFX6-NEXT:    v_alignbit_b32 v3, v0, v3, 1
2637; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2638; GFX6-NEXT:    v_xor_b32_e32 v6, -1, v6
2639; GFX6-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2640; GFX6-NEXT:    v_alignbit_b32 v3, v1, v4, 1
2641; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2642; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v7
2643; GFX6-NEXT:    v_alignbit_b32 v1, v1, v3, v4
2644; GFX6-NEXT:    v_alignbit_b32 v3, v2, v5, 1
2645; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2646; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v8
2647; GFX6-NEXT:    v_alignbit_b32 v2, v2, v3, v4
2648; GFX6-NEXT:    s_setpc_b64 s[30:31]
2649;
2650; GFX8-LABEL: v_fshl_v3i32:
2651; GFX8:       ; %bb.0:
2652; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2653; GFX8-NEXT:    v_alignbit_b32 v3, v0, v3, 1
2654; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2655; GFX8-NEXT:    v_xor_b32_e32 v6, -1, v6
2656; GFX8-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2657; GFX8-NEXT:    v_alignbit_b32 v3, v1, v4, 1
2658; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2659; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v7
2660; GFX8-NEXT:    v_alignbit_b32 v1, v1, v3, v4
2661; GFX8-NEXT:    v_alignbit_b32 v3, v2, v5, 1
2662; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2663; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v8
2664; GFX8-NEXT:    v_alignbit_b32 v2, v2, v3, v4
2665; GFX8-NEXT:    s_setpc_b64 s[30:31]
2666;
2667; GFX9-LABEL: v_fshl_v3i32:
2668; GFX9:       ; %bb.0:
2669; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2670; GFX9-NEXT:    v_alignbit_b32 v3, v0, v3, 1
2671; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2672; GFX9-NEXT:    v_xor_b32_e32 v6, -1, v6
2673; GFX9-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2674; GFX9-NEXT:    v_alignbit_b32 v3, v1, v4, 1
2675; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2676; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v7
2677; GFX9-NEXT:    v_alignbit_b32 v1, v1, v3, v4
2678; GFX9-NEXT:    v_alignbit_b32 v3, v2, v5, 1
2679; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2680; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v8
2681; GFX9-NEXT:    v_alignbit_b32 v2, v2, v3, v4
2682; GFX9-NEXT:    s_setpc_b64 s[30:31]
2683;
2684; GFX10-LABEL: v_fshl_v3i32:
2685; GFX10:       ; %bb.0:
2686; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2687; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2688; GFX10-NEXT:    v_alignbit_b32 v3, v0, v3, 1
2689; GFX10-NEXT:    v_alignbit_b32 v4, v1, v4, 1
2690; GFX10-NEXT:    v_alignbit_b32 v5, v2, v5, 1
2691; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2692; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v6
2693; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2694; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v7
2695; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2696; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v8
2697; GFX10-NEXT:    v_alignbit_b32 v0, v0, v3, v6
2698; GFX10-NEXT:    v_alignbit_b32 v1, v1, v4, v7
2699; GFX10-NEXT:    v_alignbit_b32 v2, v2, v5, v8
2700; GFX10-NEXT:    s_setpc_b64 s[30:31]
2701  %result = call <3 x i32> @llvm.fshl.v3i32(<3 x i32> %lhs, <3 x i32> %rhs, <3 x i32> %amt)
2702  ret <3 x i32> %result
2703}
2704
2705define <4 x i32> @v_fshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt) {
2706; GFX6-LABEL: v_fshl_v4i32:
2707; GFX6:       ; %bb.0:
2708; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2709; GFX6-NEXT:    v_alignbit_b32 v4, v0, v4, 1
2710; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2711; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
2712; GFX6-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2713; GFX6-NEXT:    v_alignbit_b32 v4, v1, v5, 1
2714; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2715; GFX6-NEXT:    v_xor_b32_e32 v5, -1, v9
2716; GFX6-NEXT:    v_alignbit_b32 v1, v1, v4, v5
2717; GFX6-NEXT:    v_alignbit_b32 v4, v2, v6, 1
2718; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2719; GFX6-NEXT:    v_xor_b32_e32 v5, -1, v10
2720; GFX6-NEXT:    v_alignbit_b32 v2, v2, v4, v5
2721; GFX6-NEXT:    v_alignbit_b32 v4, v3, v7, 1
2722; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
2723; GFX6-NEXT:    v_xor_b32_e32 v5, -1, v11
2724; GFX6-NEXT:    v_alignbit_b32 v3, v3, v4, v5
2725; GFX6-NEXT:    s_setpc_b64 s[30:31]
2726;
2727; GFX8-LABEL: v_fshl_v4i32:
2728; GFX8:       ; %bb.0:
2729; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2730; GFX8-NEXT:    v_alignbit_b32 v4, v0, v4, 1
2731; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2732; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
2733; GFX8-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2734; GFX8-NEXT:    v_alignbit_b32 v4, v1, v5, 1
2735; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2736; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v9
2737; GFX8-NEXT:    v_alignbit_b32 v1, v1, v4, v5
2738; GFX8-NEXT:    v_alignbit_b32 v4, v2, v6, 1
2739; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2740; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v10
2741; GFX8-NEXT:    v_alignbit_b32 v2, v2, v4, v5
2742; GFX8-NEXT:    v_alignbit_b32 v4, v3, v7, 1
2743; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
2744; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v11
2745; GFX8-NEXT:    v_alignbit_b32 v3, v3, v4, v5
2746; GFX8-NEXT:    s_setpc_b64 s[30:31]
2747;
2748; GFX9-LABEL: v_fshl_v4i32:
2749; GFX9:       ; %bb.0:
2750; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2751; GFX9-NEXT:    v_alignbit_b32 v4, v0, v4, 1
2752; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2753; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
2754; GFX9-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2755; GFX9-NEXT:    v_alignbit_b32 v4, v1, v5, 1
2756; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2757; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v9
2758; GFX9-NEXT:    v_alignbit_b32 v1, v1, v4, v5
2759; GFX9-NEXT:    v_alignbit_b32 v4, v2, v6, 1
2760; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2761; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v10
2762; GFX9-NEXT:    v_alignbit_b32 v2, v2, v4, v5
2763; GFX9-NEXT:    v_alignbit_b32 v4, v3, v7, 1
2764; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
2765; GFX9-NEXT:    v_xor_b32_e32 v5, -1, v11
2766; GFX9-NEXT:    v_alignbit_b32 v3, v3, v4, v5
2767; GFX9-NEXT:    s_setpc_b64 s[30:31]
2768;
2769; GFX10-LABEL: v_fshl_v4i32:
2770; GFX10:       ; %bb.0:
2771; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2772; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2773; GFX10-NEXT:    v_alignbit_b32 v4, v0, v4, 1
2774; GFX10-NEXT:    v_alignbit_b32 v5, v1, v5, 1
2775; GFX10-NEXT:    v_alignbit_b32 v6, v2, v6, 1
2776; GFX10-NEXT:    v_alignbit_b32 v7, v3, v7, 1
2777; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
2778; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v8
2779; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2780; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v9
2781; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
2782; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v10
2783; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
2784; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v11
2785; GFX10-NEXT:    v_alignbit_b32 v0, v0, v4, v8
2786; GFX10-NEXT:    v_alignbit_b32 v1, v1, v5, v9
2787; GFX10-NEXT:    v_alignbit_b32 v2, v2, v6, v10
2788; GFX10-NEXT:    v_alignbit_b32 v3, v3, v7, v11
2789; GFX10-NEXT:    s_setpc_b64 s[30:31]
2790  %result = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %lhs, <4 x i32> %rhs, <4 x i32> %amt)
2791  ret <4 x i32> %result
2792}
2793
2794define amdgpu_ps i16 @s_fshl_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt) {
2795; GFX6-LABEL: s_fshl_i16:
2796; GFX6:       ; %bb.0:
2797; GFX6-NEXT:    s_and_b32 s3, s2, 15
2798; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
2799; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2800; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
2801; GFX6-NEXT:    s_lshr_b32 s1, s1, 1
2802; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
2803; GFX6-NEXT:    s_lshl_b32 s0, s0, s3
2804; GFX6-NEXT:    s_lshr_b32 s1, s1, s2
2805; GFX6-NEXT:    s_or_b32 s0, s0, s1
2806; GFX6-NEXT:    ; return to shader part epilog
2807;
2808; GFX8-LABEL: s_fshl_i16:
2809; GFX8:       ; %bb.0:
2810; GFX8-NEXT:    s_and_b32 s3, s2, 15
2811; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
2812; GFX8-NEXT:    s_andn2_b32 s2, 15, s2
2813; GFX8-NEXT:    s_lshl_b32 s0, s0, s3
2814; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2815; GFX8-NEXT:    s_bfe_u32 s3, 1, 0x100000
2816; GFX8-NEXT:    s_lshr_b32 s1, s1, s3
2817; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
2818; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2819; GFX8-NEXT:    s_or_b32 s0, s0, s1
2820; GFX8-NEXT:    ; return to shader part epilog
2821;
2822; GFX9-LABEL: s_fshl_i16:
2823; GFX9:       ; %bb.0:
2824; GFX9-NEXT:    s_and_b32 s3, s2, 15
2825; GFX9-NEXT:    s_bfe_u32 s3, s3, 0x100000
2826; GFX9-NEXT:    s_andn2_b32 s2, 15, s2
2827; GFX9-NEXT:    s_lshl_b32 s0, s0, s3
2828; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2829; GFX9-NEXT:    s_bfe_u32 s3, 1, 0x100000
2830; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
2831; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
2832; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2833; GFX9-NEXT:    s_or_b32 s0, s0, s1
2834; GFX9-NEXT:    ; return to shader part epilog
2835;
2836; GFX10-LABEL: s_fshl_i16:
2837; GFX10:       ; %bb.0:
2838; GFX10-NEXT:    s_and_b32 s3, s2, 15
2839; GFX10-NEXT:    s_andn2_b32 s2, 15, s2
2840; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2841; GFX10-NEXT:    s_bfe_u32 s4, 1, 0x100000
2842; GFX10-NEXT:    s_bfe_u32 s3, s3, 0x100000
2843; GFX10-NEXT:    s_lshr_b32 s1, s1, s4
2844; GFX10-NEXT:    s_bfe_u32 s2, s2, 0x100000
2845; GFX10-NEXT:    s_lshl_b32 s0, s0, s3
2846; GFX10-NEXT:    s_lshr_b32 s1, s1, s2
2847; GFX10-NEXT:    s_or_b32 s0, s0, s1
2848; GFX10-NEXT:    ; return to shader part epilog
2849  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
2850  ret i16 %result
2851}
2852
2853define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
2854; GFX6-LABEL: s_fshl_i16_4:
2855; GFX6:       ; %bb.0:
2856; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2857; GFX6-NEXT:    s_lshl_b32 s0, s0, 4
2858; GFX6-NEXT:    s_lshr_b32 s1, s1, 12
2859; GFX6-NEXT:    s_or_b32 s0, s0, s1
2860; GFX6-NEXT:    ; return to shader part epilog
2861;
2862; GFX8-LABEL: s_fshl_i16_4:
2863; GFX8:       ; %bb.0:
2864; GFX8-NEXT:    s_bfe_u32 s2, 4, 0x100000
2865; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2866; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2867; GFX8-NEXT:    s_bfe_u32 s2, 12, 0x100000
2868; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2869; GFX8-NEXT:    s_or_b32 s0, s0, s1
2870; GFX8-NEXT:    ; return to shader part epilog
2871;
2872; GFX9-LABEL: s_fshl_i16_4:
2873; GFX9:       ; %bb.0:
2874; GFX9-NEXT:    s_bfe_u32 s2, 4, 0x100000
2875; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2876; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2877; GFX9-NEXT:    s_bfe_u32 s2, 12, 0x100000
2878; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2879; GFX9-NEXT:    s_or_b32 s0, s0, s1
2880; GFX9-NEXT:    ; return to shader part epilog
2881;
2882; GFX10-LABEL: s_fshl_i16_4:
2883; GFX10:       ; %bb.0:
2884; GFX10-NEXT:    s_bfe_u32 s2, 4, 0x100000
2885; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2886; GFX10-NEXT:    s_bfe_u32 s3, 12, 0x100000
2887; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2888; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2889; GFX10-NEXT:    s_or_b32 s0, s0, s1
2890; GFX10-NEXT:    ; return to shader part epilog
2891  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 4)
2892  ret i16 %result
2893}
2894
2895define amdgpu_ps i16 @s_fshl_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
2896; GFX6-LABEL: s_fshl_i16_5:
2897; GFX6:       ; %bb.0:
2898; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff
2899; GFX6-NEXT:    s_lshl_b32 s0, s0, 5
2900; GFX6-NEXT:    s_lshr_b32 s1, s1, 11
2901; GFX6-NEXT:    s_or_b32 s0, s0, s1
2902; GFX6-NEXT:    ; return to shader part epilog
2903;
2904; GFX8-LABEL: s_fshl_i16_5:
2905; GFX8:       ; %bb.0:
2906; GFX8-NEXT:    s_bfe_u32 s2, 5, 0x100000
2907; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
2908; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
2909; GFX8-NEXT:    s_bfe_u32 s2, 11, 0x100000
2910; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
2911; GFX8-NEXT:    s_or_b32 s0, s0, s1
2912; GFX8-NEXT:    ; return to shader part epilog
2913;
2914; GFX9-LABEL: s_fshl_i16_5:
2915; GFX9:       ; %bb.0:
2916; GFX9-NEXT:    s_bfe_u32 s2, 5, 0x100000
2917; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
2918; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
2919; GFX9-NEXT:    s_bfe_u32 s2, 11, 0x100000
2920; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
2921; GFX9-NEXT:    s_or_b32 s0, s0, s1
2922; GFX9-NEXT:    ; return to shader part epilog
2923;
2924; GFX10-LABEL: s_fshl_i16_5:
2925; GFX10:       ; %bb.0:
2926; GFX10-NEXT:    s_bfe_u32 s2, 5, 0x100000
2927; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
2928; GFX10-NEXT:    s_bfe_u32 s3, 11, 0x100000
2929; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
2930; GFX10-NEXT:    s_lshr_b32 s1, s1, s3
2931; GFX10-NEXT:    s_or_b32 s0, s0, s1
2932; GFX10-NEXT:    ; return to shader part epilog
2933  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 5)
2934  ret i16 %result
2935}
2936
2937define i16 @v_fshl_i16(i16 %lhs, i16 %rhs, i16 %amt) {
2938; GFX6-LABEL: v_fshl_i16:
2939; GFX6:       ; %bb.0:
2940; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2941; GFX6-NEXT:    v_and_b32_e32 v3, 15, v2
2942; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
2943; GFX6-NEXT:    v_and_b32_e32 v2, 15, v2
2944; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2945; GFX6-NEXT:    v_bfe_u32 v3, v3, 0, 16
2946; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
2947; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
2948; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v3, v0
2949; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v2, v1
2950; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
2951; GFX6-NEXT:    s_setpc_b64 s[30:31]
2952;
2953; GFX8-LABEL: v_fshl_i16:
2954; GFX8:       ; %bb.0:
2955; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2956; GFX8-NEXT:    v_and_b32_e32 v3, 15, v2
2957; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
2958; GFX8-NEXT:    v_and_b32_e32 v2, 15, v2
2959; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 1, v1
2960; GFX8-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
2961; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
2962; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
2963; GFX8-NEXT:    s_setpc_b64 s[30:31]
2964;
2965; GFX9-LABEL: v_fshl_i16:
2966; GFX9:       ; %bb.0:
2967; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2968; GFX9-NEXT:    v_and_b32_e32 v3, 15, v2
2969; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
2970; GFX9-NEXT:    v_and_b32_e32 v2, 15, v2
2971; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 1, v1
2972; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
2973; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
2974; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
2975; GFX9-NEXT:    s_setpc_b64 s[30:31]
2976;
2977; GFX10-LABEL: v_fshl_i16:
2978; GFX10:       ; %bb.0:
2979; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2980; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2981; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
2982; GFX10-NEXT:    v_and_b32_e32 v2, 15, v2
2983; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
2984; GFX10-NEXT:    v_and_b32_e32 v3, 15, v3
2985; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
2986; GFX10-NEXT:    v_lshrrev_b16 v1, v3, v1
2987; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
2988; GFX10-NEXT:    s_setpc_b64 s[30:31]
2989  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
2990  ret i16 %result
2991}
2992
2993define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) {
2994; GFX6-LABEL: v_fshl_i16_4:
2995; GFX6:       ; %bb.0:
2996; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2997; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
2998; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
2999; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 12, v1
3000; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3001; GFX6-NEXT:    s_setpc_b64 s[30:31]
3002;
3003; GFX8-LABEL: v_fshl_i16_4:
3004; GFX8:       ; %bb.0:
3005; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3006; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
3007; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 12, v1
3008; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
3009; GFX8-NEXT:    s_setpc_b64 s[30:31]
3010;
3011; GFX9-LABEL: v_fshl_i16_4:
3012; GFX9:       ; %bb.0:
3013; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3014; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
3015; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 12, v1
3016; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3017; GFX9-NEXT:    s_setpc_b64 s[30:31]
3018;
3019; GFX10-LABEL: v_fshl_i16_4:
3020; GFX10:       ; %bb.0:
3021; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3022; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3023; GFX10-NEXT:    v_lshlrev_b16 v0, 4, v0
3024; GFX10-NEXT:    v_lshrrev_b16 v1, 12, v1
3025; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3026; GFX10-NEXT:    s_setpc_b64 s[30:31]
3027  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 4)
3028  ret i16 %result
3029}
3030
3031define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) {
3032; GFX6-LABEL: v_fshl_i16_5:
3033; GFX6:       ; %bb.0:
3034; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3035; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
3036; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 5, v0
3037; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 11, v1
3038; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3039; GFX6-NEXT:    s_setpc_b64 s[30:31]
3040;
3041; GFX8-LABEL: v_fshl_i16_5:
3042; GFX8:       ; %bb.0:
3043; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3044; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 5, v0
3045; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 11, v1
3046; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
3047; GFX8-NEXT:    s_setpc_b64 s[30:31]
3048;
3049; GFX9-LABEL: v_fshl_i16_5:
3050; GFX9:       ; %bb.0:
3051; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3052; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 5, v0
3053; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 11, v1
3054; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3055; GFX9-NEXT:    s_setpc_b64 s[30:31]
3056;
3057; GFX10-LABEL: v_fshl_i16_5:
3058; GFX10:       ; %bb.0:
3059; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3060; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3061; GFX10-NEXT:    v_lshlrev_b16 v0, 5, v0
3062; GFX10-NEXT:    v_lshrrev_b16 v1, 11, v1
3063; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3064; GFX10-NEXT:    s_setpc_b64 s[30:31]
3065  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 5)
3066  ret i16 %result
3067}
3068
3069define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt) {
3070; GFX6-LABEL: v_fshl_i16_ssv:
3071; GFX6:       ; %bb.0:
3072; GFX6-NEXT:    v_and_b32_e32 v1, 15, v0
3073; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
3074; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3075; GFX6-NEXT:    v_and_b32_e32 v0, 15, v0
3076; GFX6-NEXT:    v_lshl_b32_e32 v1, s0, v1
3077; GFX6-NEXT:    s_and_b32 s0, s1, 0xffff
3078; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3079; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3080; GFX6-NEXT:    v_lshr_b32_e32 v0, s0, v0
3081; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
3082; GFX6-NEXT:    ; return to shader part epilog
3083;
3084; GFX8-LABEL: v_fshl_i16_ssv:
3085; GFX8:       ; %bb.0:
3086; GFX8-NEXT:    v_and_b32_e32 v1, 15, v0
3087; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
3088; GFX8-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
3089; GFX8-NEXT:    s_bfe_u32 s0, s1, 0x100000
3090; GFX8-NEXT:    s_bfe_u32 s1, 1, 0x100000
3091; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
3092; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3093; GFX8-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
3094; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
3095; GFX8-NEXT:    ; return to shader part epilog
3096;
3097; GFX9-LABEL: v_fshl_i16_ssv:
3098; GFX9:       ; %bb.0:
3099; GFX9-NEXT:    v_and_b32_e32 v1, 15, v0
3100; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
3101; GFX9-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
3102; GFX9-NEXT:    s_bfe_u32 s0, s1, 0x100000
3103; GFX9-NEXT:    s_bfe_u32 s1, 1, 0x100000
3104; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
3105; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
3106; GFX9-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
3107; GFX9-NEXT:    v_or_b32_e32 v0, v1, v0
3108; GFX9-NEXT:    ; return to shader part epilog
3109;
3110; GFX10-LABEL: v_fshl_i16_ssv:
3111; GFX10:       ; %bb.0:
3112; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
3113; GFX10-NEXT:    v_and_b32_e32 v0, 15, v0
3114; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
3115; GFX10-NEXT:    s_bfe_u32 s2, 1, 0x100000
3116; GFX10-NEXT:    v_and_b32_e32 v1, 15, v1
3117; GFX10-NEXT:    s_lshr_b32 s1, s1, s2
3118; GFX10-NEXT:    v_lshlrev_b16 v0, v0, s0
3119; GFX10-NEXT:    v_lshrrev_b16 v1, v1, s1
3120; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3121; GFX10-NEXT:    ; return to shader part epilog
3122  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
3123  %cast.result = bitcast i16 %result to half
3124  ret half %cast.result
3125}
3126
3127define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt) {
3128; GFX6-LABEL: v_fshl_i16_svs:
3129; GFX6:       ; %bb.0:
3130; GFX6-NEXT:    s_and_b32 s2, s1, 15
3131; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3132; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
3133; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3134; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 1, v0
3135; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3136; GFX6-NEXT:    s_lshl_b32 s0, s0, s2
3137; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s1, v0
3138; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
3139; GFX6-NEXT:    ; return to shader part epilog
3140;
3141; GFX8-LABEL: v_fshl_i16_svs:
3142; GFX8:       ; %bb.0:
3143; GFX8-NEXT:    s_and_b32 s2, s1, 15
3144; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3145; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3146; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 1, v0
3147; GFX8-NEXT:    s_lshl_b32 s0, s0, s2
3148; GFX8-NEXT:    v_lshrrev_b16_e32 v0, s1, v0
3149; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3150; GFX8-NEXT:    ; return to shader part epilog
3151;
3152; GFX9-LABEL: v_fshl_i16_svs:
3153; GFX9:       ; %bb.0:
3154; GFX9-NEXT:    s_and_b32 s2, s1, 15
3155; GFX9-NEXT:    s_bfe_u32 s2, s2, 0x100000
3156; GFX9-NEXT:    s_andn2_b32 s1, 15, s1
3157; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 1, v0
3158; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
3159; GFX9-NEXT:    v_lshrrev_b16_e32 v0, s1, v0
3160; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3161; GFX9-NEXT:    ; return to shader part epilog
3162;
3163; GFX10-LABEL: v_fshl_i16_svs:
3164; GFX10:       ; %bb.0:
3165; GFX10-NEXT:    v_lshrrev_b16 v0, 1, v0
3166; GFX10-NEXT:    s_andn2_b32 s2, 15, s1
3167; GFX10-NEXT:    s_and_b32 s1, s1, 15
3168; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
3169; GFX10-NEXT:    v_lshrrev_b16 v0, s2, v0
3170; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
3171; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3172; GFX10-NEXT:    ; return to shader part epilog
3173  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
3174  %cast.result = bitcast i16 %result to half
3175  ret half %cast.result
3176}
3177
3178define amdgpu_ps half @v_fshl_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt) {
3179; GFX6-LABEL: v_fshl_i16_vss:
3180; GFX6:       ; %bb.0:
3181; GFX6-NEXT:    s_and_b32 s2, s1, 15
3182; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3183; GFX6-NEXT:    s_and_b32 s0, s0, 0xffff
3184; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3185; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3186; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3187; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
3188; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
3189; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
3190; GFX6-NEXT:    ; return to shader part epilog
3191;
3192; GFX8-LABEL: v_fshl_i16_vss:
3193; GFX8:       ; %bb.0:
3194; GFX8-NEXT:    s_and_b32 s2, s1, 15
3195; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3196; GFX8-NEXT:    v_lshlrev_b16_e32 v0, s2, v0
3197; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3198; GFX8-NEXT:    s_bfe_u32 s2, 1, 0x100000
3199; GFX8-NEXT:    s_lshr_b32 s0, s0, s2
3200; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3201; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3202; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3203; GFX8-NEXT:    ; return to shader part epilog
3204;
3205; GFX9-LABEL: v_fshl_i16_vss:
3206; GFX9:       ; %bb.0:
3207; GFX9-NEXT:    s_and_b32 s2, s1, 15
3208; GFX9-NEXT:    s_andn2_b32 s1, 15, s1
3209; GFX9-NEXT:    v_lshlrev_b16_e32 v0, s2, v0
3210; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
3211; GFX9-NEXT:    s_bfe_u32 s2, 1, 0x100000
3212; GFX9-NEXT:    s_lshr_b32 s0, s0, s2
3213; GFX9-NEXT:    s_bfe_u32 s1, s1, 0x100000
3214; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
3215; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3216; GFX9-NEXT:    ; return to shader part epilog
3217;
3218; GFX10-LABEL: v_fshl_i16_vss:
3219; GFX10:       ; %bb.0:
3220; GFX10-NEXT:    s_and_b32 s2, s1, 15
3221; GFX10-NEXT:    s_andn2_b32 s1, 15, s1
3222; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
3223; GFX10-NEXT:    s_bfe_u32 s3, 1, 0x100000
3224; GFX10-NEXT:    v_lshlrev_b16 v0, s2, v0
3225; GFX10-NEXT:    s_lshr_b32 s0, s0, s3
3226; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
3227; GFX10-NEXT:    s_lshr_b32 s0, s0, s1
3228; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3229; GFX10-NEXT:    ; return to shader part epilog
3230  %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
3231  %cast.result = bitcast i16 %result to half
3232  ret half %cast.result
3233}
3234
3235define amdgpu_ps i32 @s_fshl_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
3236; GFX6-LABEL: s_fshl_v2i16:
3237; GFX6:       ; %bb.0:
3238; GFX6-NEXT:    s_and_b32 s5, s2, 15
3239; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
3240; GFX6-NEXT:    s_lshr_b32 s3, s0, 16
3241; GFX6-NEXT:    s_lshr_b32 s4, s2, 16
3242; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
3243; GFX6-NEXT:    s_lshl_b32 s0, s0, s5
3244; GFX6-NEXT:    s_and_b32 s5, s1, 0xffff
3245; GFX6-NEXT:    s_lshr_b32 s5, s5, 1
3246; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3247; GFX6-NEXT:    s_lshr_b32 s2, s5, s2
3248; GFX6-NEXT:    s_or_b32 s0, s0, s2
3249; GFX6-NEXT:    s_and_b32 s2, s4, 15
3250; GFX6-NEXT:    s_bfe_u32 s2, s2, 0x100000
3251; GFX6-NEXT:    s_andn2_b32 s4, 15, s4
3252; GFX6-NEXT:    s_lshl_b32 s2, s3, s2
3253; GFX6-NEXT:    s_lshr_b32 s1, s1, 17
3254; GFX6-NEXT:    s_bfe_u32 s3, s4, 0x100000
3255; GFX6-NEXT:    s_lshr_b32 s1, s1, s3
3256; GFX6-NEXT:    s_or_b32 s1, s2, s1
3257; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3258; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3259; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
3260; GFX6-NEXT:    s_or_b32 s0, s0, s1
3261; GFX6-NEXT:    ; return to shader part epilog
3262;
3263; GFX8-LABEL: s_fshl_v2i16:
3264; GFX8:       ; %bb.0:
3265; GFX8-NEXT:    s_and_b32 s6, s2, 15
3266; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
3267; GFX8-NEXT:    s_lshr_b32 s3, s0, 16
3268; GFX8-NEXT:    s_lshr_b32 s4, s1, 16
3269; GFX8-NEXT:    s_lshr_b32 s5, s2, 16
3270; GFX8-NEXT:    s_andn2_b32 s2, 15, s2
3271; GFX8-NEXT:    s_lshl_b32 s0, s0, s6
3272; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3273; GFX8-NEXT:    s_bfe_u32 s6, 1, 0x100000
3274; GFX8-NEXT:    s_lshr_b32 s1, s1, s6
3275; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3276; GFX8-NEXT:    s_lshr_b32 s1, s1, s2
3277; GFX8-NEXT:    s_or_b32 s0, s0, s1
3278; GFX8-NEXT:    s_and_b32 s1, s5, 15
3279; GFX8-NEXT:    s_andn2_b32 s2, 15, s5
3280; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3281; GFX8-NEXT:    s_lshl_b32 s1, s3, s1
3282; GFX8-NEXT:    s_lshr_b32 s3, s4, s6
3283; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3284; GFX8-NEXT:    s_lshr_b32 s2, s3, s2
3285; GFX8-NEXT:    s_or_b32 s1, s1, s2
3286; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3287; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3288; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
3289; GFX8-NEXT:    s_or_b32 s0, s0, s1
3290; GFX8-NEXT:    ; return to shader part epilog
3291;
3292; GFX9-LABEL: s_fshl_v2i16:
3293; GFX9:       ; %bb.0:
3294; GFX9-NEXT:    s_mov_b32 s3, 0xf000f
3295; GFX9-NEXT:    s_and_b32 s4, s2, s3
3296; GFX9-NEXT:    s_andn2_b32 s2, s3, s2
3297; GFX9-NEXT:    s_lshr_b32 s3, s0, 16
3298; GFX9-NEXT:    s_lshr_b32 s5, s4, 16
3299; GFX9-NEXT:    s_lshl_b32 s0, s0, s4
3300; GFX9-NEXT:    s_lshl_b32 s3, s3, s5
3301; GFX9-NEXT:    s_mov_b32 s4, 0xffff
3302; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
3303; GFX9-NEXT:    s_lshr_b32 s3, s1, 16
3304; GFX9-NEXT:    s_and_b32 s1, s1, s4
3305; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
3306; GFX9-NEXT:    s_lshr_b32 s3, s3, 1
3307; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s3
3308; GFX9-NEXT:    s_lshr_b32 s3, s1, 16
3309; GFX9-NEXT:    s_lshr_b32 s5, s2, 16
3310; GFX9-NEXT:    s_and_b32 s1, s1, s4
3311; GFX9-NEXT:    s_and_b32 s2, s2, s4
3312; GFX9-NEXT:    s_lshr_b32 s1, s1, s2
3313; GFX9-NEXT:    s_lshr_b32 s2, s3, s5
3314; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
3315; GFX9-NEXT:    s_or_b32 s0, s0, s1
3316; GFX9-NEXT:    ; return to shader part epilog
3317;
3318; GFX10-LABEL: s_fshl_v2i16:
3319; GFX10:       ; %bb.0:
3320; GFX10-NEXT:    s_mov_b32 s5, 0xffff
3321; GFX10-NEXT:    s_mov_b32 s3, 0xf000f
3322; GFX10-NEXT:    s_and_b32 s7, s1, s5
3323; GFX10-NEXT:    s_lshr_b32 s1, s1, 16
3324; GFX10-NEXT:    s_lshr_b32 s7, s7, 1
3325; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
3326; GFX10-NEXT:    s_and_b32 s4, s2, s3
3327; GFX10-NEXT:    s_andn2_b32 s2, s3, s2
3328; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s7, s1
3329; GFX10-NEXT:    s_lshr_b32 s3, s0, 16
3330; GFX10-NEXT:    s_lshr_b32 s6, s4, 16
3331; GFX10-NEXT:    s_lshl_b32 s0, s0, s4
3332; GFX10-NEXT:    s_lshr_b32 s4, s1, 16
3333; GFX10-NEXT:    s_and_b32 s1, s1, s5
3334; GFX10-NEXT:    s_and_b32 s5, s2, s5
3335; GFX10-NEXT:    s_lshr_b32 s2, s2, 16
3336; GFX10-NEXT:    s_lshl_b32 s3, s3, s6
3337; GFX10-NEXT:    s_lshr_b32 s1, s1, s5
3338; GFX10-NEXT:    s_lshr_b32 s2, s4, s2
3339; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s3
3340; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
3341; GFX10-NEXT:    s_or_b32 s0, s0, s1
3342; GFX10-NEXT:    ; return to shader part epilog
3343  %result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3344  %cast = bitcast <2 x i16> %result to i32
3345  ret i32 %cast
3346}
3347
3348define <2 x i16> @v_fshl_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
3349; GFX6-LABEL: v_fshl_v2i16:
3350; GFX6:       ; %bb.0:
3351; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3352; GFX6-NEXT:    v_and_b32_e32 v5, 15, v2
3353; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
3354; GFX6-NEXT:    v_xor_b32_e32 v2, -1, v2
3355; GFX6-NEXT:    v_bfe_u32 v5, v5, 0, 16
3356; GFX6-NEXT:    v_and_b32_e32 v2, 15, v2
3357; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
3358; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v5, v0
3359; GFX6-NEXT:    v_and_b32_e32 v5, 0xffff, v1
3360; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 1, v5
3361; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3362; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v5
3363; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
3364; GFX6-NEXT:    v_and_b32_e32 v2, 15, v4
3365; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
3366; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3367; GFX6-NEXT:    v_and_b32_e32 v4, 15, v4
3368; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v2, v3
3369; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 17, v1
3370; GFX6-NEXT:    v_bfe_u32 v3, v4, 0, 16
3371; GFX6-NEXT:    v_lshrrev_b32_e32 v1, v3, v1
3372; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3373; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3374; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3375; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3376; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3377; GFX6-NEXT:    s_setpc_b64 s[30:31]
3378;
3379; GFX8-LABEL: v_fshl_v2i16:
3380; GFX8:       ; %bb.0:
3381; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3382; GFX8-NEXT:    v_and_b32_e32 v4, 15, v2
3383; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
3384; GFX8-NEXT:    v_xor_b32_e32 v2, -1, v2
3385; GFX8-NEXT:    v_and_b32_e32 v2, 15, v2
3386; GFX8-NEXT:    v_lshrrev_b16_e32 v5, 1, v1
3387; GFX8-NEXT:    v_lshlrev_b16_e32 v4, v4, v0
3388; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v2, v5
3389; GFX8-NEXT:    v_or_b32_e32 v2, v4, v2
3390; GFX8-NEXT:    v_and_b32_e32 v4, 15, v3
3391; GFX8-NEXT:    v_xor_b32_e32 v3, -1, v3
3392; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3393; GFX8-NEXT:    v_mov_b32_e32 v4, 1
3394; GFX8-NEXT:    v_and_b32_e32 v3, 15, v3
3395; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3396; GFX8-NEXT:    v_lshrrev_b16_e32 v1, v3, v1
3397; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
3398; GFX8-NEXT:    v_mov_b32_e32 v1, 16
3399; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3400; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3401; GFX8-NEXT:    s_setpc_b64 s[30:31]
3402;
3403; GFX9-LABEL: v_fshl_v2i16:
3404; GFX9:       ; %bb.0:
3405; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3406; GFX9-NEXT:    s_mov_b32 s4, 0xf000f
3407; GFX9-NEXT:    v_and_b32_e32 v3, s4, v2
3408; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
3409; GFX9-NEXT:    v_and_b32_e32 v2, s4, v2
3410; GFX9-NEXT:    v_pk_lshrrev_b16 v1, 1, v1 op_sel_hi:[0,1]
3411; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v3, v0
3412; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
3413; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3414; GFX9-NEXT:    s_setpc_b64 s[30:31]
3415;
3416; GFX10-LABEL: v_fshl_v2i16:
3417; GFX10:       ; %bb.0:
3418; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3419; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3420; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
3421; GFX10-NEXT:    s_mov_b32 s4, 0xf000f
3422; GFX10-NEXT:    v_pk_lshrrev_b16 v1, 1, v1 op_sel_hi:[0,1]
3423; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
3424; GFX10-NEXT:    v_and_b32_e32 v3, s4, v3
3425; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
3426; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v3, v1
3427; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3428; GFX10-NEXT:    s_setpc_b64 s[30:31]
3429  %result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3430  ret <2 x i16> %result
3431}
3432
3433define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
3434; GFX6-LABEL: v_fshl_v2i16_4_8:
3435; GFX6:       ; %bb.0:
3436; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3437; GFX6-NEXT:    v_and_b32_e32 v3, 0xffff, v1
3438; GFX6-NEXT:    s_bfe_u32 s4, 4, 0x100000
3439; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
3440; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s4, v0
3441; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
3442; GFX6-NEXT:    s_bfe_u32 s4, 11, 0x100000
3443; GFX6-NEXT:    v_lshrrev_b32_e32 v3, s4, v3
3444; GFX6-NEXT:    s_bfe_u32 s4, 8, 0x100000
3445; GFX6-NEXT:    v_lshlrev_b32_e32 v2, s4, v2
3446; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 17, v1
3447; GFX6-NEXT:    s_bfe_u32 s4, 7, 0x100000
3448; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s4, v1
3449; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3450; GFX6-NEXT:    v_or_b32_e32 v0, v0, v3
3451; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3452; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3453; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3454; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3455; GFX6-NEXT:    s_setpc_b64 s[30:31]
3456;
3457; GFX8-LABEL: v_fshl_v2i16_4_8:
3458; GFX8:       ; %bb.0:
3459; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3460; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 1, v1
3461; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
3462; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 4, v0
3463; GFX8-NEXT:    v_lshrrev_b16_e32 v3, 11, v3
3464; GFX8-NEXT:    v_or_b32_e32 v0, v0, v3
3465; GFX8-NEXT:    v_mov_b32_e32 v3, 1
3466; GFX8-NEXT:    v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3467; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 8, v2
3468; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 7, v1
3469; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
3470; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3471; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3472; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3473; GFX8-NEXT:    s_setpc_b64 s[30:31]
3474;
3475; GFX9-LABEL: v_fshl_v2i16_4_8:
3476; GFX9:       ; %bb.0:
3477; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3478; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, 16
3479; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v2
3480; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, 16
3481; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v3
3482; GFX9-NEXT:    s_sub_i32 s4, 0, 16
3483; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
3484; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
3485; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
3486; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
3487; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v2
3488; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v3
3489; GFX9-NEXT:    v_mul_hi_u32 v4, v2, v4
3490; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v5
3491; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
3492; GFX9-NEXT:    v_mul_hi_u32 v2, 4, v2
3493; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
3494; GFX9-NEXT:    v_mul_hi_u32 v3, 8, v3
3495; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
3496; GFX9-NEXT:    v_sub_u32_e32 v2, 4, v2
3497; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v2
3498; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v2
3499; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3500; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 4, v3
3501; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v2
3502; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v2
3503; GFX9-NEXT:    v_sub_u32_e32 v3, 8, v3
3504; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
3505; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v3
3506; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v3
3507; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3508; GFX9-NEXT:    v_subrev_u32_e32 v4, 16, v3
3509; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, 16, v3
3510; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
3511; GFX9-NEXT:    v_mov_b32_e32 v4, 0xffff
3512; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
3513; GFX9-NEXT:    v_and_or_b32 v2, v2, v4, v3
3514; GFX9-NEXT:    v_pk_sub_i16 v3, 16, v2 op_sel_hi:[0,1]
3515; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
3516; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v3, v1
3517; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
3518; GFX9-NEXT:    s_setpc_b64 s[30:31]
3519;
3520; GFX10-LABEL: v_fshl_v2i16_4_8:
3521; GFX10:       ; %bb.0:
3522; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3523; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
3524; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v2, 16
3525; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 16
3526; GFX10-NEXT:    s_sub_i32 s4, 0, 16
3527; GFX10-NEXT:    v_rcp_iflag_f32_e32 v2, v2
3528; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
3529; GFX10-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2
3530; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
3531; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
3532; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
3533; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v2
3534; GFX10-NEXT:    v_mul_lo_u32 v5, s4, v3
3535; GFX10-NEXT:    v_mul_hi_u32 v4, v2, v4
3536; GFX10-NEXT:    v_mul_hi_u32 v5, v3, v5
3537; GFX10-NEXT:    v_add_nc_u32_e32 v2, v2, v4
3538; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v5
3539; GFX10-NEXT:    v_mul_hi_u32 v2, 8, v2
3540; GFX10-NEXT:    v_mul_hi_u32 v3, 4, v3
3541; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 4, v2
3542; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 4, v3
3543; GFX10-NEXT:    v_sub_nc_u32_e32 v2, 8, v2
3544; GFX10-NEXT:    v_sub_nc_u32_e32 v3, 4, v3
3545; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 16, v2
3546; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v2
3547; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, 16, v3
3548; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
3549; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v3
3550; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, 16, v2
3551; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
3552; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v2
3553; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, 16, v3
3554; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
3555; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 16, v3
3556; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
3557; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
3558; GFX10-NEXT:    v_and_or_b32 v2, 0xffff, v3, v2
3559; GFX10-NEXT:    v_pk_sub_i16 v3, 16, v2 op_sel_hi:[0,1]
3560; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
3561; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v3, v1
3562; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3563; GFX10-NEXT:    s_setpc_b64 s[30:31]
3564  %result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> <i16 4, i16 8>)
3565  ret <2 x i16> %result
3566}
3567
3568define amdgpu_ps float @v_fshl_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> %amt) {
3569; GFX6-LABEL: v_fshl_v2i16_ssv:
3570; GFX6:       ; %bb.0:
3571; GFX6-NEXT:    v_and_b32_e32 v2, 15, v0
3572; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3573; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3574; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
3575; GFX6-NEXT:    v_and_b32_e32 v0, 15, v0
3576; GFX6-NEXT:    s_lshr_b32 s2, s0, 16
3577; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
3578; GFX6-NEXT:    s_and_b32 s0, s1, 0xffff
3579; GFX6-NEXT:    s_lshr_b32 s0, s0, 1
3580; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3581; GFX6-NEXT:    v_lshr_b32_e32 v0, s0, v0
3582; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
3583; GFX6-NEXT:    v_and_b32_e32 v2, 15, v1
3584; GFX6-NEXT:    v_xor_b32_e32 v1, -1, v1
3585; GFX6-NEXT:    v_and_b32_e32 v1, 15, v1
3586; GFX6-NEXT:    v_bfe_u32 v2, v2, 0, 16
3587; GFX6-NEXT:    s_lshr_b32 s0, s1, 17
3588; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3589; GFX6-NEXT:    v_lshl_b32_e32 v2, s2, v2
3590; GFX6-NEXT:    v_lshr_b32_e32 v1, s0, v1
3591; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
3592; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3593; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3594; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3595; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3596; GFX6-NEXT:    ; return to shader part epilog
3597;
3598; GFX8-LABEL: v_fshl_v2i16_ssv:
3599; GFX8:       ; %bb.0:
3600; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
3601; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3602; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
3603; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3604; GFX8-NEXT:    v_lshlrev_b16_e64 v2, v2, s0
3605; GFX8-NEXT:    s_lshr_b32 s3, s1, 16
3606; GFX8-NEXT:    s_bfe_u32 s0, s1, 0x100000
3607; GFX8-NEXT:    s_bfe_u32 s1, 1, 0x100000
3608; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
3609; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3610; GFX8-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
3611; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
3612; GFX8-NEXT:    v_and_b32_e32 v2, 15, v1
3613; GFX8-NEXT:    v_xor_b32_e32 v1, -1, v1
3614; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
3615; GFX8-NEXT:    s_lshr_b32 s0, s3, s1
3616; GFX8-NEXT:    v_lshlrev_b16_e64 v2, v2, s2
3617; GFX8-NEXT:    v_lshrrev_b16_e64 v1, v1, s0
3618; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
3619; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3620; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3621; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3622; GFX8-NEXT:    ; return to shader part epilog
3623;
3624; GFX9-LABEL: v_fshl_v2i16_ssv:
3625; GFX9:       ; %bb.0:
3626; GFX9-NEXT:    s_mov_b32 s2, 0xf000f
3627; GFX9-NEXT:    v_and_b32_e32 v1, s2, v0
3628; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v1, s0
3629; GFX9-NEXT:    s_lshr_b32 s0, s1, 16
3630; GFX9-NEXT:    s_and_b32 s1, s1, 0xffff
3631; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
3632; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
3633; GFX9-NEXT:    s_lshr_b32 s0, s0, 1
3634; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
3635; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s1, s0
3636; GFX9-NEXT:    v_pk_lshrrev_b16 v0, v0, s0
3637; GFX9-NEXT:    v_or_b32_e32 v0, v1, v0
3638; GFX9-NEXT:    ; return to shader part epilog
3639;
3640; GFX10-LABEL: v_fshl_v2i16_ssv:
3641; GFX10:       ; %bb.0:
3642; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
3643; GFX10-NEXT:    s_mov_b32 s2, 0xf000f
3644; GFX10-NEXT:    s_lshr_b32 s3, s1, 16
3645; GFX10-NEXT:    s_and_b32 s1, s1, 0xffff
3646; GFX10-NEXT:    v_and_b32_e32 v0, s2, v0
3647; GFX10-NEXT:    v_and_b32_e32 v1, s2, v1
3648; GFX10-NEXT:    s_lshr_b32 s1, s1, 1
3649; GFX10-NEXT:    s_lshr_b32 s2, s3, 1
3650; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
3651; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v0, s0
3652; GFX10-NEXT:    v_pk_lshrrev_b16 v1, v1, s1
3653; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
3654; GFX10-NEXT:    ; return to shader part epilog
3655  %result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3656  %cast = bitcast <2 x i16> %result to float
3657  ret float %cast
3658}
3659
3660define amdgpu_ps float @v_fshl_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <2 x i16> inreg %amt) {
3661; GFX6-LABEL: v_fshl_v2i16_svs:
3662; GFX6:       ; %bb.0:
3663; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v0
3664; GFX6-NEXT:    s_and_b32 s4, s1, 15
3665; GFX6-NEXT:    s_lshr_b32 s3, s1, 16
3666; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3667; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3668; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
3669; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3670; GFX6-NEXT:    s_lshr_b32 s2, s0, 16
3671; GFX6-NEXT:    v_lshrrev_b32_e32 v1, s1, v1
3672; GFX6-NEXT:    s_lshl_b32 s0, s0, s4
3673; GFX6-NEXT:    v_or_b32_e32 v1, s0, v1
3674; GFX6-NEXT:    s_and_b32 s0, s3, 15
3675; GFX6-NEXT:    s_andn2_b32 s1, 15, s3
3676; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3677; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 17, v0
3678; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3679; GFX6-NEXT:    s_lshl_b32 s0, s2, s0
3680; GFX6-NEXT:    v_lshrrev_b32_e32 v0, s1, v0
3681; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
3682; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3683; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3684; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
3685; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
3686; GFX6-NEXT:    ; return to shader part epilog
3687;
3688; GFX8-LABEL: v_fshl_v2i16_svs:
3689; GFX8:       ; %bb.0:
3690; GFX8-NEXT:    s_and_b32 s4, s1, 15
3691; GFX8-NEXT:    s_lshr_b32 s3, s1, 16
3692; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3693; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 1, v0
3694; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3695; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3696; GFX8-NEXT:    v_lshrrev_b16_e32 v1, s1, v1
3697; GFX8-NEXT:    s_lshl_b32 s0, s0, s4
3698; GFX8-NEXT:    v_or_b32_e32 v1, s0, v1
3699; GFX8-NEXT:    s_and_b32 s0, s3, 15
3700; GFX8-NEXT:    v_mov_b32_e32 v2, 1
3701; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3702; GFX8-NEXT:    v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3703; GFX8-NEXT:    s_andn2_b32 s1, 15, s3
3704; GFX8-NEXT:    s_lshl_b32 s0, s2, s0
3705; GFX8-NEXT:    v_lshrrev_b16_e32 v0, s1, v0
3706; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3707; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3708; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3709; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3710; GFX8-NEXT:    ; return to shader part epilog
3711;
3712; GFX9-LABEL: v_fshl_v2i16_svs:
3713; GFX9:       ; %bb.0:
3714; GFX9-NEXT:    s_mov_b32 s2, 0xf000f
3715; GFX9-NEXT:    s_and_b32 s3, s1, s2
3716; GFX9-NEXT:    s_andn2_b32 s1, s2, s1
3717; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3718; GFX9-NEXT:    s_lshr_b32 s4, s3, 16
3719; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3720; GFX9-NEXT:    s_lshl_b32 s0, s0, s3
3721; GFX9-NEXT:    s_lshl_b32 s2, s2, s4
3722; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3723; GFX9-NEXT:    v_pk_lshrrev_b16 v0, s1, v0
3724; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3725; GFX9-NEXT:    ; return to shader part epilog
3726;
3727; GFX10-LABEL: v_fshl_v2i16_svs:
3728; GFX10:       ; %bb.0:
3729; GFX10-NEXT:    s_mov_b32 s2, 0xf000f
3730; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 1, v0 op_sel_hi:[0,1]
3731; GFX10-NEXT:    s_and_b32 s3, s1, s2
3732; GFX10-NEXT:    s_andn2_b32 s1, s2, s1
3733; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3734; GFX10-NEXT:    s_lshr_b32 s4, s3, 16
3735; GFX10-NEXT:    v_pk_lshrrev_b16 v0, s1, v0
3736; GFX10-NEXT:    s_lshl_b32 s0, s0, s3
3737; GFX10-NEXT:    s_lshl_b32 s1, s2, s4
3738; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3739; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3740; GFX10-NEXT:    ; return to shader part epilog
3741  %result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3742  %cast = bitcast <2 x i16> %result to float
3743  ret float %cast
3744}
3745
3746define amdgpu_ps float @v_fshl_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
3747; GFX6-LABEL: v_fshl_v2i16_vss:
3748; GFX6:       ; %bb.0:
3749; GFX6-NEXT:    s_and_b32 s3, s1, 15
3750; GFX6-NEXT:    s_bfe_u32 s3, s3, 0x100000
3751; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
3752; GFX6-NEXT:    s_lshr_b32 s2, s1, 16
3753; GFX6-NEXT:    s_andn2_b32 s1, 15, s1
3754; GFX6-NEXT:    v_lshlrev_b32_e32 v0, s3, v0
3755; GFX6-NEXT:    s_and_b32 s3, s0, 0xffff
3756; GFX6-NEXT:    s_lshr_b32 s3, s3, 1
3757; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3758; GFX6-NEXT:    s_lshr_b32 s1, s3, s1
3759; GFX6-NEXT:    v_or_b32_e32 v0, s1, v0
3760; GFX6-NEXT:    s_and_b32 s1, s2, 15
3761; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3762; GFX6-NEXT:    s_andn2_b32 s2, 15, s2
3763; GFX6-NEXT:    v_lshlrev_b32_e32 v1, s1, v1
3764; GFX6-NEXT:    s_lshr_b32 s0, s0, 17
3765; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
3766; GFX6-NEXT:    s_lshr_b32 s0, s0, s1
3767; GFX6-NEXT:    v_or_b32_e32 v1, s0, v1
3768; GFX6-NEXT:    v_bfe_u32 v1, v1, 0, 16
3769; GFX6-NEXT:    v_bfe_u32 v0, v0, 0, 16
3770; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
3771; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
3772; GFX6-NEXT:    ; return to shader part epilog
3773;
3774; GFX8-LABEL: v_fshl_v2i16_vss:
3775; GFX8:       ; %bb.0:
3776; GFX8-NEXT:    s_and_b32 s4, s1, 15
3777; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
3778; GFX8-NEXT:    s_lshr_b32 s3, s1, 16
3779; GFX8-NEXT:    s_andn2_b32 s1, 15, s1
3780; GFX8-NEXT:    v_lshlrev_b16_e32 v1, s4, v0
3781; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3782; GFX8-NEXT:    s_bfe_u32 s4, 1, 0x100000
3783; GFX8-NEXT:    s_lshr_b32 s0, s0, s4
3784; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3785; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3786; GFX8-NEXT:    s_andn2_b32 s1, 15, s3
3787; GFX8-NEXT:    v_or_b32_e32 v1, s0, v1
3788; GFX8-NEXT:    s_and_b32 s0, s3, 15
3789; GFX8-NEXT:    v_mov_b32_e32 v2, s0
3790; GFX8-NEXT:    s_lshr_b32 s0, s2, s4
3791; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3792; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3793; GFX8-NEXT:    s_lshr_b32 s0, s0, s1
3794; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
3795; GFX8-NEXT:    v_mov_b32_e32 v2, 16
3796; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3797; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3798; GFX8-NEXT:    ; return to shader part epilog
3799;
3800; GFX9-LABEL: v_fshl_v2i16_vss:
3801; GFX9:       ; %bb.0:
3802; GFX9-NEXT:    s_mov_b32 s2, 0xf000f
3803; GFX9-NEXT:    s_and_b32 s3, s1, s2
3804; GFX9-NEXT:    v_pk_lshlrev_b16 v0, s3, v0
3805; GFX9-NEXT:    s_mov_b32 s3, 0xffff
3806; GFX9-NEXT:    s_andn2_b32 s1, s2, s1
3807; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3808; GFX9-NEXT:    s_and_b32 s0, s0, s3
3809; GFX9-NEXT:    s_lshr_b32 s0, s0, 1
3810; GFX9-NEXT:    s_lshr_b32 s2, s2, 1
3811; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2
3812; GFX9-NEXT:    s_lshr_b32 s2, s0, 16
3813; GFX9-NEXT:    s_lshr_b32 s4, s1, 16
3814; GFX9-NEXT:    s_and_b32 s0, s0, s3
3815; GFX9-NEXT:    s_and_b32 s1, s1, s3
3816; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
3817; GFX9-NEXT:    s_lshr_b32 s1, s2, s4
3818; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3819; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
3820; GFX9-NEXT:    ; return to shader part epilog
3821;
3822; GFX10-LABEL: v_fshl_v2i16_vss:
3823; GFX10:       ; %bb.0:
3824; GFX10-NEXT:    s_mov_b32 s3, 0xffff
3825; GFX10-NEXT:    s_mov_b32 s2, 0xf000f
3826; GFX10-NEXT:    s_and_b32 s5, s0, s3
3827; GFX10-NEXT:    s_lshr_b32 s0, s0, 16
3828; GFX10-NEXT:    s_lshr_b32 s5, s5, 1
3829; GFX10-NEXT:    s_lshr_b32 s0, s0, 1
3830; GFX10-NEXT:    s_and_b32 s4, s1, s2
3831; GFX10-NEXT:    s_andn2_b32 s1, s2, s1
3832; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s5, s0
3833; GFX10-NEXT:    v_pk_lshlrev_b16 v0, s4, v0
3834; GFX10-NEXT:    s_lshr_b32 s2, s0, 16
3835; GFX10-NEXT:    s_and_b32 s0, s0, s3
3836; GFX10-NEXT:    s_and_b32 s3, s1, s3
3837; GFX10-NEXT:    s_lshr_b32 s1, s1, 16
3838; GFX10-NEXT:    s_lshr_b32 s0, s0, s3
3839; GFX10-NEXT:    s_lshr_b32 s1, s2, s1
3840; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s1
3841; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
3842; GFX10-NEXT:    ; return to shader part epilog
3843  %result = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt)
3844  %cast = bitcast <2 x i16> %result to float
3845  ret float %cast
3846}
3847
3848; ; FIXME
3849; define amdgpu_ps i48 @s_fshl_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <3 x i16> inreg %amt) {
3850;   %result = call <3 x i16> @llvm.fshl.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
3851;   %cast = bitcast <3 x i16> %result to i48
3852;   ret i48 %cast
3853; }
3854
3855; ; FIXME
3856; define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt) {
3857;   %result = call <3 x i16> @llvm.fshl.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
3858;   %cast.result = bitcast <3 x i16> %result to <3 x half>
3859;   ret <3 x half> %cast.result
3860; }
3861
3862define amdgpu_ps <2 x i32> @s_fshl_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs, <4 x i16> inreg %amt) {
3863; GFX6-LABEL: s_fshl_v4i16:
3864; GFX6:       ; %bb.0:
3865; GFX6-NEXT:    s_and_b32 s12, s8, 15
3866; GFX6-NEXT:    s_bfe_u32 s12, s12, 0x100000
3867; GFX6-NEXT:    s_lshl_b32 s0, s0, s12
3868; GFX6-NEXT:    s_mov_b32 s12, 0xffff
3869; GFX6-NEXT:    s_andn2_b32 s8, 15, s8
3870; GFX6-NEXT:    s_and_b32 s4, s4, s12
3871; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3872; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
3873; GFX6-NEXT:    s_lshr_b32 s4, s4, s8
3874; GFX6-NEXT:    s_or_b32 s0, s0, s4
3875; GFX6-NEXT:    s_and_b32 s4, s9, 15
3876; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3877; GFX6-NEXT:    s_lshl_b32 s1, s1, s4
3878; GFX6-NEXT:    s_and_b32 s4, s5, s12
3879; GFX6-NEXT:    s_andn2_b32 s8, 15, s9
3880; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3881; GFX6-NEXT:    s_bfe_u32 s5, s8, 0x100000
3882; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3883; GFX6-NEXT:    s_or_b32 s1, s1, s4
3884; GFX6-NEXT:    s_and_b32 s4, s10, 15
3885; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3886; GFX6-NEXT:    s_andn2_b32 s5, 15, s10
3887; GFX6-NEXT:    s_lshl_b32 s2, s2, s4
3888; GFX6-NEXT:    s_and_b32 s4, s6, s12
3889; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3890; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
3891; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3892; GFX6-NEXT:    s_or_b32 s2, s2, s4
3893; GFX6-NEXT:    s_and_b32 s4, s11, 15
3894; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
3895; GFX6-NEXT:    s_andn2_b32 s5, 15, s11
3896; GFX6-NEXT:    s_lshl_b32 s3, s3, s4
3897; GFX6-NEXT:    s_and_b32 s4, s7, s12
3898; GFX6-NEXT:    s_lshr_b32 s4, s4, 1
3899; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
3900; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
3901; GFX6-NEXT:    s_lshr_b32 s4, s4, s5
3902; GFX6-NEXT:    s_or_b32 s3, s3, s4
3903; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
3904; GFX6-NEXT:    s_lshl_b32 s1, s1, 16
3905; GFX6-NEXT:    s_or_b32 s0, s0, s1
3906; GFX6-NEXT:    s_bfe_u32 s1, s2, 0x100000
3907; GFX6-NEXT:    s_bfe_u32 s2, s3, 0x100000
3908; GFX6-NEXT:    s_lshl_b32 s2, s2, 16
3909; GFX6-NEXT:    s_or_b32 s1, s1, s2
3910; GFX6-NEXT:    ; return to shader part epilog
3911;
3912; GFX8-LABEL: s_fshl_v4i16:
3913; GFX8:       ; %bb.0:
3914; GFX8-NEXT:    s_and_b32 s12, s4, 15
3915; GFX8-NEXT:    s_bfe_u32 s12, s12, 0x100000
3916; GFX8-NEXT:    s_lshr_b32 s6, s0, 16
3917; GFX8-NEXT:    s_lshr_b32 s8, s2, 16
3918; GFX8-NEXT:    s_lshr_b32 s10, s4, 16
3919; GFX8-NEXT:    s_andn2_b32 s4, 15, s4
3920; GFX8-NEXT:    s_lshl_b32 s0, s0, s12
3921; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3922; GFX8-NEXT:    s_bfe_u32 s12, 1, 0x100000
3923; GFX8-NEXT:    s_lshr_b32 s2, s2, s12
3924; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3925; GFX8-NEXT:    s_lshr_b32 s2, s2, s4
3926; GFX8-NEXT:    s_or_b32 s0, s0, s2
3927; GFX8-NEXT:    s_and_b32 s2, s10, 15
3928; GFX8-NEXT:    s_andn2_b32 s4, 15, s10
3929; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3930; GFX8-NEXT:    s_lshl_b32 s2, s6, s2
3931; GFX8-NEXT:    s_lshr_b32 s6, s8, s12
3932; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3933; GFX8-NEXT:    s_lshr_b32 s4, s6, s4
3934; GFX8-NEXT:    s_or_b32 s2, s2, s4
3935; GFX8-NEXT:    s_and_b32 s4, s5, 15
3936; GFX8-NEXT:    s_lshr_b32 s9, s3, 16
3937; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
3938; GFX8-NEXT:    s_lshr_b32 s11, s5, 16
3939; GFX8-NEXT:    s_andn2_b32 s5, 15, s5
3940; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3941; GFX8-NEXT:    s_lshr_b32 s7, s1, 16
3942; GFX8-NEXT:    s_lshl_b32 s1, s1, s4
3943; GFX8-NEXT:    s_bfe_u32 s4, s5, 0x100000
3944; GFX8-NEXT:    s_lshr_b32 s3, s3, s12
3945; GFX8-NEXT:    s_lshr_b32 s3, s3, s4
3946; GFX8-NEXT:    s_or_b32 s1, s1, s3
3947; GFX8-NEXT:    s_and_b32 s3, s11, 15
3948; GFX8-NEXT:    s_andn2_b32 s4, 15, s11
3949; GFX8-NEXT:    s_bfe_u32 s3, s3, 0x100000
3950; GFX8-NEXT:    s_lshr_b32 s5, s9, s12
3951; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
3952; GFX8-NEXT:    s_bfe_u32 s2, s2, 0x100000
3953; GFX8-NEXT:    s_lshl_b32 s3, s7, s3
3954; GFX8-NEXT:    s_lshr_b32 s4, s5, s4
3955; GFX8-NEXT:    s_or_b32 s3, s3, s4
3956; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
3957; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
3958; GFX8-NEXT:    s_or_b32 s0, s0, s2
3959; GFX8-NEXT:    s_bfe_u32 s2, s3, 0x100000
3960; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
3961; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
3962; GFX8-NEXT:    s_or_b32 s1, s1, s2
3963; GFX8-NEXT:    ; return to shader part epilog
3964;
3965; GFX9-LABEL: s_fshl_v4i16:
3966; GFX9:       ; %bb.0:
3967; GFX9-NEXT:    s_mov_b32 s6, 0xf000f
3968; GFX9-NEXT:    s_and_b32 s7, s4, s6
3969; GFX9-NEXT:    s_lshr_b32 s8, s0, 16
3970; GFX9-NEXT:    s_lshr_b32 s9, s7, 16
3971; GFX9-NEXT:    s_lshl_b32 s0, s0, s7
3972; GFX9-NEXT:    s_lshl_b32 s7, s8, s9
3973; GFX9-NEXT:    s_mov_b32 s8, 0xffff
3974; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s7
3975; GFX9-NEXT:    s_lshr_b32 s7, s2, 16
3976; GFX9-NEXT:    s_and_b32 s2, s2, s8
3977; GFX9-NEXT:    s_lshr_b32 s2, s2, 1
3978; GFX9-NEXT:    s_lshr_b32 s7, s7, 1
3979; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s7
3980; GFX9-NEXT:    s_andn2_b32 s4, s6, s4
3981; GFX9-NEXT:    s_lshr_b32 s7, s2, 16
3982; GFX9-NEXT:    s_lshr_b32 s9, s4, 16
3983; GFX9-NEXT:    s_and_b32 s2, s2, s8
3984; GFX9-NEXT:    s_and_b32 s4, s4, s8
3985; GFX9-NEXT:    s_lshr_b32 s2, s2, s4
3986; GFX9-NEXT:    s_lshr_b32 s4, s7, s9
3987; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s4
3988; GFX9-NEXT:    s_or_b32 s0, s0, s2
3989; GFX9-NEXT:    s_and_b32 s2, s5, s6
3990; GFX9-NEXT:    s_andn2_b32 s4, s6, s5
3991; GFX9-NEXT:    s_lshr_b32 s5, s1, 16
3992; GFX9-NEXT:    s_lshr_b32 s6, s2, 16
3993; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
3994; GFX9-NEXT:    s_lshl_b32 s2, s5, s6
3995; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s2
3996; GFX9-NEXT:    s_lshr_b32 s2, s3, 16
3997; GFX9-NEXT:    s_and_b32 s3, s3, s8
3998; GFX9-NEXT:    s_lshr_b32 s3, s3, 1
3999; GFX9-NEXT:    s_lshr_b32 s2, s2, 1
4000; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
4001; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
4002; GFX9-NEXT:    s_lshr_b32 s5, s4, 16
4003; GFX9-NEXT:    s_and_b32 s2, s2, s8
4004; GFX9-NEXT:    s_and_b32 s4, s4, s8
4005; GFX9-NEXT:    s_lshr_b32 s2, s2, s4
4006; GFX9-NEXT:    s_lshr_b32 s3, s3, s5
4007; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
4008; GFX9-NEXT:    s_or_b32 s1, s1, s2
4009; GFX9-NEXT:    ; return to shader part epilog
4010;
4011; GFX10-LABEL: s_fshl_v4i16:
4012; GFX10:       ; %bb.0:
4013; GFX10-NEXT:    s_mov_b32 s9, 0xffff
4014; GFX10-NEXT:    s_mov_b32 s6, 0xf000f
4015; GFX10-NEXT:    s_and_b32 s11, s2, s9
4016; GFX10-NEXT:    s_lshr_b32 s2, s2, 16
4017; GFX10-NEXT:    s_and_b32 s7, s4, s6
4018; GFX10-NEXT:    s_lshr_b32 s11, s11, 1
4019; GFX10-NEXT:    s_lshr_b32 s2, s2, 1
4020; GFX10-NEXT:    s_lshr_b32 s8, s0, 16
4021; GFX10-NEXT:    s_andn2_b32 s4, s6, s4
4022; GFX10-NEXT:    s_lshr_b32 s10, s7, 16
4023; GFX10-NEXT:    s_pack_ll_b32_b16 s2, s11, s2
4024; GFX10-NEXT:    s_lshl_b32 s0, s0, s7
4025; GFX10-NEXT:    s_lshl_b32 s7, s8, s10
4026; GFX10-NEXT:    s_lshr_b32 s8, s2, 16
4027; GFX10-NEXT:    s_and_b32 s10, s4, s9
4028; GFX10-NEXT:    s_and_b32 s2, s2, s9
4029; GFX10-NEXT:    s_lshr_b32 s4, s4, 16
4030; GFX10-NEXT:    s_lshr_b32 s2, s2, s10
4031; GFX10-NEXT:    s_lshr_b32 s4, s8, s4
4032; GFX10-NEXT:    s_and_b32 s8, s3, s9
4033; GFX10-NEXT:    s_lshr_b32 s3, s3, 16
4034; GFX10-NEXT:    s_pack_ll_b32_b16 s2, s2, s4
4035; GFX10-NEXT:    s_and_b32 s4, s5, s6
4036; GFX10-NEXT:    s_lshr_b32 s8, s8, 1
4037; GFX10-NEXT:    s_lshr_b32 s3, s3, 1
4038; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s7
4039; GFX10-NEXT:    s_andn2_b32 s5, s6, s5
4040; GFX10-NEXT:    s_lshr_b32 s6, s1, 16
4041; GFX10-NEXT:    s_lshr_b32 s7, s4, 16
4042; GFX10-NEXT:    s_pack_ll_b32_b16 s3, s8, s3
4043; GFX10-NEXT:    s_lshl_b32 s1, s1, s4
4044; GFX10-NEXT:    s_lshl_b32 s4, s6, s7
4045; GFX10-NEXT:    s_lshr_b32 s6, s3, 16
4046; GFX10-NEXT:    s_and_b32 s7, s5, s9
4047; GFX10-NEXT:    s_and_b32 s3, s3, s9
4048; GFX10-NEXT:    s_lshr_b32 s5, s5, 16
4049; GFX10-NEXT:    s_lshr_b32 s3, s3, s7
4050; GFX10-NEXT:    s_lshr_b32 s5, s6, s5
4051; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s4
4052; GFX10-NEXT:    s_pack_ll_b32_b16 s3, s3, s5
4053; GFX10-NEXT:    s_or_b32 s0, s0, s2
4054; GFX10-NEXT:    s_or_b32 s1, s1, s3
4055; GFX10-NEXT:    ; return to shader part epilog
4056  %result = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
4057  %cast.result = bitcast <4 x i16> %result to <2 x i32>
4058  ret <2 x i32> %cast.result
4059}
4060
4061define <4 x half> @v_fshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt) {
4062; GFX6-LABEL: v_fshl_v4i16:
4063; GFX6:       ; %bb.0:
4064; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4065; GFX6-NEXT:    v_and_b32_e32 v12, 15, v8
4066; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4067; GFX6-NEXT:    s_mov_b32 s4, 0xffff
4068; GFX6-NEXT:    v_and_b32_e32 v8, 15, v8
4069; GFX6-NEXT:    v_and_b32_e32 v4, s4, v4
4070; GFX6-NEXT:    v_bfe_u32 v12, v12, 0, 16
4071; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4072; GFX6-NEXT:    v_bfe_u32 v8, v8, 0, 16
4073; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v12, v0
4074; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v8, v4
4075; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
4076; GFX6-NEXT:    v_and_b32_e32 v4, 15, v9
4077; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v9
4078; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
4079; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
4080; GFX6-NEXT:    v_and_b32_e32 v4, s4, v5
4081; GFX6-NEXT:    v_and_b32_e32 v8, 15, v8
4082; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4083; GFX6-NEXT:    v_bfe_u32 v5, v8, 0, 16
4084; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
4085; GFX6-NEXT:    v_or_b32_e32 v1, v1, v4
4086; GFX6-NEXT:    v_and_b32_e32 v4, 15, v10
4087; GFX6-NEXT:    v_xor_b32_e32 v5, -1, v10
4088; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
4089; GFX6-NEXT:    v_mov_b32_e32 v12, 0xffff
4090; GFX6-NEXT:    v_and_b32_e32 v5, 15, v5
4091; GFX6-NEXT:    v_lshlrev_b32_e32 v2, v4, v2
4092; GFX6-NEXT:    v_and_b32_e32 v4, v6, v12
4093; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4094; GFX6-NEXT:    v_bfe_u32 v5, v5, 0, 16
4095; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
4096; GFX6-NEXT:    v_or_b32_e32 v2, v2, v4
4097; GFX6-NEXT:    v_and_b32_e32 v4, 15, v11
4098; GFX6-NEXT:    v_xor_b32_e32 v5, -1, v11
4099; GFX6-NEXT:    v_bfe_u32 v4, v4, 0, 16
4100; GFX6-NEXT:    v_and_b32_e32 v5, 15, v5
4101; GFX6-NEXT:    v_lshlrev_b32_e32 v3, v4, v3
4102; GFX6-NEXT:    v_and_b32_e32 v4, v7, v12
4103; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
4104; GFX6-NEXT:    v_bfe_u32 v5, v5, 0, 16
4105; GFX6-NEXT:    v_lshrrev_b32_e32 v4, v5, v4
4106; GFX6-NEXT:    v_or_b32_e32 v3, v3, v4
4107; GFX6-NEXT:    s_setpc_b64 s[30:31]
4108;
4109; GFX8-LABEL: v_fshl_v4i16:
4110; GFX8:       ; %bb.0:
4111; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4112; GFX8-NEXT:    v_and_b32_e32 v8, 15, v4
4113; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
4114; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
4115; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
4116; GFX8-NEXT:    v_lshrrev_b16_e32 v9, 1, v2
4117; GFX8-NEXT:    v_lshlrev_b16_e32 v8, v8, v0
4118; GFX8-NEXT:    v_lshrrev_b16_e32 v4, v4, v9
4119; GFX8-NEXT:    v_or_b32_e32 v4, v8, v4
4120; GFX8-NEXT:    v_and_b32_e32 v8, 15, v6
4121; GFX8-NEXT:    v_xor_b32_e32 v6, -1, v6
4122; GFX8-NEXT:    v_lshlrev_b16_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4123; GFX8-NEXT:    v_mov_b32_e32 v8, 1
4124; GFX8-NEXT:    v_and_b32_e32 v6, 15, v6
4125; GFX8-NEXT:    v_lshrrev_b16_sdwa v2, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4126; GFX8-NEXT:    v_lshrrev_b16_e32 v2, v6, v2
4127; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4128; GFX8-NEXT:    v_and_b32_e32 v2, 15, v5
4129; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v5
4130; GFX8-NEXT:    v_xor_b32_e32 v5, -1, v5
4131; GFX8-NEXT:    v_and_b32_e32 v5, 15, v5
4132; GFX8-NEXT:    v_lshrrev_b16_e32 v6, 1, v3
4133; GFX8-NEXT:    v_lshrrev_b16_e32 v5, v5, v6
4134; GFX8-NEXT:    v_lshlrev_b16_e32 v2, v2, v1
4135; GFX8-NEXT:    v_or_b32_e32 v2, v2, v5
4136; GFX8-NEXT:    v_and_b32_e32 v5, 15, v7
4137; GFX8-NEXT:    v_xor_b32_e32 v6, -1, v7
4138; GFX8-NEXT:    v_lshlrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4139; GFX8-NEXT:    v_mov_b32_e32 v5, 1
4140; GFX8-NEXT:    v_and_b32_e32 v6, 15, v6
4141; GFX8-NEXT:    v_lshrrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4142; GFX8-NEXT:    v_lshrrev_b16_e32 v3, v6, v3
4143; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4144; GFX8-NEXT:    v_mov_b32_e32 v3, 16
4145; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4146; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4147; GFX8-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4148; GFX8-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4149; GFX8-NEXT:    s_setpc_b64 s[30:31]
4150;
4151; GFX9-LABEL: v_fshl_v4i16:
4152; GFX9:       ; %bb.0:
4153; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4154; GFX9-NEXT:    s_mov_b32 s4, 0xf000f
4155; GFX9-NEXT:    v_and_b32_e32 v6, s4, v4
4156; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
4157; GFX9-NEXT:    v_and_b32_e32 v4, s4, v4
4158; GFX9-NEXT:    v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
4159; GFX9-NEXT:    v_pk_lshrrev_b16 v2, v4, v2
4160; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v6, v0
4161; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v5
4162; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4163; GFX9-NEXT:    v_and_b32_e32 v2, s4, v5
4164; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v2, v1
4165; GFX9-NEXT:    v_and_b32_e32 v4, s4, v4
4166; GFX9-NEXT:    v_pk_lshrrev_b16 v2, 1, v3 op_sel_hi:[0,1]
4167; GFX9-NEXT:    v_pk_lshrrev_b16 v2, v4, v2
4168; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
4169; GFX9-NEXT:    s_setpc_b64 s[30:31]
4170;
4171; GFX10-LABEL: v_fshl_v4i16:
4172; GFX10:       ; %bb.0:
4173; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4174; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4175; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v4
4176; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v5
4177; GFX10-NEXT:    s_mov_b32 s4, 0xf000f
4178; GFX10-NEXT:    v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
4179; GFX10-NEXT:    v_and_b32_e32 v4, s4, v4
4180; GFX10-NEXT:    v_and_b32_e32 v6, s4, v6
4181; GFX10-NEXT:    v_and_b32_e32 v5, s4, v5
4182; GFX10-NEXT:    v_and_b32_e32 v7, s4, v7
4183; GFX10-NEXT:    v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
4184; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v4, v0
4185; GFX10-NEXT:    v_pk_lshrrev_b16 v2, v6, v2
4186; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v5, v1
4187; GFX10-NEXT:    v_pk_lshrrev_b16 v3, v7, v3
4188; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4189; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4190; GFX10-NEXT:    s_setpc_b64 s[30:31]
4191  %result = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
4192  %cast.result = bitcast <4 x i16> %result to <4 x half>
4193  ret <4 x half> %cast.result
4194}
4195
4196define amdgpu_ps i64 @s_fshl_i64(i64 inreg %lhs, i64 inreg %rhs, i64 inreg %amt) {
4197; GCN-LABEL: s_fshl_i64:
4198; GCN:       ; %bb.0:
4199; GCN-NEXT:    s_and_b64 s[6:7], s[4:5], 63
4200; GCN-NEXT:    s_andn2_b64 s[4:5], 63, s[4:5]
4201; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
4202; GCN-NEXT:    s_lshl_b64 s[0:1], s[0:1], s6
4203; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], s4
4204; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4205; GCN-NEXT:    ; return to shader part epilog
4206  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
4207  ret i64 %result
4208}
4209
4210define amdgpu_ps i64 @s_fshl_i64_5(i64 inreg %lhs, i64 inreg %rhs) {
4211; GCN-LABEL: s_fshl_i64_5:
4212; GCN:       ; %bb.0:
4213; GCN-NEXT:    s_lshr_b32 s2, s3, 27
4214; GCN-NEXT:    s_lshl_b64 s[0:1], s[0:1], 5
4215; GCN-NEXT:    s_mov_b32 s3, 0
4216; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4217; GCN-NEXT:    ; return to shader part epilog
4218  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 5)
4219  ret i64 %result
4220}
4221
4222define amdgpu_ps i64 @s_fshl_i64_32(i64 inreg %lhs, i64 inreg %rhs) {
4223; GCN-LABEL: s_fshl_i64_32:
4224; GCN:       ; %bb.0:
4225; GCN-NEXT:    s_mov_b32 s1, s0
4226; GCN-NEXT:    s_mov_b32 s0, 0
4227; GCN-NEXT:    s_mov_b32 s2, s3
4228; GCN-NEXT:    s_mov_b32 s3, s0
4229; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4230; GCN-NEXT:    ; return to shader part epilog
4231  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 32)
4232  ret i64 %result
4233}
4234
4235define amdgpu_ps i64 @s_fshl_i64_48(i64 inreg %lhs, i64 inreg %rhs) {
4236; GCN-LABEL: s_fshl_i64_48:
4237; GCN:       ; %bb.0:
4238; GCN-NEXT:    s_lshl_b32 s1, s0, 16
4239; GCN-NEXT:    s_mov_b32 s0, 0
4240; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], 16
4241; GCN-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
4242; GCN-NEXT:    ; return to shader part epilog
4243  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 48)
4244  ret i64 %result
4245}
4246
4247define i64 @v_fshl_i64(i64 %lhs, i64 %rhs, i64 %amt) {
4248; GFX6-LABEL: v_fshl_i64:
4249; GFX6:       ; %bb.0:
4250; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4251; GFX6-NEXT:    v_and_b32_e32 v5, 63, v4
4252; GFX6-NEXT:    v_xor_b32_e32 v4, -1, v4
4253; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], 1
4254; GFX6-NEXT:    v_and_b32_e32 v4, 63, v4
4255; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v5
4256; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], v4
4257; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4258; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
4259; GFX6-NEXT:    s_setpc_b64 s[30:31]
4260;
4261; GFX8-LABEL: v_fshl_i64:
4262; GFX8:       ; %bb.0:
4263; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4264; GFX8-NEXT:    v_and_b32_e32 v5, 63, v4
4265; GFX8-NEXT:    v_xor_b32_e32 v4, -1, v4
4266; GFX8-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
4267; GFX8-NEXT:    v_and_b32_e32 v4, 63, v4
4268; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v5, v[0:1]
4269; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]
4270; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4271; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4272; GFX8-NEXT:    s_setpc_b64 s[30:31]
4273;
4274; GFX9-LABEL: v_fshl_i64:
4275; GFX9:       ; %bb.0:
4276; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4277; GFX9-NEXT:    v_and_b32_e32 v5, 63, v4
4278; GFX9-NEXT:    v_xor_b32_e32 v4, -1, v4
4279; GFX9-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
4280; GFX9-NEXT:    v_and_b32_e32 v4, 63, v4
4281; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v5, v[0:1]
4282; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v4, v[2:3]
4283; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4284; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
4285; GFX9-NEXT:    s_setpc_b64 s[30:31]
4286;
4287; GFX10-LABEL: v_fshl_i64:
4288; GFX10:       ; %bb.0:
4289; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4290; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4291; GFX10-NEXT:    v_xor_b32_e32 v5, -1, v4
4292; GFX10-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
4293; GFX10-NEXT:    v_and_b32_e32 v4, 63, v4
4294; GFX10-NEXT:    v_and_b32_e32 v5, 63, v5
4295; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
4296; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
4297; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4298; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4299; GFX10-NEXT:    s_setpc_b64 s[30:31]
4300  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
4301  ret i64 %result
4302}
4303
4304define i64 @v_fshl_i64_5(i64 %lhs, i64 %rhs) {
4305; GFX6-LABEL: v_fshl_i64_5:
4306; GFX6:       ; %bb.0:
4307; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4308; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 5
4309; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 27, v3
4310; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4311; GFX6-NEXT:    s_setpc_b64 s[30:31]
4312;
4313; GFX8-LABEL: v_fshl_i64_5:
4314; GFX8:       ; %bb.0:
4315; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4316; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 5, v[0:1]
4317; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 27, v3
4318; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4319; GFX8-NEXT:    s_setpc_b64 s[30:31]
4320;
4321; GFX9-LABEL: v_fshl_i64_5:
4322; GFX9:       ; %bb.0:
4323; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4324; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 5, v[0:1]
4325; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 27, v3
4326; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4327; GFX9-NEXT:    s_setpc_b64 s[30:31]
4328;
4329; GFX10-LABEL: v_fshl_i64_5:
4330; GFX10:       ; %bb.0:
4331; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4332; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4333; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 5, v[0:1]
4334; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 27, v3
4335; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4336; GFX10-NEXT:    s_setpc_b64 s[30:31]
4337  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 5)
4338  ret i64 %result
4339}
4340
4341define i64 @v_fshl_i64_32(i64 %lhs, i64 %rhs) {
4342; GFX6-LABEL: v_fshl_i64_32:
4343; GFX6:       ; %bb.0:
4344; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4345; GFX6-NEXT:    v_mov_b32_e32 v1, v0
4346; GFX6-NEXT:    v_mov_b32_e32 v0, v3
4347; GFX6-NEXT:    s_setpc_b64 s[30:31]
4348;
4349; GFX8-LABEL: v_fshl_i64_32:
4350; GFX8:       ; %bb.0:
4351; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4352; GFX8-NEXT:    v_mov_b32_e32 v1, v0
4353; GFX8-NEXT:    v_mov_b32_e32 v0, v3
4354; GFX8-NEXT:    s_setpc_b64 s[30:31]
4355;
4356; GFX9-LABEL: v_fshl_i64_32:
4357; GFX9:       ; %bb.0:
4358; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4359; GFX9-NEXT:    v_mov_b32_e32 v1, v0
4360; GFX9-NEXT:    v_mov_b32_e32 v0, v3
4361; GFX9-NEXT:    s_setpc_b64 s[30:31]
4362;
4363; GFX10-LABEL: v_fshl_i64_32:
4364; GFX10:       ; %bb.0:
4365; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4366; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4367; GFX10-NEXT:    v_mov_b32_e32 v1, v0
4368; GFX10-NEXT:    v_mov_b32_e32 v0, v3
4369; GFX10-NEXT:    s_setpc_b64 s[30:31]
4370  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 32)
4371  ret i64 %result
4372}
4373
4374define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
4375; GFX6-LABEL: v_fshl_i64_48:
4376; GFX6:       ; %bb.0:
4377; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4378; GFX6-NEXT:    v_mov_b32_e32 v4, v0
4379; GFX6-NEXT:    v_lshr_b64 v[0:1], v[2:3], 16
4380; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
4381; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
4382; GFX6-NEXT:    s_setpc_b64 s[30:31]
4383;
4384; GFX8-LABEL: v_fshl_i64_48:
4385; GFX8:       ; %bb.0:
4386; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4387; GFX8-NEXT:    v_mov_b32_e32 v4, v0
4388; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 16, v[2:3]
4389; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
4390; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
4391; GFX8-NEXT:    s_setpc_b64 s[30:31]
4392;
4393; GFX9-LABEL: v_fshl_i64_48:
4394; GFX9:       ; %bb.0:
4395; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4396; GFX9-NEXT:    v_mov_b32_e32 v4, v0
4397; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 16, v[2:3]
4398; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
4399; GFX9-NEXT:    v_or_b32_e32 v1, v2, v1
4400; GFX9-NEXT:    s_setpc_b64 s[30:31]
4401;
4402; GFX10-LABEL: v_fshl_i64_48:
4403; GFX10:       ; %bb.0:
4404; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4405; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4406; GFX10-NEXT:    v_mov_b32_e32 v4, v0
4407; GFX10-NEXT:    v_lshrrev_b64 v[0:1], 16, v[2:3]
4408; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
4409; GFX10-NEXT:    v_or_b32_e32 v1, v2, v1
4410; GFX10-NEXT:    s_setpc_b64 s[30:31]
4411  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 48)
4412  ret i64 %result
4413}
4414
4415define amdgpu_ps <2 x float> @v_fshl_i64_ssv(i64 inreg %lhs, i64 inreg %rhs, i64 %amt) {
4416; GFX6-LABEL: v_fshl_i64_ssv:
4417; GFX6:       ; %bb.0:
4418; GFX6-NEXT:    v_and_b32_e32 v1, 63, v0
4419; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
4420; GFX6-NEXT:    v_and_b32_e32 v2, 63, v0
4421; GFX6-NEXT:    v_lshl_b64 v[0:1], s[0:1], v1
4422; GFX6-NEXT:    s_lshr_b64 s[0:1], s[2:3], 1
4423; GFX6-NEXT:    v_lshr_b64 v[2:3], s[0:1], v2
4424; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
4425; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
4426; GFX6-NEXT:    ; return to shader part epilog
4427;
4428; GFX8-LABEL: v_fshl_i64_ssv:
4429; GFX8:       ; %bb.0:
4430; GFX8-NEXT:    v_and_b32_e32 v1, 63, v0
4431; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
4432; GFX8-NEXT:    v_and_b32_e32 v2, 63, v0
4433; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v1, s[0:1]
4434; GFX8-NEXT:    s_lshr_b64 s[0:1], s[2:3], 1
4435; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v2, s[0:1]
4436; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
4437; GFX8-NEXT:    v_or_b32_e32 v1, v1, v3
4438; GFX8-NEXT:    ; return to shader part epilog
4439;
4440; GFX9-LABEL: v_fshl_i64_ssv:
4441; GFX9:       ; %bb.0:
4442; GFX9-NEXT:    v_and_b32_e32 v1, 63, v0
4443; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
4444; GFX9-NEXT:    v_and_b32_e32 v2, 63, v0
4445; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v1, s[0:1]
4446; GFX9-NEXT:    s_lshr_b64 s[0:1], s[2:3], 1
4447; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v2, s[0:1]
4448; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
4449; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
4450; GFX9-NEXT:    ; return to shader part epilog
4451;
4452; GFX10-LABEL: v_fshl_i64_ssv:
4453; GFX10:       ; %bb.0:
4454; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
4455; GFX10-NEXT:    v_and_b32_e32 v0, 63, v0
4456; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], 1
4457; GFX10-NEXT:    v_and_b32_e32 v2, 63, v1
4458; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v0, s[0:1]
4459; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v2, s[2:3]
4460; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
4461; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
4462; GFX10-NEXT:    ; return to shader part epilog
4463  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
4464  %cast = bitcast i64 %result to <2 x float>
4465  ret <2 x float> %cast
4466}
4467
4468define amdgpu_ps <2 x float> @v_fshl_i64_svs(i64 inreg %lhs, i64 %rhs, i64 inreg %amt) {
4469; GFX6-LABEL: v_fshl_i64_svs:
4470; GFX6:       ; %bb.0:
4471; GFX6-NEXT:    v_lshr_b64 v[0:1], v[0:1], 1
4472; GFX6-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4473; GFX6-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4474; GFX6-NEXT:    v_lshr_b64 v[0:1], v[0:1], s2
4475; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4476; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
4477; GFX6-NEXT:    v_or_b32_e32 v1, s1, v1
4478; GFX6-NEXT:    ; return to shader part epilog
4479;
4480; GFX8-LABEL: v_fshl_i64_svs:
4481; GFX8:       ; %bb.0:
4482; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 1, v[0:1]
4483; GFX8-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4484; GFX8-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4485; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s2, v[0:1]
4486; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4487; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
4488; GFX8-NEXT:    v_or_b32_e32 v1, s1, v1
4489; GFX8-NEXT:    ; return to shader part epilog
4490;
4491; GFX9-LABEL: v_fshl_i64_svs:
4492; GFX9:       ; %bb.0:
4493; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 1, v[0:1]
4494; GFX9-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4495; GFX9-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4496; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s2, v[0:1]
4497; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
4498; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
4499; GFX9-NEXT:    v_or_b32_e32 v1, s1, v1
4500; GFX9-NEXT:    ; return to shader part epilog
4501;
4502; GFX10-LABEL: v_fshl_i64_svs:
4503; GFX10:       ; %bb.0:
4504; GFX10-NEXT:    v_lshrrev_b64 v[0:1], 1, v[0:1]
4505; GFX10-NEXT:    s_andn2_b64 s[4:5], 63, s[2:3]
4506; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], 63
4507; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
4508; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s4, v[0:1]
4509; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
4510; GFX10-NEXT:    v_or_b32_e32 v1, s1, v1
4511; GFX10-NEXT:    ; return to shader part epilog
4512  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
4513  %cast = bitcast i64 %result to <2 x float>
4514  ret <2 x float> %cast
4515}
4516
4517define amdgpu_ps <2 x float> @v_fshl_i64_vss(i64 %lhs, i64 inreg %rhs, i64 inreg %amt) {
4518; GFX6-LABEL: v_fshl_i64_vss:
4519; GFX6:       ; %bb.0:
4520; GFX6-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4521; GFX6-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4522; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
4523; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s4
4524; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
4525; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0
4526; GFX6-NEXT:    v_or_b32_e32 v1, s1, v1
4527; GFX6-NEXT:    ; return to shader part epilog
4528;
4529; GFX8-LABEL: v_fshl_i64_vss:
4530; GFX8:       ; %bb.0:
4531; GFX8-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4532; GFX8-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4533; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
4534; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
4535; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
4536; GFX8-NEXT:    v_or_b32_e32 v0, s0, v0
4537; GFX8-NEXT:    v_or_b32_e32 v1, s1, v1
4538; GFX8-NEXT:    ; return to shader part epilog
4539;
4540; GFX9-LABEL: v_fshl_i64_vss:
4541; GFX9:       ; %bb.0:
4542; GFX9-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4543; GFX9-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4544; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
4545; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
4546; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
4547; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
4548; GFX9-NEXT:    v_or_b32_e32 v1, s1, v1
4549; GFX9-NEXT:    ; return to shader part epilog
4550;
4551; GFX10-LABEL: v_fshl_i64_vss:
4552; GFX10:       ; %bb.0:
4553; GFX10-NEXT:    s_and_b64 s[4:5], s[2:3], 63
4554; GFX10-NEXT:    s_andn2_b64 s[2:3], 63, s[2:3]
4555; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s4, v[0:1]
4556; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], 1
4557; GFX10-NEXT:    s_lshr_b64 s[0:1], s[0:1], s2
4558; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
4559; GFX10-NEXT:    v_or_b32_e32 v1, s1, v1
4560; GFX10-NEXT:    ; return to shader part epilog
4561  %result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 %amt)
4562  %cast = bitcast i64 %result to <2 x float>
4563  ret <2 x float> %cast
4564}
4565
4566define amdgpu_ps <2 x i64> @s_fshl_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs, <2 x i64> inreg %amt) {
4567; GFX6-LABEL: s_fshl_v2i64:
4568; GFX6:       ; %bb.0:
4569; GFX6-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4570; GFX6-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4571; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], 1
4572; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4573; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s12
4574; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4575; GFX6-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4576; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
4577; GFX6-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4578; GFX6-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
4579; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4580; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4581; GFX6-NEXT:    ; return to shader part epilog
4582;
4583; GFX8-LABEL: s_fshl_v2i64:
4584; GFX8:       ; %bb.0:
4585; GFX8-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4586; GFX8-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4587; GFX8-NEXT:    s_lshr_b64 s[4:5], s[4:5], 1
4588; GFX8-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4589; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s12
4590; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4591; GFX8-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4592; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
4593; GFX8-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4594; GFX8-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
4595; GFX8-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4596; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4597; GFX8-NEXT:    ; return to shader part epilog
4598;
4599; GFX9-LABEL: s_fshl_v2i64:
4600; GFX9:       ; %bb.0:
4601; GFX9-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4602; GFX9-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4603; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 1
4604; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4605; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s12
4606; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4607; GFX9-NEXT:    s_and_b64 s[4:5], s[10:11], 63
4608; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
4609; GFX9-NEXT:    s_andn2_b64 s[8:9], 63, s[10:11]
4610; GFX9-NEXT:    s_lshr_b64 s[4:5], s[6:7], 1
4611; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4612; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4613; GFX9-NEXT:    ; return to shader part epilog
4614;
4615; GFX10-LABEL: s_fshl_v2i64:
4616; GFX10:       ; %bb.0:
4617; GFX10-NEXT:    s_and_b64 s[12:13], s[8:9], 63
4618; GFX10-NEXT:    s_andn2_b64 s[8:9], 63, s[8:9]
4619; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], 1
4620; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], 1
4621; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], s8
4622; GFX10-NEXT:    s_and_b64 s[8:9], s[10:11], 63
4623; GFX10-NEXT:    s_andn2_b64 s[10:11], 63, s[10:11]
4624; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s12
4625; GFX10-NEXT:    s_lshl_b64 s[2:3], s[2:3], s8
4626; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s10
4627; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
4628; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
4629; GFX10-NEXT:    ; return to shader part epilog
4630  %result = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
4631  ret <2 x i64> %result
4632}
4633
4634define <2 x i64> @v_fshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
4635; GFX6-LABEL: v_fshl_v2i64:
4636; GFX6:       ; %bb.0:
4637; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4638; GFX6-NEXT:    v_and_b32_e32 v9, 63, v8
4639; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4640; GFX6-NEXT:    v_lshr_b64 v[4:5], v[4:5], 1
4641; GFX6-NEXT:    v_and_b32_e32 v8, 63, v8
4642; GFX6-NEXT:    v_lshr_b64 v[4:5], v[4:5], v8
4643; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v9
4644; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v10
4645; GFX6-NEXT:    v_lshr_b64 v[6:7], v[6:7], 1
4646; GFX6-NEXT:    v_or_b32_e32 v0, v0, v4
4647; GFX6-NEXT:    v_and_b32_e32 v4, 63, v10
4648; GFX6-NEXT:    v_and_b32_e32 v8, 63, v8
4649; GFX6-NEXT:    v_lshl_b64 v[2:3], v[2:3], v4
4650; GFX6-NEXT:    v_lshr_b64 v[6:7], v[6:7], v8
4651; GFX6-NEXT:    v_or_b32_e32 v1, v1, v5
4652; GFX6-NEXT:    v_or_b32_e32 v2, v2, v6
4653; GFX6-NEXT:    v_or_b32_e32 v3, v3, v7
4654; GFX6-NEXT:    s_setpc_b64 s[30:31]
4655;
4656; GFX8-LABEL: v_fshl_v2i64:
4657; GFX8:       ; %bb.0:
4658; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4659; GFX8-NEXT:    v_and_b32_e32 v9, 63, v8
4660; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
4661; GFX8-NEXT:    v_lshrrev_b64 v[4:5], 1, v[4:5]
4662; GFX8-NEXT:    v_and_b32_e32 v8, 63, v8
4663; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]
4664; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v9, v[0:1]
4665; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v10
4666; GFX8-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
4667; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
4668; GFX8-NEXT:    v_and_b32_e32 v4, 63, v10
4669; GFX8-NEXT:    v_and_b32_e32 v8, 63, v8
4670; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v4, v[2:3]
4671; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v8, v[6:7]
4672; GFX8-NEXT:    v_or_b32_e32 v1, v1, v5
4673; GFX8-NEXT:    v_or_b32_e32 v2, v2, v6
4674; GFX8-NEXT:    v_or_b32_e32 v3, v3, v7
4675; GFX8-NEXT:    s_setpc_b64 s[30:31]
4676;
4677; GFX9-LABEL: v_fshl_v2i64:
4678; GFX9:       ; %bb.0:
4679; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4680; GFX9-NEXT:    v_and_b32_e32 v9, 63, v8
4681; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
4682; GFX9-NEXT:    v_lshrrev_b64 v[4:5], 1, v[4:5]
4683; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
4684; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]
4685; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v9, v[0:1]
4686; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v10
4687; GFX9-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
4688; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
4689; GFX9-NEXT:    v_and_b32_e32 v4, 63, v10
4690; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
4691; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v4, v[2:3]
4692; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v8, v[6:7]
4693; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
4694; GFX9-NEXT:    v_or_b32_e32 v2, v2, v6
4695; GFX9-NEXT:    v_or_b32_e32 v3, v3, v7
4696; GFX9-NEXT:    s_setpc_b64 s[30:31]
4697;
4698; GFX10-LABEL: v_fshl_v2i64:
4699; GFX10:       ; %bb.0:
4700; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4701; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
4702; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v8
4703; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v10
4704; GFX10-NEXT:    v_lshrrev_b64 v[4:5], 1, v[4:5]
4705; GFX10-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
4706; GFX10-NEXT:    v_and_b32_e32 v8, 63, v8
4707; GFX10-NEXT:    v_and_b32_e32 v9, 63, v9
4708; GFX10-NEXT:    v_and_b32_e32 v10, 63, v10
4709; GFX10-NEXT:    v_and_b32_e32 v11, 63, v11
4710; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
4711; GFX10-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
4712; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v10, v[2:3]
4713; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v11, v[6:7]
4714; GFX10-NEXT:    v_or_b32_e32 v0, v0, v4
4715; GFX10-NEXT:    v_or_b32_e32 v1, v1, v5
4716; GFX10-NEXT:    v_or_b32_e32 v2, v2, v6
4717; GFX10-NEXT:    v_or_b32_e32 v3, v3, v7
4718; GFX10-NEXT:    s_setpc_b64 s[30:31]
4719  %result = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt)
4720  ret <2 x i64> %result
4721}
4722
4723define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg %amt) {
4724; GFX6-LABEL: s_fshl_i128:
4725; GFX6:       ; %bb.0:
4726; GFX6-NEXT:    s_movk_i32 s10, 0x7f
4727; GFX6-NEXT:    s_mov_b32 s11, 0
4728; GFX6-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4729; GFX6-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4730; GFX6-NEXT:    s_sub_i32 s9, s12, 64
4731; GFX6-NEXT:    s_sub_i32 s13, 64, s12
4732; GFX6-NEXT:    s_cmp_lt_u32 s12, 64
4733; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4734; GFX6-NEXT:    s_cmp_eq_u32 s12, 0
4735; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
4736; GFX6-NEXT:    s_lshl_b64 s[10:11], s[0:1], s12
4737; GFX6-NEXT:    s_lshr_b64 s[14:15], s[0:1], s13
4738; GFX6-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
4739; GFX6-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
4740; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4741; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4742; GFX6-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
4743; GFX6-NEXT:    s_cselect_b64 s[0:1], s[12:13], s[0:1]
4744; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
4745; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
4746; GFX6-NEXT:    s_sub_i32 s9, 1, 64
4747; GFX6-NEXT:    s_sub_i32 s14, 64, 1
4748; GFX6-NEXT:    s_cmp_lt_u32 1, 64
4749; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4750; GFX6-NEXT:    s_cmp_eq_u32 1, 0
4751; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
4752; GFX6-NEXT:    s_lshr_b64 s[12:13], s[4:5], 1
4753; GFX6-NEXT:    s_lshl_b64 s[14:15], s[6:7], s14
4754; GFX6-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
4755; GFX6-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
4756; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s9
4757; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4758; GFX6-NEXT:    s_cselect_b64 s[6:7], s[12:13], s[6:7]
4759; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
4760; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4761; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4762; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
4763; GFX6-NEXT:    s_sub_i32 s14, s8, 64
4764; GFX6-NEXT:    s_sub_i32 s12, 64, s8
4765; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
4766; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
4767; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
4768; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
4769; GFX6-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
4770; GFX6-NEXT:    s_lshl_b64 s[12:13], s[0:1], s12
4771; GFX6-NEXT:    s_lshr_b64 s[8:9], s[4:5], s8
4772; GFX6-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
4773; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], s14
4774; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
4775; GFX6-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
4776; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
4777; GFX6-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
4778; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
4779; GFX6-NEXT:    s_cselect_b64 s[4:5], s[6:7], 0
4780; GFX6-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
4781; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4782; GFX6-NEXT:    ; return to shader part epilog
4783;
4784; GFX8-LABEL: s_fshl_i128:
4785; GFX8:       ; %bb.0:
4786; GFX8-NEXT:    s_movk_i32 s10, 0x7f
4787; GFX8-NEXT:    s_mov_b32 s11, 0
4788; GFX8-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4789; GFX8-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4790; GFX8-NEXT:    s_sub_i32 s9, s12, 64
4791; GFX8-NEXT:    s_sub_i32 s13, 64, s12
4792; GFX8-NEXT:    s_cmp_lt_u32 s12, 64
4793; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4794; GFX8-NEXT:    s_cmp_eq_u32 s12, 0
4795; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
4796; GFX8-NEXT:    s_lshl_b64 s[10:11], s[0:1], s12
4797; GFX8-NEXT:    s_lshr_b64 s[14:15], s[0:1], s13
4798; GFX8-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
4799; GFX8-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
4800; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4801; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4802; GFX8-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
4803; GFX8-NEXT:    s_cselect_b64 s[0:1], s[12:13], s[0:1]
4804; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
4805; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
4806; GFX8-NEXT:    s_sub_i32 s9, 1, 64
4807; GFX8-NEXT:    s_sub_i32 s14, 64, 1
4808; GFX8-NEXT:    s_cmp_lt_u32 1, 64
4809; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4810; GFX8-NEXT:    s_cmp_eq_u32 1, 0
4811; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
4812; GFX8-NEXT:    s_lshr_b64 s[12:13], s[4:5], 1
4813; GFX8-NEXT:    s_lshl_b64 s[14:15], s[6:7], s14
4814; GFX8-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
4815; GFX8-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
4816; GFX8-NEXT:    s_lshr_b64 s[6:7], s[6:7], s9
4817; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4818; GFX8-NEXT:    s_cselect_b64 s[6:7], s[12:13], s[6:7]
4819; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
4820; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4821; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4822; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
4823; GFX8-NEXT:    s_sub_i32 s14, s8, 64
4824; GFX8-NEXT:    s_sub_i32 s12, 64, s8
4825; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
4826; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
4827; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
4828; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
4829; GFX8-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
4830; GFX8-NEXT:    s_lshl_b64 s[12:13], s[0:1], s12
4831; GFX8-NEXT:    s_lshr_b64 s[8:9], s[4:5], s8
4832; GFX8-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
4833; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], s14
4834; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
4835; GFX8-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
4836; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
4837; GFX8-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
4838; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
4839; GFX8-NEXT:    s_cselect_b64 s[4:5], s[6:7], 0
4840; GFX8-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
4841; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4842; GFX8-NEXT:    ; return to shader part epilog
4843;
4844; GFX9-LABEL: s_fshl_i128:
4845; GFX9:       ; %bb.0:
4846; GFX9-NEXT:    s_movk_i32 s10, 0x7f
4847; GFX9-NEXT:    s_mov_b32 s11, 0
4848; GFX9-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4849; GFX9-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4850; GFX9-NEXT:    s_sub_i32 s9, s12, 64
4851; GFX9-NEXT:    s_sub_i32 s13, 64, s12
4852; GFX9-NEXT:    s_cmp_lt_u32 s12, 64
4853; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
4854; GFX9-NEXT:    s_cmp_eq_u32 s12, 0
4855; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
4856; GFX9-NEXT:    s_lshl_b64 s[10:11], s[0:1], s12
4857; GFX9-NEXT:    s_lshr_b64 s[14:15], s[0:1], s13
4858; GFX9-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
4859; GFX9-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
4860; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4861; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
4862; GFX9-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
4863; GFX9-NEXT:    s_cselect_b64 s[0:1], s[12:13], s[0:1]
4864; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
4865; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
4866; GFX9-NEXT:    s_sub_i32 s9, 1, 64
4867; GFX9-NEXT:    s_sub_i32 s14, 64, 1
4868; GFX9-NEXT:    s_cmp_lt_u32 1, 64
4869; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
4870; GFX9-NEXT:    s_cmp_eq_u32 1, 0
4871; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
4872; GFX9-NEXT:    s_lshr_b64 s[12:13], s[4:5], 1
4873; GFX9-NEXT:    s_lshl_b64 s[14:15], s[6:7], s14
4874; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
4875; GFX9-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
4876; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s9
4877; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
4878; GFX9-NEXT:    s_cselect_b64 s[6:7], s[12:13], s[6:7]
4879; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
4880; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
4881; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
4882; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
4883; GFX9-NEXT:    s_sub_i32 s14, s8, 64
4884; GFX9-NEXT:    s_sub_i32 s12, 64, s8
4885; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
4886; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
4887; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
4888; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
4889; GFX9-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
4890; GFX9-NEXT:    s_lshl_b64 s[12:13], s[0:1], s12
4891; GFX9-NEXT:    s_lshr_b64 s[8:9], s[4:5], s8
4892; GFX9-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
4893; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s14
4894; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
4895; GFX9-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
4896; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
4897; GFX9-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
4898; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
4899; GFX9-NEXT:    s_cselect_b64 s[4:5], s[6:7], 0
4900; GFX9-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
4901; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4902; GFX9-NEXT:    ; return to shader part epilog
4903;
4904; GFX10-LABEL: s_fshl_i128:
4905; GFX10:       ; %bb.0:
4906; GFX10-NEXT:    s_movk_i32 s10, 0x7f
4907; GFX10-NEXT:    s_mov_b32 s11, 0
4908; GFX10-NEXT:    s_and_b64 s[12:13], s[8:9], s[10:11]
4909; GFX10-NEXT:    s_andn2_b64 s[8:9], s[10:11], s[8:9]
4910; GFX10-NEXT:    s_sub_i32 s9, s12, 64
4911; GFX10-NEXT:    s_sub_i32 s10, 64, s12
4912; GFX10-NEXT:    s_cmp_lt_u32 s12, 64
4913; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
4914; GFX10-NEXT:    s_cmp_eq_u32 s12, 0
4915; GFX10-NEXT:    s_cselect_b32 s17, 1, 0
4916; GFX10-NEXT:    s_lshl_b64 s[14:15], s[2:3], s12
4917; GFX10-NEXT:    s_lshr_b64 s[10:11], s[0:1], s10
4918; GFX10-NEXT:    s_lshl_b64 s[12:13], s[0:1], s12
4919; GFX10-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
4920; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s9
4921; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
4922; GFX10-NEXT:    s_cselect_b64 s[12:13], s[12:13], 0
4923; GFX10-NEXT:    s_cselect_b64 s[0:1], s[10:11], s[0:1]
4924; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
4925; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
4926; GFX10-NEXT:    s_sub_i32 s9, 1, 64
4927; GFX10-NEXT:    s_sub_i32 s10, 64, 1
4928; GFX10-NEXT:    s_cmp_lt_u32 1, 64
4929; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
4930; GFX10-NEXT:    s_cmp_eq_u32 1, 0
4931; GFX10-NEXT:    s_cselect_b32 s17, 1, 0
4932; GFX10-NEXT:    s_lshr_b64 s[0:1], s[4:5], 1
4933; GFX10-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
4934; GFX10-NEXT:    s_lshr_b64 s[14:15], s[6:7], 1
4935; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[10:11]
4936; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s9
4937; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
4938; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
4939; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
4940; GFX10-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
4941; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
4942; GFX10-NEXT:    s_cselect_b64 s[4:5], s[14:15], 0
4943; GFX10-NEXT:    s_sub_i32 s14, s8, 64
4944; GFX10-NEXT:    s_sub_i32 s9, 64, s8
4945; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
4946; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
4947; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
4948; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
4949; GFX10-NEXT:    s_lshr_b64 s[6:7], s[0:1], s8
4950; GFX10-NEXT:    s_lshl_b64 s[10:11], s[4:5], s9
4951; GFX10-NEXT:    s_lshr_b64 s[8:9], s[4:5], s8
4952; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
4953; GFX10-NEXT:    s_lshr_b64 s[4:5], s[4:5], s14
4954; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
4955; GFX10-NEXT:    s_cselect_b64 s[4:5], s[6:7], s[4:5]
4956; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
4957; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
4958; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
4959; GFX10-NEXT:    s_cselect_b64 s[4:5], s[8:9], 0
4960; GFX10-NEXT:    s_or_b64 s[0:1], s[12:13], s[0:1]
4961; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
4962; GFX10-NEXT:    ; return to shader part epilog
4963  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
4964  ret i128 %result
4965}
4966
4967define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
4968; GFX6-LABEL: v_fshl_i128:
4969; GFX6:       ; %bb.0:
4970; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4971; GFX6-NEXT:    s_movk_i32 s4, 0x7f
4972; GFX6-NEXT:    v_and_b32_e32 v14, s4, v8
4973; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v8
4974; GFX6-NEXT:    v_and_b32_e32 v15, s4, v8
4975; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, 64, v14
4976; GFX6-NEXT:    v_subrev_i32_e32 v16, vcc, 64, v14
4977; GFX6-NEXT:    v_lshr_b64 v[8:9], v[0:1], v8
4978; GFX6-NEXT:    v_lshl_b64 v[10:11], v[2:3], v14
4979; GFX6-NEXT:    v_lshl_b64 v[12:13], v[0:1], v14
4980; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v16
4981; GFX6-NEXT:    v_or_b32_e32 v8, v8, v10
4982; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
4983; GFX6-NEXT:    v_or_b32_e32 v9, v9, v11
4984; GFX6-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
4985; GFX6-NEXT:    v_cndmask_b32_e32 v11, 0, v13, vcc
4986; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
4987; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
4988; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v14
4989; GFX6-NEXT:    s_sub_i32 s4, 1, 64
4990; GFX6-NEXT:    s_sub_i32 s5, 64, 1
4991; GFX6-NEXT:    s_cmp_lt_u32 1, 64
4992; GFX6-NEXT:    v_cndmask_b32_e32 v12, v0, v2, vcc
4993; GFX6-NEXT:    v_cndmask_b32_e32 v13, v1, v3, vcc
4994; GFX6-NEXT:    v_lshr_b64 v[0:1], v[4:5], 1
4995; GFX6-NEXT:    v_lshl_b64 v[2:3], v[6:7], s5
4996; GFX6-NEXT:    s_cselect_b32 s6, 1, 0
4997; GFX6-NEXT:    s_cmp_eq_u32 1, 0
4998; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
4999; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5000; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5001; GFX6-NEXT:    v_lshr_b64 v[0:1], v[6:7], s4
5002; GFX6-NEXT:    s_and_b32 s4, 1, s6
5003; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5004; GFX6-NEXT:    s_and_b32 s4, 1, s7
5005; GFX6-NEXT:    v_lshr_b64 v[8:9], v[6:7], 1
5006; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5007; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5008; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5009; GFX6-NEXT:    s_and_b32 s4, 1, s6
5010; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
5011; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
5012; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5013; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5014; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5015; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 64, v15
5016; GFX6-NEXT:    v_subrev_i32_e32 v14, vcc, 64, v15
5017; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], v15
5018; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], v6
5019; GFX6-NEXT:    v_lshr_b64 v[8:9], v[2:3], v15
5020; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], v14
5021; GFX6-NEXT:    v_or_b32_e32 v4, v4, v6
5022; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
5023; GFX6-NEXT:    v_or_b32_e32 v5, v5, v7
5024; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5025; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v15
5026; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5027; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
5028; GFX6-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
5029; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5030; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5031; GFX6-NEXT:    v_or_b32_e32 v0, v10, v0
5032; GFX6-NEXT:    v_or_b32_e32 v1, v11, v1
5033; GFX6-NEXT:    v_or_b32_e32 v2, v12, v2
5034; GFX6-NEXT:    v_or_b32_e32 v3, v13, v3
5035; GFX6-NEXT:    s_setpc_b64 s[30:31]
5036;
5037; GFX8-LABEL: v_fshl_i128:
5038; GFX8:       ; %bb.0:
5039; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5040; GFX8-NEXT:    s_movk_i32 s4, 0x7f
5041; GFX8-NEXT:    v_and_b32_e32 v14, s4, v8
5042; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v8
5043; GFX8-NEXT:    v_and_b32_e32 v15, s4, v8
5044; GFX8-NEXT:    v_sub_u32_e32 v8, vcc, 64, v14
5045; GFX8-NEXT:    v_subrev_u32_e32 v16, vcc, 64, v14
5046; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v8, v[0:1]
5047; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v14, v[2:3]
5048; GFX8-NEXT:    v_lshlrev_b64 v[12:13], v14, v[0:1]
5049; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v16, v[0:1]
5050; GFX8-NEXT:    v_or_b32_e32 v8, v8, v10
5051; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
5052; GFX8-NEXT:    v_or_b32_e32 v9, v9, v11
5053; GFX8-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
5054; GFX8-NEXT:    v_cndmask_b32_e32 v11, 0, v13, vcc
5055; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
5056; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
5057; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v14
5058; GFX8-NEXT:    s_sub_i32 s4, 1, 64
5059; GFX8-NEXT:    s_sub_i32 s5, 64, 1
5060; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5061; GFX8-NEXT:    v_cndmask_b32_e32 v12, v0, v2, vcc
5062; GFX8-NEXT:    v_cndmask_b32_e32 v13, v1, v3, vcc
5063; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 1, v[4:5]
5064; GFX8-NEXT:    v_lshlrev_b64 v[2:3], s5, v[6:7]
5065; GFX8-NEXT:    s_cselect_b32 s6, 1, 0
5066; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5067; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5068; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5069; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5070; GFX8-NEXT:    v_lshrrev_b64 v[0:1], s4, v[6:7]
5071; GFX8-NEXT:    s_and_b32 s4, 1, s6
5072; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5073; GFX8-NEXT:    s_and_b32 s4, 1, s7
5074; GFX8-NEXT:    v_lshrrev_b64 v[8:9], 1, v[6:7]
5075; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5076; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5077; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5078; GFX8-NEXT:    s_and_b32 s4, 1, s6
5079; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
5080; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
5081; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5082; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5083; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5084; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 64, v15
5085; GFX8-NEXT:    v_subrev_u32_e32 v14, vcc, 64, v15
5086; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v15, v[0:1]
5087; GFX8-NEXT:    v_lshlrev_b64 v[6:7], v6, v[2:3]
5088; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v15, v[2:3]
5089; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v14, v[2:3]
5090; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
5091; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
5092; GFX8-NEXT:    v_or_b32_e32 v5, v5, v7
5093; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5094; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v15
5095; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5096; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
5097; GFX8-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
5098; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5099; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5100; GFX8-NEXT:    v_or_b32_e32 v0, v10, v0
5101; GFX8-NEXT:    v_or_b32_e32 v1, v11, v1
5102; GFX8-NEXT:    v_or_b32_e32 v2, v12, v2
5103; GFX8-NEXT:    v_or_b32_e32 v3, v13, v3
5104; GFX8-NEXT:    s_setpc_b64 s[30:31]
5105;
5106; GFX9-LABEL: v_fshl_i128:
5107; GFX9:       ; %bb.0:
5108; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5109; GFX9-NEXT:    s_movk_i32 s4, 0x7f
5110; GFX9-NEXT:    v_and_b32_e32 v14, s4, v8
5111; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v8
5112; GFX9-NEXT:    v_and_b32_e32 v15, s4, v8
5113; GFX9-NEXT:    v_sub_u32_e32 v8, 64, v14
5114; GFX9-NEXT:    v_subrev_u32_e32 v16, 64, v14
5115; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v8, v[0:1]
5116; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v14, v[2:3]
5117; GFX9-NEXT:    v_lshlrev_b64 v[12:13], v14, v[0:1]
5118; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v16, v[0:1]
5119; GFX9-NEXT:    v_or_b32_e32 v8, v8, v10
5120; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
5121; GFX9-NEXT:    v_or_b32_e32 v9, v9, v11
5122; GFX9-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
5123; GFX9-NEXT:    v_cndmask_b32_e32 v11, 0, v13, vcc
5124; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
5125; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
5126; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v14
5127; GFX9-NEXT:    s_sub_i32 s4, 1, 64
5128; GFX9-NEXT:    s_sub_i32 s5, 64, 1
5129; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5130; GFX9-NEXT:    v_cndmask_b32_e32 v12, v0, v2, vcc
5131; GFX9-NEXT:    v_cndmask_b32_e32 v13, v1, v3, vcc
5132; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 1, v[4:5]
5133; GFX9-NEXT:    v_lshlrev_b64 v[2:3], s5, v[6:7]
5134; GFX9-NEXT:    s_cselect_b32 s6, 1, 0
5135; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5136; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
5137; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5138; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5139; GFX9-NEXT:    v_lshrrev_b64 v[0:1], s4, v[6:7]
5140; GFX9-NEXT:    s_and_b32 s4, 1, s6
5141; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5142; GFX9-NEXT:    s_and_b32 s4, 1, s7
5143; GFX9-NEXT:    v_lshrrev_b64 v[8:9], 1, v[6:7]
5144; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5145; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5146; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5147; GFX9-NEXT:    s_and_b32 s4, 1, s6
5148; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
5149; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
5150; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
5151; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5152; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5153; GFX9-NEXT:    v_sub_u32_e32 v6, 64, v15
5154; GFX9-NEXT:    v_subrev_u32_e32 v14, 64, v15
5155; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v15, v[0:1]
5156; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v6, v[2:3]
5157; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v15, v[2:3]
5158; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v14, v[2:3]
5159; GFX9-NEXT:    v_or_b32_e32 v4, v4, v6
5160; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v15
5161; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
5162; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5163; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v15
5164; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5165; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
5166; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
5167; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5168; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5169; GFX9-NEXT:    v_or_b32_e32 v0, v10, v0
5170; GFX9-NEXT:    v_or_b32_e32 v1, v11, v1
5171; GFX9-NEXT:    v_or_b32_e32 v2, v12, v2
5172; GFX9-NEXT:    v_or_b32_e32 v3, v13, v3
5173; GFX9-NEXT:    s_setpc_b64 s[30:31]
5174;
5175; GFX10-LABEL: v_fshl_i128:
5176; GFX10:       ; %bb.0:
5177; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
5178; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
5179; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v8
5180; GFX10-NEXT:    s_movk_i32 s4, 0x7f
5181; GFX10-NEXT:    v_and_b32_e32 v18, s4, v8
5182; GFX10-NEXT:    v_and_b32_e32 v19, s4, v9
5183; GFX10-NEXT:    s_sub_i32 s4, 64, 1
5184; GFX10-NEXT:    v_lshrrev_b64 v[8:9], 1, v[4:5]
5185; GFX10-NEXT:    v_lshlrev_b64 v[10:11], s4, v[6:7]
5186; GFX10-NEXT:    s_sub_i32 s4, 1, 64
5187; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5188; GFX10-NEXT:    v_lshrrev_b64 v[12:13], s4, v[6:7]
5189; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
5190; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5191; GFX10-NEXT:    v_or_b32_e32 v8, v8, v10
5192; GFX10-NEXT:    v_or_b32_e32 v9, v9, v11
5193; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
5194; GFX10-NEXT:    s_and_b32 s5, 1, vcc_lo
5195; GFX10-NEXT:    s_and_b32 s4, 1, s4
5196; GFX10-NEXT:    v_sub_nc_u32_e32 v14, 64, v18
5197; GFX10-NEXT:    v_lshrrev_b64 v[6:7], 1, v[6:7]
5198; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v8, vcc_lo
5199; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v9, vcc_lo
5200; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
5201; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
5202; GFX10-NEXT:    v_lshrrev_b64 v[8:9], v14, v[0:1]
5203; GFX10-NEXT:    v_lshlrev_b64 v[10:11], v18, v[2:3]
5204; GFX10-NEXT:    v_sub_nc_u32_e32 v16, 64, v19
5205; GFX10-NEXT:    v_cndmask_b32_e32 v4, v12, v4, vcc_lo
5206; GFX10-NEXT:    v_cndmask_b32_e32 v5, v13, v5, vcc_lo
5207; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, v6, s4
5208; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, v7, s4
5209; GFX10-NEXT:    v_subrev_nc_u32_e32 v20, 64, v18
5210; GFX10-NEXT:    v_or_b32_e32 v10, v8, v10
5211; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, 64, v19
5212; GFX10-NEXT:    v_lshrrev_b64 v[14:15], v19, v[4:5]
5213; GFX10-NEXT:    v_lshlrev_b64 v[16:17], v16, v[6:7]
5214; GFX10-NEXT:    v_lshlrev_b64 v[12:13], v18, v[0:1]
5215; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v20, v[0:1]
5216; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v18
5217; GFX10-NEXT:    v_or_b32_e32 v11, v9, v11
5218; GFX10-NEXT:    v_lshrrev_b64 v[8:9], v8, v[6:7]
5219; GFX10-NEXT:    v_or_b32_e32 v14, v14, v16
5220; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v19
5221; GFX10-NEXT:    v_or_b32_e32 v15, v15, v17
5222; GFX10-NEXT:    v_cndmask_b32_e32 v10, v0, v10, vcc_lo
5223; GFX10-NEXT:    v_cndmask_b32_e32 v11, v1, v11, vcc_lo
5224; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v19, v[6:7]
5225; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v18
5226; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v14, s4
5227; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v19
5228; GFX10-NEXT:    v_cndmask_b32_e64 v6, v9, v15, s4
5229; GFX10-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc_lo
5230; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0, v13, vcc_lo
5231; GFX10-NEXT:    v_cndmask_b32_e64 v2, v10, v2, s6
5232; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s5
5233; GFX10-NEXT:    v_cndmask_b32_e64 v5, v6, v5, s5
5234; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, v0, s4
5235; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, v1, s4
5236; GFX10-NEXT:    v_cndmask_b32_e64 v3, v11, v3, s6
5237; GFX10-NEXT:    v_or_b32_e32 v0, v12, v4
5238; GFX10-NEXT:    v_or_b32_e32 v1, v7, v5
5239; GFX10-NEXT:    v_or_b32_e32 v2, v2, v6
5240; GFX10-NEXT:    v_or_b32_e32 v3, v3, v8
5241; GFX10-NEXT:    s_setpc_b64 s[30:31]
5242  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
5243  ret i128 %result
5244}
5245
5246define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs, i128 %amt) {
5247; GFX6-LABEL: v_fshl_i128_ssv:
5248; GFX6:       ; %bb.0:
5249; GFX6-NEXT:    s_movk_i32 s8, 0x7f
5250; GFX6-NEXT:    v_and_b32_e32 v6, s8, v0
5251; GFX6-NEXT:    v_xor_b32_e32 v0, -1, v0
5252; GFX6-NEXT:    v_and_b32_e32 v7, s8, v0
5253; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, 64, v6
5254; GFX6-NEXT:    v_lshr_b64 v[0:1], s[0:1], v0
5255; GFX6-NEXT:    v_lshl_b64 v[2:3], s[2:3], v6
5256; GFX6-NEXT:    v_subrev_i32_e32 v8, vcc, 64, v6
5257; GFX6-NEXT:    s_sub_i32 s10, 1, 64
5258; GFX6-NEXT:    s_sub_i32 s8, 64, 1
5259; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5260; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5261; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5262; GFX6-NEXT:    v_lshl_b64 v[0:1], s[0:1], v8
5263; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5264; GFX6-NEXT:    s_cselect_b32 s11, 1, 0
5265; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5266; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5267; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5268; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5269; GFX6-NEXT:    v_mov_b32_e32 v2, s2
5270; GFX6-NEXT:    v_mov_b32_e32 v3, s3
5271; GFX6-NEXT:    s_lshr_b64 s[2:3], s[4:5], 1
5272; GFX6-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
5273; GFX6-NEXT:    v_lshl_b64 v[4:5], s[0:1], v6
5274; GFX6-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
5275; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
5276; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s10
5277; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5278; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[6:7]
5279; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5280; GFX6-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5281; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5282; GFX6-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5283; GFX6-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5284; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
5285; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
5286; GFX6-NEXT:    v_cndmask_b32_e32 v6, v0, v2, vcc
5287; GFX6-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5288; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 64, v7
5289; GFX6-NEXT:    v_lshr_b64 v[0:1], s[2:3], v7
5290; GFX6-NEXT:    v_lshl_b64 v[2:3], s[0:1], v2
5291; GFX6-NEXT:    v_subrev_i32_e32 v11, vcc, 64, v7
5292; GFX6-NEXT:    v_or_b32_e32 v2, v0, v2
5293; GFX6-NEXT:    v_or_b32_e32 v3, v1, v3
5294; GFX6-NEXT:    v_lshr_b64 v[0:1], s[0:1], v11
5295; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5296; GFX6-NEXT:    v_lshr_b64 v[4:5], s[0:1], v7
5297; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5298; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5299; GFX6-NEXT:    v_mov_b32_e32 v2, s2
5300; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v7
5301; GFX6-NEXT:    v_mov_b32_e32 v3, s3
5302; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5303; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5304; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5305; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5306; GFX6-NEXT:    v_or_b32_e32 v0, v8, v0
5307; GFX6-NEXT:    v_or_b32_e32 v1, v9, v1
5308; GFX6-NEXT:    v_or_b32_e32 v2, v6, v2
5309; GFX6-NEXT:    v_or_b32_e32 v3, v10, v3
5310; GFX6-NEXT:    ; return to shader part epilog
5311;
5312; GFX8-LABEL: v_fshl_i128_ssv:
5313; GFX8:       ; %bb.0:
5314; GFX8-NEXT:    s_movk_i32 s8, 0x7f
5315; GFX8-NEXT:    v_and_b32_e32 v6, s8, v0
5316; GFX8-NEXT:    v_xor_b32_e32 v0, -1, v0
5317; GFX8-NEXT:    v_and_b32_e32 v7, s8, v0
5318; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, 64, v6
5319; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v0, s[0:1]
5320; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v6, s[2:3]
5321; GFX8-NEXT:    v_subrev_u32_e32 v8, vcc, 64, v6
5322; GFX8-NEXT:    s_sub_i32 s10, 1, 64
5323; GFX8-NEXT:    s_sub_i32 s8, 64, 1
5324; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5325; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5326; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5327; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v8, s[0:1]
5328; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5329; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
5330; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5331; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5332; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5333; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5334; GFX8-NEXT:    v_mov_b32_e32 v2, s2
5335; GFX8-NEXT:    v_mov_b32_e32 v3, s3
5336; GFX8-NEXT:    s_lshr_b64 s[2:3], s[4:5], 1
5337; GFX8-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
5338; GFX8-NEXT:    v_lshlrev_b64 v[4:5], v6, s[0:1]
5339; GFX8-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
5340; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
5341; GFX8-NEXT:    s_lshr_b64 s[6:7], s[6:7], s10
5342; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
5343; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[6:7]
5344; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5345; GFX8-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5346; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
5347; GFX8-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5348; GFX8-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5349; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
5350; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
5351; GFX8-NEXT:    v_cndmask_b32_e32 v6, v0, v2, vcc
5352; GFX8-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5353; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 64, v7
5354; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v7, s[2:3]
5355; GFX8-NEXT:    v_lshlrev_b64 v[2:3], v2, s[0:1]
5356; GFX8-NEXT:    v_subrev_u32_e32 v11, vcc, 64, v7
5357; GFX8-NEXT:    v_or_b32_e32 v2, v0, v2
5358; GFX8-NEXT:    v_or_b32_e32 v3, v1, v3
5359; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v11, s[0:1]
5360; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5361; GFX8-NEXT:    v_lshrrev_b64 v[4:5], v7, s[0:1]
5362; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5363; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5364; GFX8-NEXT:    v_mov_b32_e32 v2, s2
5365; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v7
5366; GFX8-NEXT:    v_mov_b32_e32 v3, s3
5367; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5368; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5369; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5370; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5371; GFX8-NEXT:    v_or_b32_e32 v0, v8, v0
5372; GFX8-NEXT:    v_or_b32_e32 v1, v9, v1
5373; GFX8-NEXT:    v_or_b32_e32 v2, v6, v2
5374; GFX8-NEXT:    v_or_b32_e32 v3, v10, v3
5375; GFX8-NEXT:    ; return to shader part epilog
5376;
5377; GFX9-LABEL: v_fshl_i128_ssv:
5378; GFX9:       ; %bb.0:
5379; GFX9-NEXT:    s_movk_i32 s8, 0x7f
5380; GFX9-NEXT:    v_and_b32_e32 v6, s8, v0
5381; GFX9-NEXT:    v_xor_b32_e32 v0, -1, v0
5382; GFX9-NEXT:    v_and_b32_e32 v7, s8, v0
5383; GFX9-NEXT:    v_sub_u32_e32 v0, 64, v6
5384; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v0, s[0:1]
5385; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v6, s[2:3]
5386; GFX9-NEXT:    v_subrev_u32_e32 v8, 64, v6
5387; GFX9-NEXT:    s_sub_i32 s10, 1, 64
5388; GFX9-NEXT:    s_sub_i32 s8, 64, 1
5389; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5390; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5391; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5392; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, s[0:1]
5393; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
5394; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
5395; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5396; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5397; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5398; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5399; GFX9-NEXT:    v_mov_b32_e32 v2, s2
5400; GFX9-NEXT:    v_mov_b32_e32 v3, s3
5401; GFX9-NEXT:    s_lshr_b64 s[2:3], s[4:5], 1
5402; GFX9-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
5403; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v6, s[0:1]
5404; GFX9-NEXT:    s_lshr_b64 s[0:1], s[6:7], 1
5405; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
5406; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s10
5407; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
5408; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[6:7]
5409; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5410; GFX9-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5411; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
5412; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v4, vcc
5413; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
5414; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
5415; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v2, vcc
5416; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
5417; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v7
5418; GFX9-NEXT:    v_cndmask_b32_e32 v10, v1, v3, vcc
5419; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v7, s[2:3]
5420; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v2, s[0:1]
5421; GFX9-NEXT:    v_subrev_u32_e32 v11, 64, v7
5422; GFX9-NEXT:    v_or_b32_e32 v2, v0, v2
5423; GFX9-NEXT:    v_or_b32_e32 v3, v1, v3
5424; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v11, s[0:1]
5425; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v7
5426; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v7, s[0:1]
5427; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
5428; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
5429; GFX9-NEXT:    v_mov_b32_e32 v2, s2
5430; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v7
5431; GFX9-NEXT:    v_mov_b32_e32 v3, s3
5432; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
5433; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
5434; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
5435; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc
5436; GFX9-NEXT:    v_or_b32_e32 v0, v8, v0
5437; GFX9-NEXT:    v_or_b32_e32 v1, v9, v1
5438; GFX9-NEXT:    v_or_b32_e32 v2, v6, v2
5439; GFX9-NEXT:    v_or_b32_e32 v3, v10, v3
5440; GFX9-NEXT:    ; return to shader part epilog
5441;
5442; GFX10-LABEL: v_fshl_i128_ssv:
5443; GFX10:       ; %bb.0:
5444; GFX10-NEXT:    s_movk_i32 s8, 0x7f
5445; GFX10-NEXT:    s_sub_i32 s14, 1, 64
5446; GFX10-NEXT:    v_and_b32_e32 v12, s8, v0
5447; GFX10-NEXT:    v_xor_b32_e32 v0, -1, v0
5448; GFX10-NEXT:    s_sub_i32 s10, 64, 1
5449; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5450; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 64, v12
5451; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
5452; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5453; GFX10-NEXT:    v_and_b32_e32 v13, s8, v0
5454; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
5455; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v1, s[0:1]
5456; GFX10-NEXT:    v_lshlrev_b64 v[2:3], v12, s[2:3]
5457; GFX10-NEXT:    s_lshr_b64 s[8:9], s[4:5], 1
5458; GFX10-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
5459; GFX10-NEXT:    s_lshr_b64 s[12:13], s[6:7], 1
5460; GFX10-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
5461; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
5462; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
5463; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
5464; GFX10-NEXT:    s_cselect_b64 s[6:7], s[8:9], s[6:7]
5465; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
5466; GFX10-NEXT:    v_sub_nc_u32_e32 v0, 64, v13
5467; GFX10-NEXT:    s_cselect_b64 s[6:7], s[4:5], s[6:7]
5468; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
5469; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 64, v12
5470; GFX10-NEXT:    s_cselect_b64 s[8:9], s[12:13], 0
5471; GFX10-NEXT:    v_subrev_nc_u32_e32 v14, 64, v13
5472; GFX10-NEXT:    v_lshrrev_b64 v[6:7], v13, s[6:7]
5473; GFX10-NEXT:    v_lshlrev_b64 v[8:9], v0, s[8:9]
5474; GFX10-NEXT:    v_lshlrev_b64 v[10:11], v10, s[0:1]
5475; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
5476; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v12
5477; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v14, s[8:9]
5478; GFX10-NEXT:    v_lshlrev_b64 v[4:5], v12, s[0:1]
5479; GFX10-NEXT:    v_or_b32_e32 v6, v6, v8
5480; GFX10-NEXT:    v_cmp_gt_u32_e64 s0, 64, v13
5481; GFX10-NEXT:    v_or_b32_e32 v7, v7, v9
5482; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc_lo
5483; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v3, vcc_lo
5484; GFX10-NEXT:    v_lshrrev_b64 v[2:3], v13, s[8:9]
5485; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s0
5486; GFX10-NEXT:    v_cmp_eq_u32_e64 s1, 0, v13
5487; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v7, s0
5488; GFX10-NEXT:    v_cmp_eq_u32_e64 s4, 0, v12
5489; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc_lo
5490; GFX10-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc_lo
5491; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, s6, s1
5492; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s7, s1
5493; GFX10-NEXT:    v_cndmask_b32_e64 v6, v8, s2, s4
5494; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5495; GFX10-NEXT:    v_cndmask_b32_e64 v7, v10, s3, s4
5496; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5497; GFX10-NEXT:    v_or_b32_e32 v0, v4, v0
5498; GFX10-NEXT:    v_or_b32_e32 v1, v5, v1
5499; GFX10-NEXT:    v_or_b32_e32 v2, v6, v2
5500; GFX10-NEXT:    v_or_b32_e32 v3, v7, v3
5501; GFX10-NEXT:    ; return to shader part epilog
5502  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
5503  %cast.result = bitcast i128 %result to <4 x float>
5504  ret <4 x float> %cast.result
5505}
5506
5507define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 inreg %amt) {
5508; GFX6-LABEL: v_fshl_i128_svs:
5509; GFX6:       ; %bb.0:
5510; GFX6-NEXT:    s_movk_i32 s6, 0x7f
5511; GFX6-NEXT:    s_mov_b32 s7, 0
5512; GFX6-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5513; GFX6-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5514; GFX6-NEXT:    s_sub_i32 s5, s8, 64
5515; GFX6-NEXT:    s_sub_i32 s9, 64, s8
5516; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5517; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5518; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5519; GFX6-NEXT:    s_cselect_b32 s13, 1, 0
5520; GFX6-NEXT:    s_lshl_b64 s[6:7], s[0:1], s8
5521; GFX6-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
5522; GFX6-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
5523; GFX6-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
5524; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5525; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5526; GFX6-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5527; GFX6-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
5528; GFX6-NEXT:    s_cmp_lg_u32 s13, 0
5529; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
5530; GFX6-NEXT:    s_sub_i32 s1, 64, 1
5531; GFX6-NEXT:    s_sub_i32 s0, 1, 64
5532; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5533; GFX6-NEXT:    s_cselect_b32 s5, 1, 0
5534; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5535; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], 1
5536; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], s1
5537; GFX6-NEXT:    v_lshr_b64 v[8:9], v[2:3], 1
5538; GFX6-NEXT:    s_cselect_b32 s8, 1, 0
5539; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], s0
5540; GFX6-NEXT:    s_and_b32 s0, 1, s5
5541; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5542; GFX6-NEXT:    s_and_b32 s0, 1, s8
5543; GFX6-NEXT:    v_or_b32_e32 v4, v4, v6
5544; GFX6-NEXT:    v_or_b32_e32 v5, v5, v7
5545; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5546; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, s0
5547; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5548; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
5549; GFX6-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
5550; GFX6-NEXT:    s_sub_i32 s0, s4, 64
5551; GFX6-NEXT:    s_sub_i32 s1, 64, s4
5552; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
5553; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5554; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5555; GFX6-NEXT:    s_cselect_b32 s5, 1, 0
5556; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
5557; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], s4
5558; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], s1
5559; GFX6-NEXT:    v_lshr_b64 v[8:9], v[2:3], s4
5560; GFX6-NEXT:    s_cselect_b32 s8, 1, 0
5561; GFX6-NEXT:    v_lshr_b64 v[2:3], v[2:3], s0
5562; GFX6-NEXT:    s_and_b32 s0, 1, s5
5563; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5564; GFX6-NEXT:    v_or_b32_e32 v4, v4, v6
5565; GFX6-NEXT:    v_or_b32_e32 v5, v5, v7
5566; GFX6-NEXT:    s_and_b32 s0, 1, s8
5567; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5568; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5569; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5570; GFX6-NEXT:    s_and_b32 s0, 1, s5
5571; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5572; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5573; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5574; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5575; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5576; GFX6-NEXT:    v_or_b32_e32 v0, s6, v0
5577; GFX6-NEXT:    v_or_b32_e32 v1, s7, v1
5578; GFX6-NEXT:    v_or_b32_e32 v2, s2, v2
5579; GFX6-NEXT:    v_or_b32_e32 v3, s3, v3
5580; GFX6-NEXT:    ; return to shader part epilog
5581;
5582; GFX8-LABEL: v_fshl_i128_svs:
5583; GFX8:       ; %bb.0:
5584; GFX8-NEXT:    s_movk_i32 s6, 0x7f
5585; GFX8-NEXT:    s_mov_b32 s7, 0
5586; GFX8-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5587; GFX8-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5588; GFX8-NEXT:    s_sub_i32 s5, s8, 64
5589; GFX8-NEXT:    s_sub_i32 s9, 64, s8
5590; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
5591; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5592; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
5593; GFX8-NEXT:    s_cselect_b32 s13, 1, 0
5594; GFX8-NEXT:    s_lshl_b64 s[6:7], s[0:1], s8
5595; GFX8-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
5596; GFX8-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
5597; GFX8-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
5598; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5599; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5600; GFX8-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5601; GFX8-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
5602; GFX8-NEXT:    s_cmp_lg_u32 s13, 0
5603; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
5604; GFX8-NEXT:    s_sub_i32 s1, 64, 1
5605; GFX8-NEXT:    s_sub_i32 s0, 1, 64
5606; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5607; GFX8-NEXT:    s_cselect_b32 s5, 1, 0
5608; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5609; GFX8-NEXT:    v_lshrrev_b64 v[4:5], 1, v[0:1]
5610; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s1, v[2:3]
5611; GFX8-NEXT:    v_lshrrev_b64 v[8:9], 1, v[2:3]
5612; GFX8-NEXT:    s_cselect_b32 s8, 1, 0
5613; GFX8-NEXT:    v_lshrrev_b64 v[2:3], s0, v[2:3]
5614; GFX8-NEXT:    s_and_b32 s0, 1, s5
5615; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5616; GFX8-NEXT:    s_and_b32 s0, 1, s8
5617; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
5618; GFX8-NEXT:    v_or_b32_e32 v5, v5, v7
5619; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5620; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, s0
5621; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5622; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
5623; GFX8-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
5624; GFX8-NEXT:    s_sub_i32 s0, s4, 64
5625; GFX8-NEXT:    s_sub_i32 s1, 64, s4
5626; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
5627; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5628; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5629; GFX8-NEXT:    s_cselect_b32 s5, 1, 0
5630; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
5631; GFX8-NEXT:    v_lshrrev_b64 v[4:5], s4, v[0:1]
5632; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s1, v[2:3]
5633; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s4, v[2:3]
5634; GFX8-NEXT:    s_cselect_b32 s8, 1, 0
5635; GFX8-NEXT:    v_lshrrev_b64 v[2:3], s0, v[2:3]
5636; GFX8-NEXT:    s_and_b32 s0, 1, s5
5637; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5638; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
5639; GFX8-NEXT:    v_or_b32_e32 v5, v5, v7
5640; GFX8-NEXT:    s_and_b32 s0, 1, s8
5641; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5642; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5643; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5644; GFX8-NEXT:    s_and_b32 s0, 1, s5
5645; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5646; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5647; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5648; GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5649; GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5650; GFX8-NEXT:    v_or_b32_e32 v0, s6, v0
5651; GFX8-NEXT:    v_or_b32_e32 v1, s7, v1
5652; GFX8-NEXT:    v_or_b32_e32 v2, s2, v2
5653; GFX8-NEXT:    v_or_b32_e32 v3, s3, v3
5654; GFX8-NEXT:    ; return to shader part epilog
5655;
5656; GFX9-LABEL: v_fshl_i128_svs:
5657; GFX9:       ; %bb.0:
5658; GFX9-NEXT:    s_movk_i32 s6, 0x7f
5659; GFX9-NEXT:    s_mov_b32 s7, 0
5660; GFX9-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5661; GFX9-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5662; GFX9-NEXT:    s_sub_i32 s5, s8, 64
5663; GFX9-NEXT:    s_sub_i32 s9, 64, s8
5664; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
5665; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5666; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
5667; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
5668; GFX9-NEXT:    s_lshl_b64 s[6:7], s[0:1], s8
5669; GFX9-NEXT:    s_lshr_b64 s[10:11], s[0:1], s9
5670; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
5671; GFX9-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
5672; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5673; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5674; GFX9-NEXT:    s_cselect_b64 s[6:7], s[6:7], 0
5675; GFX9-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
5676; GFX9-NEXT:    s_cmp_lg_u32 s13, 0
5677; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
5678; GFX9-NEXT:    s_sub_i32 s1, 64, 1
5679; GFX9-NEXT:    s_sub_i32 s0, 1, 64
5680; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5681; GFX9-NEXT:    s_cselect_b32 s5, 1, 0
5682; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5683; GFX9-NEXT:    v_lshrrev_b64 v[4:5], 1, v[0:1]
5684; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s1, v[2:3]
5685; GFX9-NEXT:    v_lshrrev_b64 v[8:9], 1, v[2:3]
5686; GFX9-NEXT:    s_cselect_b32 s8, 1, 0
5687; GFX9-NEXT:    v_lshrrev_b64 v[2:3], s0, v[2:3]
5688; GFX9-NEXT:    s_and_b32 s0, 1, s5
5689; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5690; GFX9-NEXT:    s_and_b32 s0, 1, s8
5691; GFX9-NEXT:    v_or_b32_e32 v4, v4, v6
5692; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
5693; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5694; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, s0
5695; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5696; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
5697; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
5698; GFX9-NEXT:    s_sub_i32 s0, s4, 64
5699; GFX9-NEXT:    s_sub_i32 s1, 64, s4
5700; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
5701; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5702; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5703; GFX9-NEXT:    s_cselect_b32 s5, 1, 0
5704; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
5705; GFX9-NEXT:    v_lshrrev_b64 v[4:5], s4, v[0:1]
5706; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s1, v[2:3]
5707; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s4, v[2:3]
5708; GFX9-NEXT:    s_cselect_b32 s8, 1, 0
5709; GFX9-NEXT:    v_lshrrev_b64 v[2:3], s0, v[2:3]
5710; GFX9-NEXT:    s_and_b32 s0, 1, s5
5711; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5712; GFX9-NEXT:    v_or_b32_e32 v4, v4, v6
5713; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
5714; GFX9-NEXT:    s_and_b32 s0, 1, s8
5715; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
5716; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
5717; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5718; GFX9-NEXT:    s_and_b32 s0, 1, s5
5719; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
5720; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
5721; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s0
5722; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc
5723; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v9, vcc
5724; GFX9-NEXT:    v_or_b32_e32 v0, s6, v0
5725; GFX9-NEXT:    v_or_b32_e32 v1, s7, v1
5726; GFX9-NEXT:    v_or_b32_e32 v2, s2, v2
5727; GFX9-NEXT:    v_or_b32_e32 v3, s3, v3
5728; GFX9-NEXT:    ; return to shader part epilog
5729;
5730; GFX10-LABEL: v_fshl_i128_svs:
5731; GFX10:       ; %bb.0:
5732; GFX10-NEXT:    s_movk_i32 s6, 0x7f
5733; GFX10-NEXT:    s_mov_b32 s7, 0
5734; GFX10-NEXT:    v_lshrrev_b64 v[4:5], 1, v[0:1]
5735; GFX10-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5736; GFX10-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5737; GFX10-NEXT:    s_sub_i32 s5, s8, 64
5738; GFX10-NEXT:    s_sub_i32 s6, 64, s8
5739; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
5740; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
5741; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
5742; GFX10-NEXT:    s_cselect_b32 s13, 1, 0
5743; GFX10-NEXT:    s_lshl_b64 s[10:11], s[2:3], s8
5744; GFX10-NEXT:    s_lshr_b64 s[6:7], s[0:1], s6
5745; GFX10-NEXT:    s_lshl_b64 s[8:9], s[0:1], s8
5746; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
5747; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s5
5748; GFX10-NEXT:    s_cmp_lg_u32 s12, 0
5749; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
5750; GFX10-NEXT:    s_cselect_b64 s[0:1], s[6:7], s[0:1]
5751; GFX10-NEXT:    s_cmp_lg_u32 s13, 0
5752; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
5753; GFX10-NEXT:    s_sub_i32 s0, 64, 1
5754; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s0, v[2:3]
5755; GFX10-NEXT:    s_sub_i32 s0, 1, 64
5756; GFX10-NEXT:    s_cmp_lt_u32 1, 64
5757; GFX10-NEXT:    v_lshrrev_b64 v[8:9], s0, v[2:3]
5758; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
5759; GFX10-NEXT:    s_cmp_eq_u32 1, 0
5760; GFX10-NEXT:    v_or_b32_e32 v4, v4, v6
5761; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
5762; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
5763; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
5764; GFX10-NEXT:    s_and_b32 s0, 1, s0
5765; GFX10-NEXT:    v_lshrrev_b64 v[2:3], 1, v[2:3]
5766; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc_lo
5767; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo
5768; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
5769; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
5770; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
5771; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
5772; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5773; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5774; GFX10-NEXT:    s_sub_i32 s0, 64, s4
5775; GFX10-NEXT:    v_lshrrev_b64 v[4:5], s4, v[0:1]
5776; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s0, v[2:3]
5777; GFX10-NEXT:    s_sub_i32 s0, s4, 64
5778; GFX10-NEXT:    s_cmp_lt_u32 s4, 64
5779; GFX10-NEXT:    v_lshrrev_b64 v[8:9], s0, v[2:3]
5780; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
5781; GFX10-NEXT:    s_cmp_eq_u32 s4, 0
5782; GFX10-NEXT:    v_or_b32_e32 v4, v4, v6
5783; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
5784; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
5785; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
5786; GFX10-NEXT:    s_and_b32 s0, 1, s0
5787; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s4, v[2:3]
5788; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc_lo
5789; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo
5790; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
5791; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
5792; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
5793; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
5794; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s0
5795; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v3, s0
5796; GFX10-NEXT:    v_or_b32_e32 v0, s8, v0
5797; GFX10-NEXT:    v_or_b32_e32 v1, s9, v1
5798; GFX10-NEXT:    v_or_b32_e32 v2, s2, v2
5799; GFX10-NEXT:    v_or_b32_e32 v3, s3, v3
5800; GFX10-NEXT:    ; return to shader part epilog
5801  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
5802  %cast.result = bitcast i128 %result to <4 x float>
5803  ret <4 x float> %cast.result
5804}
5805
5806define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 inreg %amt) {
5807; GFX6-LABEL: v_fshl_i128_vss:
5808; GFX6:       ; %bb.0:
5809; GFX6-NEXT:    s_movk_i32 s6, 0x7f
5810; GFX6-NEXT:    s_mov_b32 s7, 0
5811; GFX6-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5812; GFX6-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5813; GFX6-NEXT:    s_sub_i32 s6, 64, s8
5814; GFX6-NEXT:    s_sub_i32 s5, s8, 64
5815; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
5816; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
5817; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
5818; GFX6-NEXT:    v_lshr_b64 v[4:5], v[0:1], s6
5819; GFX6-NEXT:    v_lshl_b64 v[6:7], v[2:3], s8
5820; GFX6-NEXT:    s_cselect_b32 s9, 1, 0
5821; GFX6-NEXT:    v_lshl_b64 v[8:9], v[0:1], s8
5822; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s5
5823; GFX6-NEXT:    s_and_b32 s5, 1, s7
5824; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5825; GFX6-NEXT:    v_or_b32_e32 v4, v4, v6
5826; GFX6-NEXT:    v_or_b32_e32 v5, v5, v7
5827; GFX6-NEXT:    s_and_b32 s5, 1, s9
5828; GFX6-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
5829; GFX6-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
5830; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
5831; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
5832; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5833; GFX6-NEXT:    s_sub_i32 s5, 1, 64
5834; GFX6-NEXT:    s_sub_i32 s10, 64, 1
5835; GFX6-NEXT:    s_cmp_lt_u32 1, 64
5836; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5837; GFX6-NEXT:    s_cmp_eq_u32 1, 0
5838; GFX6-NEXT:    s_cselect_b32 s13, 1, 0
5839; GFX6-NEXT:    s_lshr_b64 s[8:9], s[0:1], 1
5840; GFX6-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
5841; GFX6-NEXT:    s_lshr_b64 s[6:7], s[2:3], 1
5842; GFX6-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
5843; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], s5
5844; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5845; GFX6-NEXT:    s_cselect_b64 s[2:3], s[8:9], s[2:3]
5846; GFX6-NEXT:    s_cmp_lg_u32 s13, 0
5847; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5848; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5849; GFX6-NEXT:    s_cselect_b64 s[2:3], s[6:7], 0
5850; GFX6-NEXT:    s_sub_i32 s10, s4, 64
5851; GFX6-NEXT:    s_sub_i32 s8, 64, s4
5852; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
5853; GFX6-NEXT:    s_cselect_b32 s11, 1, 0
5854; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
5855; GFX6-NEXT:    s_cselect_b32 s12, 1, 0
5856; GFX6-NEXT:    s_lshr_b64 s[6:7], s[2:3], s4
5857; GFX6-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
5858; GFX6-NEXT:    s_lshr_b64 s[4:5], s[0:1], s4
5859; GFX6-NEXT:    s_or_b64 s[4:5], s[4:5], s[8:9]
5860; GFX6-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5861; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5862; GFX6-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5863; GFX6-NEXT:    s_cmp_lg_u32 s12, 0
5864; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5865; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
5866; GFX6-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
5867; GFX6-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
5868; GFX6-NEXT:    s_cselect_b64 s[2:3], s[6:7], 0
5869; GFX6-NEXT:    v_or_b32_e32 v0, s0, v6
5870; GFX6-NEXT:    v_or_b32_e32 v1, s1, v7
5871; GFX6-NEXT:    v_or_b32_e32 v2, s2, v2
5872; GFX6-NEXT:    v_or_b32_e32 v3, s3, v3
5873; GFX6-NEXT:    ; return to shader part epilog
5874;
5875; GFX8-LABEL: v_fshl_i128_vss:
5876; GFX8:       ; %bb.0:
5877; GFX8-NEXT:    s_movk_i32 s6, 0x7f
5878; GFX8-NEXT:    s_mov_b32 s7, 0
5879; GFX8-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5880; GFX8-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5881; GFX8-NEXT:    s_sub_i32 s6, 64, s8
5882; GFX8-NEXT:    s_sub_i32 s5, s8, 64
5883; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
5884; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
5885; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
5886; GFX8-NEXT:    v_lshrrev_b64 v[4:5], s6, v[0:1]
5887; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s8, v[2:3]
5888; GFX8-NEXT:    s_cselect_b32 s9, 1, 0
5889; GFX8-NEXT:    v_lshlrev_b64 v[8:9], s8, v[0:1]
5890; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
5891; GFX8-NEXT:    s_and_b32 s5, 1, s7
5892; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5893; GFX8-NEXT:    v_or_b32_e32 v4, v4, v6
5894; GFX8-NEXT:    v_or_b32_e32 v5, v5, v7
5895; GFX8-NEXT:    s_and_b32 s5, 1, s9
5896; GFX8-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
5897; GFX8-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
5898; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
5899; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
5900; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5901; GFX8-NEXT:    s_sub_i32 s5, 1, 64
5902; GFX8-NEXT:    s_sub_i32 s10, 64, 1
5903; GFX8-NEXT:    s_cmp_lt_u32 1, 64
5904; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5905; GFX8-NEXT:    s_cmp_eq_u32 1, 0
5906; GFX8-NEXT:    s_cselect_b32 s13, 1, 0
5907; GFX8-NEXT:    s_lshr_b64 s[8:9], s[0:1], 1
5908; GFX8-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
5909; GFX8-NEXT:    s_lshr_b64 s[6:7], s[2:3], 1
5910; GFX8-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
5911; GFX8-NEXT:    s_lshr_b64 s[2:3], s[2:3], s5
5912; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5913; GFX8-NEXT:    s_cselect_b64 s[2:3], s[8:9], s[2:3]
5914; GFX8-NEXT:    s_cmp_lg_u32 s13, 0
5915; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5916; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5917; GFX8-NEXT:    s_cselect_b64 s[2:3], s[6:7], 0
5918; GFX8-NEXT:    s_sub_i32 s10, s4, 64
5919; GFX8-NEXT:    s_sub_i32 s8, 64, s4
5920; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
5921; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
5922; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
5923; GFX8-NEXT:    s_cselect_b32 s12, 1, 0
5924; GFX8-NEXT:    s_lshr_b64 s[6:7], s[2:3], s4
5925; GFX8-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
5926; GFX8-NEXT:    s_lshr_b64 s[4:5], s[0:1], s4
5927; GFX8-NEXT:    s_or_b64 s[4:5], s[4:5], s[8:9]
5928; GFX8-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5929; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
5930; GFX8-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5931; GFX8-NEXT:    s_cmp_lg_u32 s12, 0
5932; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5933; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
5934; GFX8-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
5935; GFX8-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
5936; GFX8-NEXT:    s_cselect_b64 s[2:3], s[6:7], 0
5937; GFX8-NEXT:    v_or_b32_e32 v0, s0, v6
5938; GFX8-NEXT:    v_or_b32_e32 v1, s1, v7
5939; GFX8-NEXT:    v_or_b32_e32 v2, s2, v2
5940; GFX8-NEXT:    v_or_b32_e32 v3, s3, v3
5941; GFX8-NEXT:    ; return to shader part epilog
5942;
5943; GFX9-LABEL: v_fshl_i128_vss:
5944; GFX9:       ; %bb.0:
5945; GFX9-NEXT:    s_movk_i32 s6, 0x7f
5946; GFX9-NEXT:    s_mov_b32 s7, 0
5947; GFX9-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
5948; GFX9-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
5949; GFX9-NEXT:    s_sub_i32 s6, 64, s8
5950; GFX9-NEXT:    s_sub_i32 s5, s8, 64
5951; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
5952; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
5953; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
5954; GFX9-NEXT:    v_lshrrev_b64 v[4:5], s6, v[0:1]
5955; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s8, v[2:3]
5956; GFX9-NEXT:    s_cselect_b32 s9, 1, 0
5957; GFX9-NEXT:    v_lshlrev_b64 v[8:9], s8, v[0:1]
5958; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
5959; GFX9-NEXT:    s_and_b32 s5, 1, s7
5960; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5961; GFX9-NEXT:    v_or_b32_e32 v4, v4, v6
5962; GFX9-NEXT:    v_or_b32_e32 v5, v5, v7
5963; GFX9-NEXT:    s_and_b32 s5, 1, s9
5964; GFX9-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
5965; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
5966; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
5967; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
5968; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
5969; GFX9-NEXT:    s_sub_i32 s5, 1, 64
5970; GFX9-NEXT:    s_sub_i32 s10, 64, 1
5971; GFX9-NEXT:    s_cmp_lt_u32 1, 64
5972; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5973; GFX9-NEXT:    s_cmp_eq_u32 1, 0
5974; GFX9-NEXT:    s_cselect_b32 s13, 1, 0
5975; GFX9-NEXT:    s_lshr_b64 s[8:9], s[0:1], 1
5976; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
5977; GFX9-NEXT:    s_lshr_b64 s[6:7], s[2:3], 1
5978; GFX9-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
5979; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s5
5980; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5981; GFX9-NEXT:    s_cselect_b64 s[2:3], s[8:9], s[2:3]
5982; GFX9-NEXT:    s_cmp_lg_u32 s13, 0
5983; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
5984; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
5985; GFX9-NEXT:    s_cselect_b64 s[2:3], s[6:7], 0
5986; GFX9-NEXT:    s_sub_i32 s10, s4, 64
5987; GFX9-NEXT:    s_sub_i32 s8, 64, s4
5988; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
5989; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
5990; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
5991; GFX9-NEXT:    s_cselect_b32 s12, 1, 0
5992; GFX9-NEXT:    s_lshr_b64 s[6:7], s[2:3], s4
5993; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
5994; GFX9-NEXT:    s_lshr_b64 s[4:5], s[0:1], s4
5995; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[8:9]
5996; GFX9-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
5997; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
5998; GFX9-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
5999; GFX9-NEXT:    s_cmp_lg_u32 s12, 0
6000; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
6001; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
6002; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
6003; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
6004; GFX9-NEXT:    s_cselect_b64 s[2:3], s[6:7], 0
6005; GFX9-NEXT:    v_or_b32_e32 v0, s0, v6
6006; GFX9-NEXT:    v_or_b32_e32 v1, s1, v7
6007; GFX9-NEXT:    v_or_b32_e32 v2, s2, v2
6008; GFX9-NEXT:    v_or_b32_e32 v3, s3, v3
6009; GFX9-NEXT:    ; return to shader part epilog
6010;
6011; GFX10-LABEL: v_fshl_i128_vss:
6012; GFX10:       ; %bb.0:
6013; GFX10-NEXT:    s_movk_i32 s6, 0x7f
6014; GFX10-NEXT:    s_mov_b32 s7, 0
6015; GFX10-NEXT:    s_and_b64 s[8:9], s[4:5], s[6:7]
6016; GFX10-NEXT:    s_andn2_b64 s[4:5], s[6:7], s[4:5]
6017; GFX10-NEXT:    s_sub_i32 s9, 64, s8
6018; GFX10-NEXT:    s_sub_i32 s5, s8, 64
6019; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
6020; GFX10-NEXT:    v_lshrrev_b64 v[4:5], s9, v[0:1]
6021; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
6022; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
6023; GFX10-NEXT:    v_lshlrev_b64 v[6:7], s8, v[2:3]
6024; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s8, v[0:1]
6025; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
6026; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
6027; GFX10-NEXT:    s_and_b32 s5, 1, vcc_lo
6028; GFX10-NEXT:    s_and_b32 s12, 1, s6
6029; GFX10-NEXT:    s_sub_i32 s13, 1, 64
6030; GFX10-NEXT:    s_sub_i32 s8, 64, 1
6031; GFX10-NEXT:    s_cmp_lt_u32 1, 64
6032; GFX10-NEXT:    v_or_b32_e32 v4, v4, v6
6033; GFX10-NEXT:    v_or_b32_e32 v5, v5, v7
6034; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc_lo
6035; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc_lo
6036; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s5
6037; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
6038; GFX10-NEXT:    s_cmp_eq_u32 1, 0
6039; GFX10-NEXT:    s_cselect_b32 s14, 1, 0
6040; GFX10-NEXT:    s_lshr_b64 s[6:7], s[0:1], 1
6041; GFX10-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
6042; GFX10-NEXT:    s_lshr_b64 s[10:11], s[2:3], 1
6043; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6044; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s13
6045; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
6046; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
6047; GFX10-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
6048; GFX10-NEXT:    s_cmp_lg_u32 s14, 0
6049; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
6050; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
6051; GFX10-NEXT:    s_cmp_lg_u32 s5, 0
6052; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s12
6053; GFX10-NEXT:    s_cselect_b64 s[2:3], s[10:11], 0
6054; GFX10-NEXT:    s_sub_i32 s10, s4, 64
6055; GFX10-NEXT:    s_sub_i32 s5, 64, s4
6056; GFX10-NEXT:    s_cmp_lt_u32 s4, 64
6057; GFX10-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
6058; GFX10-NEXT:    s_cselect_b32 s11, 1, 0
6059; GFX10-NEXT:    s_cmp_eq_u32 s4, 0
6060; GFX10-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc_lo
6061; GFX10-NEXT:    s_cselect_b32 s12, 1, 0
6062; GFX10-NEXT:    s_lshr_b64 s[6:7], s[0:1], s4
6063; GFX10-NEXT:    s_lshl_b64 s[8:9], s[2:3], s5
6064; GFX10-NEXT:    s_lshr_b64 s[4:5], s[2:3], s4
6065; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6066; GFX10-NEXT:    s_lshr_b64 s[2:3], s[2:3], s10
6067; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6068; GFX10-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
6069; GFX10-NEXT:    s_cmp_lg_u32 s12, 0
6070; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
6071; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6072; GFX10-NEXT:    v_or_b32_e32 v0, s0, v6
6073; GFX10-NEXT:    s_cselect_b64 s[2:3], s[4:5], 0
6074; GFX10-NEXT:    v_or_b32_e32 v1, s1, v7
6075; GFX10-NEXT:    v_or_b32_e32 v2, s2, v2
6076; GFX10-NEXT:    v_or_b32_e32 v3, s3, v3
6077; GFX10-NEXT:    ; return to shader part epilog
6078  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
6079  %cast.result = bitcast i128 %result to <4 x float>
6080  ret <4 x float> %cast.result
6081}
6082
6083define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
6084; GFX6-LABEL: s_fshl_i128_65:
6085; GFX6:       ; %bb.0:
6086; GFX6-NEXT:    s_movk_i32 s8, 0x41
6087; GFX6-NEXT:    s_sub_i32 s16, s8, 64
6088; GFX6-NEXT:    s_sub_i32 s12, 64, s8
6089; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
6090; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
6091; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
6092; GFX6-NEXT:    s_cselect_b32 s18, 1, 0
6093; GFX6-NEXT:    s_lshr_b64 s[12:13], s[0:1], s12
6094; GFX6-NEXT:    s_lshl_b64 s[14:15], s[2:3], s8
6095; GFX6-NEXT:    s_lshl_b64 s[10:11], s[0:1], s8
6096; GFX6-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
6097; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s16
6098; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
6099; GFX6-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
6100; GFX6-NEXT:    s_cselect_b64 s[0:1], s[12:13], s[0:1]
6101; GFX6-NEXT:    s_cmp_lg_u32 s18, 0
6102; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6103; GFX6-NEXT:    s_sub_i32 s14, 63, 64
6104; GFX6-NEXT:    s_sub_i32 s12, 64, 63
6105; GFX6-NEXT:    s_cmp_lt_u32 63, 64
6106; GFX6-NEXT:    s_mov_b32 s9, 0
6107; GFX6-NEXT:    s_cselect_b32 s15, 1, 0
6108; GFX6-NEXT:    s_cmp_eq_u32 63, 0
6109; GFX6-NEXT:    s_cselect_b32 s16, 1, 0
6110; GFX6-NEXT:    s_lshr_b32 s0, s5, 31
6111; GFX6-NEXT:    s_mov_b32 s1, s9
6112; GFX6-NEXT:    s_lshl_b64 s[12:13], s[6:7], s12
6113; GFX6-NEXT:    s_lshr_b32 s8, s7, 31
6114; GFX6-NEXT:    s_or_b64 s[0:1], s[0:1], s[12:13]
6115; GFX6-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6116; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
6117; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
6118; GFX6-NEXT:    s_cmp_lg_u32 s16, 0
6119; GFX6-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
6120; GFX6-NEXT:    s_cmp_lg_u32 s15, 0
6121; GFX6-NEXT:    s_cselect_b64 s[4:5], s[8:9], 0
6122; GFX6-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
6123; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
6124; GFX6-NEXT:    ; return to shader part epilog
6125;
6126; GFX8-LABEL: s_fshl_i128_65:
6127; GFX8:       ; %bb.0:
6128; GFX8-NEXT:    s_movk_i32 s8, 0x41
6129; GFX8-NEXT:    s_sub_i32 s16, s8, 64
6130; GFX8-NEXT:    s_sub_i32 s12, 64, s8
6131; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
6132; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
6133; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
6134; GFX8-NEXT:    s_cselect_b32 s18, 1, 0
6135; GFX8-NEXT:    s_lshr_b64 s[12:13], s[0:1], s12
6136; GFX8-NEXT:    s_lshl_b64 s[14:15], s[2:3], s8
6137; GFX8-NEXT:    s_lshl_b64 s[10:11], s[0:1], s8
6138; GFX8-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
6139; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s16
6140; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
6141; GFX8-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
6142; GFX8-NEXT:    s_cselect_b64 s[0:1], s[12:13], s[0:1]
6143; GFX8-NEXT:    s_cmp_lg_u32 s18, 0
6144; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6145; GFX8-NEXT:    s_sub_i32 s14, 63, 64
6146; GFX8-NEXT:    s_sub_i32 s12, 64, 63
6147; GFX8-NEXT:    s_cmp_lt_u32 63, 64
6148; GFX8-NEXT:    s_mov_b32 s9, 0
6149; GFX8-NEXT:    s_cselect_b32 s15, 1, 0
6150; GFX8-NEXT:    s_cmp_eq_u32 63, 0
6151; GFX8-NEXT:    s_cselect_b32 s16, 1, 0
6152; GFX8-NEXT:    s_lshr_b32 s0, s5, 31
6153; GFX8-NEXT:    s_mov_b32 s1, s9
6154; GFX8-NEXT:    s_lshl_b64 s[12:13], s[6:7], s12
6155; GFX8-NEXT:    s_lshr_b32 s8, s7, 31
6156; GFX8-NEXT:    s_or_b64 s[0:1], s[0:1], s[12:13]
6157; GFX8-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6158; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
6159; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
6160; GFX8-NEXT:    s_cmp_lg_u32 s16, 0
6161; GFX8-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
6162; GFX8-NEXT:    s_cmp_lg_u32 s15, 0
6163; GFX8-NEXT:    s_cselect_b64 s[4:5], s[8:9], 0
6164; GFX8-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
6165; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
6166; GFX8-NEXT:    ; return to shader part epilog
6167;
6168; GFX9-LABEL: s_fshl_i128_65:
6169; GFX9:       ; %bb.0:
6170; GFX9-NEXT:    s_movk_i32 s8, 0x41
6171; GFX9-NEXT:    s_sub_i32 s16, s8, 64
6172; GFX9-NEXT:    s_sub_i32 s12, 64, s8
6173; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
6174; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
6175; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
6176; GFX9-NEXT:    s_cselect_b32 s18, 1, 0
6177; GFX9-NEXT:    s_lshr_b64 s[12:13], s[0:1], s12
6178; GFX9-NEXT:    s_lshl_b64 s[14:15], s[2:3], s8
6179; GFX9-NEXT:    s_lshl_b64 s[10:11], s[0:1], s8
6180; GFX9-NEXT:    s_or_b64 s[12:13], s[12:13], s[14:15]
6181; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s16
6182; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
6183; GFX9-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
6184; GFX9-NEXT:    s_cselect_b64 s[0:1], s[12:13], s[0:1]
6185; GFX9-NEXT:    s_cmp_lg_u32 s18, 0
6186; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6187; GFX9-NEXT:    s_sub_i32 s14, 63, 64
6188; GFX9-NEXT:    s_sub_i32 s12, 64, 63
6189; GFX9-NEXT:    s_cmp_lt_u32 63, 64
6190; GFX9-NEXT:    s_mov_b32 s9, 0
6191; GFX9-NEXT:    s_cselect_b32 s15, 1, 0
6192; GFX9-NEXT:    s_cmp_eq_u32 63, 0
6193; GFX9-NEXT:    s_cselect_b32 s16, 1, 0
6194; GFX9-NEXT:    s_lshr_b32 s0, s5, 31
6195; GFX9-NEXT:    s_mov_b32 s1, s9
6196; GFX9-NEXT:    s_lshl_b64 s[12:13], s[6:7], s12
6197; GFX9-NEXT:    s_lshr_b32 s8, s7, 31
6198; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[12:13]
6199; GFX9-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6200; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
6201; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[6:7]
6202; GFX9-NEXT:    s_cmp_lg_u32 s16, 0
6203; GFX9-NEXT:    s_cselect_b64 s[0:1], s[4:5], s[0:1]
6204; GFX9-NEXT:    s_cmp_lg_u32 s15, 0
6205; GFX9-NEXT:    s_cselect_b64 s[4:5], s[8:9], 0
6206; GFX9-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
6207; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[4:5]
6208; GFX9-NEXT:    ; return to shader part epilog
6209;
6210; GFX10-LABEL: s_fshl_i128_65:
6211; GFX10:       ; %bb.0:
6212; GFX10-NEXT:    s_movk_i32 s12, 0x41
6213; GFX10-NEXT:    s_sub_i32 s14, s12, 64
6214; GFX10-NEXT:    s_sub_i32 s8, 64, s12
6215; GFX10-NEXT:    s_cmp_lt_u32 s12, 64
6216; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
6217; GFX10-NEXT:    s_cmp_eq_u32 s12, 0
6218; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
6219; GFX10-NEXT:    s_lshl_b64 s[10:11], s[2:3], s12
6220; GFX10-NEXT:    s_lshr_b64 s[8:9], s[0:1], s8
6221; GFX10-NEXT:    s_lshl_b64 s[12:13], s[0:1], s12
6222; GFX10-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
6223; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s14
6224; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
6225; GFX10-NEXT:    s_cselect_b64 s[10:11], s[12:13], 0
6226; GFX10-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6227; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
6228; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6229; GFX10-NEXT:    s_sub_i32 s14, 63, 64
6230; GFX10-NEXT:    s_sub_i32 s0, 64, 63
6231; GFX10-NEXT:    s_cmp_lt_u32 63, 64
6232; GFX10-NEXT:    s_mov_b32 s1, 0
6233; GFX10-NEXT:    s_cselect_b32 s15, 1, 0
6234; GFX10-NEXT:    s_cmp_eq_u32 63, 0
6235; GFX10-NEXT:    s_mov_b32 s9, s1
6236; GFX10-NEXT:    s_cselect_b32 s16, 1, 0
6237; GFX10-NEXT:    s_lshl_b64 s[12:13], s[6:7], s0
6238; GFX10-NEXT:    s_lshr_b32 s8, s5, 31
6239; GFX10-NEXT:    s_lshr_b32 s0, s7, 31
6240; GFX10-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
6241; GFX10-NEXT:    s_lshr_b64 s[6:7], s[6:7], s14
6242; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
6243; GFX10-NEXT:    s_cselect_b64 s[6:7], s[8:9], s[6:7]
6244; GFX10-NEXT:    s_cmp_lg_u32 s16, 0
6245; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[6:7]
6246; GFX10-NEXT:    s_cmp_lg_u32 s15, 0
6247; GFX10-NEXT:    s_cselect_b64 s[6:7], s[0:1], 0
6248; GFX10-NEXT:    s_or_b64 s[0:1], s[10:11], s[4:5]
6249; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
6250; GFX10-NEXT:    ; return to shader part epilog
6251  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
6252  ret i128 %result
6253}
6254
6255define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
6256; GFX6-LABEL: v_fshl_i128_65:
6257; GFX6:       ; %bb.0:
6258; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6259; GFX6-NEXT:    s_movk_i32 s4, 0x41
6260; GFX6-NEXT:    s_sub_i32 s6, 64, s4
6261; GFX6-NEXT:    s_sub_i32 s5, s4, 64
6262; GFX6-NEXT:    s_cmp_lt_u32 s4, 64
6263; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
6264; GFX6-NEXT:    s_cmp_eq_u32 s4, 0
6265; GFX6-NEXT:    v_lshr_b64 v[8:9], v[0:1], s6
6266; GFX6-NEXT:    v_lshl_b64 v[10:11], v[2:3], s4
6267; GFX6-NEXT:    v_lshl_b64 v[12:13], v[0:1], s4
6268; GFX6-NEXT:    s_cselect_b32 s8, 1, 0
6269; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], s5
6270; GFX6-NEXT:    s_and_b32 s4, 1, s7
6271; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6272; GFX6-NEXT:    v_or_b32_e32 v8, v8, v10
6273; GFX6-NEXT:    v_or_b32_e32 v9, v9, v11
6274; GFX6-NEXT:    s_and_b32 s4, 1, s8
6275; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
6276; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
6277; GFX6-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
6278; GFX6-NEXT:    v_cndmask_b32_e32 v11, 0, v13, vcc
6279; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6280; GFX6-NEXT:    s_sub_i32 s4, 63, 64
6281; GFX6-NEXT:    s_sub_i32 s5, 64, 63
6282; GFX6-NEXT:    s_cmp_lt_u32 63, 64
6283; GFX6-NEXT:    s_cselect_b32 s6, 1, 0
6284; GFX6-NEXT:    s_cmp_eq_u32 63, 0
6285; GFX6-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
6286; GFX6-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
6287; GFX6-NEXT:    v_lshl_b64 v[0:1], v[6:7], s5
6288; GFX6-NEXT:    v_lshrrev_b32_e32 v8, 31, v7
6289; GFX6-NEXT:    v_lshrrev_b32_e32 v9, 31, v5
6290; GFX6-NEXT:    s_cselect_b32 s7, 1, 0
6291; GFX6-NEXT:    v_lshr_b64 v[6:7], v[6:7], s4
6292; GFX6-NEXT:    s_and_b32 s4, 1, s6
6293; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6294; GFX6-NEXT:    v_or_b32_e32 v0, v9, v0
6295; GFX6-NEXT:    s_and_b32 s4, 1, s7
6296; GFX6-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
6297; GFX6-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
6298; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6299; GFX6-NEXT:    s_and_b32 s4, 1, s6
6300; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6301; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
6302; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6303; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
6304; GFX6-NEXT:    v_or_b32_e32 v0, v10, v0
6305; GFX6-NEXT:    v_or_b32_e32 v1, v11, v1
6306; GFX6-NEXT:    v_or_b32_e32 v2, v2, v4
6307; GFX6-NEXT:    s_setpc_b64 s[30:31]
6308;
6309; GFX8-LABEL: v_fshl_i128_65:
6310; GFX8:       ; %bb.0:
6311; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6312; GFX8-NEXT:    s_movk_i32 s4, 0x41
6313; GFX8-NEXT:    s_sub_i32 s6, 64, s4
6314; GFX8-NEXT:    s_sub_i32 s5, s4, 64
6315; GFX8-NEXT:    s_cmp_lt_u32 s4, 64
6316; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
6317; GFX8-NEXT:    s_cmp_eq_u32 s4, 0
6318; GFX8-NEXT:    v_lshrrev_b64 v[8:9], s6, v[0:1]
6319; GFX8-NEXT:    v_lshlrev_b64 v[10:11], s4, v[2:3]
6320; GFX8-NEXT:    v_lshlrev_b64 v[12:13], s4, v[0:1]
6321; GFX8-NEXT:    s_cselect_b32 s8, 1, 0
6322; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
6323; GFX8-NEXT:    s_and_b32 s4, 1, s7
6324; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6325; GFX8-NEXT:    v_or_b32_e32 v8, v8, v10
6326; GFX8-NEXT:    v_or_b32_e32 v9, v9, v11
6327; GFX8-NEXT:    s_and_b32 s4, 1, s8
6328; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
6329; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
6330; GFX8-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
6331; GFX8-NEXT:    v_cndmask_b32_e32 v11, 0, v13, vcc
6332; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6333; GFX8-NEXT:    s_sub_i32 s4, 63, 64
6334; GFX8-NEXT:    s_sub_i32 s5, 64, 63
6335; GFX8-NEXT:    s_cmp_lt_u32 63, 64
6336; GFX8-NEXT:    s_cselect_b32 s6, 1, 0
6337; GFX8-NEXT:    s_cmp_eq_u32 63, 0
6338; GFX8-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
6339; GFX8-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
6340; GFX8-NEXT:    v_lshlrev_b64 v[0:1], s5, v[6:7]
6341; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 31, v7
6342; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 31, v5
6343; GFX8-NEXT:    s_cselect_b32 s7, 1, 0
6344; GFX8-NEXT:    v_lshrrev_b64 v[6:7], s4, v[6:7]
6345; GFX8-NEXT:    s_and_b32 s4, 1, s6
6346; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6347; GFX8-NEXT:    v_or_b32_e32 v0, v9, v0
6348; GFX8-NEXT:    s_and_b32 s4, 1, s7
6349; GFX8-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
6350; GFX8-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
6351; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6352; GFX8-NEXT:    s_and_b32 s4, 1, s6
6353; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6354; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
6355; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6356; GFX8-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
6357; GFX8-NEXT:    v_or_b32_e32 v0, v10, v0
6358; GFX8-NEXT:    v_or_b32_e32 v1, v11, v1
6359; GFX8-NEXT:    v_or_b32_e32 v2, v2, v4
6360; GFX8-NEXT:    s_setpc_b64 s[30:31]
6361;
6362; GFX9-LABEL: v_fshl_i128_65:
6363; GFX9:       ; %bb.0:
6364; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6365; GFX9-NEXT:    s_movk_i32 s4, 0x41
6366; GFX9-NEXT:    s_sub_i32 s6, 64, s4
6367; GFX9-NEXT:    s_sub_i32 s5, s4, 64
6368; GFX9-NEXT:    s_cmp_lt_u32 s4, 64
6369; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
6370; GFX9-NEXT:    s_cmp_eq_u32 s4, 0
6371; GFX9-NEXT:    v_lshrrev_b64 v[8:9], s6, v[0:1]
6372; GFX9-NEXT:    v_lshlrev_b64 v[10:11], s4, v[2:3]
6373; GFX9-NEXT:    v_lshlrev_b64 v[12:13], s4, v[0:1]
6374; GFX9-NEXT:    s_cselect_b32 s8, 1, 0
6375; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
6376; GFX9-NEXT:    s_and_b32 s4, 1, s7
6377; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6378; GFX9-NEXT:    v_or_b32_e32 v8, v8, v10
6379; GFX9-NEXT:    v_or_b32_e32 v9, v9, v11
6380; GFX9-NEXT:    s_and_b32 s4, 1, s8
6381; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
6382; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
6383; GFX9-NEXT:    v_cndmask_b32_e32 v10, 0, v12, vcc
6384; GFX9-NEXT:    v_cndmask_b32_e32 v11, 0, v13, vcc
6385; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6386; GFX9-NEXT:    s_sub_i32 s4, 63, 64
6387; GFX9-NEXT:    s_sub_i32 s5, 64, 63
6388; GFX9-NEXT:    s_cmp_lt_u32 63, 64
6389; GFX9-NEXT:    s_cselect_b32 s6, 1, 0
6390; GFX9-NEXT:    s_cmp_eq_u32 63, 0
6391; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
6392; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
6393; GFX9-NEXT:    v_lshlrev_b64 v[0:1], s5, v[6:7]
6394; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 31, v7
6395; GFX9-NEXT:    v_lshrrev_b32_e32 v9, 31, v5
6396; GFX9-NEXT:    s_cselect_b32 s7, 1, 0
6397; GFX9-NEXT:    v_lshrrev_b64 v[6:7], s4, v[6:7]
6398; GFX9-NEXT:    s_and_b32 s4, 1, s6
6399; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6400; GFX9-NEXT:    v_or_b32_e32 v0, v9, v0
6401; GFX9-NEXT:    s_and_b32 s4, 1, s7
6402; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
6403; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
6404; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6405; GFX9-NEXT:    s_and_b32 s4, 1, s6
6406; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
6407; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
6408; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6409; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v8, vcc
6410; GFX9-NEXT:    v_or_b32_e32 v0, v10, v0
6411; GFX9-NEXT:    v_or_b32_e32 v1, v11, v1
6412; GFX9-NEXT:    v_or_b32_e32 v2, v2, v4
6413; GFX9-NEXT:    s_setpc_b64 s[30:31]
6414;
6415; GFX10-LABEL: v_fshl_i128_65:
6416; GFX10:       ; %bb.0:
6417; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6418; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
6419; GFX10-NEXT:    s_movk_i32 s4, 0x41
6420; GFX10-NEXT:    v_lshrrev_b32_e32 v16, 31, v5
6421; GFX10-NEXT:    s_sub_i32 s5, 64, s4
6422; GFX10-NEXT:    v_lshlrev_b64 v[10:11], s4, v[2:3]
6423; GFX10-NEXT:    v_lshrrev_b64 v[8:9], s5, v[0:1]
6424; GFX10-NEXT:    s_sub_i32 s5, s4, 64
6425; GFX10-NEXT:    s_cmp_lt_u32 s4, 64
6426; GFX10-NEXT:    v_lshlrev_b64 v[12:13], s4, v[0:1]
6427; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
6428; GFX10-NEXT:    s_cmp_eq_u32 s4, 0
6429; GFX10-NEXT:    v_lshlrev_b64 v[0:1], s5, v[0:1]
6430; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
6431; GFX10-NEXT:    s_sub_i32 s5, 64, 63
6432; GFX10-NEXT:    v_or_b32_e32 v14, v8, v10
6433; GFX10-NEXT:    v_or_b32_e32 v15, v9, v11
6434; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s5, v[6:7]
6435; GFX10-NEXT:    s_and_b32 s6, 1, vcc_lo
6436; GFX10-NEXT:    s_and_b32 s7, 1, s4
6437; GFX10-NEXT:    s_sub_i32 s4, 63, 64
6438; GFX10-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc_lo
6439; GFX10-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc_lo
6440; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s6
6441; GFX10-NEXT:    v_lshrrev_b64 v[10:11], s4, v[6:7]
6442; GFX10-NEXT:    s_cmp_lt_u32 63, 64
6443; GFX10-NEXT:    v_or_b32_e32 v6, v16, v8
6444; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
6445; GFX10-NEXT:    s_cmp_eq_u32 63, 0
6446; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc_lo
6447; GFX10-NEXT:    v_cmp_ne_u32_e64 s6, 0, s7
6448; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
6449; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v6, s4
6450; GFX10-NEXT:    s_and_b32 s5, 1, s5
6451; GFX10-NEXT:    v_cndmask_b32_e64 v8, v11, v9, s4
6452; GFX10-NEXT:    s_and_b32 s4, 1, s4
6453; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s5
6454; GFX10-NEXT:    v_cndmask_b32_e64 v2, v0, v2, s6
6455; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 31, v7
6456; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
6457; GFX10-NEXT:    v_cndmask_b32_e32 v7, v1, v15, vcc_lo
6458; GFX10-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s5
6459; GFX10-NEXT:    v_cndmask_b32_e64 v5, v8, v5, s5
6460; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, v0, s4
6461; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v3, s6
6462; GFX10-NEXT:    v_or_b32_e32 v0, v12, v4
6463; GFX10-NEXT:    v_or_b32_e32 v1, v13, v5
6464; GFX10-NEXT:    v_or_b32_e32 v2, v2, v6
6465; GFX10-NEXT:    s_setpc_b64 s[30:31]
6466  %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
6467  ret i128 %result
6468}
6469
6470define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
6471; GFX6-LABEL: s_fshl_v2i128:
6472; GFX6:       ; %bb.0:
6473; GFX6-NEXT:    s_movk_i32 s18, 0x7f
6474; GFX6-NEXT:    s_mov_b32 s19, 0
6475; GFX6-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6476; GFX6-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6477; GFX6-NEXT:    s_sub_i32 s17, s22, 64
6478; GFX6-NEXT:    s_sub_i32 s23, 64, s22
6479; GFX6-NEXT:    s_cmp_lt_u32 s22, 64
6480; GFX6-NEXT:    s_cselect_b32 s28, 1, 0
6481; GFX6-NEXT:    s_cmp_eq_u32 s22, 0
6482; GFX6-NEXT:    s_cselect_b32 s29, 1, 0
6483; GFX6-NEXT:    s_lshl_b64 s[24:25], s[0:1], s22
6484; GFX6-NEXT:    s_lshr_b64 s[26:27], s[0:1], s23
6485; GFX6-NEXT:    s_lshl_b64 s[22:23], s[2:3], s22
6486; GFX6-NEXT:    s_or_b64 s[22:23], s[26:27], s[22:23]
6487; GFX6-NEXT:    s_lshl_b64 s[0:1], s[0:1], s17
6488; GFX6-NEXT:    s_cmp_lg_u32 s28, 0
6489; GFX6-NEXT:    s_cselect_b64 s[24:25], s[24:25], 0
6490; GFX6-NEXT:    s_cselect_b64 s[0:1], s[22:23], s[0:1]
6491; GFX6-NEXT:    s_cmp_lg_u32 s29, 0
6492; GFX6-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6493; GFX6-NEXT:    s_sub_i32 s28, 1, 64
6494; GFX6-NEXT:    s_sub_i32 s29, 64, 1
6495; GFX6-NEXT:    s_cmp_lt_u32 1, 64
6496; GFX6-NEXT:    s_cselect_b32 s17, 1, 0
6497; GFX6-NEXT:    s_cmp_eq_u32 1, 0
6498; GFX6-NEXT:    s_cselect_b32 s30, 1, 0
6499; GFX6-NEXT:    s_lshr_b64 s[22:23], s[8:9], 1
6500; GFX6-NEXT:    s_lshl_b64 s[26:27], s[10:11], s29
6501; GFX6-NEXT:    s_lshr_b64 s[0:1], s[10:11], 1
6502; GFX6-NEXT:    s_or_b64 s[22:23], s[22:23], s[26:27]
6503; GFX6-NEXT:    s_lshr_b64 s[10:11], s[10:11], s28
6504; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
6505; GFX6-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
6506; GFX6-NEXT:    s_cmp_lg_u32 s30, 0
6507; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
6508; GFX6-NEXT:    s_cmp_lg_u32 s17, 0
6509; GFX6-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
6510; GFX6-NEXT:    s_sub_i32 s26, s16, 64
6511; GFX6-NEXT:    s_sub_i32 s22, 64, s16
6512; GFX6-NEXT:    s_cmp_lt_u32 s16, 64
6513; GFX6-NEXT:    s_cselect_b32 s27, 1, 0
6514; GFX6-NEXT:    s_cmp_eq_u32 s16, 0
6515; GFX6-NEXT:    s_cselect_b32 s30, 1, 0
6516; GFX6-NEXT:    s_lshr_b64 s[10:11], s[0:1], s16
6517; GFX6-NEXT:    s_lshl_b64 s[22:23], s[0:1], s22
6518; GFX6-NEXT:    s_lshr_b64 s[16:17], s[8:9], s16
6519; GFX6-NEXT:    s_or_b64 s[16:17], s[16:17], s[22:23]
6520; GFX6-NEXT:    s_lshr_b64 s[0:1], s[0:1], s26
6521; GFX6-NEXT:    s_cmp_lg_u32 s27, 0
6522; GFX6-NEXT:    s_cselect_b64 s[0:1], s[16:17], s[0:1]
6523; GFX6-NEXT:    s_cmp_lg_u32 s30, 0
6524; GFX6-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6525; GFX6-NEXT:    s_cmp_lg_u32 s27, 0
6526; GFX6-NEXT:    s_cselect_b64 s[8:9], s[10:11], 0
6527; GFX6-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
6528; GFX6-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6529; GFX6-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6530; GFX6-NEXT:    s_or_b64 s[0:1], s[24:25], s[0:1]
6531; GFX6-NEXT:    s_sub_i32 s11, s8, 64
6532; GFX6-NEXT:    s_sub_i32 s9, 64, s8
6533; GFX6-NEXT:    s_cmp_lt_u32 s8, 64
6534; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
6535; GFX6-NEXT:    s_cmp_eq_u32 s8, 0
6536; GFX6-NEXT:    s_cselect_b32 s21, 1, 0
6537; GFX6-NEXT:    s_lshl_b64 s[16:17], s[4:5], s8
6538; GFX6-NEXT:    s_lshr_b64 s[18:19], s[4:5], s9
6539; GFX6-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
6540; GFX6-NEXT:    s_or_b64 s[8:9], s[18:19], s[8:9]
6541; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s11
6542; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
6543; GFX6-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6544; GFX6-NEXT:    s_cselect_b64 s[4:5], s[8:9], s[4:5]
6545; GFX6-NEXT:    s_cmp_lg_u32 s21, 0
6546; GFX6-NEXT:    s_cselect_b64 s[6:7], s[6:7], s[4:5]
6547; GFX6-NEXT:    s_cmp_lt_u32 1, 64
6548; GFX6-NEXT:    s_cselect_b32 s11, 1, 0
6549; GFX6-NEXT:    s_cmp_eq_u32 1, 0
6550; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
6551; GFX6-NEXT:    s_lshr_b64 s[8:9], s[12:13], 1
6552; GFX6-NEXT:    s_lshl_b64 s[18:19], s[14:15], s29
6553; GFX6-NEXT:    s_lshr_b64 s[4:5], s[14:15], 1
6554; GFX6-NEXT:    s_or_b64 s[8:9], s[8:9], s[18:19]
6555; GFX6-NEXT:    s_lshr_b64 s[14:15], s[14:15], s28
6556; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
6557; GFX6-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6558; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
6559; GFX6-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6560; GFX6-NEXT:    s_cmp_lg_u32 s11, 0
6561; GFX6-NEXT:    s_cselect_b64 s[4:5], s[4:5], 0
6562; GFX6-NEXT:    s_sub_i32 s18, s10, 64
6563; GFX6-NEXT:    s_sub_i32 s14, 64, s10
6564; GFX6-NEXT:    s_cmp_lt_u32 s10, 64
6565; GFX6-NEXT:    s_cselect_b32 s19, 1, 0
6566; GFX6-NEXT:    s_cmp_eq_u32 s10, 0
6567; GFX6-NEXT:    s_cselect_b32 s20, 1, 0
6568; GFX6-NEXT:    s_lshr_b64 s[12:13], s[4:5], s10
6569; GFX6-NEXT:    s_lshl_b64 s[14:15], s[4:5], s14
6570; GFX6-NEXT:    s_lshr_b64 s[10:11], s[8:9], s10
6571; GFX6-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
6572; GFX6-NEXT:    s_lshr_b64 s[4:5], s[4:5], s18
6573; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
6574; GFX6-NEXT:    s_cselect_b64 s[4:5], s[10:11], s[4:5]
6575; GFX6-NEXT:    s_cmp_lg_u32 s20, 0
6576; GFX6-NEXT:    s_cselect_b64 s[4:5], s[8:9], s[4:5]
6577; GFX6-NEXT:    s_cmp_lg_u32 s19, 0
6578; GFX6-NEXT:    s_cselect_b64 s[8:9], s[12:13], 0
6579; GFX6-NEXT:    s_or_b64 s[4:5], s[16:17], s[4:5]
6580; GFX6-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6581; GFX6-NEXT:    ; return to shader part epilog
6582;
6583; GFX8-LABEL: s_fshl_v2i128:
6584; GFX8:       ; %bb.0:
6585; GFX8-NEXT:    s_movk_i32 s18, 0x7f
6586; GFX8-NEXT:    s_mov_b32 s19, 0
6587; GFX8-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6588; GFX8-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6589; GFX8-NEXT:    s_sub_i32 s17, s22, 64
6590; GFX8-NEXT:    s_sub_i32 s23, 64, s22
6591; GFX8-NEXT:    s_cmp_lt_u32 s22, 64
6592; GFX8-NEXT:    s_cselect_b32 s28, 1, 0
6593; GFX8-NEXT:    s_cmp_eq_u32 s22, 0
6594; GFX8-NEXT:    s_cselect_b32 s29, 1, 0
6595; GFX8-NEXT:    s_lshl_b64 s[24:25], s[0:1], s22
6596; GFX8-NEXT:    s_lshr_b64 s[26:27], s[0:1], s23
6597; GFX8-NEXT:    s_lshl_b64 s[22:23], s[2:3], s22
6598; GFX8-NEXT:    s_or_b64 s[22:23], s[26:27], s[22:23]
6599; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s17
6600; GFX8-NEXT:    s_cmp_lg_u32 s28, 0
6601; GFX8-NEXT:    s_cselect_b64 s[24:25], s[24:25], 0
6602; GFX8-NEXT:    s_cselect_b64 s[0:1], s[22:23], s[0:1]
6603; GFX8-NEXT:    s_cmp_lg_u32 s29, 0
6604; GFX8-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6605; GFX8-NEXT:    s_sub_i32 s28, 1, 64
6606; GFX8-NEXT:    s_sub_i32 s29, 64, 1
6607; GFX8-NEXT:    s_cmp_lt_u32 1, 64
6608; GFX8-NEXT:    s_cselect_b32 s17, 1, 0
6609; GFX8-NEXT:    s_cmp_eq_u32 1, 0
6610; GFX8-NEXT:    s_cselect_b32 s30, 1, 0
6611; GFX8-NEXT:    s_lshr_b64 s[22:23], s[8:9], 1
6612; GFX8-NEXT:    s_lshl_b64 s[26:27], s[10:11], s29
6613; GFX8-NEXT:    s_lshr_b64 s[0:1], s[10:11], 1
6614; GFX8-NEXT:    s_or_b64 s[22:23], s[22:23], s[26:27]
6615; GFX8-NEXT:    s_lshr_b64 s[10:11], s[10:11], s28
6616; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
6617; GFX8-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
6618; GFX8-NEXT:    s_cmp_lg_u32 s30, 0
6619; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
6620; GFX8-NEXT:    s_cmp_lg_u32 s17, 0
6621; GFX8-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
6622; GFX8-NEXT:    s_sub_i32 s26, s16, 64
6623; GFX8-NEXT:    s_sub_i32 s22, 64, s16
6624; GFX8-NEXT:    s_cmp_lt_u32 s16, 64
6625; GFX8-NEXT:    s_cselect_b32 s27, 1, 0
6626; GFX8-NEXT:    s_cmp_eq_u32 s16, 0
6627; GFX8-NEXT:    s_cselect_b32 s30, 1, 0
6628; GFX8-NEXT:    s_lshr_b64 s[10:11], s[0:1], s16
6629; GFX8-NEXT:    s_lshl_b64 s[22:23], s[0:1], s22
6630; GFX8-NEXT:    s_lshr_b64 s[16:17], s[8:9], s16
6631; GFX8-NEXT:    s_or_b64 s[16:17], s[16:17], s[22:23]
6632; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], s26
6633; GFX8-NEXT:    s_cmp_lg_u32 s27, 0
6634; GFX8-NEXT:    s_cselect_b64 s[0:1], s[16:17], s[0:1]
6635; GFX8-NEXT:    s_cmp_lg_u32 s30, 0
6636; GFX8-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6637; GFX8-NEXT:    s_cmp_lg_u32 s27, 0
6638; GFX8-NEXT:    s_cselect_b64 s[8:9], s[10:11], 0
6639; GFX8-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
6640; GFX8-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6641; GFX8-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6642; GFX8-NEXT:    s_or_b64 s[0:1], s[24:25], s[0:1]
6643; GFX8-NEXT:    s_sub_i32 s11, s8, 64
6644; GFX8-NEXT:    s_sub_i32 s9, 64, s8
6645; GFX8-NEXT:    s_cmp_lt_u32 s8, 64
6646; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
6647; GFX8-NEXT:    s_cmp_eq_u32 s8, 0
6648; GFX8-NEXT:    s_cselect_b32 s21, 1, 0
6649; GFX8-NEXT:    s_lshl_b64 s[16:17], s[4:5], s8
6650; GFX8-NEXT:    s_lshr_b64 s[18:19], s[4:5], s9
6651; GFX8-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
6652; GFX8-NEXT:    s_or_b64 s[8:9], s[18:19], s[8:9]
6653; GFX8-NEXT:    s_lshl_b64 s[4:5], s[4:5], s11
6654; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
6655; GFX8-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6656; GFX8-NEXT:    s_cselect_b64 s[4:5], s[8:9], s[4:5]
6657; GFX8-NEXT:    s_cmp_lg_u32 s21, 0
6658; GFX8-NEXT:    s_cselect_b64 s[6:7], s[6:7], s[4:5]
6659; GFX8-NEXT:    s_cmp_lt_u32 1, 64
6660; GFX8-NEXT:    s_cselect_b32 s11, 1, 0
6661; GFX8-NEXT:    s_cmp_eq_u32 1, 0
6662; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
6663; GFX8-NEXT:    s_lshr_b64 s[8:9], s[12:13], 1
6664; GFX8-NEXT:    s_lshl_b64 s[18:19], s[14:15], s29
6665; GFX8-NEXT:    s_lshr_b64 s[4:5], s[14:15], 1
6666; GFX8-NEXT:    s_or_b64 s[8:9], s[8:9], s[18:19]
6667; GFX8-NEXT:    s_lshr_b64 s[14:15], s[14:15], s28
6668; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
6669; GFX8-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6670; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
6671; GFX8-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6672; GFX8-NEXT:    s_cmp_lg_u32 s11, 0
6673; GFX8-NEXT:    s_cselect_b64 s[4:5], s[4:5], 0
6674; GFX8-NEXT:    s_sub_i32 s18, s10, 64
6675; GFX8-NEXT:    s_sub_i32 s14, 64, s10
6676; GFX8-NEXT:    s_cmp_lt_u32 s10, 64
6677; GFX8-NEXT:    s_cselect_b32 s19, 1, 0
6678; GFX8-NEXT:    s_cmp_eq_u32 s10, 0
6679; GFX8-NEXT:    s_cselect_b32 s20, 1, 0
6680; GFX8-NEXT:    s_lshr_b64 s[12:13], s[4:5], s10
6681; GFX8-NEXT:    s_lshl_b64 s[14:15], s[4:5], s14
6682; GFX8-NEXT:    s_lshr_b64 s[10:11], s[8:9], s10
6683; GFX8-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
6684; GFX8-NEXT:    s_lshr_b64 s[4:5], s[4:5], s18
6685; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
6686; GFX8-NEXT:    s_cselect_b64 s[4:5], s[10:11], s[4:5]
6687; GFX8-NEXT:    s_cmp_lg_u32 s20, 0
6688; GFX8-NEXT:    s_cselect_b64 s[4:5], s[8:9], s[4:5]
6689; GFX8-NEXT:    s_cmp_lg_u32 s19, 0
6690; GFX8-NEXT:    s_cselect_b64 s[8:9], s[12:13], 0
6691; GFX8-NEXT:    s_or_b64 s[4:5], s[16:17], s[4:5]
6692; GFX8-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6693; GFX8-NEXT:    ; return to shader part epilog
6694;
6695; GFX9-LABEL: s_fshl_v2i128:
6696; GFX9:       ; %bb.0:
6697; GFX9-NEXT:    s_movk_i32 s18, 0x7f
6698; GFX9-NEXT:    s_mov_b32 s19, 0
6699; GFX9-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6700; GFX9-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6701; GFX9-NEXT:    s_sub_i32 s17, s22, 64
6702; GFX9-NEXT:    s_sub_i32 s23, 64, s22
6703; GFX9-NEXT:    s_cmp_lt_u32 s22, 64
6704; GFX9-NEXT:    s_cselect_b32 s28, 1, 0
6705; GFX9-NEXT:    s_cmp_eq_u32 s22, 0
6706; GFX9-NEXT:    s_cselect_b32 s29, 1, 0
6707; GFX9-NEXT:    s_lshl_b64 s[24:25], s[0:1], s22
6708; GFX9-NEXT:    s_lshr_b64 s[26:27], s[0:1], s23
6709; GFX9-NEXT:    s_lshl_b64 s[22:23], s[2:3], s22
6710; GFX9-NEXT:    s_or_b64 s[22:23], s[26:27], s[22:23]
6711; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], s17
6712; GFX9-NEXT:    s_cmp_lg_u32 s28, 0
6713; GFX9-NEXT:    s_cselect_b64 s[24:25], s[24:25], 0
6714; GFX9-NEXT:    s_cselect_b64 s[0:1], s[22:23], s[0:1]
6715; GFX9-NEXT:    s_cmp_lg_u32 s29, 0
6716; GFX9-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6717; GFX9-NEXT:    s_sub_i32 s28, 1, 64
6718; GFX9-NEXT:    s_sub_i32 s29, 64, 1
6719; GFX9-NEXT:    s_cmp_lt_u32 1, 64
6720; GFX9-NEXT:    s_cselect_b32 s17, 1, 0
6721; GFX9-NEXT:    s_cmp_eq_u32 1, 0
6722; GFX9-NEXT:    s_cselect_b32 s30, 1, 0
6723; GFX9-NEXT:    s_lshr_b64 s[22:23], s[8:9], 1
6724; GFX9-NEXT:    s_lshl_b64 s[26:27], s[10:11], s29
6725; GFX9-NEXT:    s_lshr_b64 s[0:1], s[10:11], 1
6726; GFX9-NEXT:    s_or_b64 s[22:23], s[22:23], s[26:27]
6727; GFX9-NEXT:    s_lshr_b64 s[10:11], s[10:11], s28
6728; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
6729; GFX9-NEXT:    s_cselect_b64 s[10:11], s[22:23], s[10:11]
6730; GFX9-NEXT:    s_cmp_lg_u32 s30, 0
6731; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[10:11]
6732; GFX9-NEXT:    s_cmp_lg_u32 s17, 0
6733; GFX9-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
6734; GFX9-NEXT:    s_sub_i32 s26, s16, 64
6735; GFX9-NEXT:    s_sub_i32 s22, 64, s16
6736; GFX9-NEXT:    s_cmp_lt_u32 s16, 64
6737; GFX9-NEXT:    s_cselect_b32 s27, 1, 0
6738; GFX9-NEXT:    s_cmp_eq_u32 s16, 0
6739; GFX9-NEXT:    s_cselect_b32 s30, 1, 0
6740; GFX9-NEXT:    s_lshr_b64 s[10:11], s[0:1], s16
6741; GFX9-NEXT:    s_lshl_b64 s[22:23], s[0:1], s22
6742; GFX9-NEXT:    s_lshr_b64 s[16:17], s[8:9], s16
6743; GFX9-NEXT:    s_or_b64 s[16:17], s[16:17], s[22:23]
6744; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], s26
6745; GFX9-NEXT:    s_cmp_lg_u32 s27, 0
6746; GFX9-NEXT:    s_cselect_b64 s[0:1], s[16:17], s[0:1]
6747; GFX9-NEXT:    s_cmp_lg_u32 s30, 0
6748; GFX9-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6749; GFX9-NEXT:    s_cmp_lg_u32 s27, 0
6750; GFX9-NEXT:    s_cselect_b64 s[8:9], s[10:11], 0
6751; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
6752; GFX9-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6753; GFX9-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6754; GFX9-NEXT:    s_or_b64 s[0:1], s[24:25], s[0:1]
6755; GFX9-NEXT:    s_sub_i32 s11, s8, 64
6756; GFX9-NEXT:    s_sub_i32 s9, 64, s8
6757; GFX9-NEXT:    s_cmp_lt_u32 s8, 64
6758; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
6759; GFX9-NEXT:    s_cmp_eq_u32 s8, 0
6760; GFX9-NEXT:    s_cselect_b32 s21, 1, 0
6761; GFX9-NEXT:    s_lshl_b64 s[16:17], s[4:5], s8
6762; GFX9-NEXT:    s_lshr_b64 s[18:19], s[4:5], s9
6763; GFX9-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
6764; GFX9-NEXT:    s_or_b64 s[8:9], s[18:19], s[8:9]
6765; GFX9-NEXT:    s_lshl_b64 s[4:5], s[4:5], s11
6766; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
6767; GFX9-NEXT:    s_cselect_b64 s[16:17], s[16:17], 0
6768; GFX9-NEXT:    s_cselect_b64 s[4:5], s[8:9], s[4:5]
6769; GFX9-NEXT:    s_cmp_lg_u32 s21, 0
6770; GFX9-NEXT:    s_cselect_b64 s[6:7], s[6:7], s[4:5]
6771; GFX9-NEXT:    s_cmp_lt_u32 1, 64
6772; GFX9-NEXT:    s_cselect_b32 s11, 1, 0
6773; GFX9-NEXT:    s_cmp_eq_u32 1, 0
6774; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
6775; GFX9-NEXT:    s_lshr_b64 s[8:9], s[12:13], 1
6776; GFX9-NEXT:    s_lshl_b64 s[18:19], s[14:15], s29
6777; GFX9-NEXT:    s_lshr_b64 s[4:5], s[14:15], 1
6778; GFX9-NEXT:    s_or_b64 s[8:9], s[8:9], s[18:19]
6779; GFX9-NEXT:    s_lshr_b64 s[14:15], s[14:15], s28
6780; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
6781; GFX9-NEXT:    s_cselect_b64 s[8:9], s[8:9], s[14:15]
6782; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
6783; GFX9-NEXT:    s_cselect_b64 s[8:9], s[12:13], s[8:9]
6784; GFX9-NEXT:    s_cmp_lg_u32 s11, 0
6785; GFX9-NEXT:    s_cselect_b64 s[4:5], s[4:5], 0
6786; GFX9-NEXT:    s_sub_i32 s18, s10, 64
6787; GFX9-NEXT:    s_sub_i32 s14, 64, s10
6788; GFX9-NEXT:    s_cmp_lt_u32 s10, 64
6789; GFX9-NEXT:    s_cselect_b32 s19, 1, 0
6790; GFX9-NEXT:    s_cmp_eq_u32 s10, 0
6791; GFX9-NEXT:    s_cselect_b32 s20, 1, 0
6792; GFX9-NEXT:    s_lshr_b64 s[12:13], s[4:5], s10
6793; GFX9-NEXT:    s_lshl_b64 s[14:15], s[4:5], s14
6794; GFX9-NEXT:    s_lshr_b64 s[10:11], s[8:9], s10
6795; GFX9-NEXT:    s_or_b64 s[10:11], s[10:11], s[14:15]
6796; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], s18
6797; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
6798; GFX9-NEXT:    s_cselect_b64 s[4:5], s[10:11], s[4:5]
6799; GFX9-NEXT:    s_cmp_lg_u32 s20, 0
6800; GFX9-NEXT:    s_cselect_b64 s[4:5], s[8:9], s[4:5]
6801; GFX9-NEXT:    s_cmp_lg_u32 s19, 0
6802; GFX9-NEXT:    s_cselect_b64 s[8:9], s[12:13], 0
6803; GFX9-NEXT:    s_or_b64 s[4:5], s[16:17], s[4:5]
6804; GFX9-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
6805; GFX9-NEXT:    ; return to shader part epilog
6806;
6807; GFX10-LABEL: s_fshl_v2i128:
6808; GFX10:       ; %bb.0:
6809; GFX10-NEXT:    s_movk_i32 s18, 0x7f
6810; GFX10-NEXT:    s_mov_b32 s19, 0
6811; GFX10-NEXT:    s_and_b64 s[22:23], s[16:17], s[18:19]
6812; GFX10-NEXT:    s_andn2_b64 s[16:17], s[18:19], s[16:17]
6813; GFX10-NEXT:    s_sub_i32 s17, s22, 64
6814; GFX10-NEXT:    s_sub_i32 s23, 64, s22
6815; GFX10-NEXT:    s_cmp_lt_u32 s22, 64
6816; GFX10-NEXT:    s_cselect_b32 s28, 1, 0
6817; GFX10-NEXT:    s_cmp_eq_u32 s22, 0
6818; GFX10-NEXT:    s_cselect_b32 s29, 1, 0
6819; GFX10-NEXT:    s_lshr_b64 s[24:25], s[0:1], s23
6820; GFX10-NEXT:    s_lshl_b64 s[26:27], s[2:3], s22
6821; GFX10-NEXT:    s_lshl_b64 s[22:23], s[0:1], s22
6822; GFX10-NEXT:    s_or_b64 s[24:25], s[24:25], s[26:27]
6823; GFX10-NEXT:    s_lshl_b64 s[0:1], s[0:1], s17
6824; GFX10-NEXT:    s_cmp_lg_u32 s28, 0
6825; GFX10-NEXT:    s_cselect_b64 s[22:23], s[22:23], 0
6826; GFX10-NEXT:    s_cselect_b64 s[0:1], s[24:25], s[0:1]
6827; GFX10-NEXT:    s_cmp_lg_u32 s29, 0
6828; GFX10-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[0:1]
6829; GFX10-NEXT:    s_sub_i32 s28, 1, 64
6830; GFX10-NEXT:    s_sub_i32 s29, 64, 1
6831; GFX10-NEXT:    s_cmp_lt_u32 1, 64
6832; GFX10-NEXT:    s_cselect_b32 s17, 1, 0
6833; GFX10-NEXT:    s_cmp_eq_u32 1, 0
6834; GFX10-NEXT:    s_cselect_b32 s30, 1, 0
6835; GFX10-NEXT:    s_lshr_b64 s[0:1], s[8:9], 1
6836; GFX10-NEXT:    s_lshl_b64 s[24:25], s[10:11], s29
6837; GFX10-NEXT:    s_lshr_b64 s[26:27], s[10:11], 1
6838; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[24:25]
6839; GFX10-NEXT:    s_lshr_b64 s[10:11], s[10:11], s28
6840; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
6841; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[10:11]
6842; GFX10-NEXT:    s_cmp_lg_u32 s30, 0
6843; GFX10-NEXT:    s_cselect_b64 s[0:1], s[8:9], s[0:1]
6844; GFX10-NEXT:    s_cmp_lg_u32 s17, 0
6845; GFX10-NEXT:    s_cselect_b64 s[8:9], s[26:27], 0
6846; GFX10-NEXT:    s_sub_i32 s26, s16, 64
6847; GFX10-NEXT:    s_sub_i32 s17, 64, s16
6848; GFX10-NEXT:    s_cmp_lt_u32 s16, 64
6849; GFX10-NEXT:    s_cselect_b32 s27, 1, 0
6850; GFX10-NEXT:    s_cmp_eq_u32 s16, 0
6851; GFX10-NEXT:    s_cselect_b32 s30, 1, 0
6852; GFX10-NEXT:    s_lshr_b64 s[10:11], s[0:1], s16
6853; GFX10-NEXT:    s_lshl_b64 s[24:25], s[8:9], s17
6854; GFX10-NEXT:    s_lshr_b64 s[16:17], s[8:9], s16
6855; GFX10-NEXT:    s_or_b64 s[10:11], s[10:11], s[24:25]
6856; GFX10-NEXT:    s_lshr_b64 s[8:9], s[8:9], s26
6857; GFX10-NEXT:    s_cmp_lg_u32 s27, 0
6858; GFX10-NEXT:    s_cselect_b64 s[8:9], s[10:11], s[8:9]
6859; GFX10-NEXT:    s_cmp_lg_u32 s30, 0
6860; GFX10-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[8:9]
6861; GFX10-NEXT:    s_cmp_lg_u32 s27, 0
6862; GFX10-NEXT:    s_cselect_b64 s[8:9], s[16:17], 0
6863; GFX10-NEXT:    s_andn2_b64 s[10:11], s[18:19], s[20:21]
6864; GFX10-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
6865; GFX10-NEXT:    s_and_b64 s[8:9], s[20:21], s[18:19]
6866; GFX10-NEXT:    s_or_b64 s[0:1], s[22:23], s[0:1]
6867; GFX10-NEXT:    s_sub_i32 s11, s8, 64
6868; GFX10-NEXT:    s_sub_i32 s9, 64, s8
6869; GFX10-NEXT:    s_cmp_lt_u32 s8, 64
6870; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
6871; GFX10-NEXT:    s_cmp_eq_u32 s8, 0
6872; GFX10-NEXT:    s_cselect_b32 s21, 1, 0
6873; GFX10-NEXT:    s_lshr_b64 s[16:17], s[4:5], s9
6874; GFX10-NEXT:    s_lshl_b64 s[18:19], s[6:7], s8
6875; GFX10-NEXT:    s_lshl_b64 s[8:9], s[4:5], s8
6876; GFX10-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
6877; GFX10-NEXT:    s_lshl_b64 s[4:5], s[4:5], s11
6878; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
6879; GFX10-NEXT:    s_cselect_b64 s[8:9], s[8:9], 0
6880; GFX10-NEXT:    s_cselect_b64 s[4:5], s[16:17], s[4:5]
6881; GFX10-NEXT:    s_cmp_lg_u32 s21, 0
6882; GFX10-NEXT:    s_cselect_b64 s[6:7], s[6:7], s[4:5]
6883; GFX10-NEXT:    s_cmp_lt_u32 1, 64
6884; GFX10-NEXT:    s_cselect_b32 s11, 1, 0
6885; GFX10-NEXT:    s_cmp_eq_u32 1, 0
6886; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
6887; GFX10-NEXT:    s_lshr_b64 s[4:5], s[12:13], 1
6888; GFX10-NEXT:    s_lshl_b64 s[16:17], s[14:15], s29
6889; GFX10-NEXT:    s_lshr_b64 s[18:19], s[14:15], 1
6890; GFX10-NEXT:    s_or_b64 s[4:5], s[4:5], s[16:17]
6891; GFX10-NEXT:    s_lshr_b64 s[14:15], s[14:15], s28
6892; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6893; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[14:15]
6894; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
6895; GFX10-NEXT:    s_cselect_b64 s[4:5], s[12:13], s[4:5]
6896; GFX10-NEXT:    s_cmp_lg_u32 s11, 0
6897; GFX10-NEXT:    s_cselect_b64 s[12:13], s[18:19], 0
6898; GFX10-NEXT:    s_sub_i32 s18, s10, 64
6899; GFX10-NEXT:    s_sub_i32 s11, 64, s10
6900; GFX10-NEXT:    s_cmp_lt_u32 s10, 64
6901; GFX10-NEXT:    s_cselect_b32 s19, 1, 0
6902; GFX10-NEXT:    s_cmp_eq_u32 s10, 0
6903; GFX10-NEXT:    s_cselect_b32 s20, 1, 0
6904; GFX10-NEXT:    s_lshr_b64 s[14:15], s[4:5], s10
6905; GFX10-NEXT:    s_lshl_b64 s[16:17], s[12:13], s11
6906; GFX10-NEXT:    s_lshr_b64 s[10:11], s[12:13], s10
6907; GFX10-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
6908; GFX10-NEXT:    s_lshr_b64 s[12:13], s[12:13], s18
6909; GFX10-NEXT:    s_cmp_lg_u32 s19, 0
6910; GFX10-NEXT:    s_cselect_b64 s[12:13], s[14:15], s[12:13]
6911; GFX10-NEXT:    s_cmp_lg_u32 s20, 0
6912; GFX10-NEXT:    s_cselect_b64 s[4:5], s[4:5], s[12:13]
6913; GFX10-NEXT:    s_cmp_lg_u32 s19, 0
6914; GFX10-NEXT:    s_cselect_b64 s[10:11], s[10:11], 0
6915; GFX10-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
6916; GFX10-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
6917; GFX10-NEXT:    ; return to shader part epilog
6918  %result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
6919  ret <2 x i128> %result
6920}
6921
6922define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) {
6923; GFX6-LABEL: v_fshl_v2i128:
6924; GFX6:       ; %bb.0:
6925; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
6926; GFX6-NEXT:    s_movk_i32 s6, 0x7f
6927; GFX6-NEXT:    v_and_b32_e32 v23, s6, v16
6928; GFX6-NEXT:    v_sub_i32_e32 v17, vcc, 64, v23
6929; GFX6-NEXT:    v_lshr_b64 v[17:18], v[0:1], v17
6930; GFX6-NEXT:    v_lshl_b64 v[21:22], v[2:3], v23
6931; GFX6-NEXT:    s_sub_i32 s7, 64, 1
6932; GFX6-NEXT:    s_sub_i32 s8, 1, 64
6933; GFX6-NEXT:    s_cmp_lt_u32 1, 64
6934; GFX6-NEXT:    v_or_b32_e32 v24, v17, v21
6935; GFX6-NEXT:    v_or_b32_e32 v25, v18, v22
6936; GFX6-NEXT:    v_lshr_b64 v[17:18], v[8:9], 1
6937; GFX6-NEXT:    v_lshl_b64 v[21:22], v[10:11], s7
6938; GFX6-NEXT:    s_cselect_b32 s4, 1, 0
6939; GFX6-NEXT:    s_cmp_eq_u32 1, 0
6940; GFX6-NEXT:    v_or_b32_e32 v19, v17, v21
6941; GFX6-NEXT:    v_or_b32_e32 v21, v18, v22
6942; GFX6-NEXT:    s_cselect_b32 s5, 1, 0
6943; GFX6-NEXT:    s_and_b32 s4, 1, s4
6944; GFX6-NEXT:    v_lshr_b64 v[17:18], v[10:11], s8
6945; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
6946; GFX6-NEXT:    s_and_b32 s4, 1, s5
6947; GFX6-NEXT:    v_lshr_b64 v[10:11], v[10:11], 1
6948; GFX6-NEXT:    v_xor_b32_e32 v16, -1, v16
6949; GFX6-NEXT:    v_cndmask_b32_e32 v18, v18, v21, vcc
6950; GFX6-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, s4
6951; GFX6-NEXT:    v_cndmask_b32_e32 v17, v17, v19, vcc
6952; GFX6-NEXT:    v_and_b32_e32 v21, s6, v16
6953; GFX6-NEXT:    v_cndmask_b32_e64 v8, v17, v8, s[4:5]
6954; GFX6-NEXT:    v_cndmask_b32_e64 v9, v18, v9, s[4:5]
6955; GFX6-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
6956; GFX6-NEXT:    v_cndmask_b32_e32 v11, 0, v11, vcc
6957; GFX6-NEXT:    v_sub_i32_e32 v16, vcc, 64, v21
6958; GFX6-NEXT:    v_lshl_b64 v[16:17], v[10:11], v16
6959; GFX6-NEXT:    v_lshr_b64 v[18:19], v[8:9], v21
6960; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
6961; GFX6-NEXT:    v_or_b32_e32 v18, v18, v16
6962; GFX6-NEXT:    v_subrev_i32_e32 v16, vcc, 64, v23
6963; GFX6-NEXT:    v_or_b32_e32 v19, v19, v17
6964; GFX6-NEXT:    v_lshl_b64 v[16:17], v[0:1], v16
6965; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], v23
6966; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
6967; GFX6-NEXT:    v_cndmask_b32_e32 v22, 0, v0, vcc
6968; GFX6-NEXT:    v_cndmask_b32_e32 v0, v16, v24, vcc
6969; GFX6-NEXT:    v_cndmask_b32_e32 v16, v17, v25, vcc
6970; GFX6-NEXT:    v_cndmask_b32_e64 v17, v0, v2, s[4:5]
6971; GFX6-NEXT:    v_cndmask_b32_e64 v16, v16, v3, s[4:5]
6972; GFX6-NEXT:    v_subrev_i32_e64 v0, s[4:5], 64, v21
6973; GFX6-NEXT:    v_lshr_b64 v[2:3], v[10:11], v0
6974; GFX6-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v21
6975; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v18, s[4:5]
6976; GFX6-NEXT:    v_cndmask_b32_e32 v18, 0, v1, vcc
6977; GFX6-NEXT:    v_lshr_b64 v[0:1], v[10:11], v21
6978; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v21
6979; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v19, s[4:5]
6980; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
6981; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
6982; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, v0, s[4:5]
6983; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, v1, s[4:5]
6984; GFX6-NEXT:    v_or_b32_e32 v0, v22, v2
6985; GFX6-NEXT:    v_or_b32_e32 v1, v18, v3
6986; GFX6-NEXT:    v_or_b32_e32 v2, v17, v8
6987; GFX6-NEXT:    v_or_b32_e32 v3, v16, v9
6988; GFX6-NEXT:    v_and_b32_e32 v16, s6, v20
6989; GFX6-NEXT:    v_xor_b32_e32 v8, -1, v20
6990; GFX6-NEXT:    v_and_b32_e32 v17, s6, v8
6991; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, 64, v16
6992; GFX6-NEXT:    v_lshr_b64 v[8:9], v[4:5], v8
6993; GFX6-NEXT:    v_lshl_b64 v[10:11], v[6:7], v16
6994; GFX6-NEXT:    v_subrev_i32_e32 v18, vcc, 64, v16
6995; GFX6-NEXT:    v_or_b32_e32 v10, v8, v10
6996; GFX6-NEXT:    v_or_b32_e32 v11, v9, v11
6997; GFX6-NEXT:    v_lshl_b64 v[8:9], v[4:5], v16
6998; GFX6-NEXT:    v_lshl_b64 v[4:5], v[4:5], v18
6999; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
7000; GFX6-NEXT:    v_cndmask_b32_e32 v18, 0, v8, vcc
7001; GFX6-NEXT:    v_cndmask_b32_e32 v19, 0, v9, vcc
7002; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
7003; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
7004; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v16
7005; GFX6-NEXT:    s_cmp_lt_u32 1, 64
7006; GFX6-NEXT:    v_cndmask_b32_e32 v16, v4, v6, vcc
7007; GFX6-NEXT:    v_cndmask_b32_e32 v20, v5, v7, vcc
7008; GFX6-NEXT:    v_lshr_b64 v[4:5], v[12:13], 1
7009; GFX6-NEXT:    v_lshl_b64 v[6:7], v[14:15], s7
7010; GFX6-NEXT:    s_cselect_b32 s4, 1, 0
7011; GFX6-NEXT:    s_cmp_eq_u32 1, 0
7012; GFX6-NEXT:    s_cselect_b32 s5, 1, 0
7013; GFX6-NEXT:    s_and_b32 s6, 1, s4
7014; GFX6-NEXT:    v_or_b32_e32 v6, v4, v6
7015; GFX6-NEXT:    v_or_b32_e32 v7, v5, v7
7016; GFX6-NEXT:    v_lshr_b64 v[4:5], v[14:15], s8
7017; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s6
7018; GFX6-NEXT:    s_and_b32 s5, 1, s5
7019; GFX6-NEXT:    v_lshr_b64 v[8:9], v[14:15], 1
7020; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
7021; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7022; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
7023; GFX6-NEXT:    s_and_b32 s4, 1, s4
7024; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
7025; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
7026; GFX6-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7027; GFX6-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
7028; GFX6-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
7029; GFX6-NEXT:    v_sub_i32_e32 v10, vcc, 64, v17
7030; GFX6-NEXT:    v_lshr_b64 v[8:9], v[4:5], v17
7031; GFX6-NEXT:    v_lshl_b64 v[10:11], v[6:7], v10
7032; GFX6-NEXT:    v_subrev_i32_e32 v12, vcc, 64, v17
7033; GFX6-NEXT:    v_or_b32_e32 v10, v8, v10
7034; GFX6-NEXT:    v_or_b32_e32 v11, v9, v11
7035; GFX6-NEXT:    v_lshr_b64 v[8:9], v[6:7], v17
7036; GFX6-NEXT:    v_lshr_b64 v[6:7], v[6:7], v12
7037; GFX6-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
7038; GFX6-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
7039; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v17
7040; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc
7041; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
7042; GFX6-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[4:5]
7043; GFX6-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
7044; GFX6-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
7045; GFX6-NEXT:    v_or_b32_e32 v4, v18, v4
7046; GFX6-NEXT:    v_or_b32_e32 v5, v19, v5
7047; GFX6-NEXT:    v_or_b32_e32 v6, v16, v6
7048; GFX6-NEXT:    v_or_b32_e32 v7, v20, v7
7049; GFX6-NEXT:    s_setpc_b64 s[30:31]
7050;
7051; GFX8-LABEL: v_fshl_v2i128:
7052; GFX8:       ; %bb.0:
7053; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7054; GFX8-NEXT:    s_movk_i32 s6, 0x7f
7055; GFX8-NEXT:    v_and_b32_e32 v23, s6, v16
7056; GFX8-NEXT:    v_sub_u32_e32 v17, vcc, 64, v23
7057; GFX8-NEXT:    v_lshrrev_b64 v[17:18], v17, v[0:1]
7058; GFX8-NEXT:    v_lshlrev_b64 v[21:22], v23, v[2:3]
7059; GFX8-NEXT:    s_sub_i32 s7, 64, 1
7060; GFX8-NEXT:    s_sub_i32 s8, 1, 64
7061; GFX8-NEXT:    s_cmp_lt_u32 1, 64
7062; GFX8-NEXT:    v_or_b32_e32 v24, v17, v21
7063; GFX8-NEXT:    v_or_b32_e32 v25, v18, v22
7064; GFX8-NEXT:    v_lshrrev_b64 v[17:18], 1, v[8:9]
7065; GFX8-NEXT:    v_lshlrev_b64 v[21:22], s7, v[10:11]
7066; GFX8-NEXT:    s_cselect_b32 s4, 1, 0
7067; GFX8-NEXT:    s_cmp_eq_u32 1, 0
7068; GFX8-NEXT:    v_or_b32_e32 v19, v17, v21
7069; GFX8-NEXT:    v_or_b32_e32 v21, v18, v22
7070; GFX8-NEXT:    s_cselect_b32 s5, 1, 0
7071; GFX8-NEXT:    s_and_b32 s4, 1, s4
7072; GFX8-NEXT:    v_lshrrev_b64 v[17:18], s8, v[10:11]
7073; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7074; GFX8-NEXT:    s_and_b32 s4, 1, s5
7075; GFX8-NEXT:    v_lshrrev_b64 v[10:11], 1, v[10:11]
7076; GFX8-NEXT:    v_xor_b32_e32 v16, -1, v16
7077; GFX8-NEXT:    v_cndmask_b32_e32 v18, v18, v21, vcc
7078; GFX8-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, s4
7079; GFX8-NEXT:    v_cndmask_b32_e32 v17, v17, v19, vcc
7080; GFX8-NEXT:    v_and_b32_e32 v21, s6, v16
7081; GFX8-NEXT:    v_cndmask_b32_e64 v8, v17, v8, s[4:5]
7082; GFX8-NEXT:    v_cndmask_b32_e64 v9, v18, v9, s[4:5]
7083; GFX8-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
7084; GFX8-NEXT:    v_cndmask_b32_e32 v11, 0, v11, vcc
7085; GFX8-NEXT:    v_sub_u32_e32 v16, vcc, 64, v21
7086; GFX8-NEXT:    v_lshlrev_b64 v[16:17], v16, v[10:11]
7087; GFX8-NEXT:    v_lshrrev_b64 v[18:19], v21, v[8:9]
7088; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
7089; GFX8-NEXT:    v_or_b32_e32 v18, v18, v16
7090; GFX8-NEXT:    v_subrev_u32_e32 v16, vcc, 64, v23
7091; GFX8-NEXT:    v_or_b32_e32 v19, v19, v17
7092; GFX8-NEXT:    v_lshlrev_b64 v[16:17], v16, v[0:1]
7093; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v23, v[0:1]
7094; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
7095; GFX8-NEXT:    v_cndmask_b32_e32 v22, 0, v0, vcc
7096; GFX8-NEXT:    v_cndmask_b32_e32 v0, v16, v24, vcc
7097; GFX8-NEXT:    v_cndmask_b32_e32 v16, v17, v25, vcc
7098; GFX8-NEXT:    v_cndmask_b32_e64 v17, v0, v2, s[4:5]
7099; GFX8-NEXT:    v_cndmask_b32_e64 v16, v16, v3, s[4:5]
7100; GFX8-NEXT:    v_subrev_u32_e64 v0, s[4:5], 64, v21
7101; GFX8-NEXT:    v_lshrrev_b64 v[2:3], v0, v[10:11]
7102; GFX8-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v21
7103; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, v18, s[4:5]
7104; GFX8-NEXT:    v_cndmask_b32_e32 v18, 0, v1, vcc
7105; GFX8-NEXT:    v_lshrrev_b64 v[0:1], v21, v[10:11]
7106; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v21
7107; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, v19, s[4:5]
7108; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
7109; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
7110; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, v0, s[4:5]
7111; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, v1, s[4:5]
7112; GFX8-NEXT:    v_or_b32_e32 v0, v22, v2
7113; GFX8-NEXT:    v_or_b32_e32 v1, v18, v3
7114; GFX8-NEXT:    v_or_b32_e32 v2, v17, v8
7115; GFX8-NEXT:    v_or_b32_e32 v3, v16, v9
7116; GFX8-NEXT:    v_and_b32_e32 v16, s6, v20
7117; GFX8-NEXT:    v_xor_b32_e32 v8, -1, v20
7118; GFX8-NEXT:    v_and_b32_e32 v17, s6, v8
7119; GFX8-NEXT:    v_sub_u32_e32 v8, vcc, 64, v16
7120; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v8, v[4:5]
7121; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v16, v[6:7]
7122; GFX8-NEXT:    v_subrev_u32_e32 v18, vcc, 64, v16
7123; GFX8-NEXT:    v_or_b32_e32 v10, v8, v10
7124; GFX8-NEXT:    v_or_b32_e32 v11, v9, v11
7125; GFX8-NEXT:    v_lshlrev_b64 v[8:9], v16, v[4:5]
7126; GFX8-NEXT:    v_lshlrev_b64 v[4:5], v18, v[4:5]
7127; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
7128; GFX8-NEXT:    v_cndmask_b32_e32 v18, 0, v8, vcc
7129; GFX8-NEXT:    v_cndmask_b32_e32 v19, 0, v9, vcc
7130; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
7131; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
7132; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v16
7133; GFX8-NEXT:    s_cmp_lt_u32 1, 64
7134; GFX8-NEXT:    v_cndmask_b32_e32 v16, v4, v6, vcc
7135; GFX8-NEXT:    v_cndmask_b32_e32 v20, v5, v7, vcc
7136; GFX8-NEXT:    v_lshrrev_b64 v[4:5], 1, v[12:13]
7137; GFX8-NEXT:    v_lshlrev_b64 v[6:7], s7, v[14:15]
7138; GFX8-NEXT:    s_cselect_b32 s4, 1, 0
7139; GFX8-NEXT:    s_cmp_eq_u32 1, 0
7140; GFX8-NEXT:    s_cselect_b32 s5, 1, 0
7141; GFX8-NEXT:    s_and_b32 s6, 1, s4
7142; GFX8-NEXT:    v_or_b32_e32 v6, v4, v6
7143; GFX8-NEXT:    v_or_b32_e32 v7, v5, v7
7144; GFX8-NEXT:    v_lshrrev_b64 v[4:5], s8, v[14:15]
7145; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s6
7146; GFX8-NEXT:    s_and_b32 s5, 1, s5
7147; GFX8-NEXT:    v_lshrrev_b64 v[8:9], 1, v[14:15]
7148; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
7149; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7150; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
7151; GFX8-NEXT:    s_and_b32 s4, 1, s4
7152; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
7153; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
7154; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7155; GFX8-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
7156; GFX8-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
7157; GFX8-NEXT:    v_sub_u32_e32 v10, vcc, 64, v17
7158; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v17, v[4:5]
7159; GFX8-NEXT:    v_lshlrev_b64 v[10:11], v10, v[6:7]
7160; GFX8-NEXT:    v_subrev_u32_e32 v12, vcc, 64, v17
7161; GFX8-NEXT:    v_or_b32_e32 v10, v8, v10
7162; GFX8-NEXT:    v_or_b32_e32 v11, v9, v11
7163; GFX8-NEXT:    v_lshrrev_b64 v[8:9], v17, v[6:7]
7164; GFX8-NEXT:    v_lshrrev_b64 v[6:7], v12, v[6:7]
7165; GFX8-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
7166; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
7167; GFX8-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v17
7168; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc
7169; GFX8-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
7170; GFX8-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[4:5]
7171; GFX8-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
7172; GFX8-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
7173; GFX8-NEXT:    v_or_b32_e32 v4, v18, v4
7174; GFX8-NEXT:    v_or_b32_e32 v5, v19, v5
7175; GFX8-NEXT:    v_or_b32_e32 v6, v16, v6
7176; GFX8-NEXT:    v_or_b32_e32 v7, v20, v7
7177; GFX8-NEXT:    s_setpc_b64 s[30:31]
7178;
7179; GFX9-LABEL: v_fshl_v2i128:
7180; GFX9:       ; %bb.0:
7181; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7182; GFX9-NEXT:    s_movk_i32 s6, 0x7f
7183; GFX9-NEXT:    v_and_b32_e32 v23, s6, v16
7184; GFX9-NEXT:    v_sub_u32_e32 v17, 64, v23
7185; GFX9-NEXT:    v_lshrrev_b64 v[17:18], v17, v[0:1]
7186; GFX9-NEXT:    v_lshlrev_b64 v[21:22], v23, v[2:3]
7187; GFX9-NEXT:    s_sub_i32 s7, 64, 1
7188; GFX9-NEXT:    s_sub_i32 s8, 1, 64
7189; GFX9-NEXT:    s_cmp_lt_u32 1, 64
7190; GFX9-NEXT:    v_or_b32_e32 v24, v17, v21
7191; GFX9-NEXT:    v_or_b32_e32 v25, v18, v22
7192; GFX9-NEXT:    v_lshrrev_b64 v[17:18], 1, v[8:9]
7193; GFX9-NEXT:    v_lshlrev_b64 v[21:22], s7, v[10:11]
7194; GFX9-NEXT:    s_cselect_b32 s4, 1, 0
7195; GFX9-NEXT:    s_cmp_eq_u32 1, 0
7196; GFX9-NEXT:    v_or_b32_e32 v19, v17, v21
7197; GFX9-NEXT:    v_or_b32_e32 v21, v18, v22
7198; GFX9-NEXT:    s_cselect_b32 s5, 1, 0
7199; GFX9-NEXT:    s_and_b32 s4, 1, s4
7200; GFX9-NEXT:    v_lshrrev_b64 v[17:18], s8, v[10:11]
7201; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7202; GFX9-NEXT:    s_and_b32 s4, 1, s5
7203; GFX9-NEXT:    v_lshrrev_b64 v[10:11], 1, v[10:11]
7204; GFX9-NEXT:    v_xor_b32_e32 v16, -1, v16
7205; GFX9-NEXT:    v_cndmask_b32_e32 v18, v18, v21, vcc
7206; GFX9-NEXT:    v_and_b32_e32 v21, s6, v16
7207; GFX9-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, s4
7208; GFX9-NEXT:    v_cndmask_b32_e32 v17, v17, v19, vcc
7209; GFX9-NEXT:    v_cndmask_b32_e64 v8, v17, v8, s[4:5]
7210; GFX9-NEXT:    v_cndmask_b32_e64 v9, v18, v9, s[4:5]
7211; GFX9-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
7212; GFX9-NEXT:    v_cndmask_b32_e32 v11, 0, v11, vcc
7213; GFX9-NEXT:    v_sub_u32_e32 v16, 64, v21
7214; GFX9-NEXT:    v_lshlrev_b64 v[16:17], v16, v[10:11]
7215; GFX9-NEXT:    v_lshrrev_b64 v[18:19], v21, v[8:9]
7216; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
7217; GFX9-NEXT:    v_or_b32_e32 v18, v18, v16
7218; GFX9-NEXT:    v_subrev_u32_e32 v16, 64, v23
7219; GFX9-NEXT:    v_or_b32_e32 v19, v19, v17
7220; GFX9-NEXT:    v_lshlrev_b64 v[16:17], v16, v[0:1]
7221; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v23, v[0:1]
7222; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
7223; GFX9-NEXT:    v_cndmask_b32_e32 v22, 0, v0, vcc
7224; GFX9-NEXT:    v_cndmask_b32_e32 v0, v16, v24, vcc
7225; GFX9-NEXT:    v_cndmask_b32_e32 v16, v17, v25, vcc
7226; GFX9-NEXT:    v_cndmask_b32_e64 v17, v0, v2, s[4:5]
7227; GFX9-NEXT:    v_subrev_u32_e32 v0, 64, v21
7228; GFX9-NEXT:    v_cndmask_b32_e64 v16, v16, v3, s[4:5]
7229; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v0, v[10:11]
7230; GFX9-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v21
7231; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, v18, s[4:5]
7232; GFX9-NEXT:    v_cndmask_b32_e32 v18, 0, v1, vcc
7233; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v21, v[10:11]
7234; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v21
7235; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v19, s[4:5]
7236; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
7237; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
7238; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, v0, s[4:5]
7239; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, v1, s[4:5]
7240; GFX9-NEXT:    v_or_b32_e32 v0, v22, v2
7241; GFX9-NEXT:    v_or_b32_e32 v1, v18, v3
7242; GFX9-NEXT:    v_or_b32_e32 v2, v17, v8
7243; GFX9-NEXT:    v_or_b32_e32 v3, v16, v9
7244; GFX9-NEXT:    v_and_b32_e32 v16, s6, v20
7245; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v20
7246; GFX9-NEXT:    v_and_b32_e32 v17, s6, v8
7247; GFX9-NEXT:    v_sub_u32_e32 v8, 64, v16
7248; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v8, v[4:5]
7249; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v16, v[6:7]
7250; GFX9-NEXT:    v_subrev_u32_e32 v18, 64, v16
7251; GFX9-NEXT:    v_or_b32_e32 v10, v8, v10
7252; GFX9-NEXT:    v_or_b32_e32 v11, v9, v11
7253; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v16, v[4:5]
7254; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v18, v[4:5]
7255; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
7256; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v10, vcc
7257; GFX9-NEXT:    v_cndmask_b32_e32 v18, 0, v8, vcc
7258; GFX9-NEXT:    v_cndmask_b32_e32 v19, 0, v9, vcc
7259; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v11, vcc
7260; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v16
7261; GFX9-NEXT:    s_cmp_lt_u32 1, 64
7262; GFX9-NEXT:    v_cndmask_b32_e32 v16, v4, v6, vcc
7263; GFX9-NEXT:    v_cndmask_b32_e32 v20, v5, v7, vcc
7264; GFX9-NEXT:    v_lshrrev_b64 v[4:5], 1, v[12:13]
7265; GFX9-NEXT:    v_lshlrev_b64 v[6:7], s7, v[14:15]
7266; GFX9-NEXT:    s_cselect_b32 s4, 1, 0
7267; GFX9-NEXT:    s_cmp_eq_u32 1, 0
7268; GFX9-NEXT:    s_cselect_b32 s5, 1, 0
7269; GFX9-NEXT:    s_and_b32 s6, 1, s4
7270; GFX9-NEXT:    v_or_b32_e32 v6, v4, v6
7271; GFX9-NEXT:    v_or_b32_e32 v7, v5, v7
7272; GFX9-NEXT:    v_lshrrev_b64 v[4:5], s8, v[14:15]
7273; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s6
7274; GFX9-NEXT:    s_and_b32 s5, 1, s5
7275; GFX9-NEXT:    v_lshrrev_b64 v[8:9], 1, v[14:15]
7276; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
7277; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
7278; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s5
7279; GFX9-NEXT:    s_and_b32 s4, 1, s4
7280; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
7281; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
7282; GFX9-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s4
7283; GFX9-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
7284; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
7285; GFX9-NEXT:    v_sub_u32_e32 v10, 64, v17
7286; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v17, v[4:5]
7287; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v10, v[6:7]
7288; GFX9-NEXT:    v_subrev_u32_e32 v12, 64, v17
7289; GFX9-NEXT:    v_or_b32_e32 v10, v8, v10
7290; GFX9-NEXT:    v_or_b32_e32 v11, v9, v11
7291; GFX9-NEXT:    v_lshrrev_b64 v[8:9], v17, v[6:7]
7292; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v12, v[6:7]
7293; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v17
7294; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v10, vcc
7295; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v17
7296; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc
7297; GFX9-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[4:5]
7298; GFX9-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[4:5]
7299; GFX9-NEXT:    v_cndmask_b32_e32 v6, 0, v8, vcc
7300; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v9, vcc
7301; GFX9-NEXT:    v_or_b32_e32 v4, v18, v4
7302; GFX9-NEXT:    v_or_b32_e32 v5, v19, v5
7303; GFX9-NEXT:    v_or_b32_e32 v6, v16, v6
7304; GFX9-NEXT:    v_or_b32_e32 v7, v20, v7
7305; GFX9-NEXT:    s_setpc_b64 s[30:31]
7306;
7307; GFX10-LABEL: v_fshl_v2i128:
7308; GFX10:       ; %bb.0:
7309; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
7310; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
7311; GFX10-NEXT:    v_xor_b32_e32 v17, -1, v16
7312; GFX10-NEXT:    s_movk_i32 s7, 0x7f
7313; GFX10-NEXT:    s_sub_i32 s8, 64, 1
7314; GFX10-NEXT:    v_and_b32_e32 v27, s7, v16
7315; GFX10-NEXT:    v_lshlrev_b64 v[18:19], s8, v[10:11]
7316; GFX10-NEXT:    v_and_b32_e32 v28, s7, v17
7317; GFX10-NEXT:    v_lshrrev_b64 v[16:17], 1, v[8:9]
7318; GFX10-NEXT:    s_sub_i32 s9, 1, 64
7319; GFX10-NEXT:    s_cmp_lt_u32 1, 64
7320; GFX10-NEXT:    v_lshrrev_b64 v[21:22], s9, v[10:11]
7321; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
7322; GFX10-NEXT:    s_cmp_eq_u32 1, 0
7323; GFX10-NEXT:    v_or_b32_e32 v16, v16, v18
7324; GFX10-NEXT:    v_or_b32_e32 v17, v17, v19
7325; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
7326; GFX10-NEXT:    s_and_b32 s5, 1, vcc_lo
7327; GFX10-NEXT:    s_and_b32 s4, 1, s4
7328; GFX10-NEXT:    v_sub_nc_u32_e32 v23, 64, v27
7329; GFX10-NEXT:    v_lshrrev_b64 v[10:11], 1, v[10:11]
7330; GFX10-NEXT:    v_cndmask_b32_e32 v21, v21, v16, vcc_lo
7331; GFX10-NEXT:    v_cndmask_b32_e32 v22, v22, v17, vcc_lo
7332; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
7333; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
7334; GFX10-NEXT:    v_lshrrev_b64 v[16:17], v23, v[0:1]
7335; GFX10-NEXT:    v_lshlrev_b64 v[18:19], v27, v[2:3]
7336; GFX10-NEXT:    v_sub_nc_u32_e32 v25, 64, v28
7337; GFX10-NEXT:    v_cndmask_b32_e32 v8, v21, v8, vcc_lo
7338; GFX10-NEXT:    v_cndmask_b32_e32 v9, v22, v9, vcc_lo
7339; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, v10, s4
7340; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, v11, s4
7341; GFX10-NEXT:    v_or_b32_e32 v18, v16, v18
7342; GFX10-NEXT:    v_subrev_nc_u32_e32 v29, 64, v27
7343; GFX10-NEXT:    v_subrev_nc_u32_e32 v16, 64, v28
7344; GFX10-NEXT:    v_lshrrev_b64 v[23:24], v28, v[8:9]
7345; GFX10-NEXT:    v_lshlrev_b64 v[25:26], v25, v[10:11]
7346; GFX10-NEXT:    v_lshlrev_b64 v[21:22], v27, v[0:1]
7347; GFX10-NEXT:    v_or_b32_e32 v19, v17, v19
7348; GFX10-NEXT:    v_lshlrev_b64 v[0:1], v29, v[0:1]
7349; GFX10-NEXT:    v_lshrrev_b64 v[16:17], v16, v[10:11]
7350; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v27
7351; GFX10-NEXT:    v_or_b32_e32 v23, v23, v25
7352; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v28
7353; GFX10-NEXT:    v_or_b32_e32 v24, v24, v26
7354; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v28
7355; GFX10-NEXT:    v_cndmask_b32_e32 v18, v0, v18, vcc_lo
7356; GFX10-NEXT:    v_cndmask_b32_e32 v19, v1, v19, vcc_lo
7357; GFX10-NEXT:    v_lshrrev_b64 v[0:1], v28, v[10:11]
7358; GFX10-NEXT:    v_cndmask_b32_e64 v16, v16, v23, s4
7359; GFX10-NEXT:    v_cndmask_b32_e64 v10, v17, v24, s4
7360; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v27
7361; GFX10-NEXT:    v_cndmask_b32_e32 v11, 0, v22, vcc_lo
7362; GFX10-NEXT:    v_cndmask_b32_e32 v21, 0, v21, vcc_lo
7363; GFX10-NEXT:    v_cndmask_b32_e64 v8, v16, v8, s5
7364; GFX10-NEXT:    v_cndmask_b32_e64 v9, v10, v9, s5
7365; GFX10-NEXT:    v_cndmask_b32_e64 v22, v19, v3, s6
7366; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, v0, s4
7367; GFX10-NEXT:    v_cndmask_b32_e64 v23, 0, v1, s4
7368; GFX10-NEXT:    v_xor_b32_e32 v16, -1, v20
7369; GFX10-NEXT:    v_or_b32_e32 v1, v11, v9
7370; GFX10-NEXT:    v_or_b32_e32 v0, v21, v8
7371; GFX10-NEXT:    v_lshrrev_b64 v[8:9], 1, v[12:13]
7372; GFX10-NEXT:    v_lshlrev_b64 v[10:11], s8, v[14:15]
7373; GFX10-NEXT:    s_cmp_lt_u32 1, 64
7374; GFX10-NEXT:    v_and_b32_e32 v25, s7, v16
7375; GFX10-NEXT:    v_and_b32_e32 v24, s7, v20
7376; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
7377; GFX10-NEXT:    s_cmp_eq_u32 1, 0
7378; GFX10-NEXT:    v_lshrrev_b64 v[16:17], s9, v[14:15]
7379; GFX10-NEXT:    v_or_b32_e32 v10, v8, v10
7380; GFX10-NEXT:    v_or_b32_e32 v11, v9, v11
7381; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
7382; GFX10-NEXT:    s_and_b32 s5, 1, vcc_lo
7383; GFX10-NEXT:    s_and_b32 s4, 1, s4
7384; GFX10-NEXT:    v_cndmask_b32_e64 v2, v18, v2, s6
7385; GFX10-NEXT:    v_lshrrev_b64 v[8:9], 1, v[14:15]
7386; GFX10-NEXT:    v_sub_nc_u32_e32 v18, 64, v24
7387; GFX10-NEXT:    v_cndmask_b32_e32 v16, v16, v10, vcc_lo
7388; GFX10-NEXT:    v_cndmask_b32_e32 v17, v17, v11, vcc_lo
7389; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
7390; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
7391; GFX10-NEXT:    v_lshrrev_b64 v[10:11], v18, v[4:5]
7392; GFX10-NEXT:    v_lshlrev_b64 v[14:15], v24, v[6:7]
7393; GFX10-NEXT:    v_sub_nc_u32_e32 v20, 64, v25
7394; GFX10-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc_lo
7395; GFX10-NEXT:    v_cndmask_b32_e32 v13, v17, v13, vcc_lo
7396; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, v8, s4
7397; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, v9, s4
7398; GFX10-NEXT:    v_or_b32_e32 v2, v2, v3
7399; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 64, v24
7400; GFX10-NEXT:    v_lshlrev_b64 v[16:17], v24, v[4:5]
7401; GFX10-NEXT:    v_or_b32_e32 v14, v10, v14
7402; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 64, v25
7403; GFX10-NEXT:    v_lshrrev_b64 v[18:19], v25, v[12:13]
7404; GFX10-NEXT:    v_lshlrev_b64 v[20:21], v20, v[8:9]
7405; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v24
7406; GFX10-NEXT:    v_lshlrev_b64 v[3:4], v3, v[4:5]
7407; GFX10-NEXT:    v_or_b32_e32 v5, v11, v15
7408; GFX10-NEXT:    v_lshrrev_b64 v[10:11], v10, v[8:9]
7409; GFX10-NEXT:    v_cmp_gt_u32_e64 s4, 64, v25
7410; GFX10-NEXT:    v_cndmask_b32_e32 v15, 0, v16, vcc_lo
7411; GFX10-NEXT:    v_or_b32_e32 v16, v18, v20
7412; GFX10-NEXT:    v_or_b32_e32 v18, v19, v21
7413; GFX10-NEXT:    v_cndmask_b32_e32 v14, v3, v14, vcc_lo
7414; GFX10-NEXT:    v_cndmask_b32_e32 v5, v4, v5, vcc_lo
7415; GFX10-NEXT:    v_lshrrev_b64 v[3:4], v25, v[8:9]
7416; GFX10-NEXT:    v_cmp_eq_u32_e64 s6, 0, v24
7417; GFX10-NEXT:    v_cndmask_b32_e64 v8, v11, v18, s4
7418; GFX10-NEXT:    v_cmp_eq_u32_e64 s5, 0, v25
7419; GFX10-NEXT:    v_cndmask_b32_e64 v10, v10, v16, s4
7420; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0, v17, vcc_lo
7421; GFX10-NEXT:    v_cndmask_b32_e64 v7, v5, v7, s6
7422; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, v4, s4
7423; GFX10-NEXT:    v_cndmask_b32_e64 v6, v14, v6, s6
7424; GFX10-NEXT:    v_cndmask_b32_e64 v5, v10, v12, s5
7425; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, v3, s4
7426; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v13, s5
7427; GFX10-NEXT:    v_or_b32_e32 v3, v22, v23
7428; GFX10-NEXT:    v_or_b32_e32 v7, v7, v11
7429; GFX10-NEXT:    v_or_b32_e32 v4, v15, v5
7430; GFX10-NEXT:    v_or_b32_e32 v6, v6, v10
7431; GFX10-NEXT:    v_or_b32_e32 v5, v9, v8
7432; GFX10-NEXT:    s_setpc_b64 s[30:31]
7433  %result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
7434  ret <2 x i128> %result
7435}
7436
7437declare i7 @llvm.fshl.i7(i7, i7, i7) #0
7438declare i8 @llvm.fshl.i8(i8, i8, i8) #0
7439declare <2 x i8> @llvm.fshl.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) #0
7440declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>) #0
7441
7442declare i16 @llvm.fshl.i16(i16, i16, i16) #0
7443declare <2 x i16> @llvm.fshl.v2i16(<2 x i16>, <2 x i16>, <2 x i16>) #0
7444declare <3 x i16> @llvm.fshl.v3i16(<3 x i16>, <3 x i16>, <3 x i16>) #0
7445declare <4 x i16> @llvm.fshl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) #0
7446declare <5 x i16> @llvm.fshl.v5i16(<5 x i16>, <5 x i16>, <5 x i16>) #0
7447declare <6 x i16> @llvm.fshl.v6i16(<6 x i16>, <6 x i16>, <6 x i16>) #0
7448declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) #0
7449
7450declare i24 @llvm.fshl.i24(i24, i24, i24) #0
7451declare <2 x i24> @llvm.fshl.v2i24(<2 x i24>, <2 x i24>, <2 x i24>) #0
7452
7453declare i32 @llvm.fshl.i32(i32, i32, i32) #0
7454declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) #0
7455declare <3 x i32> @llvm.fshl.v3i32(<3 x i32>, <3 x i32>, <3 x i32>) #0
7456declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #0
7457declare <5 x i32> @llvm.fshl.v5i32(<5 x i32>, <5 x i32>, <5 x i32>) #0
7458declare <16 x i32> @llvm.fshl.v16i32(<16 x i32>, <16 x i32>, <16 x i32>) #0
7459
7460declare i48 @llvm.fshl.i48(i48, i48, i48) #0
7461
7462declare i64 @llvm.fshl.i64(i64, i64, i64) #0
7463declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) #0
7464
7465declare i128 @llvm.fshl.i128(i128, i128, i128) #0
7466declare <2 x i128> @llvm.fshl.v2i128(<2 x i128>, <2 x i128>, <2 x i128>) #0
7467
7468attributes #0 = { nounwind readnone speculatable willreturn }
7469