1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN:  llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
3; RUN:  llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
4
5define amdgpu_kernel void @frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1, half addrspace(1)* %in2) #0 {
6; CI-LABEL: frem_f16:
7; CI:       ; %bb.0:
8; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
9; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
10; CI-NEXT:    s_mov_b32 s10, -1
11; CI-NEXT:    s_mov_b32 s11, 0xf000
12; CI-NEXT:    s_mov_b64 s[2:3], s[10:11]
13; CI-NEXT:    s_waitcnt lgkmcnt(0)
14; CI-NEXT:    s_mov_b64 s[8:9], s[6:7]
15; CI-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
16; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
17; CI-NEXT:    s_waitcnt vmcnt(1)
18; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
19; CI-NEXT:    s_waitcnt vmcnt(0)
20; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
21; CI-NEXT:    v_div_scale_f32 v2, s[0:1], v1, v1, v0
22; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
23; CI-NEXT:    v_rcp_f32_e32 v4, v2
24; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
25; CI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
26; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
27; CI-NEXT:    v_mul_f32_e32 v5, v3, v4
28; CI-NEXT:    v_fma_f32 v6, -v2, v5, v3
29; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
30; CI-NEXT:    v_fma_f32 v2, -v2, v5, v3
31; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
32; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
33; CI-NEXT:    s_mov_b64 s[6:7], s[10:11]
34; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
35; CI-NEXT:    v_trunc_f32_e32 v2, v2
36; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
37; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
38; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
39; CI-NEXT:    buffer_store_short v0, off, s[4:7], 0
40; CI-NEXT:    s_endpgm
41;
42; VI-LABEL: frem_f16:
43; VI:       ; %bb.0:
44; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
45; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
46; VI-NEXT:    s_waitcnt lgkmcnt(0)
47; VI-NEXT:    v_mov_b32_e32 v0, s6
48; VI-NEXT:    s_add_u32 s0, s8, 8
49; VI-NEXT:    v_mov_b32_e32 v1, s7
50; VI-NEXT:    s_addc_u32 s1, s9, 0
51; VI-NEXT:    flat_load_ushort v2, v[0:1]
52; VI-NEXT:    v_mov_b32_e32 v0, s0
53; VI-NEXT:    v_mov_b32_e32 v1, s1
54; VI-NEXT:    flat_load_ushort v0, v[0:1]
55; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
56; VI-NEXT:    v_cvt_f32_f16_e32 v1, v2
57; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
58; VI-NEXT:    v_cvt_f32_f16_e32 v3, v0
59; VI-NEXT:    v_rcp_f32_e32 v3, v3
60; VI-NEXT:    v_mul_f32_e32 v1, v1, v3
61; VI-NEXT:    v_cvt_f16_f32_e32 v1, v1
62; VI-NEXT:    v_div_fixup_f16 v1, v1, v0, v2
63; VI-NEXT:    v_trunc_f16_e32 v1, v1
64; VI-NEXT:    v_fma_f16 v2, -v1, v0, v2
65; VI-NEXT:    v_mov_b32_e32 v0, s4
66; VI-NEXT:    v_mov_b32_e32 v1, s5
67; VI-NEXT:    flat_store_short v[0:1], v2
68; VI-NEXT:    s_endpgm
69   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
70   %r0 = load half, half addrspace(1)* %in1, align 4
71   %r1 = load half, half addrspace(1)* %gep2, align 4
72   %r2 = frem half %r0, %r1
73   store half %r2, half addrspace(1)* %out, align 4
74   ret void
75}
76
77define amdgpu_kernel void @fast_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1, half addrspace(1)* %in2) #0 {
78; CI-LABEL: fast_frem_f16:
79; CI:       ; %bb.0:
80; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
81; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
82; CI-NEXT:    s_mov_b32 s10, -1
83; CI-NEXT:    s_mov_b32 s11, 0xf000
84; CI-NEXT:    s_mov_b64 s[2:3], s[10:11]
85; CI-NEXT:    s_waitcnt lgkmcnt(0)
86; CI-NEXT:    s_mov_b64 s[8:9], s[6:7]
87; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
88; CI-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
89; CI-NEXT:    s_mov_b64 s[6:7], s[10:11]
90; CI-NEXT:    s_waitcnt vmcnt(1)
91; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
92; CI-NEXT:    s_waitcnt vmcnt(0)
93; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
94; CI-NEXT:    v_rcp_f32_e32 v2, v1
95; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
96; CI-NEXT:    v_trunc_f32_e32 v2, v2
97; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
98; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
99; CI-NEXT:    buffer_store_short v0, off, s[4:7], 0
100; CI-NEXT:    s_endpgm
101;
102; VI-LABEL: fast_frem_f16:
103; VI:       ; %bb.0:
104; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
105; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
106; VI-NEXT:    s_waitcnt lgkmcnt(0)
107; VI-NEXT:    v_mov_b32_e32 v0, s6
108; VI-NEXT:    s_add_u32 s0, s8, 8
109; VI-NEXT:    v_mov_b32_e32 v1, s7
110; VI-NEXT:    s_addc_u32 s1, s9, 0
111; VI-NEXT:    flat_load_ushort v2, v[0:1]
112; VI-NEXT:    v_mov_b32_e32 v0, s0
113; VI-NEXT:    v_mov_b32_e32 v1, s1
114; VI-NEXT:    flat_load_ushort v0, v[0:1]
115; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
116; VI-NEXT:    v_rcp_f16_e32 v1, v0
117; VI-NEXT:    v_mul_f16_e32 v1, v2, v1
118; VI-NEXT:    v_trunc_f16_e32 v1, v1
119; VI-NEXT:    v_fma_f16 v2, -v1, v0, v2
120; VI-NEXT:    v_mov_b32_e32 v0, s4
121; VI-NEXT:    v_mov_b32_e32 v1, s5
122; VI-NEXT:    flat_store_short v[0:1], v2
123; VI-NEXT:    s_endpgm
124   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
125   %r0 = load half, half addrspace(1)* %in1, align 4
126   %r1 = load half, half addrspace(1)* %gep2, align 4
127   %r2 = frem fast half %r0, %r1
128   store half %r2, half addrspace(1)* %out, align 4
129   ret void
130}
131
132define amdgpu_kernel void @unsafe_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1, half addrspace(1)* %in2) #1 {
133; CI-LABEL: unsafe_frem_f16:
134; CI:       ; %bb.0:
135; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
136; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
137; CI-NEXT:    s_mov_b32 s10, -1
138; CI-NEXT:    s_mov_b32 s11, 0xf000
139; CI-NEXT:    s_mov_b64 s[2:3], s[10:11]
140; CI-NEXT:    s_waitcnt lgkmcnt(0)
141; CI-NEXT:    s_mov_b64 s[8:9], s[6:7]
142; CI-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
143; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
144; CI-NEXT:    s_waitcnt vmcnt(1)
145; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
146; CI-NEXT:    s_waitcnt vmcnt(0)
147; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
148; CI-NEXT:    v_div_scale_f32 v2, s[0:1], v1, v1, v0
149; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
150; CI-NEXT:    v_rcp_f32_e32 v4, v2
151; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
152; CI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
153; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
154; CI-NEXT:    v_mul_f32_e32 v5, v3, v4
155; CI-NEXT:    v_fma_f32 v6, -v2, v5, v3
156; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
157; CI-NEXT:    v_fma_f32 v2, -v2, v5, v3
158; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
159; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
160; CI-NEXT:    s_mov_b64 s[6:7], s[10:11]
161; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
162; CI-NEXT:    v_trunc_f32_e32 v2, v2
163; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
164; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
165; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
166; CI-NEXT:    buffer_store_short v0, off, s[4:7], 0
167; CI-NEXT:    s_endpgm
168;
169; VI-LABEL: unsafe_frem_f16:
170; VI:       ; %bb.0:
171; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
172; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
173; VI-NEXT:    s_waitcnt lgkmcnt(0)
174; VI-NEXT:    v_mov_b32_e32 v0, s6
175; VI-NEXT:    s_add_u32 s0, s8, 8
176; VI-NEXT:    v_mov_b32_e32 v1, s7
177; VI-NEXT:    s_addc_u32 s1, s9, 0
178; VI-NEXT:    flat_load_ushort v2, v[0:1]
179; VI-NEXT:    v_mov_b32_e32 v0, s0
180; VI-NEXT:    v_mov_b32_e32 v1, s1
181; VI-NEXT:    flat_load_ushort v0, v[0:1]
182; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
183; VI-NEXT:    v_cvt_f32_f16_e32 v1, v2
184; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
185; VI-NEXT:    v_cvt_f32_f16_e32 v3, v0
186; VI-NEXT:    v_rcp_f32_e32 v3, v3
187; VI-NEXT:    v_mul_f32_e32 v1, v1, v3
188; VI-NEXT:    v_cvt_f16_f32_e32 v1, v1
189; VI-NEXT:    v_div_fixup_f16 v1, v1, v0, v2
190; VI-NEXT:    v_trunc_f16_e32 v1, v1
191; VI-NEXT:    v_fma_f16 v2, -v1, v0, v2
192; VI-NEXT:    v_mov_b32_e32 v0, s4
193; VI-NEXT:    v_mov_b32_e32 v1, s5
194; VI-NEXT:    flat_store_short v[0:1], v2
195; VI-NEXT:    s_endpgm
196   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
197   %r0 = load half, half addrspace(1)* %in1, align 4
198   %r1 = load half, half addrspace(1)* %gep2, align 4
199   %r2 = frem half %r0, %r1
200   store half %r2, half addrspace(1)* %out, align 4
201   ret void
202}
203
204define amdgpu_kernel void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) #0 {
205; CI-LABEL: frem_f32:
206; CI:       ; %bb.0:
207; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
208; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
209; CI-NEXT:    s_waitcnt lgkmcnt(0)
210; CI-NEXT:    s_load_dword s2, s[6:7], 0x0
211; CI-NEXT:    s_load_dword s0, s[8:9], 0x4
212; CI-NEXT:    s_waitcnt lgkmcnt(0)
213; CI-NEXT:    v_mov_b32_e32 v0, s0
214; CI-NEXT:    v_div_scale_f32 v1, s[0:1], v0, v0, s2
215; CI-NEXT:    v_div_scale_f32 v2, vcc, s2, v0, s2
216; CI-NEXT:    v_rcp_f32_e32 v3, v1
217; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
218; CI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
219; CI-NEXT:    v_fma_f32 v3, v4, v3, v3
220; CI-NEXT:    v_mul_f32_e32 v4, v2, v3
221; CI-NEXT:    v_fma_f32 v5, -v1, v4, v2
222; CI-NEXT:    v_fma_f32 v4, v5, v3, v4
223; CI-NEXT:    v_fma_f32 v1, -v1, v4, v2
224; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
225; CI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
226; CI-NEXT:    s_mov_b32 s6, -1
227; CI-NEXT:    s_mov_b32 s7, 0xf000
228; CI-NEXT:    v_div_fixup_f32 v1, v1, v0, s2
229; CI-NEXT:    v_trunc_f32_e32 v1, v1
230; CI-NEXT:    v_fma_f32 v0, -v1, v0, s2
231; CI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
232; CI-NEXT:    s_endpgm
233;
234; VI-LABEL: frem_f32:
235; VI:       ; %bb.0:
236; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
237; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
238; VI-NEXT:    s_waitcnt lgkmcnt(0)
239; VI-NEXT:    s_load_dword s2, s[6:7], 0x0
240; VI-NEXT:    s_load_dword s0, s[8:9], 0x10
241; VI-NEXT:    s_waitcnt lgkmcnt(0)
242; VI-NEXT:    v_mov_b32_e32 v0, s0
243; VI-NEXT:    v_div_scale_f32 v1, s[0:1], v0, v0, s2
244; VI-NEXT:    v_div_scale_f32 v2, vcc, s2, v0, s2
245; VI-NEXT:    v_rcp_f32_e32 v3, v1
246; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
247; VI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
248; VI-NEXT:    v_fma_f32 v3, v4, v3, v3
249; VI-NEXT:    v_mul_f32_e32 v4, v2, v3
250; VI-NEXT:    v_fma_f32 v5, -v1, v4, v2
251; VI-NEXT:    v_fma_f32 v4, v5, v3, v4
252; VI-NEXT:    v_fma_f32 v1, -v1, v4, v2
253; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
254; VI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
255; VI-NEXT:    v_div_fixup_f32 v1, v1, v0, s2
256; VI-NEXT:    v_trunc_f32_e32 v1, v1
257; VI-NEXT:    v_fma_f32 v2, -v1, v0, s2
258; VI-NEXT:    v_mov_b32_e32 v0, s4
259; VI-NEXT:    v_mov_b32_e32 v1, s5
260; VI-NEXT:    flat_store_dword v[0:1], v2
261; VI-NEXT:    s_endpgm
262   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
263   %r0 = load float, float addrspace(1)* %in1, align 4
264   %r1 = load float, float addrspace(1)* %gep2, align 4
265   %r2 = frem float %r0, %r1
266   store float %r2, float addrspace(1)* %out, align 4
267   ret void
268}
269
270define amdgpu_kernel void @fast_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) #0 {
271; CI-LABEL: fast_frem_f32:
272; CI:       ; %bb.0:
273; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
274; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
275; CI-NEXT:    s_waitcnt lgkmcnt(0)
276; CI-NEXT:    s_load_dword s0, s[6:7], 0x0
277; CI-NEXT:    s_load_dword s1, s[8:9], 0x4
278; CI-NEXT:    s_mov_b32 s6, -1
279; CI-NEXT:    s_mov_b32 s7, 0xf000
280; CI-NEXT:    s_waitcnt lgkmcnt(0)
281; CI-NEXT:    v_mov_b32_e32 v1, s0
282; CI-NEXT:    v_rcp_f32_e32 v0, s1
283; CI-NEXT:    v_mul_f32_e32 v0, s0, v0
284; CI-NEXT:    v_trunc_f32_e32 v0, v0
285; CI-NEXT:    v_fma_f32 v0, -v0, s1, v1
286; CI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
287; CI-NEXT:    s_endpgm
288;
289; VI-LABEL: fast_frem_f32:
290; VI:       ; %bb.0:
291; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
292; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
293; VI-NEXT:    s_waitcnt lgkmcnt(0)
294; VI-NEXT:    s_load_dword s0, s[6:7], 0x0
295; VI-NEXT:    s_load_dword s1, s[8:9], 0x10
296; VI-NEXT:    s_waitcnt lgkmcnt(0)
297; VI-NEXT:    v_mov_b32_e32 v1, s0
298; VI-NEXT:    v_rcp_f32_e32 v0, s1
299; VI-NEXT:    v_mul_f32_e32 v0, s0, v0
300; VI-NEXT:    v_trunc_f32_e32 v0, v0
301; VI-NEXT:    v_fma_f32 v2, -v0, s1, v1
302; VI-NEXT:    v_mov_b32_e32 v0, s4
303; VI-NEXT:    v_mov_b32_e32 v1, s5
304; VI-NEXT:    flat_store_dword v[0:1], v2
305; VI-NEXT:    s_endpgm
306   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
307   %r0 = load float, float addrspace(1)* %in1, align 4
308   %r1 = load float, float addrspace(1)* %gep2, align 4
309   %r2 = frem fast float %r0, %r1
310   store float %r2, float addrspace(1)* %out, align 4
311   ret void
312}
313
314define amdgpu_kernel void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) #1 {
315; CI-LABEL: unsafe_frem_f32:
316; CI:       ; %bb.0:
317; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
318; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
319; CI-NEXT:    s_waitcnt lgkmcnt(0)
320; CI-NEXT:    s_load_dword s2, s[6:7], 0x0
321; CI-NEXT:    s_load_dword s0, s[8:9], 0x4
322; CI-NEXT:    s_waitcnt lgkmcnt(0)
323; CI-NEXT:    v_mov_b32_e32 v0, s0
324; CI-NEXT:    v_div_scale_f32 v1, s[0:1], v0, v0, s2
325; CI-NEXT:    v_div_scale_f32 v2, vcc, s2, v0, s2
326; CI-NEXT:    v_rcp_f32_e32 v3, v1
327; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
328; CI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
329; CI-NEXT:    v_fma_f32 v3, v4, v3, v3
330; CI-NEXT:    v_mul_f32_e32 v4, v2, v3
331; CI-NEXT:    v_fma_f32 v5, -v1, v4, v2
332; CI-NEXT:    v_fma_f32 v4, v5, v3, v4
333; CI-NEXT:    v_fma_f32 v1, -v1, v4, v2
334; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
335; CI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
336; CI-NEXT:    s_mov_b32 s6, -1
337; CI-NEXT:    s_mov_b32 s7, 0xf000
338; CI-NEXT:    v_div_fixup_f32 v1, v1, v0, s2
339; CI-NEXT:    v_trunc_f32_e32 v1, v1
340; CI-NEXT:    v_fma_f32 v0, -v1, v0, s2
341; CI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
342; CI-NEXT:    s_endpgm
343;
344; VI-LABEL: unsafe_frem_f32:
345; VI:       ; %bb.0:
346; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
347; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
348; VI-NEXT:    s_waitcnt lgkmcnt(0)
349; VI-NEXT:    s_load_dword s2, s[6:7], 0x0
350; VI-NEXT:    s_load_dword s0, s[8:9], 0x10
351; VI-NEXT:    s_waitcnt lgkmcnt(0)
352; VI-NEXT:    v_mov_b32_e32 v0, s0
353; VI-NEXT:    v_div_scale_f32 v1, s[0:1], v0, v0, s2
354; VI-NEXT:    v_div_scale_f32 v2, vcc, s2, v0, s2
355; VI-NEXT:    v_rcp_f32_e32 v3, v1
356; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
357; VI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
358; VI-NEXT:    v_fma_f32 v3, v4, v3, v3
359; VI-NEXT:    v_mul_f32_e32 v4, v2, v3
360; VI-NEXT:    v_fma_f32 v5, -v1, v4, v2
361; VI-NEXT:    v_fma_f32 v4, v5, v3, v4
362; VI-NEXT:    v_fma_f32 v1, -v1, v4, v2
363; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
364; VI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
365; VI-NEXT:    v_div_fixup_f32 v1, v1, v0, s2
366; VI-NEXT:    v_trunc_f32_e32 v1, v1
367; VI-NEXT:    v_fma_f32 v2, -v1, v0, s2
368; VI-NEXT:    v_mov_b32_e32 v0, s4
369; VI-NEXT:    v_mov_b32_e32 v1, s5
370; VI-NEXT:    flat_store_dword v[0:1], v2
371; VI-NEXT:    s_endpgm
372   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
373   %r0 = load float, float addrspace(1)* %in1, align 4
374   %r1 = load float, float addrspace(1)* %gep2, align 4
375   %r2 = frem float %r0, %r1
376   store float %r2, float addrspace(1)* %out, align 4
377   ret void
378}
379
380define amdgpu_kernel void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) #0 {
381; CI-LABEL: frem_f64:
382; CI:       ; %bb.0:
383; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
384; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
385; CI-NEXT:    s_waitcnt lgkmcnt(0)
386; CI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
387; CI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
388; CI-NEXT:    s_waitcnt lgkmcnt(0)
389; CI-NEXT:    v_mov_b32_e32 v0, s2
390; CI-NEXT:    v_mov_b32_e32 v1, s3
391; CI-NEXT:    v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[0:1]
392; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
393; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
394; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
395; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
396; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
397; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
398; CI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
399; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
400; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
401; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
402; CI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
403; CI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
404; CI-NEXT:    v_mov_b32_e32 v2, s4
405; CI-NEXT:    v_mov_b32_e32 v3, s5
406; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
407; CI-NEXT:    s_endpgm
408;
409; VI-LABEL: frem_f64:
410; VI:       ; %bb.0:
411; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
412; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
413; VI-NEXT:    s_waitcnt lgkmcnt(0)
414; VI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
415; VI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
416; VI-NEXT:    s_waitcnt lgkmcnt(0)
417; VI-NEXT:    v_mov_b32_e32 v0, s2
418; VI-NEXT:    v_mov_b32_e32 v1, s3
419; VI-NEXT:    v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[0:1]
420; VI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
421; VI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
422; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
423; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
424; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
425; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
426; VI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
427; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
428; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
429; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
430; VI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
431; VI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
432; VI-NEXT:    v_mov_b32_e32 v2, s4
433; VI-NEXT:    v_mov_b32_e32 v3, s5
434; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
435; VI-NEXT:    s_endpgm
436   %r0 = load double, double addrspace(1)* %in1, align 8
437   %r1 = load double, double addrspace(1)* %in2, align 8
438   %r2 = frem double %r0, %r1
439   store double %r2, double addrspace(1)* %out, align 8
440   ret void
441}
442
443define amdgpu_kernel void @fast_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1, double addrspace(1)* %in2) #0 {
444; CI-LABEL: fast_frem_f64:
445; CI:       ; %bb.0:
446; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
447; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
448; CI-NEXT:    s_waitcnt lgkmcnt(0)
449; CI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
450; CI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
451; CI-NEXT:    s_waitcnt lgkmcnt(0)
452; CI-NEXT:    v_mov_b32_e32 v0, s2
453; CI-NEXT:    v_mov_b32_e32 v1, s3
454; CI-NEXT:    v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[0:1]
455; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
456; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
457; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
458; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
459; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
460; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
461; CI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
462; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
463; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
464; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
465; CI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
466; CI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
467; CI-NEXT:    v_mov_b32_e32 v2, s4
468; CI-NEXT:    v_mov_b32_e32 v3, s5
469; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
470; CI-NEXT:    s_endpgm
471;
472; VI-LABEL: fast_frem_f64:
473; VI:       ; %bb.0:
474; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
475; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
476; VI-NEXT:    s_waitcnt lgkmcnt(0)
477; VI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
478; VI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
479; VI-NEXT:    s_waitcnt lgkmcnt(0)
480; VI-NEXT:    v_mov_b32_e32 v0, s2
481; VI-NEXT:    v_mov_b32_e32 v1, s3
482; VI-NEXT:    v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[0:1]
483; VI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
484; VI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
485; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
486; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
487; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
488; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
489; VI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
490; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
491; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
492; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
493; VI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
494; VI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
495; VI-NEXT:    v_mov_b32_e32 v2, s4
496; VI-NEXT:    v_mov_b32_e32 v3, s5
497; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
498; VI-NEXT:    s_endpgm
499   %r0 = load double, double addrspace(1)* %in1, align 8
500   %r1 = load double, double addrspace(1)* %in2, align 8
501   %r2 = frem fast double %r0, %r1
502   store double %r2, double addrspace(1)* %out, align 8
503   ret void
504}
505
506define amdgpu_kernel void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
507; CI-LABEL: unsafe_frem_f64:
508; CI:       ; %bb.0:
509; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
510; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
511; CI-NEXT:    s_waitcnt lgkmcnt(0)
512; CI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
513; CI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
514; CI-NEXT:    s_waitcnt lgkmcnt(0)
515; CI-NEXT:    v_mov_b32_e32 v0, s2
516; CI-NEXT:    v_mov_b32_e32 v1, s3
517; CI-NEXT:    v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[0:1]
518; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
519; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
520; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
521; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
522; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
523; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
524; CI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
525; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
526; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
527; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
528; CI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
529; CI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
530; CI-NEXT:    v_mov_b32_e32 v2, s4
531; CI-NEXT:    v_mov_b32_e32 v3, s5
532; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
533; CI-NEXT:    s_endpgm
534;
535; VI-LABEL: unsafe_frem_f64:
536; VI:       ; %bb.0:
537; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
538; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
539; VI-NEXT:    s_waitcnt lgkmcnt(0)
540; VI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
541; VI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
542; VI-NEXT:    s_waitcnt lgkmcnt(0)
543; VI-NEXT:    v_mov_b32_e32 v0, s2
544; VI-NEXT:    v_mov_b32_e32 v1, s3
545; VI-NEXT:    v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[0:1]
546; VI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
547; VI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
548; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
549; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
550; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
551; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
552; VI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
553; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
554; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
555; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
556; VI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
557; VI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
558; VI-NEXT:    v_mov_b32_e32 v2, s4
559; VI-NEXT:    v_mov_b32_e32 v3, s5
560; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
561; VI-NEXT:    s_endpgm
562                             double addrspace(1)* %in2) #1 {
563   %r0 = load double, double addrspace(1)* %in1, align 8
564   %r1 = load double, double addrspace(1)* %in2, align 8
565   %r2 = frem double %r0, %r1
566   store double %r2, double addrspace(1)* %out, align 8
567   ret void
568}
569
570define amdgpu_kernel void @frem_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in1, <2 x half> addrspace(1)* %in2) #0 {
571; CI-LABEL: frem_v2f16:
572; CI:       ; %bb.0:
573; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
574; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
575; CI-NEXT:    s_waitcnt lgkmcnt(0)
576; CI-NEXT:    s_load_dword s0, s[6:7], 0x0
577; CI-NEXT:    s_load_dword s1, s[8:9], 0x4
578; CI-NEXT:    s_waitcnt lgkmcnt(0)
579; CI-NEXT:    v_cvt_f32_f16_e32 v0, s0
580; CI-NEXT:    v_cvt_f32_f16_e32 v1, s1
581; CI-NEXT:    s_lshr_b32 s2, s0, 16
582; CI-NEXT:    s_lshr_b32 s3, s1, 16
583; CI-NEXT:    v_div_scale_f32 v2, s[0:1], v1, v1, v0
584; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
585; CI-NEXT:    v_rcp_f32_e32 v4, v2
586; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
587; CI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
588; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
589; CI-NEXT:    v_mul_f32_e32 v5, v3, v4
590; CI-NEXT:    v_fma_f32 v6, -v2, v5, v3
591; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
592; CI-NEXT:    v_fma_f32 v2, -v2, v5, v3
593; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
594; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
595; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
596; CI-NEXT:    v_trunc_f32_e32 v2, v2
597; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
598; CI-NEXT:    v_cvt_f32_f16_e32 v1, s2
599; CI-NEXT:    v_cvt_f32_f16_e32 v2, s3
600; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
601; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
602; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v2, v2, v1
603; CI-NEXT:    v_div_scale_f32 v4, vcc, v1, v2, v1
604; CI-NEXT:    v_rcp_f32_e32 v5, v3
605; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
606; CI-NEXT:    v_fma_f32 v6, -v3, v5, 1.0
607; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
608; CI-NEXT:    v_mul_f32_e32 v6, v4, v5
609; CI-NEXT:    v_fma_f32 v7, -v3, v6, v4
610; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
611; CI-NEXT:    v_fma_f32 v3, -v3, v6, v4
612; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
613; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
614; CI-NEXT:    v_bfe_u32 v0, v0, 0, 16
615; CI-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
616; CI-NEXT:    v_trunc_f32_e32 v3, v3
617; CI-NEXT:    v_fma_f32 v1, -v3, v2, v1
618; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
619; CI-NEXT:    v_bfe_u32 v1, v1, 0, 16
620; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
621; CI-NEXT:    v_or_b32_e32 v2, v0, v1
622; CI-NEXT:    v_mov_b32_e32 v0, s4
623; CI-NEXT:    v_mov_b32_e32 v1, s5
624; CI-NEXT:    flat_store_dword v[0:1], v2
625; CI-NEXT:    s_endpgm
626;
627; VI-LABEL: frem_v2f16:
628; VI:       ; %bb.0:
629; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
630; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
631; VI-NEXT:    s_waitcnt lgkmcnt(0)
632; VI-NEXT:    s_load_dword s0, s[6:7], 0x0
633; VI-NEXT:    s_load_dword s1, s[8:9], 0x10
634; VI-NEXT:    s_waitcnt lgkmcnt(0)
635; VI-NEXT:    v_cvt_f32_f16_e32 v0, s0
636; VI-NEXT:    v_cvt_f32_f16_e32 v2, s1
637; VI-NEXT:    s_lshr_b32 s3, s1, 16
638; VI-NEXT:    v_cvt_f32_f16_e32 v3, s3
639; VI-NEXT:    v_mov_b32_e32 v1, s1
640; VI-NEXT:    v_rcp_f32_e32 v2, v2
641; VI-NEXT:    s_lshr_b32 s2, s0, 16
642; VI-NEXT:    v_rcp_f32_e32 v3, v3
643; VI-NEXT:    v_mul_f32_e32 v0, v0, v2
644; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
645; VI-NEXT:    v_mov_b32_e32 v2, s3
646; VI-NEXT:    v_div_fixup_f16 v0, v0, v1, s0
647; VI-NEXT:    v_trunc_f16_e32 v0, v0
648; VI-NEXT:    v_fma_f16 v0, -v0, v1, s0
649; VI-NEXT:    v_cvt_f32_f16_e32 v1, s2
650; VI-NEXT:    v_mul_f32_e32 v1, v1, v3
651; VI-NEXT:    v_cvt_f16_f32_e32 v1, v1
652; VI-NEXT:    v_div_fixup_f16 v1, v1, v2, s2
653; VI-NEXT:    v_trunc_f16_e32 v1, v1
654; VI-NEXT:    v_fma_f16 v1, -v1, v2, s2
655; VI-NEXT:    v_mov_b32_e32 v2, 16
656; VI-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
657; VI-NEXT:    v_or_b32_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
658; VI-NEXT:    v_mov_b32_e32 v0, s4
659; VI-NEXT:    v_mov_b32_e32 v1, s5
660; VI-NEXT:    flat_store_dword v[0:1], v2
661; VI-NEXT:    s_endpgm
662   %gep2 = getelementptr <2 x half>, <2 x half> addrspace(1)* %in2, i32 4
663   %r0 = load <2 x half>, <2 x half> addrspace(1)* %in1, align 8
664   %r1 = load <2 x half>, <2 x half> addrspace(1)* %gep2, align 8
665   %r2 = frem <2 x half> %r0, %r1
666   store <2 x half> %r2, <2 x half> addrspace(1)* %out, align 8
667   ret void
668}
669
670define amdgpu_kernel void @frem_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in1, <4 x half> addrspace(1)* %in2) #0 {
671; CI-LABEL: frem_v4f16:
672; CI:       ; %bb.0:
673; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
674; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
675; CI-NEXT:    s_waitcnt lgkmcnt(0)
676; CI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
677; CI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x8
678; CI-NEXT:    s_waitcnt lgkmcnt(0)
679; CI-NEXT:    v_cvt_f32_f16_e32 v0, s0
680; CI-NEXT:    v_cvt_f32_f16_e32 v1, s2
681; CI-NEXT:    s_lshr_b32 s8, s0, 16
682; CI-NEXT:    s_lshr_b32 s9, s1, 16
683; CI-NEXT:    s_lshr_b32 s10, s2, 16
684; CI-NEXT:    v_div_scale_f32 v2, s[6:7], v1, v1, v0
685; CI-NEXT:    s_lshr_b32 s11, s3, 16
686; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
687; CI-NEXT:    v_rcp_f32_e32 v4, v2
688; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
689; CI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
690; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
691; CI-NEXT:    v_mul_f32_e32 v5, v3, v4
692; CI-NEXT:    v_fma_f32 v6, -v2, v5, v3
693; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
694; CI-NEXT:    v_fma_f32 v2, -v2, v5, v3
695; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
696; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
697; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
698; CI-NEXT:    v_trunc_f32_e32 v2, v2
699; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
700; CI-NEXT:    v_cvt_f32_f16_e32 v1, s8
701; CI-NEXT:    v_cvt_f32_f16_e32 v2, s10
702; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
703; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
704; CI-NEXT:    v_div_scale_f32 v3, s[6:7], v2, v2, v1
705; CI-NEXT:    v_div_scale_f32 v4, vcc, v1, v2, v1
706; CI-NEXT:    v_rcp_f32_e32 v5, v3
707; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
708; CI-NEXT:    v_fma_f32 v6, -v3, v5, 1.0
709; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
710; CI-NEXT:    v_mul_f32_e32 v6, v4, v5
711; CI-NEXT:    v_fma_f32 v7, -v3, v6, v4
712; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
713; CI-NEXT:    v_fma_f32 v3, -v3, v6, v4
714; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
715; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
716; CI-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
717; CI-NEXT:    v_trunc_f32_e32 v3, v3
718; CI-NEXT:    v_fma_f32 v1, -v3, v2, v1
719; CI-NEXT:    v_cvt_f32_f16_e32 v2, s1
720; CI-NEXT:    v_cvt_f32_f16_e32 v3, s3
721; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
722; CI-NEXT:    v_div_scale_f32 v4, s[0:1], v3, v3, v2
723; CI-NEXT:    v_div_scale_f32 v5, vcc, v2, v3, v2
724; CI-NEXT:    v_rcp_f32_e32 v6, v4
725; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
726; CI-NEXT:    v_fma_f32 v7, -v4, v6, 1.0
727; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
728; CI-NEXT:    v_mul_f32_e32 v7, v5, v6
729; CI-NEXT:    v_fma_f32 v8, -v4, v7, v5
730; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
731; CI-NEXT:    v_fma_f32 v4, -v4, v7, v5
732; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
733; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
734; CI-NEXT:    v_div_fixup_f32 v4, v4, v3, v2
735; CI-NEXT:    v_trunc_f32_e32 v4, v4
736; CI-NEXT:    v_fma_f32 v2, -v4, v3, v2
737; CI-NEXT:    v_cvt_f32_f16_e32 v3, s9
738; CI-NEXT:    v_cvt_f32_f16_e32 v4, s11
739; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
740; CI-NEXT:    v_div_scale_f32 v5, s[0:1], v4, v4, v3
741; CI-NEXT:    v_div_scale_f32 v6, vcc, v3, v4, v3
742; CI-NEXT:    v_rcp_f32_e32 v7, v5
743; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
744; CI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
745; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
746; CI-NEXT:    v_mul_f32_e32 v8, v6, v7
747; CI-NEXT:    v_fma_f32 v9, -v5, v8, v6
748; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
749; CI-NEXT:    v_fma_f32 v5, -v5, v8, v6
750; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
751; CI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
752; CI-NEXT:    v_bfe_u32 v1, v1, 0, 16
753; CI-NEXT:    v_bfe_u32 v0, v0, 0, 16
754; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
755; CI-NEXT:    v_or_b32_e32 v0, v0, v1
756; CI-NEXT:    v_bfe_u32 v1, v2, 0, 16
757; CI-NEXT:    v_div_fixup_f32 v5, v5, v4, v3
758; CI-NEXT:    v_trunc_f32_e32 v5, v5
759; CI-NEXT:    v_fma_f32 v3, -v5, v4, v3
760; CI-NEXT:    v_cvt_f16_f32_e32 v3, v3
761; CI-NEXT:    v_bfe_u32 v2, v3, 0, 16
762; CI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
763; CI-NEXT:    v_or_b32_e32 v1, v1, v2
764; CI-NEXT:    v_mov_b32_e32 v2, s4
765; CI-NEXT:    v_mov_b32_e32 v3, s5
766; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
767; CI-NEXT:    s_endpgm
768;
769; VI-LABEL: frem_v4f16:
770; VI:       ; %bb.0:
771; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
772; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
773; VI-NEXT:    s_waitcnt lgkmcnt(0)
774; VI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
775; VI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x20
776; VI-NEXT:    s_waitcnt lgkmcnt(0)
777; VI-NEXT:    v_cvt_f32_f16_e32 v0, s0
778; VI-NEXT:    v_cvt_f32_f16_e32 v2, s2
779; VI-NEXT:    s_lshr_b32 s8, s2, 16
780; VI-NEXT:    v_cvt_f32_f16_e32 v3, s8
781; VI-NEXT:    v_mov_b32_e32 v1, s2
782; VI-NEXT:    v_rcp_f32_e32 v2, v2
783; VI-NEXT:    s_lshr_b32 s6, s0, 16
784; VI-NEXT:    v_rcp_f32_e32 v3, v3
785; VI-NEXT:    v_cvt_f32_f16_e32 v4, s3
786; VI-NEXT:    v_mul_f32_e32 v0, v0, v2
787; VI-NEXT:    v_cvt_f16_f32_e32 v0, v0
788; VI-NEXT:    v_mov_b32_e32 v2, s8
789; VI-NEXT:    v_rcp_f32_e32 v4, v4
790; VI-NEXT:    s_lshr_b32 s9, s3, 16
791; VI-NEXT:    v_div_fixup_f16 v0, v0, v1, s0
792; VI-NEXT:    v_trunc_f16_e32 v0, v0
793; VI-NEXT:    v_fma_f16 v0, -v0, v1, s0
794; VI-NEXT:    v_cvt_f32_f16_e32 v1, s6
795; VI-NEXT:    v_cvt_f32_f16_e32 v5, s9
796; VI-NEXT:    s_lshr_b32 s7, s1, 16
797; VI-NEXT:    v_mul_f32_e32 v1, v1, v3
798; VI-NEXT:    v_cvt_f16_f32_e32 v1, v1
799; VI-NEXT:    v_mov_b32_e32 v3, s3
800; VI-NEXT:    v_rcp_f32_e32 v5, v5
801; VI-NEXT:    v_div_fixup_f16 v1, v1, v2, s6
802; VI-NEXT:    v_trunc_f16_e32 v1, v1
803; VI-NEXT:    v_fma_f16 v1, -v1, v2, s6
804; VI-NEXT:    v_cvt_f32_f16_e32 v2, s1
805; VI-NEXT:    v_mul_f32_e32 v2, v2, v4
806; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
807; VI-NEXT:    v_mov_b32_e32 v4, s9
808; VI-NEXT:    v_div_fixup_f16 v2, v2, v3, s1
809; VI-NEXT:    v_trunc_f16_e32 v2, v2
810; VI-NEXT:    v_fma_f16 v2, -v2, v3, s1
811; VI-NEXT:    v_cvt_f32_f16_e32 v3, s7
812; VI-NEXT:    v_mul_f32_e32 v3, v3, v5
813; VI-NEXT:    v_cvt_f16_f32_e32 v3, v3
814; VI-NEXT:    v_div_fixup_f16 v3, v3, v4, s7
815; VI-NEXT:    v_trunc_f16_e32 v3, v3
816; VI-NEXT:    v_fma_f16 v3, -v3, v4, s7
817; VI-NEXT:    v_mov_b32_e32 v4, 16
818; VI-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
819; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
820; VI-NEXT:    v_lshlrev_b32_sdwa v1, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
821; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
822; VI-NEXT:    v_mov_b32_e32 v2, s4
823; VI-NEXT:    v_mov_b32_e32 v3, s5
824; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
825; VI-NEXT:    s_endpgm
826   %gep2 = getelementptr <4 x half>, <4 x half> addrspace(1)* %in2, i32 4
827   %r0 = load <4 x half>, <4 x half> addrspace(1)* %in1, align 16
828   %r1 = load <4 x half>, <4 x half> addrspace(1)* %gep2, align 16
829   %r2 = frem <4 x half> %r0, %r1
830   store <4 x half> %r2, <4 x half> addrspace(1)* %out, align 16
831   ret void
832}
833
834define amdgpu_kernel void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1, <2 x float> addrspace(1)* %in2) #0 {
835; CI-LABEL: frem_v2f32:
836; CI:       ; %bb.0:
837; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
838; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
839; CI-NEXT:    s_waitcnt lgkmcnt(0)
840; CI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
841; CI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x8
842; CI-NEXT:    s_waitcnt lgkmcnt(0)
843; CI-NEXT:    v_mov_b32_e32 v0, s2
844; CI-NEXT:    v_div_scale_f32 v1, s[6:7], v0, v0, s0
845; CI-NEXT:    v_div_scale_f32 v2, vcc, s0, v0, s0
846; CI-NEXT:    v_rcp_f32_e32 v3, v1
847; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
848; CI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
849; CI-NEXT:    v_fma_f32 v3, v4, v3, v3
850; CI-NEXT:    v_mul_f32_e32 v4, v2, v3
851; CI-NEXT:    v_fma_f32 v5, -v1, v4, v2
852; CI-NEXT:    v_fma_f32 v4, v5, v3, v4
853; CI-NEXT:    v_fma_f32 v1, -v1, v4, v2
854; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
855; CI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
856; CI-NEXT:    v_div_fixup_f32 v1, v1, v0, s0
857; CI-NEXT:    v_trunc_f32_e32 v1, v1
858; CI-NEXT:    v_fma_f32 v0, -v1, v0, s0
859; CI-NEXT:    v_mov_b32_e32 v1, s3
860; CI-NEXT:    v_div_scale_f32 v2, s[2:3], v1, v1, s1
861; CI-NEXT:    v_div_scale_f32 v3, vcc, s1, v1, s1
862; CI-NEXT:    v_rcp_f32_e32 v4, v2
863; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
864; CI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
865; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
866; CI-NEXT:    v_mul_f32_e32 v5, v3, v4
867; CI-NEXT:    v_fma_f32 v6, -v2, v5, v3
868; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
869; CI-NEXT:    v_fma_f32 v2, -v2, v5, v3
870; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
871; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
872; CI-NEXT:    s_mov_b32 s6, -1
873; CI-NEXT:    s_mov_b32 s7, 0xf000
874; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, s1
875; CI-NEXT:    v_trunc_f32_e32 v2, v2
876; CI-NEXT:    v_fma_f32 v1, -v2, v1, s1
877; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
878; CI-NEXT:    s_endpgm
879;
880; VI-LABEL: frem_v2f32:
881; VI:       ; %bb.0:
882; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
883; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
884; VI-NEXT:    s_waitcnt lgkmcnt(0)
885; VI-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
886; VI-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x20
887; VI-NEXT:    s_waitcnt lgkmcnt(0)
888; VI-NEXT:    v_mov_b32_e32 v0, s2
889; VI-NEXT:    v_div_scale_f32 v1, s[6:7], v0, v0, s0
890; VI-NEXT:    v_div_scale_f32 v2, vcc, s0, v0, s0
891; VI-NEXT:    v_rcp_f32_e32 v3, v1
892; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
893; VI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
894; VI-NEXT:    v_fma_f32 v3, v4, v3, v3
895; VI-NEXT:    v_mul_f32_e32 v4, v2, v3
896; VI-NEXT:    v_fma_f32 v5, -v1, v4, v2
897; VI-NEXT:    v_fma_f32 v4, v5, v3, v4
898; VI-NEXT:    v_fma_f32 v1, -v1, v4, v2
899; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
900; VI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
901; VI-NEXT:    v_div_fixup_f32 v1, v1, v0, s0
902; VI-NEXT:    v_trunc_f32_e32 v1, v1
903; VI-NEXT:    v_fma_f32 v0, -v1, v0, s0
904; VI-NEXT:    v_mov_b32_e32 v1, s3
905; VI-NEXT:    v_div_scale_f32 v2, s[2:3], v1, v1, s1
906; VI-NEXT:    v_div_scale_f32 v3, vcc, s1, v1, s1
907; VI-NEXT:    v_rcp_f32_e32 v4, v2
908; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
909; VI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
910; VI-NEXT:    v_fma_f32 v4, v5, v4, v4
911; VI-NEXT:    v_mul_f32_e32 v5, v3, v4
912; VI-NEXT:    v_fma_f32 v6, -v2, v5, v3
913; VI-NEXT:    v_fma_f32 v5, v6, v4, v5
914; VI-NEXT:    v_fma_f32 v2, -v2, v5, v3
915; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
916; VI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
917; VI-NEXT:    v_div_fixup_f32 v2, v2, v1, s1
918; VI-NEXT:    v_trunc_f32_e32 v2, v2
919; VI-NEXT:    v_fma_f32 v1, -v2, v1, s1
920; VI-NEXT:    v_mov_b32_e32 v2, s4
921; VI-NEXT:    v_mov_b32_e32 v3, s5
922; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
923; VI-NEXT:    s_endpgm
924   %gep2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in2, i32 4
925   %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1, align 8
926   %r1 = load <2 x float>, <2 x float> addrspace(1)* %gep2, align 8
927   %r2 = frem <2 x float> %r0, %r1
928   store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
929   ret void
930}
931
932define amdgpu_kernel void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1, <4 x float> addrspace(1)* %in2) #0 {
933; CI-LABEL: frem_v4f32:
934; CI:       ; %bb.0:
935; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
936; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
937; CI-NEXT:    s_waitcnt lgkmcnt(0)
938; CI-NEXT:    s_load_dwordx4 s[0:3], s[6:7], 0x0
939; CI-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x10
940; CI-NEXT:    s_waitcnt lgkmcnt(0)
941; CI-NEXT:    v_mov_b32_e32 v0, s8
942; CI-NEXT:    v_div_scale_f32 v1, s[6:7], v0, v0, s0
943; CI-NEXT:    v_div_scale_f32 v2, vcc, s0, v0, s0
944; CI-NEXT:    v_rcp_f32_e32 v3, v1
945; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
946; CI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
947; CI-NEXT:    v_fma_f32 v3, v4, v3, v3
948; CI-NEXT:    v_mul_f32_e32 v4, v2, v3
949; CI-NEXT:    v_fma_f32 v5, -v1, v4, v2
950; CI-NEXT:    v_fma_f32 v4, v5, v3, v4
951; CI-NEXT:    v_fma_f32 v1, -v1, v4, v2
952; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
953; CI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
954; CI-NEXT:    v_div_fixup_f32 v1, v1, v0, s0
955; CI-NEXT:    v_trunc_f32_e32 v1, v1
956; CI-NEXT:    v_fma_f32 v0, -v1, v0, s0
957; CI-NEXT:    v_mov_b32_e32 v1, s9
958; CI-NEXT:    v_div_scale_f32 v2, s[6:7], v1, v1, s1
959; CI-NEXT:    v_div_scale_f32 v3, vcc, s1, v1, s1
960; CI-NEXT:    v_rcp_f32_e32 v4, v2
961; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
962; CI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
963; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
964; CI-NEXT:    v_mul_f32_e32 v5, v3, v4
965; CI-NEXT:    v_fma_f32 v6, -v2, v5, v3
966; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
967; CI-NEXT:    v_fma_f32 v2, -v2, v5, v3
968; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
969; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
970; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, s1
971; CI-NEXT:    v_trunc_f32_e32 v2, v2
972; CI-NEXT:    v_fma_f32 v1, -v2, v1, s1
973; CI-NEXT:    v_mov_b32_e32 v2, s10
974; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v2, v2, s2
975; CI-NEXT:    v_div_scale_f32 v4, vcc, s2, v2, s2
976; CI-NEXT:    v_rcp_f32_e32 v5, v3
977; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
978; CI-NEXT:    v_fma_f32 v6, -v3, v5, 1.0
979; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
980; CI-NEXT:    v_mul_f32_e32 v6, v4, v5
981; CI-NEXT:    v_fma_f32 v7, -v3, v6, v4
982; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
983; CI-NEXT:    v_fma_f32 v3, -v3, v6, v4
984; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
985; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
986; CI-NEXT:    v_div_fixup_f32 v3, v3, v2, s2
987; CI-NEXT:    v_trunc_f32_e32 v3, v3
988; CI-NEXT:    v_fma_f32 v2, -v3, v2, s2
989; CI-NEXT:    v_mov_b32_e32 v3, s11
990; CI-NEXT:    v_div_scale_f32 v4, s[0:1], v3, v3, s3
991; CI-NEXT:    v_div_scale_f32 v5, vcc, s3, v3, s3
992; CI-NEXT:    v_rcp_f32_e32 v6, v4
993; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
994; CI-NEXT:    v_fma_f32 v7, -v4, v6, 1.0
995; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
996; CI-NEXT:    v_mul_f32_e32 v7, v5, v6
997; CI-NEXT:    v_fma_f32 v8, -v4, v7, v5
998; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
999; CI-NEXT:    v_fma_f32 v4, -v4, v7, v5
1000; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1001; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1002; CI-NEXT:    s_mov_b32 s6, -1
1003; CI-NEXT:    s_mov_b32 s7, 0xf000
1004; CI-NEXT:    v_div_fixup_f32 v4, v4, v3, s3
1005; CI-NEXT:    v_trunc_f32_e32 v4, v4
1006; CI-NEXT:    v_fma_f32 v3, -v4, v3, s3
1007; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
1008; CI-NEXT:    s_endpgm
1009;
1010; VI-LABEL: frem_v4f32:
1011; VI:       ; %bb.0:
1012; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1013; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
1014; VI-NEXT:    s_waitcnt lgkmcnt(0)
1015; VI-NEXT:    s_load_dwordx4 s[0:3], s[6:7], 0x0
1016; VI-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x40
1017; VI-NEXT:    s_waitcnt lgkmcnt(0)
1018; VI-NEXT:    v_mov_b32_e32 v0, s8
1019; VI-NEXT:    v_div_scale_f32 v1, s[6:7], v0, v0, s0
1020; VI-NEXT:    v_div_scale_f32 v2, vcc, s0, v0, s0
1021; VI-NEXT:    v_rcp_f32_e32 v3, v1
1022; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1023; VI-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
1024; VI-NEXT:    v_fma_f32 v3, v4, v3, v3
1025; VI-NEXT:    v_mul_f32_e32 v4, v2, v3
1026; VI-NEXT:    v_fma_f32 v5, -v1, v4, v2
1027; VI-NEXT:    v_fma_f32 v4, v5, v3, v4
1028; VI-NEXT:    v_fma_f32 v1, -v1, v4, v2
1029; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1030; VI-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
1031; VI-NEXT:    v_div_fixup_f32 v1, v1, v0, s0
1032; VI-NEXT:    v_trunc_f32_e32 v1, v1
1033; VI-NEXT:    v_fma_f32 v0, -v1, v0, s0
1034; VI-NEXT:    v_mov_b32_e32 v1, s9
1035; VI-NEXT:    v_div_scale_f32 v2, s[6:7], v1, v1, s1
1036; VI-NEXT:    v_div_scale_f32 v3, vcc, s1, v1, s1
1037; VI-NEXT:    v_rcp_f32_e32 v4, v2
1038; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1039; VI-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
1040; VI-NEXT:    v_fma_f32 v4, v5, v4, v4
1041; VI-NEXT:    v_mul_f32_e32 v5, v3, v4
1042; VI-NEXT:    v_fma_f32 v6, -v2, v5, v3
1043; VI-NEXT:    v_fma_f32 v5, v6, v4, v5
1044; VI-NEXT:    v_fma_f32 v2, -v2, v5, v3
1045; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1046; VI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1047; VI-NEXT:    v_div_fixup_f32 v2, v2, v1, s1
1048; VI-NEXT:    v_trunc_f32_e32 v2, v2
1049; VI-NEXT:    v_fma_f32 v1, -v2, v1, s1
1050; VI-NEXT:    v_mov_b32_e32 v2, s10
1051; VI-NEXT:    v_div_scale_f32 v3, s[0:1], v2, v2, s2
1052; VI-NEXT:    v_div_scale_f32 v4, vcc, s2, v2, s2
1053; VI-NEXT:    v_rcp_f32_e32 v5, v3
1054; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1055; VI-NEXT:    v_fma_f32 v6, -v3, v5, 1.0
1056; VI-NEXT:    v_fma_f32 v5, v6, v5, v5
1057; VI-NEXT:    v_mul_f32_e32 v6, v4, v5
1058; VI-NEXT:    v_fma_f32 v7, -v3, v6, v4
1059; VI-NEXT:    v_fma_f32 v6, v7, v5, v6
1060; VI-NEXT:    v_fma_f32 v3, -v3, v6, v4
1061; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1062; VI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
1063; VI-NEXT:    v_div_fixup_f32 v3, v3, v2, s2
1064; VI-NEXT:    v_trunc_f32_e32 v3, v3
1065; VI-NEXT:    v_fma_f32 v2, -v3, v2, s2
1066; VI-NEXT:    v_mov_b32_e32 v3, s11
1067; VI-NEXT:    v_div_scale_f32 v4, s[0:1], v3, v3, s3
1068; VI-NEXT:    v_div_scale_f32 v5, vcc, s3, v3, s3
1069; VI-NEXT:    v_rcp_f32_e32 v6, v4
1070; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1071; VI-NEXT:    v_fma_f32 v7, -v4, v6, 1.0
1072; VI-NEXT:    v_fma_f32 v6, v7, v6, v6
1073; VI-NEXT:    v_mul_f32_e32 v7, v5, v6
1074; VI-NEXT:    v_fma_f32 v8, -v4, v7, v5
1075; VI-NEXT:    v_fma_f32 v7, v8, v6, v7
1076; VI-NEXT:    v_fma_f32 v4, -v4, v7, v5
1077; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1078; VI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1079; VI-NEXT:    v_div_fixup_f32 v4, v4, v3, s3
1080; VI-NEXT:    v_trunc_f32_e32 v4, v4
1081; VI-NEXT:    v_fma_f32 v3, -v4, v3, s3
1082; VI-NEXT:    v_mov_b32_e32 v4, s4
1083; VI-NEXT:    v_mov_b32_e32 v5, s5
1084; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
1085; VI-NEXT:    s_endpgm
1086   %gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %in2, i32 4
1087   %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1, align 16
1088   %r1 = load <4 x float>, <4 x float> addrspace(1)* %gep2, align 16
1089   %r2 = frem <4 x float> %r0, %r1
1090   store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
1091   ret void
1092}
1093
1094define amdgpu_kernel void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1, <2 x double> addrspace(1)* %in2) #0 {
1095; CI-LABEL: frem_v2f64:
1096; CI:       ; %bb.0:
1097; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1098; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1099; CI-NEXT:    s_waitcnt lgkmcnt(0)
1100; CI-NEXT:    s_load_dwordx4 s[0:3], s[6:7], 0x0
1101; CI-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x10
1102; CI-NEXT:    s_waitcnt lgkmcnt(0)
1103; CI-NEXT:    v_mov_b32_e32 v0, s8
1104; CI-NEXT:    v_mov_b32_e32 v1, s9
1105; CI-NEXT:    v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], s[0:1]
1106; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
1107; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
1108; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
1109; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
1110; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
1111; CI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
1112; CI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
1113; CI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
1114; CI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
1115; CI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
1116; CI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
1117; CI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
1118; CI-NEXT:    v_mov_b32_e32 v2, s10
1119; CI-NEXT:    v_mov_b32_e32 v3, s11
1120; CI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], s[2:3]
1121; CI-NEXT:    v_div_scale_f64 v[10:11], vcc, s[2:3], v[2:3], s[2:3]
1122; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
1123; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
1124; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
1125; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
1126; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
1127; CI-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
1128; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
1129; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
1130; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], s[2:3]
1131; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
1132; CI-NEXT:    v_fma_f64 v[2:3], -v[4:5], v[2:3], s[2:3]
1133; CI-NEXT:    v_mov_b32_e32 v4, s4
1134; CI-NEXT:    v_mov_b32_e32 v5, s5
1135; CI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
1136; CI-NEXT:    s_endpgm
1137;
1138; VI-LABEL: frem_v2f64:
1139; VI:       ; %bb.0:
1140; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1141; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x34
1142; VI-NEXT:    s_waitcnt lgkmcnt(0)
1143; VI-NEXT:    s_load_dwordx4 s[0:3], s[6:7], 0x0
1144; VI-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x40
1145; VI-NEXT:    s_waitcnt lgkmcnt(0)
1146; VI-NEXT:    v_mov_b32_e32 v0, s8
1147; VI-NEXT:    v_mov_b32_e32 v1, s9
1148; VI-NEXT:    v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], s[0:1]
1149; VI-NEXT:    v_div_scale_f64 v[8:9], vcc, s[0:1], v[0:1], s[0:1]
1150; VI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
1151; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
1152; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
1153; VI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
1154; VI-NEXT:    v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
1155; VI-NEXT:    v_mul_f64 v[6:7], v[8:9], v[4:5]
1156; VI-NEXT:    v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
1157; VI-NEXT:    v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
1158; VI-NEXT:    v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[0:1]
1159; VI-NEXT:    v_trunc_f64_e32 v[2:3], v[2:3]
1160; VI-NEXT:    v_fma_f64 v[0:1], -v[2:3], v[0:1], s[0:1]
1161; VI-NEXT:    v_mov_b32_e32 v2, s10
1162; VI-NEXT:    v_mov_b32_e32 v3, s11
1163; VI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], s[2:3]
1164; VI-NEXT:    v_div_scale_f64 v[10:11], vcc, s[2:3], v[2:3], s[2:3]
1165; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
1166; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
1167; VI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
1168; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
1169; VI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
1170; VI-NEXT:    v_mul_f64 v[8:9], v[10:11], v[6:7]
1171; VI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
1172; VI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
1173; VI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], s[2:3]
1174; VI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
1175; VI-NEXT:    v_fma_f64 v[2:3], -v[4:5], v[2:3], s[2:3]
1176; VI-NEXT:    v_mov_b32_e32 v4, s4
1177; VI-NEXT:    v_mov_b32_e32 v5, s5
1178; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
1179; VI-NEXT:    s_endpgm
1180   %gep2 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in2, i32 4
1181   %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1, align 16
1182   %r1 = load <2 x double>, <2 x double> addrspace(1)* %gep2, align 16
1183   %r2 = frem <2 x double> %r0, %r1
1184   store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
1185   ret void
1186}
1187
1188attributes #0 = { nounwind "unsafe-fp-math"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
1189attributes #1 = { nounwind "unsafe-fp-math"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
1190