1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s 6; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s 7 8define float @v_pow_f32(float %x, float %y) { 9; GFX6-LABEL: v_pow_f32: 10; GFX6: ; %bb.0: 11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 12; GFX6-NEXT: v_log_f32_e32 v0, v0 13; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 14; GFX6-NEXT: v_exp_f32_e32 v0, v0 15; GFX6-NEXT: s_setpc_b64 s[30:31] 16; 17; GFX8-LABEL: v_pow_f32: 18; GFX8: ; %bb.0: 19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; GFX8-NEXT: v_log_f32_e32 v0, v0 21; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 22; GFX8-NEXT: v_exp_f32_e32 v0, v0 23; GFX8-NEXT: s_setpc_b64 s[30:31] 24; 25; GFX9-LABEL: v_pow_f32: 26; GFX9: ; %bb.0: 27; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 28; GFX9-NEXT: v_log_f32_e32 v0, v0 29; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 30; GFX9-NEXT: v_exp_f32_e32 v0, v0 31; GFX9-NEXT: s_setpc_b64 s[30:31] 32; 33; GFX10-LABEL: v_pow_f32: 34; GFX10: ; %bb.0: 35; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 36; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 37; GFX10-NEXT: v_log_f32_e32 v0, v0 38; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 39; GFX10-NEXT: v_exp_f32_e32 v0, v0 40; GFX10-NEXT: s_setpc_b64 s[30:31] 41; 42; GFX11-LABEL: v_pow_f32: 43; GFX11: ; %bb.0: 44; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 45; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 46; GFX11-NEXT: v_log_f32_e32 v0, v0 47; GFX11-NEXT: s_waitcnt_depctr 0xfff 48; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 49; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 50; GFX11-NEXT: v_exp_f32_e32 v0, v0 51; GFX11-NEXT: s_setpc_b64 s[30:31] 52 %pow = call float @llvm.pow.f32(float %x, float %y) 53 ret float %pow 54} 55 56define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { 57; GFX6-LABEL: v_pow_v2f32: 58; GFX6: ; %bb.0: 59; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 60; GFX6-NEXT: v_log_f32_e32 v0, v0 61; GFX6-NEXT: v_log_f32_e32 v1, v1 62; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 63; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 64; GFX6-NEXT: v_exp_f32_e32 v0, v0 65; GFX6-NEXT: v_exp_f32_e32 v1, v1 66; GFX6-NEXT: s_setpc_b64 s[30:31] 67; 68; GFX8-LABEL: v_pow_v2f32: 69; GFX8: ; %bb.0: 70; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 71; GFX8-NEXT: v_log_f32_e32 v0, v0 72; GFX8-NEXT: v_log_f32_e32 v1, v1 73; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 74; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 75; GFX8-NEXT: v_exp_f32_e32 v0, v0 76; GFX8-NEXT: v_exp_f32_e32 v1, v1 77; GFX8-NEXT: s_setpc_b64 s[30:31] 78; 79; GFX9-LABEL: v_pow_v2f32: 80; GFX9: ; %bb.0: 81; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 82; GFX9-NEXT: v_log_f32_e32 v0, v0 83; GFX9-NEXT: v_log_f32_e32 v1, v1 84; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 85; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 86; GFX9-NEXT: v_exp_f32_e32 v0, v0 87; GFX9-NEXT: v_exp_f32_e32 v1, v1 88; GFX9-NEXT: s_setpc_b64 s[30:31] 89; 90; GFX10-LABEL: v_pow_v2f32: 91; GFX10: ; %bb.0: 92; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 93; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 94; GFX10-NEXT: v_log_f32_e32 v0, v0 95; GFX10-NEXT: v_log_f32_e32 v1, v1 96; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 97; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 98; GFX10-NEXT: v_exp_f32_e32 v0, v0 99; GFX10-NEXT: v_exp_f32_e32 v1, v1 100; GFX10-NEXT: s_setpc_b64 s[30:31] 101; 102; GFX11-LABEL: v_pow_v2f32: 103; GFX11: ; %bb.0: 104; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 105; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 106; GFX11-NEXT: v_log_f32_e32 v0, v0 107; GFX11-NEXT: v_log_f32_e32 v1, v1 108; GFX11-NEXT: s_waitcnt_depctr 0xfff 109; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v0, v2 :: v_dual_mul_dx9_zero_f32 v1, v1, v3 110; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) 111; GFX11-NEXT: v_exp_f32_e32 v0, v0 112; GFX11-NEXT: v_exp_f32_e32 v1, v1 113; GFX11-NEXT: s_setpc_b64 s[30:31] 114 %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) 115 ret <2 x float> %pow 116} 117 118define half @v_pow_f16(half %x, half %y) { 119; GFX6-LABEL: v_pow_f16: 120; GFX6: ; %bb.0: 121; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 122; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 123; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 124; GFX6-NEXT: v_log_f32_e32 v0, v0 125; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 126; GFX6-NEXT: v_exp_f32_e32 v0, v0 127; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 128; GFX6-NEXT: s_setpc_b64 s[30:31] 129; 130; GFX8-LABEL: v_pow_f16: 131; GFX8: ; %bb.0: 132; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 133; GFX8-NEXT: v_log_f16_e32 v0, v0 134; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 135; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 136; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 137; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 138; GFX8-NEXT: v_exp_f16_e32 v0, v0 139; GFX8-NEXT: s_setpc_b64 s[30:31] 140; 141; GFX9-LABEL: v_pow_f16: 142; GFX9: ; %bb.0: 143; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 144; GFX9-NEXT: v_log_f16_e32 v0, v0 145; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 146; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 147; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 148; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 149; GFX9-NEXT: v_exp_f16_e32 v0, v0 150; GFX9-NEXT: s_setpc_b64 s[30:31] 151; 152; GFX10-LABEL: v_pow_f16: 153; GFX10: ; %bb.0: 154; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 155; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 156; GFX10-NEXT: v_log_f16_e32 v0, v0 157; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 158; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 159; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 160; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 161; GFX10-NEXT: v_exp_f16_e32 v0, v0 162; GFX10-NEXT: s_setpc_b64 s[30:31] 163; 164; GFX11-LABEL: v_pow_f16: 165; GFX11: ; %bb.0: 166; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 167; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 168; GFX11-NEXT: v_log_f16_e32 v0, v0 169; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v1 170; GFX11-NEXT: s_waitcnt_depctr 0xfff 171; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0 172; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) 173; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 174; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 175; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 176; GFX11-NEXT: v_exp_f16_e32 v0, v0 177; GFX11-NEXT: s_setpc_b64 s[30:31] 178 %pow = call half @llvm.pow.f16(half %x, half %y) 179 ret half %pow 180} 181 182define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { 183; GFX6-LABEL: v_pow_v2f16: 184; GFX6: ; %bb.0: 185; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 186; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 187; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 188; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 189; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 190; GFX6-NEXT: v_log_f32_e32 v0, v0 191; GFX6-NEXT: v_log_f32_e32 v1, v1 192; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 193; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 194; GFX6-NEXT: v_exp_f32_e32 v0, v0 195; GFX6-NEXT: v_exp_f32_e32 v1, v1 196; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 197; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 198; GFX6-NEXT: s_setpc_b64 s[30:31] 199; 200; GFX8-LABEL: v_pow_v2f16: 201; GFX8: ; %bb.0: 202; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 203; GFX8-NEXT: v_log_f16_e32 v2, v0 204; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 205; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 206; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 207; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 208; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 209; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 210; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 211; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 212; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 213; GFX8-NEXT: v_mov_b32_e32 v2, 16 214; GFX8-NEXT: v_exp_f16_e32 v0, v0 215; GFX8-NEXT: v_exp_f16_e32 v1, v1 216; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 217; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 218; GFX8-NEXT: s_setpc_b64 s[30:31] 219; 220; GFX9-LABEL: v_pow_v2f16: 221; GFX9: ; %bb.0: 222; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 223; GFX9-NEXT: v_log_f16_e32 v2, v0 224; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 225; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 226; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 227; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 228; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 229; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 230; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 231; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 232; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 233; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 234; GFX9-NEXT: v_exp_f16_e32 v1, v1 235; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 236; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 237; GFX9-NEXT: s_setpc_b64 s[30:31] 238; 239; GFX10-LABEL: v_pow_v2f16: 240; GFX10: ; %bb.0: 241; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 242; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 243; GFX10-NEXT: v_log_f16_e32 v2, v0 244; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 245; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 246; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 247; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 248; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 249; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 250; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 251; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 252; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 253; GFX10-NEXT: v_exp_f16_e32 v1, v1 254; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 255; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 256; GFX10-NEXT: s_setpc_b64 s[30:31] 257; 258; GFX11-LABEL: v_pow_v2f16: 259; GFX11: ; %bb.0: 260; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 261; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 262; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 263; GFX11-NEXT: v_log_f16_e32 v0, v0 264; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v1 265; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v1 266; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) 267; GFX11-NEXT: v_log_f16_e32 v2, v2 268; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v3 269; GFX11-NEXT: s_waitcnt_depctr 0xfff 270; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0 271; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v2 272; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 273; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 274; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v2, v3 275; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 276; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 277; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v2 278; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) 279; GFX11-NEXT: v_exp_f16_e32 v0, v0 280; GFX11-NEXT: v_exp_f16_e32 v1, v1 281; GFX11-NEXT: s_waitcnt_depctr 0xfff 282; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 283; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 284; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 285; GFX11-NEXT: s_setpc_b64 s[30:31] 286 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y) 287 ret <2 x half> %pow 288} 289 290define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { 291; GFX6-LABEL: v_pow_v2f16_fneg_lhs: 292; GFX6: ; %bb.0: 293; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 294; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 295; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 296; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 297; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 298; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0 299; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 300; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 301; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 302; GFX6-NEXT: v_log_f32_e32 v1, v1 303; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 304; GFX6-NEXT: v_log_f32_e32 v0, v0 305; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v2 306; GFX6-NEXT: v_exp_f32_e32 v1, v1 307; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v3 308; GFX6-NEXT: v_exp_f32_e32 v2, v0 309; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v1 310; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2 311; GFX6-NEXT: s_setpc_b64 s[30:31] 312; 313; GFX8-LABEL: v_pow_v2f16_fneg_lhs: 314; GFX8: ; %bb.0: 315; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 316; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 317; GFX8-NEXT: v_log_f16_e32 v2, v0 318; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 319; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 320; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 321; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 322; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 323; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 324; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 325; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 326; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 327; GFX8-NEXT: v_mov_b32_e32 v2, 16 328; GFX8-NEXT: v_exp_f16_e32 v0, v0 329; GFX8-NEXT: v_exp_f16_e32 v1, v1 330; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 331; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 332; GFX8-NEXT: s_setpc_b64 s[30:31] 333; 334; GFX9-LABEL: v_pow_v2f16_fneg_lhs: 335; GFX9: ; %bb.0: 336; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 337; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 338; GFX9-NEXT: v_log_f16_e32 v2, v0 339; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 340; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 341; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 342; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 343; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 344; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 345; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 346; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 347; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 348; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 349; GFX9-NEXT: v_exp_f16_e32 v1, v1 350; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 351; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 352; GFX9-NEXT: s_setpc_b64 s[30:31] 353; 354; GFX10-LABEL: v_pow_v2f16_fneg_lhs: 355; GFX10: ; %bb.0: 356; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 357; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 358; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 359; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 360; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 361; GFX10-NEXT: v_log_f16_e32 v2, v0 362; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 363; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 364; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 365; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 366; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 367; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 368; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 369; GFX10-NEXT: v_exp_f16_e32 v1, v1 370; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 371; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 372; GFX10-NEXT: s_setpc_b64 s[30:31] 373; 374; GFX11-LABEL: v_pow_v2f16_fneg_lhs: 375; GFX11: ; %bb.0: 376; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 377; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 378; GFX11-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 379; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v1 380; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v1 381; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) 382; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 383; GFX11-NEXT: v_log_f16_e32 v0, v0 384; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v3 385; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) 386; GFX11-NEXT: v_log_f16_e32 v2, v2 387; GFX11-NEXT: s_waitcnt_depctr 0xfff 388; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0 389; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v2 390; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 391; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 392; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v2, v3 393; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 394; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 395; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v2 396; GFX11-NEXT: v_exp_f16_e32 v0, v0 397; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) 398; GFX11-NEXT: v_exp_f16_e32 v1, v1 399; GFX11-NEXT: s_waitcnt_depctr 0xfff 400; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 401; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 402; GFX11-NEXT: s_setpc_b64 s[30:31] 403 %x.fneg = fneg <2 x half> %x 404 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y) 405 ret <2 x half> %pow 406} 407 408define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { 409; GFX6-LABEL: v_pow_v2f16_fneg_rhs: 410; GFX6: ; %bb.0: 411; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 412; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 413; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 414; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 415; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 416; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 417; GFX6-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 418; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2 419; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 420; GFX6-NEXT: v_log_f32_e32 v0, v0 421; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 422; GFX6-NEXT: v_log_f32_e32 v1, v1 423; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 424; GFX6-NEXT: v_exp_f32_e32 v0, v0 425; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 426; GFX6-NEXT: v_exp_f32_e32 v1, v1 427; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 428; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 429; GFX6-NEXT: s_setpc_b64 s[30:31] 430; 431; GFX8-LABEL: v_pow_v2f16_fneg_rhs: 432; GFX8: ; %bb.0: 433; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 434; GFX8-NEXT: v_log_f16_e32 v2, v0 435; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 436; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 437; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 438; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 439; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 440; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 441; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 442; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 443; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 444; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 445; GFX8-NEXT: v_mov_b32_e32 v2, 16 446; GFX8-NEXT: v_exp_f16_e32 v0, v0 447; GFX8-NEXT: v_exp_f16_e32 v1, v1 448; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 449; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 450; GFX8-NEXT: s_setpc_b64 s[30:31] 451; 452; GFX9-LABEL: v_pow_v2f16_fneg_rhs: 453; GFX9: ; %bb.0: 454; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 455; GFX9-NEXT: v_log_f16_e32 v2, v0 456; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 457; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 458; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 459; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 460; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 461; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 462; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 463; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 464; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 465; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 466; GFX9-NEXT: v_exp_f16_e32 v1, v2 467; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 468; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 469; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 470; GFX9-NEXT: s_setpc_b64 s[30:31] 471; 472; GFX10-LABEL: v_pow_v2f16_fneg_rhs: 473; GFX10: ; %bb.0: 474; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 475; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 476; GFX10-NEXT: v_log_f16_e32 v2, v0 477; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 478; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 479; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 480; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 481; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 482; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 483; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 484; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 485; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 486; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 487; GFX10-NEXT: v_exp_f16_e32 v1, v1 488; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 489; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 490; GFX10-NEXT: s_setpc_b64 s[30:31] 491; 492; GFX11-LABEL: v_pow_v2f16_fneg_rhs: 493; GFX11: ; %bb.0: 494; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 495; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 496; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 497; GFX11-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 498; GFX11-NEXT: v_log_f16_e32 v0, v0 499; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) 500; GFX11-NEXT: v_log_f16_e32 v2, v2 501; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v1 502; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v1 503; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) 504; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v3 505; GFX11-NEXT: s_waitcnt_depctr 0xfff 506; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0 507; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v2 508; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 509; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 510; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v2, v3 511; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 512; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 513; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v2 514; GFX11-NEXT: v_exp_f16_e32 v0, v0 515; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) 516; GFX11-NEXT: v_exp_f16_e32 v1, v1 517; GFX11-NEXT: s_waitcnt_depctr 0xfff 518; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 519; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 520; GFX11-NEXT: s_setpc_b64 s[30:31] 521 %y.fneg = fneg <2 x half> %y 522 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg) 523 ret <2 x half> %pow 524} 525 526define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { 527; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs: 528; GFX6: ; %bb.0: 529; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 530; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 531; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 532; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 533; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 534; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 535; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 536; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 537; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 538; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 539; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 540; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 541; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 542; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 543; GFX6-NEXT: v_log_f32_e32 v0, v0 544; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 545; GFX6-NEXT: v_log_f32_e32 v2, v2 546; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 547; GFX6-NEXT: v_exp_f32_e32 v0, v0 548; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 549; GFX6-NEXT: v_exp_f32_e32 v1, v1 550; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 551; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 552; GFX6-NEXT: s_setpc_b64 s[30:31] 553; 554; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs: 555; GFX8: ; %bb.0: 556; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 557; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 558; GFX8-NEXT: v_log_f16_e32 v2, v0 559; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 560; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 561; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 562; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 563; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 564; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 565; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 566; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 567; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 568; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 569; GFX8-NEXT: v_mov_b32_e32 v2, 16 570; GFX8-NEXT: v_exp_f16_e32 v0, v0 571; GFX8-NEXT: v_exp_f16_e32 v1, v1 572; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 573; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 574; GFX8-NEXT: s_setpc_b64 s[30:31] 575; 576; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs: 577; GFX9: ; %bb.0: 578; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 579; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 580; GFX9-NEXT: v_log_f16_e32 v2, v0 581; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 582; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 583; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 584; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 585; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 586; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 587; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 588; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 589; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 590; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 591; GFX9-NEXT: v_exp_f16_e32 v1, v2 592; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 593; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 594; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 595; GFX9-NEXT: s_setpc_b64 s[30:31] 596; 597; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: 598; GFX10: ; %bb.0: 599; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 600; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 601; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 602; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 603; GFX10-NEXT: v_log_f16_e32 v2, v0 604; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 605; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 606; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 607; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 608; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 609; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 610; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 611; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 612; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 613; GFX10-NEXT: v_exp_f16_e32 v1, v1 614; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 615; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 616; GFX10-NEXT: s_setpc_b64 s[30:31] 617; 618; GFX11-LABEL: v_pow_v2f16_fneg_lhs_rhs: 619; GFX11: ; %bb.0: 620; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 621; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 622; GFX11-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 623; GFX11-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 624; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) 625; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 626; GFX11-NEXT: v_log_f16_e32 v0, v0 627; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v1 628; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v1 629; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) 630; GFX11-NEXT: v_log_f16_e32 v2, v2 631; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v3 632; GFX11-NEXT: s_waitcnt_depctr 0xfff 633; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0 634; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v2 635; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 636; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 637; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v2, v2, v3 638; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) 639; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0 640; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v2 641; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) 642; GFX11-NEXT: v_exp_f16_e32 v0, v0 643; GFX11-NEXT: v_exp_f16_e32 v1, v1 644; GFX11-NEXT: s_waitcnt_depctr 0xfff 645; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 646; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 647; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 648; GFX11-NEXT: s_setpc_b64 s[30:31] 649 %x.fneg = fneg <2 x half> %x 650 %y.fneg = fneg <2 x half> %y 651 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg) 652 ret <2 x half> %pow 653} 654 655; FIXME 656; define double @v_pow_f64(double %x, double %y) { 657; %pow = call double @llvm.pow.f64(double %x, double %y) 658; ret double %pow 659; } 660 661define float @v_pow_f32_fabs_lhs(float %x, float %y) { 662; GFX6-LABEL: v_pow_f32_fabs_lhs: 663; GFX6: ; %bb.0: 664; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 665; GFX6-NEXT: v_log_f32_e64 v0, |v0| 666; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 667; GFX6-NEXT: v_exp_f32_e32 v0, v0 668; GFX6-NEXT: s_setpc_b64 s[30:31] 669; 670; GFX8-LABEL: v_pow_f32_fabs_lhs: 671; GFX8: ; %bb.0: 672; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 673; GFX8-NEXT: v_log_f32_e64 v0, |v0| 674; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 675; GFX8-NEXT: v_exp_f32_e32 v0, v0 676; GFX8-NEXT: s_setpc_b64 s[30:31] 677; 678; GFX9-LABEL: v_pow_f32_fabs_lhs: 679; GFX9: ; %bb.0: 680; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 681; GFX9-NEXT: v_log_f32_e64 v0, |v0| 682; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 683; GFX9-NEXT: v_exp_f32_e32 v0, v0 684; GFX9-NEXT: s_setpc_b64 s[30:31] 685; 686; GFX10-LABEL: v_pow_f32_fabs_lhs: 687; GFX10: ; %bb.0: 688; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 689; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 690; GFX10-NEXT: v_log_f32_e64 v0, |v0| 691; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 692; GFX10-NEXT: v_exp_f32_e32 v0, v0 693; GFX10-NEXT: s_setpc_b64 s[30:31] 694; 695; GFX11-LABEL: v_pow_f32_fabs_lhs: 696; GFX11: ; %bb.0: 697; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 698; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 699; GFX11-NEXT: v_log_f32_e64 v0, |v0| 700; GFX11-NEXT: s_waitcnt_depctr 0xfff 701; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 702; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 703; GFX11-NEXT: v_exp_f32_e32 v0, v0 704; GFX11-NEXT: s_setpc_b64 s[30:31] 705 %fabs.x = call float @llvm.fabs.f32(float %x) 706 %pow = call float @llvm.pow.f32(float %fabs.x, float %y) 707 ret float %pow 708} 709 710define float @v_pow_f32_fabs_rhs(float %x, float %y) { 711; GFX6-LABEL: v_pow_f32_fabs_rhs: 712; GFX6: ; %bb.0: 713; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 714; GFX6-NEXT: v_log_f32_e32 v0, v0 715; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 716; GFX6-NEXT: v_exp_f32_e32 v0, v0 717; GFX6-NEXT: s_setpc_b64 s[30:31] 718; 719; GFX8-LABEL: v_pow_f32_fabs_rhs: 720; GFX8: ; %bb.0: 721; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 722; GFX8-NEXT: v_log_f32_e32 v0, v0 723; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 724; GFX8-NEXT: v_exp_f32_e32 v0, v0 725; GFX8-NEXT: s_setpc_b64 s[30:31] 726; 727; GFX9-LABEL: v_pow_f32_fabs_rhs: 728; GFX9: ; %bb.0: 729; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 730; GFX9-NEXT: v_log_f32_e32 v0, v0 731; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 732; GFX9-NEXT: v_exp_f32_e32 v0, v0 733; GFX9-NEXT: s_setpc_b64 s[30:31] 734; 735; GFX10-LABEL: v_pow_f32_fabs_rhs: 736; GFX10: ; %bb.0: 737; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 738; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 739; GFX10-NEXT: v_log_f32_e32 v0, v0 740; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 741; GFX10-NEXT: v_exp_f32_e32 v0, v0 742; GFX10-NEXT: s_setpc_b64 s[30:31] 743; 744; GFX11-LABEL: v_pow_f32_fabs_rhs: 745; GFX11: ; %bb.0: 746; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 747; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 748; GFX11-NEXT: v_log_f32_e32 v0, v0 749; GFX11-NEXT: s_waitcnt_depctr 0xfff 750; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1| 751; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 752; GFX11-NEXT: v_exp_f32_e32 v0, v0 753; GFX11-NEXT: s_setpc_b64 s[30:31] 754 %fabs.y = call float @llvm.fabs.f32(float %y) 755 %pow = call float @llvm.pow.f32(float %x, float %fabs.y) 756 ret float %pow 757} 758 759define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { 760; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: 761; GFX6: ; %bb.0: 762; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 763; GFX6-NEXT: v_log_f32_e64 v0, |v0| 764; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 765; GFX6-NEXT: v_exp_f32_e32 v0, v0 766; GFX6-NEXT: s_setpc_b64 s[30:31] 767; 768; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: 769; GFX8: ; %bb.0: 770; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 771; GFX8-NEXT: v_log_f32_e64 v0, |v0| 772; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 773; GFX8-NEXT: v_exp_f32_e32 v0, v0 774; GFX8-NEXT: s_setpc_b64 s[30:31] 775; 776; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: 777; GFX9: ; %bb.0: 778; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 779; GFX9-NEXT: v_log_f32_e64 v0, |v0| 780; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 781; GFX9-NEXT: v_exp_f32_e32 v0, v0 782; GFX9-NEXT: s_setpc_b64 s[30:31] 783; 784; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: 785; GFX10: ; %bb.0: 786; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 787; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 788; GFX10-NEXT: v_log_f32_e64 v0, |v0| 789; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 790; GFX10-NEXT: v_exp_f32_e32 v0, v0 791; GFX10-NEXT: s_setpc_b64 s[30:31] 792; 793; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs: 794; GFX11: ; %bb.0: 795; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 796; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 797; GFX11-NEXT: v_log_f32_e64 v0, |v0| 798; GFX11-NEXT: s_waitcnt_depctr 0xfff 799; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1| 800; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 801; GFX11-NEXT: v_exp_f32_e32 v0, v0 802; GFX11-NEXT: s_setpc_b64 s[30:31] 803 %fabs.x = call float @llvm.fabs.f32(float %x) 804 %fabs.y = call float @llvm.fabs.f32(float %y) 805 %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) 806 ret float %pow 807} 808 809define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { 810; GFX6-LABEL: v_pow_f32_sgpr_vgpr: 811; GFX6: ; %bb.0: 812; GFX6-NEXT: v_log_f32_e32 v1, s0 813; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 814; GFX6-NEXT: v_exp_f32_e32 v0, v0 815; GFX6-NEXT: ; return to shader part epilog 816; 817; GFX8-LABEL: v_pow_f32_sgpr_vgpr: 818; GFX8: ; %bb.0: 819; GFX8-NEXT: v_log_f32_e32 v1, s0 820; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 821; GFX8-NEXT: v_exp_f32_e32 v0, v0 822; GFX8-NEXT: ; return to shader part epilog 823; 824; GFX9-LABEL: v_pow_f32_sgpr_vgpr: 825; GFX9: ; %bb.0: 826; GFX9-NEXT: v_log_f32_e32 v1, s0 827; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 828; GFX9-NEXT: v_exp_f32_e32 v0, v0 829; GFX9-NEXT: ; return to shader part epilog 830; 831; GFX10-LABEL: v_pow_f32_sgpr_vgpr: 832; GFX10: ; %bb.0: 833; GFX10-NEXT: v_log_f32_e32 v1, s0 834; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 835; GFX10-NEXT: v_exp_f32_e32 v0, v0 836; GFX10-NEXT: ; return to shader part epilog 837; 838; GFX11-LABEL: v_pow_f32_sgpr_vgpr: 839; GFX11: ; %bb.0: 840; GFX11-NEXT: v_log_f32_e32 v1, s0 841; GFX11-NEXT: s_waitcnt_depctr 0xfff 842; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 843; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 844; GFX11-NEXT: v_exp_f32_e32 v0, v0 845; GFX11-NEXT: ; return to shader part epilog 846 %pow = call float @llvm.pow.f32(float %x, float %y) 847 ret float %pow 848} 849 850define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { 851; GFX6-LABEL: v_pow_f32_vgpr_sgpr: 852; GFX6: ; %bb.0: 853; GFX6-NEXT: v_log_f32_e32 v0, v0 854; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 855; GFX6-NEXT: v_exp_f32_e32 v0, v0 856; GFX6-NEXT: ; return to shader part epilog 857; 858; GFX8-LABEL: v_pow_f32_vgpr_sgpr: 859; GFX8: ; %bb.0: 860; GFX8-NEXT: v_log_f32_e32 v0, v0 861; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 862; GFX8-NEXT: v_exp_f32_e32 v0, v0 863; GFX8-NEXT: ; return to shader part epilog 864; 865; GFX9-LABEL: v_pow_f32_vgpr_sgpr: 866; GFX9: ; %bb.0: 867; GFX9-NEXT: v_log_f32_e32 v0, v0 868; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 869; GFX9-NEXT: v_exp_f32_e32 v0, v0 870; GFX9-NEXT: ; return to shader part epilog 871; 872; GFX10-LABEL: v_pow_f32_vgpr_sgpr: 873; GFX10: ; %bb.0: 874; GFX10-NEXT: v_log_f32_e32 v0, v0 875; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 876; GFX10-NEXT: v_exp_f32_e32 v0, v0 877; GFX10-NEXT: ; return to shader part epilog 878; 879; GFX11-LABEL: v_pow_f32_vgpr_sgpr: 880; GFX11: ; %bb.0: 881; GFX11-NEXT: v_log_f32_e32 v0, v0 882; GFX11-NEXT: s_waitcnt_depctr 0xfff 883; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0 884; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 885; GFX11-NEXT: v_exp_f32_e32 v0, v0 886; GFX11-NEXT: ; return to shader part epilog 887 %pow = call float @llvm.pow.f32(float %x, float %y) 888 ret float %pow 889} 890 891define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { 892; GFX6-LABEL: v_pow_f32_sgpr_sgpr: 893; GFX6: ; %bb.0: 894; GFX6-NEXT: v_log_f32_e32 v0, s0 895; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 896; GFX6-NEXT: v_exp_f32_e32 v0, v0 897; GFX6-NEXT: ; return to shader part epilog 898; 899; GFX8-LABEL: v_pow_f32_sgpr_sgpr: 900; GFX8: ; %bb.0: 901; GFX8-NEXT: v_log_f32_e32 v0, s0 902; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 903; GFX8-NEXT: v_exp_f32_e32 v0, v0 904; GFX8-NEXT: ; return to shader part epilog 905; 906; GFX9-LABEL: v_pow_f32_sgpr_sgpr: 907; GFX9: ; %bb.0: 908; GFX9-NEXT: v_log_f32_e32 v0, s0 909; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 910; GFX9-NEXT: v_exp_f32_e32 v0, v0 911; GFX9-NEXT: ; return to shader part epilog 912; 913; GFX10-LABEL: v_pow_f32_sgpr_sgpr: 914; GFX10: ; %bb.0: 915; GFX10-NEXT: v_log_f32_e32 v0, s0 916; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 917; GFX10-NEXT: v_exp_f32_e32 v0, v0 918; GFX10-NEXT: ; return to shader part epilog 919; 920; GFX11-LABEL: v_pow_f32_sgpr_sgpr: 921; GFX11: ; %bb.0: 922; GFX11-NEXT: v_log_f32_e32 v0, s0 923; GFX11-NEXT: s_waitcnt_depctr 0xfff 924; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0 925; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 926; GFX11-NEXT: v_exp_f32_e32 v0, v0 927; GFX11-NEXT: ; return to shader part epilog 928 %pow = call float @llvm.pow.f32(float %x, float %y) 929 ret float %pow 930} 931 932define float @v_pow_f32_fneg_lhs(float %x, float %y) { 933; GFX6-LABEL: v_pow_f32_fneg_lhs: 934; GFX6: ; %bb.0: 935; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 936; GFX6-NEXT: v_log_f32_e64 v0, -v0 937; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 938; GFX6-NEXT: v_exp_f32_e32 v0, v0 939; GFX6-NEXT: s_setpc_b64 s[30:31] 940; 941; GFX8-LABEL: v_pow_f32_fneg_lhs: 942; GFX8: ; %bb.0: 943; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 944; GFX8-NEXT: v_log_f32_e64 v0, -v0 945; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 946; GFX8-NEXT: v_exp_f32_e32 v0, v0 947; GFX8-NEXT: s_setpc_b64 s[30:31] 948; 949; GFX9-LABEL: v_pow_f32_fneg_lhs: 950; GFX9: ; %bb.0: 951; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 952; GFX9-NEXT: v_log_f32_e64 v0, -v0 953; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 954; GFX9-NEXT: v_exp_f32_e32 v0, v0 955; GFX9-NEXT: s_setpc_b64 s[30:31] 956; 957; GFX10-LABEL: v_pow_f32_fneg_lhs: 958; GFX10: ; %bb.0: 959; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 960; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 961; GFX10-NEXT: v_log_f32_e64 v0, -v0 962; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 963; GFX10-NEXT: v_exp_f32_e32 v0, v0 964; GFX10-NEXT: s_setpc_b64 s[30:31] 965; 966; GFX11-LABEL: v_pow_f32_fneg_lhs: 967; GFX11: ; %bb.0: 968; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 969; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 970; GFX11-NEXT: v_log_f32_e64 v0, -v0 971; GFX11-NEXT: s_waitcnt_depctr 0xfff 972; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 973; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 974; GFX11-NEXT: v_exp_f32_e32 v0, v0 975; GFX11-NEXT: s_setpc_b64 s[30:31] 976 %neg.x = fneg float %x 977 %pow = call float @llvm.pow.f32(float %neg.x, float %y) 978 ret float %pow 979} 980 981define float @v_pow_f32_fneg_rhs(float %x, float %y) { 982; GFX6-LABEL: v_pow_f32_fneg_rhs: 983; GFX6: ; %bb.0: 984; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 985; GFX6-NEXT: v_log_f32_e32 v0, v0 986; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 987; GFX6-NEXT: v_exp_f32_e32 v0, v0 988; GFX6-NEXT: s_setpc_b64 s[30:31] 989; 990; GFX8-LABEL: v_pow_f32_fneg_rhs: 991; GFX8: ; %bb.0: 992; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 993; GFX8-NEXT: v_log_f32_e32 v0, v0 994; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 995; GFX8-NEXT: v_exp_f32_e32 v0, v0 996; GFX8-NEXT: s_setpc_b64 s[30:31] 997; 998; GFX9-LABEL: v_pow_f32_fneg_rhs: 999; GFX9: ; %bb.0: 1000; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1001; GFX9-NEXT: v_log_f32_e32 v0, v0 1002; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 1003; GFX9-NEXT: v_exp_f32_e32 v0, v0 1004; GFX9-NEXT: s_setpc_b64 s[30:31] 1005; 1006; GFX10-LABEL: v_pow_f32_fneg_rhs: 1007; GFX10: ; %bb.0: 1008; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1009; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1010; GFX10-NEXT: v_log_f32_e32 v0, v0 1011; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 1012; GFX10-NEXT: v_exp_f32_e32 v0, v0 1013; GFX10-NEXT: s_setpc_b64 s[30:31] 1014; 1015; GFX11-LABEL: v_pow_f32_fneg_rhs: 1016; GFX11: ; %bb.0: 1017; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1018; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1019; GFX11-NEXT: v_log_f32_e32 v0, v0 1020; GFX11-NEXT: s_waitcnt_depctr 0xfff 1021; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, -v1 1022; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 1023; GFX11-NEXT: v_exp_f32_e32 v0, v0 1024; GFX11-NEXT: s_setpc_b64 s[30:31] 1025 %neg.y = fneg float %y 1026 %pow = call float @llvm.pow.f32(float %x, float %neg.y) 1027 ret float %pow 1028} 1029 1030declare half @llvm.pow.f16(half, half) 1031declare float @llvm.pow.f32(float, float) 1032declare double @llvm.pow.f64(double, double) 1033 1034declare half @llvm.fabs.f16(half) 1035declare float @llvm.fabs.f32(float) 1036 1037declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) 1038declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) 1039