1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s 6 7define float @v_pow_f32(float %x, float %y) { 8; GFX6-LABEL: v_pow_f32: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_log_f32_e32 v0, v0 12; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 13; GFX6-NEXT: v_exp_f32_e32 v0, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_pow_f32: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_log_f32_e32 v0, v0 20; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 21; GFX8-NEXT: v_exp_f32_e32 v0, v0 22; GFX8-NEXT: s_setpc_b64 s[30:31] 23; 24; GFX9-LABEL: v_pow_f32: 25; GFX9: ; %bb.0: 26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 27; GFX9-NEXT: v_log_f32_e32 v0, v0 28; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 29; GFX9-NEXT: v_exp_f32_e32 v0, v0 30; GFX9-NEXT: s_setpc_b64 s[30:31] 31; 32; GFX10-LABEL: v_pow_f32: 33; GFX10: ; %bb.0: 34; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 35; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 36; GFX10-NEXT: v_log_f32_e32 v0, v0 37; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 38; GFX10-NEXT: v_exp_f32_e32 v0, v0 39; GFX10-NEXT: s_setpc_b64 s[30:31] 40 %pow = call float @llvm.pow.f32(float %x, float %y) 41 ret float %pow 42} 43 44define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { 45; GFX6-LABEL: v_pow_v2f32: 46; GFX6: ; %bb.0: 47; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 48; GFX6-NEXT: v_log_f32_e32 v0, v0 49; GFX6-NEXT: v_log_f32_e32 v1, v1 50; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 51; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 52; GFX6-NEXT: v_exp_f32_e32 v0, v0 53; GFX6-NEXT: v_exp_f32_e32 v1, v1 54; GFX6-NEXT: s_setpc_b64 s[30:31] 55; 56; GFX8-LABEL: v_pow_v2f32: 57; GFX8: ; %bb.0: 58; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 59; GFX8-NEXT: v_log_f32_e32 v0, v0 60; GFX8-NEXT: v_log_f32_e32 v1, v1 61; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 62; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 63; GFX8-NEXT: v_exp_f32_e32 v0, v0 64; GFX8-NEXT: v_exp_f32_e32 v1, v1 65; GFX8-NEXT: s_setpc_b64 s[30:31] 66; 67; GFX9-LABEL: v_pow_v2f32: 68; GFX9: ; %bb.0: 69; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 70; GFX9-NEXT: v_log_f32_e32 v0, v0 71; GFX9-NEXT: v_log_f32_e32 v1, v1 72; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 73; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 74; GFX9-NEXT: v_exp_f32_e32 v0, v0 75; GFX9-NEXT: v_exp_f32_e32 v1, v1 76; GFX9-NEXT: s_setpc_b64 s[30:31] 77; 78; GFX10-LABEL: v_pow_v2f32: 79; GFX10: ; %bb.0: 80; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 81; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 82; GFX10-NEXT: v_log_f32_e32 v0, v0 83; GFX10-NEXT: v_log_f32_e32 v1, v1 84; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 85; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 86; GFX10-NEXT: v_exp_f32_e32 v0, v0 87; GFX10-NEXT: v_exp_f32_e32 v1, v1 88; GFX10-NEXT: s_setpc_b64 s[30:31] 89 %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) 90 ret <2 x float> %pow 91} 92 93define half @v_pow_f16(half %x, half %y) { 94; GFX6-LABEL: v_pow_f16: 95; GFX6: ; %bb.0: 96; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 97; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 98; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 99; GFX6-NEXT: v_log_f32_e32 v0, v0 100; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 101; GFX6-NEXT: v_exp_f32_e32 v0, v0 102; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 103; GFX6-NEXT: s_setpc_b64 s[30:31] 104; 105; GFX8-LABEL: v_pow_f16: 106; GFX8: ; %bb.0: 107; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 108; GFX8-NEXT: v_log_f16_e32 v0, v0 109; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 110; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 111; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 112; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 113; GFX8-NEXT: v_exp_f16_e32 v0, v0 114; GFX8-NEXT: s_setpc_b64 s[30:31] 115; 116; GFX9-LABEL: v_pow_f16: 117; GFX9: ; %bb.0: 118; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 119; GFX9-NEXT: v_log_f16_e32 v0, v0 120; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 121; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 122; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 123; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 124; GFX9-NEXT: v_exp_f16_e32 v0, v0 125; GFX9-NEXT: s_setpc_b64 s[30:31] 126; 127; GFX10-LABEL: v_pow_f16: 128; GFX10: ; %bb.0: 129; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 130; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 131; GFX10-NEXT: v_log_f16_e32 v0, v0 132; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 133; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 134; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 135; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 136; GFX10-NEXT: v_exp_f16_e32 v0, v0 137; GFX10-NEXT: s_setpc_b64 s[30:31] 138 %pow = call half @llvm.pow.f16(half %x, half %y) 139 ret half %pow 140} 141 142define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { 143; GFX6-LABEL: v_pow_v2f16: 144; GFX6: ; %bb.0: 145; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 146; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 147; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 148; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 149; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 150; GFX6-NEXT: v_log_f32_e32 v0, v0 151; GFX6-NEXT: v_log_f32_e32 v1, v1 152; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 153; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 154; GFX6-NEXT: v_exp_f32_e32 v0, v0 155; GFX6-NEXT: v_exp_f32_e32 v1, v1 156; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 157; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 158; GFX6-NEXT: s_setpc_b64 s[30:31] 159; 160; GFX8-LABEL: v_pow_v2f16: 161; GFX8: ; %bb.0: 162; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 163; GFX8-NEXT: v_log_f16_e32 v2, v0 164; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 165; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 166; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 167; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 168; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 169; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 170; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 171; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 172; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 173; GFX8-NEXT: v_mov_b32_e32 v2, 16 174; GFX8-NEXT: v_exp_f16_e32 v0, v0 175; GFX8-NEXT: v_exp_f16_e32 v1, v1 176; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 177; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 178; GFX8-NEXT: s_setpc_b64 s[30:31] 179; 180; GFX9-LABEL: v_pow_v2f16: 181; GFX9: ; %bb.0: 182; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 183; GFX9-NEXT: v_log_f16_e32 v2, v0 184; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 185; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 186; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 187; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 188; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 189; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 190; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 191; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 192; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 193; GFX9-NEXT: v_exp_f16_e32 v1, v2 194; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 195; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 196; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 197; GFX9-NEXT: s_setpc_b64 s[30:31] 198; 199; GFX10-LABEL: v_pow_v2f16: 200; GFX10: ; %bb.0: 201; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 202; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 203; GFX10-NEXT: v_log_f16_e32 v2, v0 204; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 205; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 206; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 207; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 208; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 209; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 210; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 211; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 212; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 213; GFX10-NEXT: v_exp_f16_e32 v1, v1 214; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 215; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 216; GFX10-NEXT: s_setpc_b64 s[30:31] 217 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y) 218 ret <2 x half> %pow 219} 220 221define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { 222; GFX6-LABEL: v_pow_v2f16_fneg_lhs: 223; GFX6: ; %bb.0: 224; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 225; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 226; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 227; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 228; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 229; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0 230; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 231; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 232; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 233; GFX6-NEXT: v_log_f32_e32 v1, v1 234; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 235; GFX6-NEXT: v_log_f32_e32 v0, v0 236; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v2 237; GFX6-NEXT: v_exp_f32_e32 v1, v1 238; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v3 239; GFX6-NEXT: v_exp_f32_e32 v2, v0 240; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v1 241; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2 242; GFX6-NEXT: s_setpc_b64 s[30:31] 243; 244; GFX8-LABEL: v_pow_v2f16_fneg_lhs: 245; GFX8: ; %bb.0: 246; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 247; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 248; GFX8-NEXT: v_log_f16_e32 v2, v0 249; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 250; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 251; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 252; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 253; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 254; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 255; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 256; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 257; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 258; GFX8-NEXT: v_mov_b32_e32 v2, 16 259; GFX8-NEXT: v_exp_f16_e32 v0, v0 260; GFX8-NEXT: v_exp_f16_e32 v1, v1 261; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 262; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 263; GFX8-NEXT: s_setpc_b64 s[30:31] 264; 265; GFX9-LABEL: v_pow_v2f16_fneg_lhs: 266; GFX9: ; %bb.0: 267; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 268; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 269; GFX9-NEXT: v_log_f16_e32 v2, v0 270; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 271; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 272; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 273; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 274; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 275; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 276; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 277; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 278; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 279; GFX9-NEXT: v_exp_f16_e32 v1, v2 280; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 281; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 282; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 283; GFX9-NEXT: s_setpc_b64 s[30:31] 284; 285; GFX10-LABEL: v_pow_v2f16_fneg_lhs: 286; GFX10: ; %bb.0: 287; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 288; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 289; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 290; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 291; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 292; GFX10-NEXT: v_log_f16_e32 v2, v0 293; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 294; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 295; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 296; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 297; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 298; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 299; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 300; GFX10-NEXT: v_exp_f16_e32 v1, v1 301; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 302; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 303; GFX10-NEXT: s_setpc_b64 s[30:31] 304 %x.fneg = fneg <2 x half> %x 305 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y) 306 ret <2 x half> %pow 307} 308 309define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { 310; GFX6-LABEL: v_pow_v2f16_fneg_rhs: 311; GFX6: ; %bb.0: 312; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 313; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 314; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 315; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 316; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 317; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 318; GFX6-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 319; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2 320; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 321; GFX6-NEXT: v_log_f32_e32 v0, v0 322; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 323; GFX6-NEXT: v_log_f32_e32 v1, v1 324; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 325; GFX6-NEXT: v_exp_f32_e32 v0, v0 326; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 327; GFX6-NEXT: v_exp_f32_e32 v1, v1 328; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 329; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 330; GFX6-NEXT: s_setpc_b64 s[30:31] 331; 332; GFX8-LABEL: v_pow_v2f16_fneg_rhs: 333; GFX8: ; %bb.0: 334; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 335; GFX8-NEXT: v_log_f16_e32 v2, v0 336; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 337; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 338; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 339; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 340; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 341; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 342; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 343; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 344; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 345; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 346; GFX8-NEXT: v_mov_b32_e32 v2, 16 347; GFX8-NEXT: v_exp_f16_e32 v0, v0 348; GFX8-NEXT: v_exp_f16_e32 v1, v1 349; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 350; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 351; GFX8-NEXT: s_setpc_b64 s[30:31] 352; 353; GFX9-LABEL: v_pow_v2f16_fneg_rhs: 354; GFX9: ; %bb.0: 355; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 356; GFX9-NEXT: v_log_f16_e32 v2, v0 357; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 358; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 359; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 360; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 361; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 362; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 363; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 364; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 365; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 366; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 367; GFX9-NEXT: v_exp_f16_e32 v1, v2 368; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 369; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 370; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 371; GFX9-NEXT: s_setpc_b64 s[30:31] 372; 373; GFX10-LABEL: v_pow_v2f16_fneg_rhs: 374; GFX10: ; %bb.0: 375; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 376; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 377; GFX10-NEXT: v_log_f16_e32 v2, v0 378; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 379; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 380; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 381; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 382; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 383; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 384; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 385; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 386; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 387; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 388; GFX10-NEXT: v_exp_f16_e32 v1, v1 389; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 390; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 391; GFX10-NEXT: s_setpc_b64 s[30:31] 392 %y.fneg = fneg <2 x half> %y 393 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg) 394 ret <2 x half> %pow 395} 396 397define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { 398; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs: 399; GFX6: ; %bb.0: 400; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 401; GFX6-NEXT: v_mov_b32_e32 v4, 0xffff 402; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 403; GFX6-NEXT: v_and_b32_e32 v0, v0, v4 404; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 405; GFX6-NEXT: s_mov_b32 s4, 0x80008000 406; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 407; GFX6-NEXT: v_and_b32_e32 v2, v2, v4 408; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0 409; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 410; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 411; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 412; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 413; GFX6-NEXT: v_xor_b32_e32 v1, s4, v1 414; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 415; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 416; GFX6-NEXT: v_log_f32_e32 v0, v0 417; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 418; GFX6-NEXT: v_log_f32_e32 v2, v2 419; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 420; GFX6-NEXT: v_exp_f32_e32 v0, v0 421; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 422; GFX6-NEXT: v_exp_f32_e32 v1, v1 423; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 424; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 425; GFX6-NEXT: s_setpc_b64 s[30:31] 426; 427; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs: 428; GFX8: ; %bb.0: 429; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 430; GFX8-NEXT: s_mov_b32 s4, 0x80008000 431; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0 432; GFX8-NEXT: v_log_f16_e32 v2, v0 433; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 434; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1 435; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 436; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 437; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 438; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 439; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 440; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 441; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 442; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 443; GFX8-NEXT: v_mov_b32_e32 v2, 16 444; GFX8-NEXT: v_exp_f16_e32 v0, v0 445; GFX8-NEXT: v_exp_f16_e32 v1, v1 446; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 447; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 448; GFX8-NEXT: s_setpc_b64 s[30:31] 449; 450; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs: 451; GFX9: ; %bb.0: 452; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 453; GFX9-NEXT: s_mov_b32 s4, 0x80008000 454; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0 455; GFX9-NEXT: v_log_f16_e32 v2, v0 456; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 457; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 458; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 459; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 460; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 461; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 462; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 463; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 464; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 465; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 466; GFX9-NEXT: v_exp_f16_e32 v1, v2 467; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 468; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 469; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 470; GFX9-NEXT: s_setpc_b64 s[30:31] 471; 472; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: 473; GFX10: ; %bb.0: 474; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 475; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 476; GFX10-NEXT: s_mov_b32 s4, 0x80008000 477; GFX10-NEXT: v_xor_b32_e32 v0, s4, v0 478; GFX10-NEXT: v_xor_b32_e32 v1, s4, v1 479; GFX10-NEXT: v_log_f16_e32 v2, v0 480; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 481; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 482; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 483; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 484; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 485; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 486; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 487; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 488; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 489; GFX10-NEXT: v_exp_f16_e32 v1, v1 490; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 491; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 492; GFX10-NEXT: s_setpc_b64 s[30:31] 493 %x.fneg = fneg <2 x half> %x 494 %y.fneg = fneg <2 x half> %y 495 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg) 496 ret <2 x half> %pow 497} 498 499; FIXME 500; define double @v_pow_f64(double %x, double %y) { 501; %pow = call double @llvm.pow.f64(double %x, double %y) 502; ret double %pow 503; } 504 505define float @v_pow_f32_fabs_lhs(float %x, float %y) { 506; GFX6-LABEL: v_pow_f32_fabs_lhs: 507; GFX6: ; %bb.0: 508; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 509; GFX6-NEXT: v_log_f32_e64 v0, |v0| 510; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 511; GFX6-NEXT: v_exp_f32_e32 v0, v0 512; GFX6-NEXT: s_setpc_b64 s[30:31] 513; 514; GFX8-LABEL: v_pow_f32_fabs_lhs: 515; GFX8: ; %bb.0: 516; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 517; GFX8-NEXT: v_log_f32_e64 v0, |v0| 518; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 519; GFX8-NEXT: v_exp_f32_e32 v0, v0 520; GFX8-NEXT: s_setpc_b64 s[30:31] 521; 522; GFX9-LABEL: v_pow_f32_fabs_lhs: 523; GFX9: ; %bb.0: 524; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 525; GFX9-NEXT: v_log_f32_e64 v0, |v0| 526; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 527; GFX9-NEXT: v_exp_f32_e32 v0, v0 528; GFX9-NEXT: s_setpc_b64 s[30:31] 529; 530; GFX10-LABEL: v_pow_f32_fabs_lhs: 531; GFX10: ; %bb.0: 532; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 533; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 534; GFX10-NEXT: v_log_f32_e64 v0, |v0| 535; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 536; GFX10-NEXT: v_exp_f32_e32 v0, v0 537; GFX10-NEXT: s_setpc_b64 s[30:31] 538 %fabs.x = call float @llvm.fabs.f32(float %x) 539 %pow = call float @llvm.pow.f32(float %fabs.x, float %y) 540 ret float %pow 541} 542 543define float @v_pow_f32_fabs_rhs(float %x, float %y) { 544; GFX6-LABEL: v_pow_f32_fabs_rhs: 545; GFX6: ; %bb.0: 546; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 547; GFX6-NEXT: v_log_f32_e32 v0, v0 548; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 549; GFX6-NEXT: v_exp_f32_e32 v0, v0 550; GFX6-NEXT: s_setpc_b64 s[30:31] 551; 552; GFX8-LABEL: v_pow_f32_fabs_rhs: 553; GFX8: ; %bb.0: 554; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 555; GFX8-NEXT: v_log_f32_e32 v0, v0 556; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 557; GFX8-NEXT: v_exp_f32_e32 v0, v0 558; GFX8-NEXT: s_setpc_b64 s[30:31] 559; 560; GFX9-LABEL: v_pow_f32_fabs_rhs: 561; GFX9: ; %bb.0: 562; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 563; GFX9-NEXT: v_log_f32_e32 v0, v0 564; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 565; GFX9-NEXT: v_exp_f32_e32 v0, v0 566; GFX9-NEXT: s_setpc_b64 s[30:31] 567; 568; GFX10-LABEL: v_pow_f32_fabs_rhs: 569; GFX10: ; %bb.0: 570; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 571; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 572; GFX10-NEXT: v_log_f32_e32 v0, v0 573; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 574; GFX10-NEXT: v_exp_f32_e32 v0, v0 575; GFX10-NEXT: s_setpc_b64 s[30:31] 576 %fabs.y = call float @llvm.fabs.f32(float %y) 577 %pow = call float @llvm.pow.f32(float %x, float %fabs.y) 578 ret float %pow 579} 580 581define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { 582; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: 583; GFX6: ; %bb.0: 584; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 585; GFX6-NEXT: v_log_f32_e64 v0, |v0| 586; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 587; GFX6-NEXT: v_exp_f32_e32 v0, v0 588; GFX6-NEXT: s_setpc_b64 s[30:31] 589; 590; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: 591; GFX8: ; %bb.0: 592; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 593; GFX8-NEXT: v_log_f32_e64 v0, |v0| 594; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 595; GFX8-NEXT: v_exp_f32_e32 v0, v0 596; GFX8-NEXT: s_setpc_b64 s[30:31] 597; 598; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: 599; GFX9: ; %bb.0: 600; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 601; GFX9-NEXT: v_log_f32_e64 v0, |v0| 602; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 603; GFX9-NEXT: v_exp_f32_e32 v0, v0 604; GFX9-NEXT: s_setpc_b64 s[30:31] 605; 606; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: 607; GFX10: ; %bb.0: 608; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 609; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 610; GFX10-NEXT: v_log_f32_e64 v0, |v0| 611; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 612; GFX10-NEXT: v_exp_f32_e32 v0, v0 613; GFX10-NEXT: s_setpc_b64 s[30:31] 614 %fabs.x = call float @llvm.fabs.f32(float %x) 615 %fabs.y = call float @llvm.fabs.f32(float %y) 616 %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) 617 ret float %pow 618} 619 620define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { 621; GFX6-LABEL: v_pow_f32_sgpr_vgpr: 622; GFX6: ; %bb.0: 623; GFX6-NEXT: v_log_f32_e32 v1, s0 624; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 625; GFX6-NEXT: v_exp_f32_e32 v0, v0 626; GFX6-NEXT: ; return to shader part epilog 627; 628; GFX8-LABEL: v_pow_f32_sgpr_vgpr: 629; GFX8: ; %bb.0: 630; GFX8-NEXT: v_log_f32_e32 v1, s0 631; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 632; GFX8-NEXT: v_exp_f32_e32 v0, v0 633; GFX8-NEXT: ; return to shader part epilog 634; 635; GFX9-LABEL: v_pow_f32_sgpr_vgpr: 636; GFX9: ; %bb.0: 637; GFX9-NEXT: v_log_f32_e32 v1, s0 638; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 639; GFX9-NEXT: v_exp_f32_e32 v0, v0 640; GFX9-NEXT: ; return to shader part epilog 641; 642; GFX10-LABEL: v_pow_f32_sgpr_vgpr: 643; GFX10: ; %bb.0: 644; GFX10-NEXT: v_log_f32_e32 v1, s0 645; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 646; GFX10-NEXT: v_exp_f32_e32 v0, v0 647; GFX10-NEXT: ; return to shader part epilog 648 %pow = call float @llvm.pow.f32(float %x, float %y) 649 ret float %pow 650} 651 652define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { 653; GFX6-LABEL: v_pow_f32_vgpr_sgpr: 654; GFX6: ; %bb.0: 655; GFX6-NEXT: v_log_f32_e32 v0, v0 656; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 657; GFX6-NEXT: v_exp_f32_e32 v0, v0 658; GFX6-NEXT: ; return to shader part epilog 659; 660; GFX8-LABEL: v_pow_f32_vgpr_sgpr: 661; GFX8: ; %bb.0: 662; GFX8-NEXT: v_log_f32_e32 v0, v0 663; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 664; GFX8-NEXT: v_exp_f32_e32 v0, v0 665; GFX8-NEXT: ; return to shader part epilog 666; 667; GFX9-LABEL: v_pow_f32_vgpr_sgpr: 668; GFX9: ; %bb.0: 669; GFX9-NEXT: v_log_f32_e32 v0, v0 670; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 671; GFX9-NEXT: v_exp_f32_e32 v0, v0 672; GFX9-NEXT: ; return to shader part epilog 673; 674; GFX10-LABEL: v_pow_f32_vgpr_sgpr: 675; GFX10: ; %bb.0: 676; GFX10-NEXT: v_log_f32_e32 v0, v0 677; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 678; GFX10-NEXT: v_exp_f32_e32 v0, v0 679; GFX10-NEXT: ; return to shader part epilog 680 %pow = call float @llvm.pow.f32(float %x, float %y) 681 ret float %pow 682} 683 684define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { 685; GFX6-LABEL: v_pow_f32_sgpr_sgpr: 686; GFX6: ; %bb.0: 687; GFX6-NEXT: v_log_f32_e32 v0, s0 688; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 689; GFX6-NEXT: v_exp_f32_e32 v0, v0 690; GFX6-NEXT: ; return to shader part epilog 691; 692; GFX8-LABEL: v_pow_f32_sgpr_sgpr: 693; GFX8: ; %bb.0: 694; GFX8-NEXT: v_log_f32_e32 v0, s0 695; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 696; GFX8-NEXT: v_exp_f32_e32 v0, v0 697; GFX8-NEXT: ; return to shader part epilog 698; 699; GFX9-LABEL: v_pow_f32_sgpr_sgpr: 700; GFX9: ; %bb.0: 701; GFX9-NEXT: v_log_f32_e32 v0, s0 702; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 703; GFX9-NEXT: v_exp_f32_e32 v0, v0 704; GFX9-NEXT: ; return to shader part epilog 705; 706; GFX10-LABEL: v_pow_f32_sgpr_sgpr: 707; GFX10: ; %bb.0: 708; GFX10-NEXT: v_log_f32_e32 v0, s0 709; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 710; GFX10-NEXT: v_exp_f32_e32 v0, v0 711; GFX10-NEXT: ; return to shader part epilog 712 %pow = call float @llvm.pow.f32(float %x, float %y) 713 ret float %pow 714} 715 716define float @v_pow_f32_fneg_lhs(float %x, float %y) { 717; GFX6-LABEL: v_pow_f32_fneg_lhs: 718; GFX6: ; %bb.0: 719; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 720; GFX6-NEXT: v_log_f32_e64 v0, -v0 721; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 722; GFX6-NEXT: v_exp_f32_e32 v0, v0 723; GFX6-NEXT: s_setpc_b64 s[30:31] 724; 725; GFX8-LABEL: v_pow_f32_fneg_lhs: 726; GFX8: ; %bb.0: 727; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 728; GFX8-NEXT: v_log_f32_e64 v0, -v0 729; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 730; GFX8-NEXT: v_exp_f32_e32 v0, v0 731; GFX8-NEXT: s_setpc_b64 s[30:31] 732; 733; GFX9-LABEL: v_pow_f32_fneg_lhs: 734; GFX9: ; %bb.0: 735; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 736; GFX9-NEXT: v_log_f32_e64 v0, -v0 737; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 738; GFX9-NEXT: v_exp_f32_e32 v0, v0 739; GFX9-NEXT: s_setpc_b64 s[30:31] 740; 741; GFX10-LABEL: v_pow_f32_fneg_lhs: 742; GFX10: ; %bb.0: 743; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 744; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 745; GFX10-NEXT: v_log_f32_e64 v0, -v0 746; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 747; GFX10-NEXT: v_exp_f32_e32 v0, v0 748; GFX10-NEXT: s_setpc_b64 s[30:31] 749 %neg.x = fneg float %x 750 %pow = call float @llvm.pow.f32(float %neg.x, float %y) 751 ret float %pow 752} 753 754define float @v_pow_f32_fneg_rhs(float %x, float %y) { 755; GFX6-LABEL: v_pow_f32_fneg_rhs: 756; GFX6: ; %bb.0: 757; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 758; GFX6-NEXT: v_log_f32_e32 v0, v0 759; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 760; GFX6-NEXT: v_exp_f32_e32 v0, v0 761; GFX6-NEXT: s_setpc_b64 s[30:31] 762; 763; GFX8-LABEL: v_pow_f32_fneg_rhs: 764; GFX8: ; %bb.0: 765; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 766; GFX8-NEXT: v_log_f32_e32 v0, v0 767; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 768; GFX8-NEXT: v_exp_f32_e32 v0, v0 769; GFX8-NEXT: s_setpc_b64 s[30:31] 770; 771; GFX9-LABEL: v_pow_f32_fneg_rhs: 772; GFX9: ; %bb.0: 773; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 774; GFX9-NEXT: v_log_f32_e32 v0, v0 775; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 776; GFX9-NEXT: v_exp_f32_e32 v0, v0 777; GFX9-NEXT: s_setpc_b64 s[30:31] 778; 779; GFX10-LABEL: v_pow_f32_fneg_rhs: 780; GFX10: ; %bb.0: 781; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 782; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 783; GFX10-NEXT: v_log_f32_e32 v0, v0 784; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 785; GFX10-NEXT: v_exp_f32_e32 v0, v0 786; GFX10-NEXT: s_setpc_b64 s[30:31] 787 %neg.y = fneg float %y 788 %pow = call float @llvm.pow.f32(float %x, float %neg.y) 789 ret float %pow 790} 791 792declare half @llvm.pow.f16(half, half) 793declare float @llvm.pow.f32(float, float) 794declare double @llvm.pow.f64(double, double) 795 796declare half @llvm.fabs.f16(half) 797declare float @llvm.fabs.f32(float) 798 799declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) 800declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) 801