1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s 6 7define float @v_pow_f32(float %x, float %y) { 8; GFX6-LABEL: v_pow_f32: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_log_f32_e32 v0, v0 12; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 13; GFX6-NEXT: v_exp_f32_e32 v0, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_pow_f32: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_log_f32_e32 v0, v0 20; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 21; GFX8-NEXT: v_exp_f32_e32 v0, v0 22; GFX8-NEXT: s_setpc_b64 s[30:31] 23; 24; GFX9-LABEL: v_pow_f32: 25; GFX9: ; %bb.0: 26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 27; GFX9-NEXT: v_log_f32_e32 v0, v0 28; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 29; GFX9-NEXT: v_exp_f32_e32 v0, v0 30; GFX9-NEXT: s_setpc_b64 s[30:31] 31; 32; GFX10-LABEL: v_pow_f32: 33; GFX10: ; %bb.0: 34; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 35; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 36; GFX10-NEXT: v_log_f32_e32 v0, v0 37; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 38; GFX10-NEXT: v_exp_f32_e32 v0, v0 39; GFX10-NEXT: s_setpc_b64 s[30:31] 40 %pow = call float @llvm.pow.f32(float %x, float %y) 41 ret float %pow 42} 43 44define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { 45; GFX6-LABEL: v_pow_v2f32: 46; GFX6: ; %bb.0: 47; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 48; GFX6-NEXT: v_log_f32_e32 v0, v0 49; GFX6-NEXT: v_log_f32_e32 v1, v1 50; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 51; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 52; GFX6-NEXT: v_exp_f32_e32 v0, v0 53; GFX6-NEXT: v_exp_f32_e32 v1, v1 54; GFX6-NEXT: s_setpc_b64 s[30:31] 55; 56; GFX8-LABEL: v_pow_v2f32: 57; GFX8: ; %bb.0: 58; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 59; GFX8-NEXT: v_log_f32_e32 v0, v0 60; GFX8-NEXT: v_log_f32_e32 v1, v1 61; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 62; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 63; GFX8-NEXT: v_exp_f32_e32 v0, v0 64; GFX8-NEXT: v_exp_f32_e32 v1, v1 65; GFX8-NEXT: s_setpc_b64 s[30:31] 66; 67; GFX9-LABEL: v_pow_v2f32: 68; GFX9: ; %bb.0: 69; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 70; GFX9-NEXT: v_log_f32_e32 v0, v0 71; GFX9-NEXT: v_log_f32_e32 v1, v1 72; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 73; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 74; GFX9-NEXT: v_exp_f32_e32 v0, v0 75; GFX9-NEXT: v_exp_f32_e32 v1, v1 76; GFX9-NEXT: s_setpc_b64 s[30:31] 77; 78; GFX10-LABEL: v_pow_v2f32: 79; GFX10: ; %bb.0: 80; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 81; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 82; GFX10-NEXT: v_log_f32_e32 v0, v0 83; GFX10-NEXT: v_log_f32_e32 v1, v1 84; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 85; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 86; GFX10-NEXT: v_exp_f32_e32 v0, v0 87; GFX10-NEXT: v_exp_f32_e32 v1, v1 88; GFX10-NEXT: s_setpc_b64 s[30:31] 89 %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) 90 ret <2 x float> %pow 91} 92 93define half @v_pow_f16(half %x, half %y) { 94; GFX6-LABEL: v_pow_f16: 95; GFX6: ; %bb.0: 96; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 97; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 98; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 99; GFX6-NEXT: v_log_f32_e32 v0, v0 100; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 101; GFX6-NEXT: v_exp_f32_e32 v0, v0 102; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 103; GFX6-NEXT: s_setpc_b64 s[30:31] 104; 105; GFX8-LABEL: v_pow_f16: 106; GFX8: ; %bb.0: 107; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 108; GFX8-NEXT: v_log_f16_e32 v0, v0 109; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 110; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 111; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 112; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 113; GFX8-NEXT: v_exp_f16_e32 v0, v0 114; GFX8-NEXT: s_setpc_b64 s[30:31] 115; 116; GFX9-LABEL: v_pow_f16: 117; GFX9: ; %bb.0: 118; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 119; GFX9-NEXT: v_log_f16_e32 v0, v0 120; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 121; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 122; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 123; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 124; GFX9-NEXT: v_exp_f16_e32 v0, v0 125; GFX9-NEXT: s_setpc_b64 s[30:31] 126; 127; GFX10-LABEL: v_pow_f16: 128; GFX10: ; %bb.0: 129; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 130; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 131; GFX10-NEXT: v_log_f16_e32 v0, v0 132; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 133; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 134; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 135; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 136; GFX10-NEXT: v_exp_f16_e32 v0, v0 137; GFX10-NEXT: s_setpc_b64 s[30:31] 138 %pow = call half @llvm.pow.f16(half %x, half %y) 139 ret half %pow 140} 141 142define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { 143; GFX6-LABEL: v_pow_v2f16: 144; GFX6: ; %bb.0: 145; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 146; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 147; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 148; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 149; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 150; GFX6-NEXT: v_log_f32_e32 v0, v0 151; GFX6-NEXT: v_log_f32_e32 v1, v1 152; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 153; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 154; GFX6-NEXT: v_exp_f32_e32 v0, v0 155; GFX6-NEXT: v_exp_f32_e32 v1, v1 156; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 157; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 158; GFX6-NEXT: s_setpc_b64 s[30:31] 159; 160; GFX8-LABEL: v_pow_v2f16: 161; GFX8: ; %bb.0: 162; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 163; GFX8-NEXT: v_log_f16_e32 v2, v0 164; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 165; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 166; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 167; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 168; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 169; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 170; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 171; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 172; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 173; GFX8-NEXT: v_mov_b32_e32 v2, 16 174; GFX8-NEXT: v_exp_f16_e32 v0, v0 175; GFX8-NEXT: v_exp_f16_e32 v1, v1 176; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 177; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 178; GFX8-NEXT: s_setpc_b64 s[30:31] 179; 180; GFX9-LABEL: v_pow_v2f16: 181; GFX9: ; %bb.0: 182; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 183; GFX9-NEXT: v_log_f16_e32 v2, v0 184; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 185; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 186; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 187; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 188; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 189; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 190; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 191; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 192; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 193; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 194; GFX9-NEXT: v_exp_f16_e32 v1, v1 195; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 196; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 197; GFX9-NEXT: s_setpc_b64 s[30:31] 198; 199; GFX10-LABEL: v_pow_v2f16: 200; GFX10: ; %bb.0: 201; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 202; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 203; GFX10-NEXT: v_log_f16_e32 v2, v0 204; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 205; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 206; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 207; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 208; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 209; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 210; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 211; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 212; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 213; GFX10-NEXT: v_exp_f16_e32 v1, v1 214; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 215; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 216; GFX10-NEXT: s_setpc_b64 s[30:31] 217 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y) 218 ret <2 x half> %pow 219} 220 221define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { 222; GFX6-LABEL: v_pow_v2f16_fneg_lhs: 223; GFX6: ; %bb.0: 224; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 225; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 226; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 227; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 228; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 229; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0 230; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 231; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 232; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 233; GFX6-NEXT: v_log_f32_e32 v1, v1 234; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 235; GFX6-NEXT: v_log_f32_e32 v0, v0 236; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v2 237; GFX6-NEXT: v_exp_f32_e32 v1, v1 238; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v3 239; GFX6-NEXT: v_exp_f32_e32 v2, v0 240; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v1 241; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v2 242; GFX6-NEXT: s_setpc_b64 s[30:31] 243; 244; GFX8-LABEL: v_pow_v2f16_fneg_lhs: 245; GFX8: ; %bb.0: 246; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 247; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 248; GFX8-NEXT: v_log_f16_e32 v2, v0 249; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 250; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 251; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 252; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 253; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 254; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 255; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 256; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 257; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 258; GFX8-NEXT: v_mov_b32_e32 v2, 16 259; GFX8-NEXT: v_exp_f16_e32 v0, v0 260; GFX8-NEXT: v_exp_f16_e32 v1, v1 261; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 262; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 263; GFX8-NEXT: s_setpc_b64 s[30:31] 264; 265; GFX9-LABEL: v_pow_v2f16_fneg_lhs: 266; GFX9: ; %bb.0: 267; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 268; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 269; GFX9-NEXT: v_log_f16_e32 v2, v0 270; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 271; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 272; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 273; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 274; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 275; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 276; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 277; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 278; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 279; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 280; GFX9-NEXT: v_exp_f16_e32 v1, v1 281; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 282; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 283; GFX9-NEXT: s_setpc_b64 s[30:31] 284; 285; GFX10-LABEL: v_pow_v2f16_fneg_lhs: 286; GFX10: ; %bb.0: 287; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 288; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 289; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 290; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 291; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 292; GFX10-NEXT: v_log_f16_e32 v2, v0 293; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 294; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 295; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 296; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 297; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 298; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 299; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 300; GFX10-NEXT: v_exp_f16_e32 v1, v1 301; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 302; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 303; GFX10-NEXT: s_setpc_b64 s[30:31] 304 %x.fneg = fneg <2 x half> %x 305 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y) 306 ret <2 x half> %pow 307} 308 309define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { 310; GFX6-LABEL: v_pow_v2f16_fneg_rhs: 311; GFX6: ; %bb.0: 312; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 313; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 314; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 315; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 316; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 317; GFX6-NEXT: v_or_b32_e32 v2, v3, v2 318; GFX6-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 319; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2 320; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 321; GFX6-NEXT: v_log_f32_e32 v0, v0 322; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 323; GFX6-NEXT: v_log_f32_e32 v1, v1 324; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 325; GFX6-NEXT: v_exp_f32_e32 v0, v0 326; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 327; GFX6-NEXT: v_exp_f32_e32 v1, v1 328; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 329; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 330; GFX6-NEXT: s_setpc_b64 s[30:31] 331; 332; GFX8-LABEL: v_pow_v2f16_fneg_rhs: 333; GFX8: ; %bb.0: 334; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 335; GFX8-NEXT: v_log_f16_e32 v2, v0 336; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 337; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 338; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 339; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 340; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 341; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 342; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 343; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 344; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 345; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 346; GFX8-NEXT: v_mov_b32_e32 v2, 16 347; GFX8-NEXT: v_exp_f16_e32 v0, v0 348; GFX8-NEXT: v_exp_f16_e32 v1, v1 349; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 350; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 351; GFX8-NEXT: s_setpc_b64 s[30:31] 352; 353; GFX9-LABEL: v_pow_v2f16_fneg_rhs: 354; GFX9: ; %bb.0: 355; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 356; GFX9-NEXT: v_log_f16_e32 v2, v0 357; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 358; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 359; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 360; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 361; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 362; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 363; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 364; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 365; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 366; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 367; GFX9-NEXT: v_exp_f16_e32 v1, v2 368; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 369; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 370; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 371; GFX9-NEXT: s_setpc_b64 s[30:31] 372; 373; GFX10-LABEL: v_pow_v2f16_fneg_rhs: 374; GFX10: ; %bb.0: 375; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 376; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 377; GFX10-NEXT: v_log_f16_e32 v2, v0 378; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 379; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 380; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 381; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 382; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 383; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 384; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 385; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 386; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 387; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 388; GFX10-NEXT: v_exp_f16_e32 v1, v1 389; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 390; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 391; GFX10-NEXT: s_setpc_b64 s[30:31] 392 %y.fneg = fneg <2 x half> %y 393 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg) 394 ret <2 x half> %pow 395} 396 397define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { 398; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs: 399; GFX6: ; %bb.0: 400; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 401; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 402; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 403; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 404; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3 405; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 406; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 407; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 408; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 409; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 410; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 411; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 412; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 413; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 414; GFX6-NEXT: v_log_f32_e32 v0, v0 415; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 416; GFX6-NEXT: v_log_f32_e32 v2, v2 417; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 418; GFX6-NEXT: v_exp_f32_e32 v0, v0 419; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 420; GFX6-NEXT: v_exp_f32_e32 v1, v1 421; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 422; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 423; GFX6-NEXT: s_setpc_b64 s[30:31] 424; 425; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs: 426; GFX8: ; %bb.0: 427; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 428; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 429; GFX8-NEXT: v_log_f16_e32 v2, v0 430; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 431; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 432; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 433; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 434; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 435; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 436; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 437; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 438; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 439; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 440; GFX8-NEXT: v_mov_b32_e32 v2, 16 441; GFX8-NEXT: v_exp_f16_e32 v0, v0 442; GFX8-NEXT: v_exp_f16_e32 v1, v1 443; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 444; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 445; GFX8-NEXT: s_setpc_b64 s[30:31] 446; 447; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs: 448; GFX9: ; %bb.0: 449; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 450; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 451; GFX9-NEXT: v_log_f16_e32 v2, v0 452; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 453; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 454; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 455; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 456; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 457; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 458; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 459; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 460; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 461; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 462; GFX9-NEXT: v_exp_f16_e32 v1, v2 463; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 464; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 465; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 466; GFX9-NEXT: s_setpc_b64 s[30:31] 467; 468; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: 469; GFX10: ; %bb.0: 470; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 471; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 472; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 473; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 474; GFX10-NEXT: v_log_f16_e32 v2, v0 475; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 476; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 477; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 478; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 479; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 480; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 481; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 482; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 483; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 484; GFX10-NEXT: v_exp_f16_e32 v1, v1 485; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 486; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 487; GFX10-NEXT: s_setpc_b64 s[30:31] 488 %x.fneg = fneg <2 x half> %x 489 %y.fneg = fneg <2 x half> %y 490 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg) 491 ret <2 x half> %pow 492} 493 494; FIXME 495; define double @v_pow_f64(double %x, double %y) { 496; %pow = call double @llvm.pow.f64(double %x, double %y) 497; ret double %pow 498; } 499 500define float @v_pow_f32_fabs_lhs(float %x, float %y) { 501; GFX6-LABEL: v_pow_f32_fabs_lhs: 502; GFX6: ; %bb.0: 503; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 504; GFX6-NEXT: v_log_f32_e64 v0, |v0| 505; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 506; GFX6-NEXT: v_exp_f32_e32 v0, v0 507; GFX6-NEXT: s_setpc_b64 s[30:31] 508; 509; GFX8-LABEL: v_pow_f32_fabs_lhs: 510; GFX8: ; %bb.0: 511; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 512; GFX8-NEXT: v_log_f32_e64 v0, |v0| 513; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 514; GFX8-NEXT: v_exp_f32_e32 v0, v0 515; GFX8-NEXT: s_setpc_b64 s[30:31] 516; 517; GFX9-LABEL: v_pow_f32_fabs_lhs: 518; GFX9: ; %bb.0: 519; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 520; GFX9-NEXT: v_log_f32_e64 v0, |v0| 521; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 522; GFX9-NEXT: v_exp_f32_e32 v0, v0 523; GFX9-NEXT: s_setpc_b64 s[30:31] 524; 525; GFX10-LABEL: v_pow_f32_fabs_lhs: 526; GFX10: ; %bb.0: 527; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 528; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 529; GFX10-NEXT: v_log_f32_e64 v0, |v0| 530; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 531; GFX10-NEXT: v_exp_f32_e32 v0, v0 532; GFX10-NEXT: s_setpc_b64 s[30:31] 533 %fabs.x = call float @llvm.fabs.f32(float %x) 534 %pow = call float @llvm.pow.f32(float %fabs.x, float %y) 535 ret float %pow 536} 537 538define float @v_pow_f32_fabs_rhs(float %x, float %y) { 539; GFX6-LABEL: v_pow_f32_fabs_rhs: 540; GFX6: ; %bb.0: 541; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 542; GFX6-NEXT: v_log_f32_e32 v0, v0 543; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 544; GFX6-NEXT: v_exp_f32_e32 v0, v0 545; GFX6-NEXT: s_setpc_b64 s[30:31] 546; 547; GFX8-LABEL: v_pow_f32_fabs_rhs: 548; GFX8: ; %bb.0: 549; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 550; GFX8-NEXT: v_log_f32_e32 v0, v0 551; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 552; GFX8-NEXT: v_exp_f32_e32 v0, v0 553; GFX8-NEXT: s_setpc_b64 s[30:31] 554; 555; GFX9-LABEL: v_pow_f32_fabs_rhs: 556; GFX9: ; %bb.0: 557; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 558; GFX9-NEXT: v_log_f32_e32 v0, v0 559; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 560; GFX9-NEXT: v_exp_f32_e32 v0, v0 561; GFX9-NEXT: s_setpc_b64 s[30:31] 562; 563; GFX10-LABEL: v_pow_f32_fabs_rhs: 564; GFX10: ; %bb.0: 565; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 566; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 567; GFX10-NEXT: v_log_f32_e32 v0, v0 568; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 569; GFX10-NEXT: v_exp_f32_e32 v0, v0 570; GFX10-NEXT: s_setpc_b64 s[30:31] 571 %fabs.y = call float @llvm.fabs.f32(float %y) 572 %pow = call float @llvm.pow.f32(float %x, float %fabs.y) 573 ret float %pow 574} 575 576define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { 577; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: 578; GFX6: ; %bb.0: 579; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 580; GFX6-NEXT: v_log_f32_e64 v0, |v0| 581; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 582; GFX6-NEXT: v_exp_f32_e32 v0, v0 583; GFX6-NEXT: s_setpc_b64 s[30:31] 584; 585; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: 586; GFX8: ; %bb.0: 587; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 588; GFX8-NEXT: v_log_f32_e64 v0, |v0| 589; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 590; GFX8-NEXT: v_exp_f32_e32 v0, v0 591; GFX8-NEXT: s_setpc_b64 s[30:31] 592; 593; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: 594; GFX9: ; %bb.0: 595; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 596; GFX9-NEXT: v_log_f32_e64 v0, |v0| 597; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 598; GFX9-NEXT: v_exp_f32_e32 v0, v0 599; GFX9-NEXT: s_setpc_b64 s[30:31] 600; 601; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: 602; GFX10: ; %bb.0: 603; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 604; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 605; GFX10-NEXT: v_log_f32_e64 v0, |v0| 606; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 607; GFX10-NEXT: v_exp_f32_e32 v0, v0 608; GFX10-NEXT: s_setpc_b64 s[30:31] 609 %fabs.x = call float @llvm.fabs.f32(float %x) 610 %fabs.y = call float @llvm.fabs.f32(float %y) 611 %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) 612 ret float %pow 613} 614 615define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { 616; GFX6-LABEL: v_pow_f32_sgpr_vgpr: 617; GFX6: ; %bb.0: 618; GFX6-NEXT: v_log_f32_e32 v1, s0 619; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 620; GFX6-NEXT: v_exp_f32_e32 v0, v0 621; GFX6-NEXT: ; return to shader part epilog 622; 623; GFX8-LABEL: v_pow_f32_sgpr_vgpr: 624; GFX8: ; %bb.0: 625; GFX8-NEXT: v_log_f32_e32 v1, s0 626; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 627; GFX8-NEXT: v_exp_f32_e32 v0, v0 628; GFX8-NEXT: ; return to shader part epilog 629; 630; GFX9-LABEL: v_pow_f32_sgpr_vgpr: 631; GFX9: ; %bb.0: 632; GFX9-NEXT: v_log_f32_e32 v1, s0 633; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 634; GFX9-NEXT: v_exp_f32_e32 v0, v0 635; GFX9-NEXT: ; return to shader part epilog 636; 637; GFX10-LABEL: v_pow_f32_sgpr_vgpr: 638; GFX10: ; %bb.0: 639; GFX10-NEXT: v_log_f32_e32 v1, s0 640; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 641; GFX10-NEXT: v_exp_f32_e32 v0, v0 642; GFX10-NEXT: ; return to shader part epilog 643 %pow = call float @llvm.pow.f32(float %x, float %y) 644 ret float %pow 645} 646 647define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { 648; GFX6-LABEL: v_pow_f32_vgpr_sgpr: 649; GFX6: ; %bb.0: 650; GFX6-NEXT: v_log_f32_e32 v0, v0 651; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 652; GFX6-NEXT: v_exp_f32_e32 v0, v0 653; GFX6-NEXT: ; return to shader part epilog 654; 655; GFX8-LABEL: v_pow_f32_vgpr_sgpr: 656; GFX8: ; %bb.0: 657; GFX8-NEXT: v_log_f32_e32 v0, v0 658; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 659; GFX8-NEXT: v_exp_f32_e32 v0, v0 660; GFX8-NEXT: ; return to shader part epilog 661; 662; GFX9-LABEL: v_pow_f32_vgpr_sgpr: 663; GFX9: ; %bb.0: 664; GFX9-NEXT: v_log_f32_e32 v0, v0 665; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 666; GFX9-NEXT: v_exp_f32_e32 v0, v0 667; GFX9-NEXT: ; return to shader part epilog 668; 669; GFX10-LABEL: v_pow_f32_vgpr_sgpr: 670; GFX10: ; %bb.0: 671; GFX10-NEXT: v_log_f32_e32 v0, v0 672; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 673; GFX10-NEXT: v_exp_f32_e32 v0, v0 674; GFX10-NEXT: ; return to shader part epilog 675 %pow = call float @llvm.pow.f32(float %x, float %y) 676 ret float %pow 677} 678 679define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { 680; GFX6-LABEL: v_pow_f32_sgpr_sgpr: 681; GFX6: ; %bb.0: 682; GFX6-NEXT: v_log_f32_e32 v0, s0 683; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 684; GFX6-NEXT: v_exp_f32_e32 v0, v0 685; GFX6-NEXT: ; return to shader part epilog 686; 687; GFX8-LABEL: v_pow_f32_sgpr_sgpr: 688; GFX8: ; %bb.0: 689; GFX8-NEXT: v_log_f32_e32 v0, s0 690; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 691; GFX8-NEXT: v_exp_f32_e32 v0, v0 692; GFX8-NEXT: ; return to shader part epilog 693; 694; GFX9-LABEL: v_pow_f32_sgpr_sgpr: 695; GFX9: ; %bb.0: 696; GFX9-NEXT: v_log_f32_e32 v0, s0 697; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 698; GFX9-NEXT: v_exp_f32_e32 v0, v0 699; GFX9-NEXT: ; return to shader part epilog 700; 701; GFX10-LABEL: v_pow_f32_sgpr_sgpr: 702; GFX10: ; %bb.0: 703; GFX10-NEXT: v_log_f32_e32 v0, s0 704; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 705; GFX10-NEXT: v_exp_f32_e32 v0, v0 706; GFX10-NEXT: ; return to shader part epilog 707 %pow = call float @llvm.pow.f32(float %x, float %y) 708 ret float %pow 709} 710 711define float @v_pow_f32_fneg_lhs(float %x, float %y) { 712; GFX6-LABEL: v_pow_f32_fneg_lhs: 713; GFX6: ; %bb.0: 714; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 715; GFX6-NEXT: v_log_f32_e64 v0, -v0 716; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 717; GFX6-NEXT: v_exp_f32_e32 v0, v0 718; GFX6-NEXT: s_setpc_b64 s[30:31] 719; 720; GFX8-LABEL: v_pow_f32_fneg_lhs: 721; GFX8: ; %bb.0: 722; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 723; GFX8-NEXT: v_log_f32_e64 v0, -v0 724; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 725; GFX8-NEXT: v_exp_f32_e32 v0, v0 726; GFX8-NEXT: s_setpc_b64 s[30:31] 727; 728; GFX9-LABEL: v_pow_f32_fneg_lhs: 729; GFX9: ; %bb.0: 730; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 731; GFX9-NEXT: v_log_f32_e64 v0, -v0 732; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 733; GFX9-NEXT: v_exp_f32_e32 v0, v0 734; GFX9-NEXT: s_setpc_b64 s[30:31] 735; 736; GFX10-LABEL: v_pow_f32_fneg_lhs: 737; GFX10: ; %bb.0: 738; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 739; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 740; GFX10-NEXT: v_log_f32_e64 v0, -v0 741; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 742; GFX10-NEXT: v_exp_f32_e32 v0, v0 743; GFX10-NEXT: s_setpc_b64 s[30:31] 744 %neg.x = fneg float %x 745 %pow = call float @llvm.pow.f32(float %neg.x, float %y) 746 ret float %pow 747} 748 749define float @v_pow_f32_fneg_rhs(float %x, float %y) { 750; GFX6-LABEL: v_pow_f32_fneg_rhs: 751; GFX6: ; %bb.0: 752; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 753; GFX6-NEXT: v_log_f32_e32 v0, v0 754; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 755; GFX6-NEXT: v_exp_f32_e32 v0, v0 756; GFX6-NEXT: s_setpc_b64 s[30:31] 757; 758; GFX8-LABEL: v_pow_f32_fneg_rhs: 759; GFX8: ; %bb.0: 760; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 761; GFX8-NEXT: v_log_f32_e32 v0, v0 762; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 763; GFX8-NEXT: v_exp_f32_e32 v0, v0 764; GFX8-NEXT: s_setpc_b64 s[30:31] 765; 766; GFX9-LABEL: v_pow_f32_fneg_rhs: 767; GFX9: ; %bb.0: 768; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 769; GFX9-NEXT: v_log_f32_e32 v0, v0 770; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 771; GFX9-NEXT: v_exp_f32_e32 v0, v0 772; GFX9-NEXT: s_setpc_b64 s[30:31] 773; 774; GFX10-LABEL: v_pow_f32_fneg_rhs: 775; GFX10: ; %bb.0: 776; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 777; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 778; GFX10-NEXT: v_log_f32_e32 v0, v0 779; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 780; GFX10-NEXT: v_exp_f32_e32 v0, v0 781; GFX10-NEXT: s_setpc_b64 s[30:31] 782 %neg.y = fneg float %y 783 %pow = call float @llvm.pow.f32(float %x, float %neg.y) 784 ret float %pow 785} 786 787declare half @llvm.pow.f16(half, half) 788declare float @llvm.pow.f32(float, float) 789declare double @llvm.pow.f64(double, double) 790 791declare half @llvm.fabs.f16(half) 792declare float @llvm.fabs.f32(float) 793 794declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) 795declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) 796