1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s 3; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s 5; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s 6 7define float @v_pow_f32(float %x, float %y) { 8; GFX6-LABEL: v_pow_f32: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_log_f32_e32 v0, v0 12; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 13; GFX6-NEXT: v_exp_f32_e32 v0, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_pow_f32: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_log_f32_e32 v0, v0 20; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 21; GFX8-NEXT: v_exp_f32_e32 v0, v0 22; GFX8-NEXT: s_setpc_b64 s[30:31] 23; 24; GFX9-LABEL: v_pow_f32: 25; GFX9: ; %bb.0: 26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 27; GFX9-NEXT: v_log_f32_e32 v0, v0 28; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 29; GFX9-NEXT: v_exp_f32_e32 v0, v0 30; GFX9-NEXT: s_setpc_b64 s[30:31] 31; 32; GFX10-LABEL: v_pow_f32: 33; GFX10: ; %bb.0: 34; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 35; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 36; GFX10-NEXT: v_log_f32_e32 v0, v0 37; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 38; GFX10-NEXT: v_exp_f32_e32 v0, v0 39; GFX10-NEXT: s_setpc_b64 s[30:31] 40 %pow = call float @llvm.pow.f32(float %x, float %y) 41 ret float %pow 42} 43 44define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { 45; GFX6-LABEL: v_pow_v2f32: 46; GFX6: ; %bb.0: 47; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 48; GFX6-NEXT: v_log_f32_e32 v0, v0 49; GFX6-NEXT: v_log_f32_e32 v1, v1 50; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 51; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 52; GFX6-NEXT: v_exp_f32_e32 v0, v0 53; GFX6-NEXT: v_exp_f32_e32 v1, v1 54; GFX6-NEXT: s_setpc_b64 s[30:31] 55; 56; GFX8-LABEL: v_pow_v2f32: 57; GFX8: ; %bb.0: 58; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 59; GFX8-NEXT: v_log_f32_e32 v0, v0 60; GFX8-NEXT: v_log_f32_e32 v1, v1 61; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 62; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 63; GFX8-NEXT: v_exp_f32_e32 v0, v0 64; GFX8-NEXT: v_exp_f32_e32 v1, v1 65; GFX8-NEXT: s_setpc_b64 s[30:31] 66; 67; GFX9-LABEL: v_pow_v2f32: 68; GFX9: ; %bb.0: 69; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 70; GFX9-NEXT: v_log_f32_e32 v0, v0 71; GFX9-NEXT: v_log_f32_e32 v1, v1 72; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 73; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 74; GFX9-NEXT: v_exp_f32_e32 v0, v0 75; GFX9-NEXT: v_exp_f32_e32 v1, v1 76; GFX9-NEXT: s_setpc_b64 s[30:31] 77; 78; GFX10-LABEL: v_pow_v2f32: 79; GFX10: ; %bb.0: 80; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 81; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 82; GFX10-NEXT: v_log_f32_e32 v0, v0 83; GFX10-NEXT: v_log_f32_e32 v1, v1 84; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 85; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 86; GFX10-NEXT: v_exp_f32_e32 v0, v0 87; GFX10-NEXT: v_exp_f32_e32 v1, v1 88; GFX10-NEXT: s_setpc_b64 s[30:31] 89 %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) 90 ret <2 x float> %pow 91} 92 93define half @v_pow_f16(half %x, half %y) { 94; GFX6-LABEL: v_pow_f16: 95; GFX6: ; %bb.0: 96; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 97; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 98; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 99; GFX6-NEXT: v_log_f32_e32 v0, v0 100; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 101; GFX6-NEXT: v_exp_f32_e32 v0, v0 102; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 103; GFX6-NEXT: s_setpc_b64 s[30:31] 104; 105; GFX8-LABEL: v_pow_f16: 106; GFX8: ; %bb.0: 107; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 108; GFX8-NEXT: v_log_f16_e32 v0, v0 109; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 110; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 111; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 112; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 113; GFX8-NEXT: v_exp_f16_e32 v0, v0 114; GFX8-NEXT: s_setpc_b64 s[30:31] 115; 116; GFX9-LABEL: v_pow_f16: 117; GFX9: ; %bb.0: 118; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 119; GFX9-NEXT: v_log_f16_e32 v0, v0 120; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 121; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 122; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 123; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 124; GFX9-NEXT: v_exp_f16_e32 v0, v0 125; GFX9-NEXT: s_setpc_b64 s[30:31] 126; 127; GFX10-LABEL: v_pow_f16: 128; GFX10: ; %bb.0: 129; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 130; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 131; GFX10-NEXT: v_log_f16_e32 v0, v0 132; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 133; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 134; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 135; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 136; GFX10-NEXT: v_exp_f16_e32 v0, v0 137; GFX10-NEXT: s_setpc_b64 s[30:31] 138 %pow = call half @llvm.pow.f16(half %x, half %y) 139 ret half %pow 140} 141 142define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { 143; GFX6-LABEL: v_pow_v2f16: 144; GFX6: ; %bb.0: 145; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 146; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 147; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 148; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 149; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 150; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 151; GFX6-NEXT: v_log_f32_e32 v0, v0 152; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 153; GFX6-NEXT: v_log_f32_e32 v2, v2 154; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 155; GFX6-NEXT: v_exp_f32_e32 v0, v0 156; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 157; GFX6-NEXT: v_exp_f32_e32 v1, v1 158; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 159; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 160; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 161; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 162; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 163; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 164; GFX6-NEXT: s_setpc_b64 s[30:31] 165; 166; GFX8-LABEL: v_pow_v2f16: 167; GFX8: ; %bb.0: 168; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 169; GFX8-NEXT: v_log_f16_e32 v2, v0 170; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 171; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 172; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 173; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 174; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 175; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 176; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 177; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 178; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 179; GFX8-NEXT: v_mov_b32_e32 v2, 16 180; GFX8-NEXT: v_exp_f16_e32 v0, v0 181; GFX8-NEXT: v_exp_f16_e32 v1, v1 182; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 183; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 184; GFX8-NEXT: s_setpc_b64 s[30:31] 185; 186; GFX9-LABEL: v_pow_v2f16: 187; GFX9: ; %bb.0: 188; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 189; GFX9-NEXT: v_log_f16_e32 v2, v0 190; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 191; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 192; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 193; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 194; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 195; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 196; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 197; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 198; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 199; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 200; GFX9-NEXT: v_exp_f16_e32 v1, v2 201; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 202; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 203; GFX9-NEXT: s_setpc_b64 s[30:31] 204; 205; GFX10-LABEL: v_pow_v2f16: 206; GFX10: ; %bb.0: 207; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 208; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 209; GFX10-NEXT: v_log_f16_e32 v2, v0 210; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 211; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 212; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 213; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 214; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 215; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 216; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 217; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 218; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 219; GFX10-NEXT: v_exp_f16_e32 v1, v1 220; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 221; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 222; GFX10-NEXT: s_setpc_b64 s[30:31] 223 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y) 224 ret <2 x half> %pow 225} 226 227define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { 228; GFX6-LABEL: v_pow_v2f16_fneg_lhs: 229; GFX6: ; %bb.0: 230; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 231; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 232; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 233; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 234; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 235; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 236; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 237; GFX6-NEXT: v_log_f32_e32 v0, v0 238; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 239; GFX6-NEXT: v_log_f32_e32 v2, v2 240; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 241; GFX6-NEXT: v_exp_f32_e32 v0, v0 242; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 243; GFX6-NEXT: v_exp_f32_e32 v1, v1 244; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 245; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 246; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 247; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 248; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 249; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 250; GFX6-NEXT: s_setpc_b64 s[30:31] 251; 252; GFX8-LABEL: v_pow_v2f16_fneg_lhs: 253; GFX8: ; %bb.0: 254; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 255; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 256; GFX8-NEXT: v_log_f16_e32 v2, v0 257; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 258; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 259; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 260; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 261; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 262; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 263; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 264; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 265; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 266; GFX8-NEXT: v_mov_b32_e32 v2, 16 267; GFX8-NEXT: v_exp_f16_e32 v0, v0 268; GFX8-NEXT: v_exp_f16_e32 v1, v1 269; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 270; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 271; GFX8-NEXT: s_setpc_b64 s[30:31] 272; 273; GFX9-LABEL: v_pow_v2f16_fneg_lhs: 274; GFX9: ; %bb.0: 275; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 276; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 277; GFX9-NEXT: v_log_f16_e32 v2, v0 278; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 279; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 280; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 281; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 282; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 283; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 284; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 285; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 286; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 287; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 288; GFX9-NEXT: v_exp_f16_e32 v1, v2 289; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 290; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 291; GFX9-NEXT: s_setpc_b64 s[30:31] 292; 293; GFX10-LABEL: v_pow_v2f16_fneg_lhs: 294; GFX10: ; %bb.0: 295; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 296; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 297; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 298; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 299; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 300; GFX10-NEXT: v_log_f16_e32 v2, v0 301; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 302; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 303; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 304; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 305; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 306; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 307; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 308; GFX10-NEXT: v_exp_f16_e32 v1, v1 309; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 310; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 311; GFX10-NEXT: s_setpc_b64 s[30:31] 312 %x.fneg = fneg <2 x half> %x 313 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y) 314 ret <2 x half> %pow 315} 316 317define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { 318; GFX6-LABEL: v_pow_v2f16_fneg_rhs: 319; GFX6: ; %bb.0: 320; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 321; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 322; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 323; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 324; GFX6-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 325; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 326; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 327; GFX6-NEXT: v_log_f32_e32 v0, v0 328; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 329; GFX6-NEXT: v_log_f32_e32 v2, v2 330; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 331; GFX6-NEXT: v_exp_f32_e32 v0, v0 332; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 333; GFX6-NEXT: v_exp_f32_e32 v1, v1 334; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 335; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 336; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 337; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 338; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 339; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 340; GFX6-NEXT: s_setpc_b64 s[30:31] 341; 342; GFX8-LABEL: v_pow_v2f16_fneg_rhs: 343; GFX8: ; %bb.0: 344; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 345; GFX8-NEXT: v_log_f16_e32 v2, v0 346; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 347; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 348; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 349; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 350; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 351; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 352; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 353; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 354; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 355; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 356; GFX8-NEXT: v_mov_b32_e32 v2, 16 357; GFX8-NEXT: v_exp_f16_e32 v0, v0 358; GFX8-NEXT: v_exp_f16_e32 v1, v1 359; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 360; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 361; GFX8-NEXT: s_setpc_b64 s[30:31] 362; 363; GFX9-LABEL: v_pow_v2f16_fneg_rhs: 364; GFX9: ; %bb.0: 365; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 366; GFX9-NEXT: v_log_f16_e32 v2, v0 367; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 368; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 369; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 370; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 371; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 372; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 373; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 374; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 375; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 376; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 377; GFX9-NEXT: v_exp_f16_e32 v1, v2 378; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 379; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 380; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 381; GFX9-NEXT: s_setpc_b64 s[30:31] 382; 383; GFX10-LABEL: v_pow_v2f16_fneg_rhs: 384; GFX10: ; %bb.0: 385; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 386; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 387; GFX10-NEXT: v_log_f16_e32 v2, v0 388; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 389; GFX10-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 390; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 391; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 392; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 393; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 394; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 395; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 396; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 397; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 398; GFX10-NEXT: v_exp_f16_e32 v1, v1 399; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 400; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 401; GFX10-NEXT: s_setpc_b64 s[30:31] 402 %y.fneg = fneg <2 x half> %y 403 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg) 404 ret <2 x half> %pow 405} 406 407define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { 408; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs: 409; GFX6: ; %bb.0: 410; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 411; GFX6-NEXT: s_mov_b32 s4, 0x80008000 412; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0 413; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 414; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 415; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 416; GFX6-NEXT: v_xor_b32_e32 v1, s4, v1 417; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 418; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 419; GFX6-NEXT: v_log_f32_e32 v0, v0 420; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 421; GFX6-NEXT: v_log_f32_e32 v2, v2 422; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 423; GFX6-NEXT: v_exp_f32_e32 v0, v0 424; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v2, v3 425; GFX6-NEXT: v_exp_f32_e32 v1, v1 426; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 427; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 428; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 429; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 430; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 431; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 432; GFX6-NEXT: s_setpc_b64 s[30:31] 433; 434; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs: 435; GFX8: ; %bb.0: 436; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 437; GFX8-NEXT: s_mov_b32 s4, 0x80008000 438; GFX8-NEXT: v_xor_b32_e32 v0, s4, v0 439; GFX8-NEXT: v_log_f16_e32 v2, v0 440; GFX8-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 441; GFX8-NEXT: v_xor_b32_e32 v1, s4, v1 442; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v1 443; GFX8-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 444; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 445; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 446; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 447; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 448; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 449; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v2 450; GFX8-NEXT: v_mov_b32_e32 v2, 16 451; GFX8-NEXT: v_exp_f16_e32 v0, v0 452; GFX8-NEXT: v_exp_f16_e32 v1, v1 453; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 454; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 455; GFX8-NEXT: s_setpc_b64 s[30:31] 456; 457; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs: 458; GFX9: ; %bb.0: 459; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 460; GFX9-NEXT: s_mov_b32 s4, 0x80008000 461; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0 462; GFX9-NEXT: v_log_f16_e32 v2, v0 463; GFX9-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 464; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 465; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 466; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 467; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 468; GFX9-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 469; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 470; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 471; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 472; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 473; GFX9-NEXT: v_exp_f16_e32 v1, v2 474; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 475; GFX9-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 476; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 477; GFX9-NEXT: s_setpc_b64 s[30:31] 478; 479; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: 480; GFX10: ; %bb.0: 481; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 482; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 483; GFX10-NEXT: s_mov_b32 s4, 0x80008000 484; GFX10-NEXT: v_xor_b32_e32 v0, s4, v0 485; GFX10-NEXT: v_xor_b32_e32 v1, s4, v1 486; GFX10-NEXT: v_log_f16_e32 v2, v0 487; GFX10-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 488; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 489; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 490; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v2 491; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 492; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v2, v3 493; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 494; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v2 495; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 496; GFX10-NEXT: v_exp_f16_e32 v1, v1 497; GFX10-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 498; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 499; GFX10-NEXT: s_setpc_b64 s[30:31] 500 %x.fneg = fneg <2 x half> %x 501 %y.fneg = fneg <2 x half> %y 502 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg) 503 ret <2 x half> %pow 504} 505 506; FIXME 507; define double @v_pow_f64(double %x, double %y) { 508; %pow = call double @llvm.pow.f64(double %x, double %y) 509; ret double %pow 510; } 511 512define float @v_pow_f32_fabs_lhs(float %x, float %y) { 513; GFX6-LABEL: v_pow_f32_fabs_lhs: 514; GFX6: ; %bb.0: 515; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 516; GFX6-NEXT: v_log_f32_e64 v0, |v0| 517; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 518; GFX6-NEXT: v_exp_f32_e32 v0, v0 519; GFX6-NEXT: s_setpc_b64 s[30:31] 520; 521; GFX8-LABEL: v_pow_f32_fabs_lhs: 522; GFX8: ; %bb.0: 523; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 524; GFX8-NEXT: v_log_f32_e64 v0, |v0| 525; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 526; GFX8-NEXT: v_exp_f32_e32 v0, v0 527; GFX8-NEXT: s_setpc_b64 s[30:31] 528; 529; GFX9-LABEL: v_pow_f32_fabs_lhs: 530; GFX9: ; %bb.0: 531; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 532; GFX9-NEXT: v_log_f32_e64 v0, |v0| 533; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 534; GFX9-NEXT: v_exp_f32_e32 v0, v0 535; GFX9-NEXT: s_setpc_b64 s[30:31] 536; 537; GFX10-LABEL: v_pow_f32_fabs_lhs: 538; GFX10: ; %bb.0: 539; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 540; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 541; GFX10-NEXT: v_log_f32_e64 v0, |v0| 542; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 543; GFX10-NEXT: v_exp_f32_e32 v0, v0 544; GFX10-NEXT: s_setpc_b64 s[30:31] 545 %fabs.x = call float @llvm.fabs.f32(float %x) 546 %pow = call float @llvm.pow.f32(float %fabs.x, float %y) 547 ret float %pow 548} 549 550define float @v_pow_f32_fabs_rhs(float %x, float %y) { 551; GFX6-LABEL: v_pow_f32_fabs_rhs: 552; GFX6: ; %bb.0: 553; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 554; GFX6-NEXT: v_log_f32_e32 v0, v0 555; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 556; GFX6-NEXT: v_exp_f32_e32 v0, v0 557; GFX6-NEXT: s_setpc_b64 s[30:31] 558; 559; GFX8-LABEL: v_pow_f32_fabs_rhs: 560; GFX8: ; %bb.0: 561; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 562; GFX8-NEXT: v_log_f32_e32 v0, v0 563; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 564; GFX8-NEXT: v_exp_f32_e32 v0, v0 565; GFX8-NEXT: s_setpc_b64 s[30:31] 566; 567; GFX9-LABEL: v_pow_f32_fabs_rhs: 568; GFX9: ; %bb.0: 569; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 570; GFX9-NEXT: v_log_f32_e32 v0, v0 571; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 572; GFX9-NEXT: v_exp_f32_e32 v0, v0 573; GFX9-NEXT: s_setpc_b64 s[30:31] 574; 575; GFX10-LABEL: v_pow_f32_fabs_rhs: 576; GFX10: ; %bb.0: 577; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 578; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 579; GFX10-NEXT: v_log_f32_e32 v0, v0 580; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 581; GFX10-NEXT: v_exp_f32_e32 v0, v0 582; GFX10-NEXT: s_setpc_b64 s[30:31] 583 %fabs.y = call float @llvm.fabs.f32(float %y) 584 %pow = call float @llvm.pow.f32(float %x, float %fabs.y) 585 ret float %pow 586} 587 588define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { 589; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: 590; GFX6: ; %bb.0: 591; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 592; GFX6-NEXT: v_log_f32_e64 v0, |v0| 593; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 594; GFX6-NEXT: v_exp_f32_e32 v0, v0 595; GFX6-NEXT: s_setpc_b64 s[30:31] 596; 597; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: 598; GFX8: ; %bb.0: 599; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 600; GFX8-NEXT: v_log_f32_e64 v0, |v0| 601; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 602; GFX8-NEXT: v_exp_f32_e32 v0, v0 603; GFX8-NEXT: s_setpc_b64 s[30:31] 604; 605; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: 606; GFX9: ; %bb.0: 607; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 608; GFX9-NEXT: v_log_f32_e64 v0, |v0| 609; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 610; GFX9-NEXT: v_exp_f32_e32 v0, v0 611; GFX9-NEXT: s_setpc_b64 s[30:31] 612; 613; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: 614; GFX10: ; %bb.0: 615; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 616; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 617; GFX10-NEXT: v_log_f32_e64 v0, |v0| 618; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1| 619; GFX10-NEXT: v_exp_f32_e32 v0, v0 620; GFX10-NEXT: s_setpc_b64 s[30:31] 621 %fabs.x = call float @llvm.fabs.f32(float %x) 622 %fabs.y = call float @llvm.fabs.f32(float %y) 623 %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) 624 ret float %pow 625} 626 627define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { 628; GFX6-LABEL: v_pow_f32_sgpr_vgpr: 629; GFX6: ; %bb.0: 630; GFX6-NEXT: v_log_f32_e32 v1, s0 631; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 632; GFX6-NEXT: v_exp_f32_e32 v0, v0 633; GFX6-NEXT: ; return to shader part epilog 634; 635; GFX8-LABEL: v_pow_f32_sgpr_vgpr: 636; GFX8: ; %bb.0: 637; GFX8-NEXT: v_log_f32_e32 v1, s0 638; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 639; GFX8-NEXT: v_exp_f32_e32 v0, v0 640; GFX8-NEXT: ; return to shader part epilog 641; 642; GFX9-LABEL: v_pow_f32_sgpr_vgpr: 643; GFX9: ; %bb.0: 644; GFX9-NEXT: v_log_f32_e32 v1, s0 645; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 646; GFX9-NEXT: v_exp_f32_e32 v0, v0 647; GFX9-NEXT: ; return to shader part epilog 648; 649; GFX10-LABEL: v_pow_f32_sgpr_vgpr: 650; GFX10: ; %bb.0: 651; GFX10-NEXT: v_log_f32_e32 v1, s0 652; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 653; GFX10-NEXT: v_exp_f32_e32 v0, v0 654; GFX10-NEXT: ; return to shader part epilog 655 %pow = call float @llvm.pow.f32(float %x, float %y) 656 ret float %pow 657} 658 659define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { 660; GFX6-LABEL: v_pow_f32_vgpr_sgpr: 661; GFX6: ; %bb.0: 662; GFX6-NEXT: v_log_f32_e32 v0, v0 663; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 664; GFX6-NEXT: v_exp_f32_e32 v0, v0 665; GFX6-NEXT: ; return to shader part epilog 666; 667; GFX8-LABEL: v_pow_f32_vgpr_sgpr: 668; GFX8: ; %bb.0: 669; GFX8-NEXT: v_log_f32_e32 v0, v0 670; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 671; GFX8-NEXT: v_exp_f32_e32 v0, v0 672; GFX8-NEXT: ; return to shader part epilog 673; 674; GFX9-LABEL: v_pow_f32_vgpr_sgpr: 675; GFX9: ; %bb.0: 676; GFX9-NEXT: v_log_f32_e32 v0, v0 677; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 678; GFX9-NEXT: v_exp_f32_e32 v0, v0 679; GFX9-NEXT: ; return to shader part epilog 680; 681; GFX10-LABEL: v_pow_f32_vgpr_sgpr: 682; GFX10: ; %bb.0: 683; GFX10-NEXT: v_log_f32_e32 v0, v0 684; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 685; GFX10-NEXT: v_exp_f32_e32 v0, v0 686; GFX10-NEXT: ; return to shader part epilog 687 %pow = call float @llvm.pow.f32(float %x, float %y) 688 ret float %pow 689} 690 691define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { 692; GFX6-LABEL: v_pow_f32_sgpr_sgpr: 693; GFX6: ; %bb.0: 694; GFX6-NEXT: v_log_f32_e32 v0, s0 695; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 696; GFX6-NEXT: v_exp_f32_e32 v0, v0 697; GFX6-NEXT: ; return to shader part epilog 698; 699; GFX8-LABEL: v_pow_f32_sgpr_sgpr: 700; GFX8: ; %bb.0: 701; GFX8-NEXT: v_log_f32_e32 v0, s0 702; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 703; GFX8-NEXT: v_exp_f32_e32 v0, v0 704; GFX8-NEXT: ; return to shader part epilog 705; 706; GFX9-LABEL: v_pow_f32_sgpr_sgpr: 707; GFX9: ; %bb.0: 708; GFX9-NEXT: v_log_f32_e32 v0, s0 709; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 710; GFX9-NEXT: v_exp_f32_e32 v0, v0 711; GFX9-NEXT: ; return to shader part epilog 712; 713; GFX10-LABEL: v_pow_f32_sgpr_sgpr: 714; GFX10: ; %bb.0: 715; GFX10-NEXT: v_log_f32_e32 v0, s0 716; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 717; GFX10-NEXT: v_exp_f32_e32 v0, v0 718; GFX10-NEXT: ; return to shader part epilog 719 %pow = call float @llvm.pow.f32(float %x, float %y) 720 ret float %pow 721} 722 723define float @v_pow_f32_fneg_lhs(float %x, float %y) { 724; GFX6-LABEL: v_pow_f32_fneg_lhs: 725; GFX6: ; %bb.0: 726; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 727; GFX6-NEXT: v_log_f32_e64 v0, -v0 728; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 729; GFX6-NEXT: v_exp_f32_e32 v0, v0 730; GFX6-NEXT: s_setpc_b64 s[30:31] 731; 732; GFX8-LABEL: v_pow_f32_fneg_lhs: 733; GFX8: ; %bb.0: 734; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 735; GFX8-NEXT: v_log_f32_e64 v0, -v0 736; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 737; GFX8-NEXT: v_exp_f32_e32 v0, v0 738; GFX8-NEXT: s_setpc_b64 s[30:31] 739; 740; GFX9-LABEL: v_pow_f32_fneg_lhs: 741; GFX9: ; %bb.0: 742; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 743; GFX9-NEXT: v_log_f32_e64 v0, -v0 744; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 745; GFX9-NEXT: v_exp_f32_e32 v0, v0 746; GFX9-NEXT: s_setpc_b64 s[30:31] 747; 748; GFX10-LABEL: v_pow_f32_fneg_lhs: 749; GFX10: ; %bb.0: 750; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 751; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 752; GFX10-NEXT: v_log_f32_e64 v0, -v0 753; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 754; GFX10-NEXT: v_exp_f32_e32 v0, v0 755; GFX10-NEXT: s_setpc_b64 s[30:31] 756 %neg.x = fneg float %x 757 %pow = call float @llvm.pow.f32(float %neg.x, float %y) 758 ret float %pow 759} 760 761define float @v_pow_f32_fneg_rhs(float %x, float %y) { 762; GFX6-LABEL: v_pow_f32_fneg_rhs: 763; GFX6: ; %bb.0: 764; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 765; GFX6-NEXT: v_log_f32_e32 v0, v0 766; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 767; GFX6-NEXT: v_exp_f32_e32 v0, v0 768; GFX6-NEXT: s_setpc_b64 s[30:31] 769; 770; GFX8-LABEL: v_pow_f32_fneg_rhs: 771; GFX8: ; %bb.0: 772; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 773; GFX8-NEXT: v_log_f32_e32 v0, v0 774; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 775; GFX8-NEXT: v_exp_f32_e32 v0, v0 776; GFX8-NEXT: s_setpc_b64 s[30:31] 777; 778; GFX9-LABEL: v_pow_f32_fneg_rhs: 779; GFX9: ; %bb.0: 780; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 781; GFX9-NEXT: v_log_f32_e32 v0, v0 782; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 783; GFX9-NEXT: v_exp_f32_e32 v0, v0 784; GFX9-NEXT: s_setpc_b64 s[30:31] 785; 786; GFX10-LABEL: v_pow_f32_fneg_rhs: 787; GFX10: ; %bb.0: 788; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 789; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 790; GFX10-NEXT: v_log_f32_e32 v0, v0 791; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1 792; GFX10-NEXT: v_exp_f32_e32 v0, v0 793; GFX10-NEXT: s_setpc_b64 s[30:31] 794 %neg.y = fneg float %y 795 %pow = call float @llvm.pow.f32(float %x, float %neg.y) 796 ret float %pow 797} 798 799declare half @llvm.pow.f16(half, half) 800declare float @llvm.pow.f32(float, float) 801declare double @llvm.pow.f64(double, double) 802 803declare half @llvm.fabs.f16(half) 804declare float @llvm.fabs.f32(float) 805 806declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) 807declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) 808