1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s 3; RUN: llc -march=amdgcn -mcpu=gfx1030 -global-isel -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s 4 5define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) { 6; GFX9-LABEL: store_load_sindex_kernel: 7; GFX9: ; %bb.0: ; %bb 8; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 9; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 10; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 11; GFX9-NEXT: v_mov_b32_e32 v0, 15 12; GFX9-NEXT: s_waitcnt lgkmcnt(0) 13; GFX9-NEXT: s_lshl_b32 s1, s0, 2 14; GFX9-NEXT: s_and_b32 s0, s0, 15 15; GFX9-NEXT: s_lshl_b32 s0, s0, 2 16; GFX9-NEXT: s_add_u32 s1, 4, s1 17; GFX9-NEXT: scratch_store_dword off, v0, s1 18; GFX9-NEXT: s_waitcnt vmcnt(0) 19; GFX9-NEXT: s_add_u32 s0, 4, s0 20; GFX9-NEXT: scratch_load_dword v0, off, s0 glc 21; GFX9-NEXT: s_waitcnt vmcnt(0) 22; GFX9-NEXT: s_endpgm 23; 24; GFX10-LABEL: store_load_sindex_kernel: 25; GFX10: ; %bb.0: ; %bb 26; GFX10-NEXT: s_add_u32 s2, s2, s5 27; GFX10-NEXT: s_addc_u32 s3, s3, 0 28; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 29; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 30; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 31; GFX10-NEXT: v_mov_b32_e32 v0, 15 32; GFX10-NEXT: s_waitcnt lgkmcnt(0) 33; GFX10-NEXT: s_and_b32 s1, s0, 15 34; GFX10-NEXT: s_lshl_b32 s0, s0, 2 35; GFX10-NEXT: s_lshl_b32 s1, s1, 2 36; GFX10-NEXT: s_add_u32 s0, 4, s0 37; GFX10-NEXT: s_add_u32 s1, 4, s1 38; GFX10-NEXT: scratch_store_dword off, v0, s0 39; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 40; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc 41; GFX10-NEXT: s_waitcnt vmcnt(0) 42; GFX10-NEXT: s_endpgm 43bb: 44 %i = alloca [32 x float], align 4, addrspace(5) 45 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 46 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx 47 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 48 store volatile i32 15, i32 addrspace(5)* %i8, align 4 49 %i9 = and i32 %idx, 15 50 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 51 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 52 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 53 ret void 54} 55 56define amdgpu_kernel void @store_load_vindex_kernel() { 57; GFX9-LABEL: store_load_vindex_kernel: 58; GFX9: ; %bb.0: ; %bb 59; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 60; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 61; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 62; GFX9-NEXT: v_mov_b32_e32 v2, 4 63; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 64; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 65; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 66; GFX9-NEXT: v_mov_b32_e32 v3, 15 67; GFX9-NEXT: scratch_store_dword v1, v3, off 68; GFX9-NEXT: s_waitcnt vmcnt(0) 69; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 70; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc 71; GFX9-NEXT: s_waitcnt vmcnt(0) 72; GFX9-NEXT: s_endpgm 73; 74; GFX10-LABEL: store_load_vindex_kernel: 75; GFX10: ; %bb.0: ; %bb 76; GFX10-NEXT: s_add_u32 s0, s0, s3 77; GFX10-NEXT: s_addc_u32 s1, s1, 0 78; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 79; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 80; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0 81; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 82; GFX10-NEXT: v_mov_b32_e32 v2, 4 83; GFX10-NEXT: v_mov_b32_e32 v3, 15 84; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 85; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 86; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 87; GFX10-NEXT: scratch_store_dword v0, v3, off 88; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 89; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc 90; GFX10-NEXT: s_waitcnt vmcnt(0) 91; GFX10-NEXT: s_endpgm 92bb: 93 %i = alloca [32 x float], align 4, addrspace(5) 94 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 95 %i2 = tail call i32 @llvm.amdgcn.workitem.id.x() 96 %i3 = zext i32 %i2 to i64 97 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 98 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 99 store volatile i32 15, i32 addrspace(5)* %i8, align 4 100 %i9 = sub nsw i32 31, %i2 101 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 102 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 103 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 104 ret void 105} 106 107define void @store_load_vindex_foo(i32 %idx) { 108; GFX9-LABEL: store_load_vindex_foo: 109; GFX9: ; %bb.0: ; %bb 110; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 111; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 112; GFX9-NEXT: v_and_b32_e32 v0, 15, v0 113; GFX9-NEXT: v_mov_b32_e32 v2, s32 114; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 115; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 116; GFX9-NEXT: v_mov_b32_e32 v3, 15 117; GFX9-NEXT: scratch_store_dword v1, v3, off 118; GFX9-NEXT: s_waitcnt vmcnt(0) 119; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 120; GFX9-NEXT: scratch_load_dword v0, v0, off glc 121; GFX9-NEXT: s_waitcnt vmcnt(0) 122; GFX9-NEXT: s_setpc_b64 s[30:31] 123; 124; GFX10-LABEL: store_load_vindex_foo: 125; GFX10: ; %bb.0: ; %bb 126; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 127; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 128; GFX10-NEXT: v_and_b32_e32 v1, 15, v0 129; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 130; GFX10-NEXT: v_mov_b32_e32 v2, s32 131; GFX10-NEXT: v_mov_b32_e32 v3, 15 132; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 133; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 134; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 135; GFX10-NEXT: scratch_store_dword v0, v3, off 136; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 137; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc 138; GFX10-NEXT: s_waitcnt vmcnt(0) 139; GFX10-NEXT: s_setpc_b64 s[30:31] 140bb: 141 %i = alloca [32 x float], align 4, addrspace(5) 142 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 143 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx 144 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 145 store volatile i32 15, i32 addrspace(5)* %i8, align 4 146 %i9 = and i32 %idx, 15 147 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 148 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 149 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 150 ret void 151} 152 153define void @private_ptr_foo(float addrspace(5)* nocapture %arg) { 154; GFX9-LABEL: private_ptr_foo: 155; GFX9: ; %bb.0: 156; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 157; GFX9-NEXT: v_mov_b32_e32 v1, 0x41200000 158; GFX9-NEXT: scratch_store_dword v0, v1, off offset:4 159; GFX9-NEXT: s_waitcnt vmcnt(0) 160; GFX9-NEXT: s_setpc_b64 s[30:31] 161; 162; GFX10-LABEL: private_ptr_foo: 163; GFX10: ; %bb.0: 164; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 165; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 166; GFX10-NEXT: v_mov_b32_e32 v1, 0x41200000 167; GFX10-NEXT: scratch_store_dword v0, v1, off offset:4 168; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 169; GFX10-NEXT: s_setpc_b64 s[30:31] 170 %gep = getelementptr inbounds float, float addrspace(5)* %arg, i32 1 171 store float 1.000000e+01, float addrspace(5)* %gep, align 4 172 ret void 173} 174 175define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) { 176; GFX9-LABEL: store_load_sindex_small_offset_kernel: 177; GFX9: ; %bb.0: ; %bb 178; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 179; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 180; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 181; GFX9-NEXT: s_mov_b32 vcc_hi, 0 182; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc 183; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 184; GFX9-NEXT: s_lshl_b32 s1, s0, 2 185; GFX9-NEXT: s_and_b32 s0, s0, 15 186; GFX9-NEXT: s_lshl_b32 s0, s0, 2 187; GFX9-NEXT: s_waitcnt vmcnt(0) 188; GFX9-NEXT: v_mov_b32_e32 v0, 15 189; GFX9-NEXT: s_add_u32 s1, 0x104, s1 190; GFX9-NEXT: scratch_store_dword off, v0, s1 191; GFX9-NEXT: s_waitcnt vmcnt(0) 192; GFX9-NEXT: s_add_u32 s0, 0x104, s0 193; GFX9-NEXT: scratch_load_dword v0, off, s0 glc 194; GFX9-NEXT: s_waitcnt vmcnt(0) 195; GFX9-NEXT: s_endpgm 196; 197; GFX10-LABEL: store_load_sindex_small_offset_kernel: 198; GFX10: ; %bb.0: ; %bb 199; GFX10-NEXT: s_add_u32 s2, s2, s5 200; GFX10-NEXT: s_addc_u32 s3, s3, 0 201; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 202; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 203; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 204; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc 205; GFX10-NEXT: s_waitcnt vmcnt(0) 206; GFX10-NEXT: v_mov_b32_e32 v0, 15 207; GFX10-NEXT: s_waitcnt lgkmcnt(0) 208; GFX10-NEXT: s_and_b32 s1, s0, 15 209; GFX10-NEXT: s_lshl_b32 s0, s0, 2 210; GFX10-NEXT: s_lshl_b32 s1, s1, 2 211; GFX10-NEXT: s_add_u32 s0, 0x104, s0 212; GFX10-NEXT: s_add_u32 s1, 0x104, s1 213; GFX10-NEXT: scratch_store_dword off, v0, s0 214; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 215; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc 216; GFX10-NEXT: s_waitcnt vmcnt(0) 217; GFX10-NEXT: s_endpgm 218bb: 219 %padding = alloca [64 x i32], align 4, addrspace(5) 220 %i = alloca [32 x float], align 4, addrspace(5) 221 %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef 222 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 223 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 224 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx 225 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 226 store volatile i32 15, i32 addrspace(5)* %i8, align 4 227 %i9 = and i32 %idx, 15 228 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 229 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 230 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 231 ret void 232} 233 234define amdgpu_kernel void @store_load_vindex_small_offset_kernel() { 235; GFX9-LABEL: store_load_vindex_small_offset_kernel: 236; GFX9: ; %bb.0: ; %bb 237; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 238; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 239; GFX9-NEXT: s_mov_b32 vcc_hi, 0 240; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc 241; GFX9-NEXT: s_waitcnt vmcnt(0) 242; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 243; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 244; GFX9-NEXT: v_mov_b32_e32 v2, 0x104 245; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 246; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 247; GFX9-NEXT: v_mov_b32_e32 v3, 15 248; GFX9-NEXT: scratch_store_dword v1, v3, off 249; GFX9-NEXT: s_waitcnt vmcnt(0) 250; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 251; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc 252; GFX9-NEXT: s_waitcnt vmcnt(0) 253; GFX9-NEXT: s_endpgm 254; 255; GFX10-LABEL: store_load_vindex_small_offset_kernel: 256; GFX10: ; %bb.0: ; %bb 257; GFX10-NEXT: s_add_u32 s0, s0, s3 258; GFX10-NEXT: s_addc_u32 s1, s1, 0 259; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 260; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 261; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0 262; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 263; GFX10-NEXT: v_mov_b32_e32 v2, 0x104 264; GFX10-NEXT: v_mov_b32_e32 v3, 15 265; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 266; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 267; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 268; GFX10-NEXT: scratch_load_dword v2, off, off offset:4 glc dlc 269; GFX10-NEXT: s_waitcnt vmcnt(0) 270; GFX10-NEXT: scratch_store_dword v0, v3, off 271; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 272; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc 273; GFX10-NEXT: s_waitcnt vmcnt(0) 274; GFX10-NEXT: s_endpgm 275bb: 276 %padding = alloca [64 x i32], align 4, addrspace(5) 277 %i = alloca [32 x float], align 4, addrspace(5) 278 %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef 279 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 280 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 281 %i2 = tail call i32 @llvm.amdgcn.workitem.id.x() 282 %i3 = zext i32 %i2 to i64 283 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 284 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 285 store volatile i32 15, i32 addrspace(5)* %i8, align 4 286 %i9 = sub nsw i32 31, %i2 287 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 288 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 289 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 290 ret void 291} 292 293define void @store_load_vindex_small_offset_foo(i32 %idx) { 294; GFX9-LABEL: store_load_vindex_small_offset_foo: 295; GFX9: ; %bb.0: ; %bb 296; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 297; GFX9-NEXT: scratch_load_dword v1, off, s32 glc 298; GFX9-NEXT: s_waitcnt vmcnt(0) 299; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x100 300; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 301; GFX9-NEXT: v_and_b32_e32 v0, 15, v0 302; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi 303; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 304; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 305; GFX9-NEXT: v_mov_b32_e32 v3, 15 306; GFX9-NEXT: scratch_store_dword v1, v3, off 307; GFX9-NEXT: s_waitcnt vmcnt(0) 308; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 309; GFX9-NEXT: scratch_load_dword v0, v0, off glc 310; GFX9-NEXT: s_waitcnt vmcnt(0) 311; GFX9-NEXT: s_setpc_b64 s[30:31] 312; 313; GFX10-LABEL: store_load_vindex_small_offset_foo: 314; GFX10: ; %bb.0: ; %bb 315; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 316; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 317; GFX10-NEXT: v_and_b32_e32 v1, 15, v0 318; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x100 319; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 320; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo 321; GFX10-NEXT: v_mov_b32_e32 v3, 15 322; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 323; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 324; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 325; GFX10-NEXT: scratch_load_dword v2, off, s32 glc dlc 326; GFX10-NEXT: s_waitcnt vmcnt(0) 327; GFX10-NEXT: scratch_store_dword v0, v3, off 328; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 329; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc 330; GFX10-NEXT: s_waitcnt vmcnt(0) 331; GFX10-NEXT: s_setpc_b64 s[30:31] 332bb: 333 %padding = alloca [64 x i32], align 4, addrspace(5) 334 %i = alloca [32 x float], align 4, addrspace(5) 335 %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef 336 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 337 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 338 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx 339 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 340 store volatile i32 15, i32 addrspace(5)* %i8, align 4 341 %i9 = and i32 %idx, 15 342 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 343 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 344 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 345 ret void 346} 347 348define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) { 349; GFX9-LABEL: store_load_sindex_large_offset_kernel: 350; GFX9: ; %bb.0: ; %bb 351; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 352; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 353; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 354; GFX9-NEXT: s_mov_b32 vcc_hi, 0 355; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc 356; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 357; GFX9-NEXT: s_lshl_b32 s1, s0, 2 358; GFX9-NEXT: s_and_b32 s0, s0, 15 359; GFX9-NEXT: s_lshl_b32 s0, s0, 2 360; GFX9-NEXT: s_waitcnt vmcnt(0) 361; GFX9-NEXT: v_mov_b32_e32 v0, 15 362; GFX9-NEXT: s_add_u32 s1, 0x4004, s1 363; GFX9-NEXT: scratch_store_dword off, v0, s1 364; GFX9-NEXT: s_waitcnt vmcnt(0) 365; GFX9-NEXT: s_add_u32 s0, 0x4004, s0 366; GFX9-NEXT: scratch_load_dword v0, off, s0 glc 367; GFX9-NEXT: s_waitcnt vmcnt(0) 368; GFX9-NEXT: s_endpgm 369; 370; GFX10-LABEL: store_load_sindex_large_offset_kernel: 371; GFX10: ; %bb.0: ; %bb 372; GFX10-NEXT: s_add_u32 s2, s2, s5 373; GFX10-NEXT: s_addc_u32 s3, s3, 0 374; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 375; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 376; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 377; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc 378; GFX10-NEXT: s_waitcnt vmcnt(0) 379; GFX10-NEXT: v_mov_b32_e32 v0, 15 380; GFX10-NEXT: s_waitcnt lgkmcnt(0) 381; GFX10-NEXT: s_and_b32 s1, s0, 15 382; GFX10-NEXT: s_lshl_b32 s0, s0, 2 383; GFX10-NEXT: s_lshl_b32 s1, s1, 2 384; GFX10-NEXT: s_add_u32 s0, 0x4004, s0 385; GFX10-NEXT: s_add_u32 s1, 0x4004, s1 386; GFX10-NEXT: scratch_store_dword off, v0, s0 387; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 388; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc 389; GFX10-NEXT: s_waitcnt vmcnt(0) 390; GFX10-NEXT: s_endpgm 391bb: 392 %padding = alloca [4096 x i32], align 4, addrspace(5) 393 %i = alloca [32 x float], align 4, addrspace(5) 394 %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef 395 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 396 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 397 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx 398 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 399 store volatile i32 15, i32 addrspace(5)* %i8, align 4 400 %i9 = and i32 %idx, 15 401 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 402 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 403 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 404 ret void 405} 406 407define amdgpu_kernel void @store_load_vindex_large_offset_kernel() { 408; GFX9-LABEL: store_load_vindex_large_offset_kernel: 409; GFX9: ; %bb.0: ; %bb 410; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 411; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 412; GFX9-NEXT: s_mov_b32 vcc_hi, 0 413; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc 414; GFX9-NEXT: s_waitcnt vmcnt(0) 415; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 416; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 417; GFX9-NEXT: v_mov_b32_e32 v2, 0x4004 418; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 419; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 420; GFX9-NEXT: v_mov_b32_e32 v3, 15 421; GFX9-NEXT: scratch_store_dword v1, v3, off 422; GFX9-NEXT: s_waitcnt vmcnt(0) 423; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 424; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc 425; GFX9-NEXT: s_waitcnt vmcnt(0) 426; GFX9-NEXT: s_endpgm 427; 428; GFX10-LABEL: store_load_vindex_large_offset_kernel: 429; GFX10: ; %bb.0: ; %bb 430; GFX10-NEXT: s_add_u32 s0, s0, s3 431; GFX10-NEXT: s_addc_u32 s1, s1, 0 432; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 433; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 434; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0 435; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 436; GFX10-NEXT: v_mov_b32_e32 v2, 0x4004 437; GFX10-NEXT: v_mov_b32_e32 v3, 15 438; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 439; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 440; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 441; GFX10-NEXT: scratch_load_dword v2, off, off offset:4 glc dlc 442; GFX10-NEXT: s_waitcnt vmcnt(0) 443; GFX10-NEXT: scratch_store_dword v0, v3, off 444; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 445; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc 446; GFX10-NEXT: s_waitcnt vmcnt(0) 447; GFX10-NEXT: s_endpgm 448bb: 449 %padding = alloca [4096 x i32], align 4, addrspace(5) 450 %i = alloca [32 x float], align 4, addrspace(5) 451 %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef 452 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 453 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 454 %i2 = tail call i32 @llvm.amdgcn.workitem.id.x() 455 %i3 = zext i32 %i2 to i64 456 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 457 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 458 store volatile i32 15, i32 addrspace(5)* %i8, align 4 459 %i9 = sub nsw i32 31, %i2 460 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 461 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 462 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 463 ret void 464} 465 466define void @store_load_vindex_large_offset_foo(i32 %idx) { 467; GFX9-LABEL: store_load_vindex_large_offset_foo: 468; GFX9: ; %bb.0: ; %bb 469; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 470; GFX9-NEXT: scratch_load_dword v1, off, s32 glc 471; GFX9-NEXT: s_waitcnt vmcnt(0) 472; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000 473; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 474; GFX9-NEXT: v_and_b32_e32 v0, 15, v0 475; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi 476; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 477; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 478; GFX9-NEXT: v_mov_b32_e32 v3, 15 479; GFX9-NEXT: scratch_store_dword v1, v3, off 480; GFX9-NEXT: s_waitcnt vmcnt(0) 481; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 482; GFX9-NEXT: scratch_load_dword v0, v0, off glc 483; GFX9-NEXT: s_waitcnt vmcnt(0) 484; GFX9-NEXT: s_setpc_b64 s[30:31] 485; 486; GFX10-LABEL: store_load_vindex_large_offset_foo: 487; GFX10: ; %bb.0: ; %bb 488; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 489; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 490; GFX10-NEXT: v_and_b32_e32 v1, 15, v0 491; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 492; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 493; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo 494; GFX10-NEXT: v_mov_b32_e32 v3, 15 495; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 496; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 497; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 498; GFX10-NEXT: scratch_load_dword v2, off, s32 glc dlc 499; GFX10-NEXT: s_waitcnt vmcnt(0) 500; GFX10-NEXT: scratch_store_dword v0, v3, off 501; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 502; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc 503; GFX10-NEXT: s_waitcnt vmcnt(0) 504; GFX10-NEXT: s_setpc_b64 s[30:31] 505bb: 506 %padding = alloca [4096 x i32], align 4, addrspace(5) 507 %i = alloca [32 x float], align 4, addrspace(5) 508 %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef 509 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 510 %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* 511 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx 512 %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* 513 store volatile i32 15, i32 addrspace(5)* %i8, align 4 514 %i9 = and i32 %idx, 15 515 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 516 %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* 517 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 518 ret void 519} 520 521define amdgpu_kernel void @store_load_large_imm_offset_kernel() { 522; GFX9-LABEL: store_load_large_imm_offset_kernel: 523; GFX9: ; %bb.0: ; %bb 524; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 525; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 526; GFX9-NEXT: s_movk_i32 s0, 0x3e80 527; GFX9-NEXT: v_mov_b32_e32 v0, 13 528; GFX9-NEXT: s_mov_b32 vcc_hi, 0 529; GFX9-NEXT: scratch_store_dword off, v0, vcc_hi offset:4 530; GFX9-NEXT: s_waitcnt vmcnt(0) 531; GFX9-NEXT: v_mov_b32_e32 v0, 15 532; GFX9-NEXT: s_add_u32 s0, 4, s0 533; GFX9-NEXT: scratch_store_dword off, v0, s0 534; GFX9-NEXT: s_waitcnt vmcnt(0) 535; GFX9-NEXT: scratch_load_dword v0, off, s0 glc 536; GFX9-NEXT: s_waitcnt vmcnt(0) 537; GFX9-NEXT: s_endpgm 538; 539; GFX10-LABEL: store_load_large_imm_offset_kernel: 540; GFX10: ; %bb.0: ; %bb 541; GFX10-NEXT: s_add_u32 s0, s0, s3 542; GFX10-NEXT: s_addc_u32 s1, s1, 0 543; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 544; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 545; GFX10-NEXT: v_mov_b32_e32 v0, 13 546; GFX10-NEXT: v_mov_b32_e32 v1, 15 547; GFX10-NEXT: s_movk_i32 s0, 0x3e80 548; GFX10-NEXT: s_add_u32 s0, 4, s0 549; GFX10-NEXT: scratch_store_dword off, v0, off offset:4 550; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 551; GFX10-NEXT: scratch_store_dword off, v1, s0 552; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 553; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc 554; GFX10-NEXT: s_waitcnt vmcnt(0) 555; GFX10-NEXT: s_endpgm 556bb: 557 %i = alloca [4096 x i32], align 4, addrspace(5) 558 %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef 559 store volatile i32 13, i32 addrspace(5)* %i1, align 4 560 %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 561 store volatile i32 15, i32 addrspace(5)* %i7, align 4 562 %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 563 %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4 564 ret void 565} 566 567define void @store_load_large_imm_offset_foo() { 568; GFX9-LABEL: store_load_large_imm_offset_foo: 569; GFX9: ; %bb.0: ; %bb 570; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 571; GFX9-NEXT: s_movk_i32 s0, 0x3e80 572; GFX9-NEXT: v_mov_b32_e32 v0, 13 573; GFX9-NEXT: scratch_store_dword off, v0, s32 574; GFX9-NEXT: s_waitcnt vmcnt(0) 575; GFX9-NEXT: v_mov_b32_e32 v0, 15 576; GFX9-NEXT: s_add_u32 s0, s32, s0 577; GFX9-NEXT: scratch_store_dword off, v0, s0 578; GFX9-NEXT: s_waitcnt vmcnt(0) 579; GFX9-NEXT: scratch_load_dword v0, off, s0 glc 580; GFX9-NEXT: s_waitcnt vmcnt(0) 581; GFX9-NEXT: s_setpc_b64 s[30:31] 582; 583; GFX10-LABEL: store_load_large_imm_offset_foo: 584; GFX10: ; %bb.0: ; %bb 585; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 586; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 587; GFX10-NEXT: v_mov_b32_e32 v0, 13 588; GFX10-NEXT: v_mov_b32_e32 v1, 15 589; GFX10-NEXT: s_movk_i32 s0, 0x3e80 590; GFX10-NEXT: s_add_u32 s0, s32, s0 591; GFX10-NEXT: scratch_store_dword off, v0, s32 592; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 593; GFX10-NEXT: scratch_store_dword off, v1, s0 594; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 595; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc 596; GFX10-NEXT: s_waitcnt vmcnt(0) 597; GFX10-NEXT: s_setpc_b64 s[30:31] 598bb: 599 %i = alloca [4096 x i32], align 4, addrspace(5) 600 %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef 601 store volatile i32 13, i32 addrspace(5)* %i1, align 4 602 %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 603 store volatile i32 15, i32 addrspace(5)* %i7, align 4 604 %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 605 %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4 606 ret void 607} 608 609define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) { 610; GFX9-LABEL: store_load_vidx_sidx_offset: 611; GFX9: ; %bb.0: ; %bb 612; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 613; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 614; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 615; GFX9-NEXT: v_mov_b32_e32 v1, 15 616; GFX9-NEXT: s_waitcnt lgkmcnt(0) 617; GFX9-NEXT: v_add_lshl_u32 v0, s0, v0, 2 618; GFX9-NEXT: v_add_u32_e32 v0, 4, v0 619; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024 620; GFX9-NEXT: s_waitcnt vmcnt(0) 621; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 glc 622; GFX9-NEXT: s_waitcnt vmcnt(0) 623; GFX9-NEXT: s_endpgm 624; 625; GFX10-LABEL: store_load_vidx_sidx_offset: 626; GFX10: ; %bb.0: ; %bb 627; GFX10-NEXT: s_add_u32 s2, s2, s5 628; GFX10-NEXT: s_addc_u32 s3, s3, 0 629; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 630; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 631; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 632; GFX10-NEXT: v_mov_b32_e32 v1, 15 633; GFX10-NEXT: s_waitcnt lgkmcnt(0) 634; GFX10-NEXT: v_add_lshl_u32 v0, s0, v0, 2 635; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0 636; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024 637; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 638; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc 639; GFX10-NEXT: s_waitcnt vmcnt(0) 640; GFX10-NEXT: s_endpgm 641bb: 642 %alloca = alloca [32 x i32], align 4, addrspace(5) 643 %vidx = tail call i32 @llvm.amdgcn.workitem.id.x() 644 %add1 = add nsw i32 %sidx, %vidx 645 %add2 = add nsw i32 %add1, 256 646 %gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2 647 store volatile i32 15, i32 addrspace(5)* %gep, align 4 648 %load = load volatile i32, i32 addrspace(5)* %gep, align 4 649 ret void 650} 651 652define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) { 653; GFX9-LABEL: store_load_i64_aligned: 654; GFX9: ; %bb.0: ; %bb 655; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 656; GFX9-NEXT: v_mov_b32_e32 v1, 15 657; GFX9-NEXT: v_mov_b32_e32 v2, 0 658; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off 659; GFX9-NEXT: s_waitcnt vmcnt(0) 660; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc 661; GFX9-NEXT: s_waitcnt vmcnt(0) 662; GFX9-NEXT: s_setpc_b64 s[30:31] 663; 664; GFX10-LABEL: store_load_i64_aligned: 665; GFX10: ; %bb.0: ; %bb 666; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 667; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 668; GFX10-NEXT: v_mov_b32_e32 v1, 15 669; GFX10-NEXT: v_mov_b32_e32 v2, 0 670; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off 671; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 672; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc 673; GFX10-NEXT: s_waitcnt vmcnt(0) 674; GFX10-NEXT: s_setpc_b64 s[30:31] 675bb: 676 store volatile i64 15, i64 addrspace(5)* %arg, align 8 677 %load = load volatile i64, i64 addrspace(5)* %arg, align 8 678 ret void 679} 680 681define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) { 682; GFX9-LABEL: store_load_i64_unaligned: 683; GFX9: ; %bb.0: ; %bb 684; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 685; GFX9-NEXT: v_mov_b32_e32 v1, 15 686; GFX9-NEXT: v_mov_b32_e32 v2, 0 687; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off 688; GFX9-NEXT: s_waitcnt vmcnt(0) 689; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc 690; GFX9-NEXT: s_waitcnt vmcnt(0) 691; GFX9-NEXT: s_setpc_b64 s[30:31] 692; 693; GFX10-LABEL: store_load_i64_unaligned: 694; GFX10: ; %bb.0: ; %bb 695; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 696; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 697; GFX10-NEXT: v_mov_b32_e32 v1, 15 698; GFX10-NEXT: v_mov_b32_e32 v2, 0 699; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off 700; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 701; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc 702; GFX10-NEXT: s_waitcnt vmcnt(0) 703; GFX10-NEXT: s_setpc_b64 s[30:31] 704bb: 705 store volatile i64 15, i64 addrspace(5)* %arg, align 1 706 %load = load volatile i64, i64 addrspace(5)* %arg, align 1 707 ret void 708} 709 710define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) { 711; GFX9-LABEL: store_load_v3i32_unaligned: 712; GFX9: ; %bb.0: ; %bb 713; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 714; GFX9-NEXT: s_mov_b32 s2, 3 715; GFX9-NEXT: s_mov_b32 s1, 2 716; GFX9-NEXT: s_mov_b32 s0, 1 717; GFX9-NEXT: v_mov_b32_e32 v3, s2 718; GFX9-NEXT: v_mov_b32_e32 v2, s1 719; GFX9-NEXT: v_mov_b32_e32 v1, s0 720; GFX9-NEXT: scratch_store_dwordx3 v0, v[1:3], off 721; GFX9-NEXT: s_waitcnt vmcnt(0) 722; GFX9-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc 723; GFX9-NEXT: s_waitcnt vmcnt(0) 724; GFX9-NEXT: s_setpc_b64 s[30:31] 725; 726; GFX10-LABEL: store_load_v3i32_unaligned: 727; GFX10: ; %bb.0: ; %bb 728; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 729; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 730; GFX10-NEXT: s_mov_b32 s2, 3 731; GFX10-NEXT: s_mov_b32 s1, 2 732; GFX10-NEXT: s_mov_b32 s0, 1 733; GFX10-NEXT: v_mov_b32_e32 v3, s2 734; GFX10-NEXT: v_mov_b32_e32 v2, s1 735; GFX10-NEXT: v_mov_b32_e32 v1, s0 736; GFX10-NEXT: scratch_store_dwordx3 v0, v[1:3], off 737; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 738; GFX10-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc dlc 739; GFX10-NEXT: s_waitcnt vmcnt(0) 740; GFX10-NEXT: s_setpc_b64 s[30:31] 741bb: 742 store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1 743 %load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1 744 ret void 745} 746 747define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) { 748; GFX9-LABEL: store_load_v4i32_unaligned: 749; GFX9: ; %bb.0: ; %bb 750; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 751; GFX9-NEXT: s_mov_b32 s3, 4 752; GFX9-NEXT: s_mov_b32 s2, 3 753; GFX9-NEXT: s_mov_b32 s1, 2 754; GFX9-NEXT: s_mov_b32 s0, 1 755; GFX9-NEXT: v_mov_b32_e32 v4, s3 756; GFX9-NEXT: v_mov_b32_e32 v3, s2 757; GFX9-NEXT: v_mov_b32_e32 v2, s1 758; GFX9-NEXT: v_mov_b32_e32 v1, s0 759; GFX9-NEXT: scratch_store_dwordx4 v0, v[1:4], off 760; GFX9-NEXT: s_waitcnt vmcnt(0) 761; GFX9-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc 762; GFX9-NEXT: s_waitcnt vmcnt(0) 763; GFX9-NEXT: s_setpc_b64 s[30:31] 764; 765; GFX10-LABEL: store_load_v4i32_unaligned: 766; GFX10: ; %bb.0: ; %bb 767; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 768; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 769; GFX10-NEXT: s_mov_b32 s3, 4 770; GFX10-NEXT: s_mov_b32 s2, 3 771; GFX10-NEXT: s_mov_b32 s1, 2 772; GFX10-NEXT: s_mov_b32 s0, 1 773; GFX10-NEXT: v_mov_b32_e32 v4, s3 774; GFX10-NEXT: v_mov_b32_e32 v3, s2 775; GFX10-NEXT: v_mov_b32_e32 v2, s1 776; GFX10-NEXT: v_mov_b32_e32 v1, s0 777; GFX10-NEXT: scratch_store_dwordx4 v0, v[1:4], off 778; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 779; GFX10-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc dlc 780; GFX10-NEXT: s_waitcnt vmcnt(0) 781; GFX10-NEXT: s_setpc_b64 s[30:31] 782bb: 783 store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1 784 %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1 785 ret void 786} 787 788declare i32 @llvm.amdgcn.workitem.id.x() 789