1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE %s
3; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH %s
4
5; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
6; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
7
8; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
9; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
10
11; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
12; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
13
14; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s
15; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
16
17define float @v_fdiv_f32(float %a, float %b) {
18; GFX6-IEEE-LABEL: v_fdiv_f32:
19; GFX6-IEEE:       ; %bb.0:
20; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
22; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
23; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
24; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
25; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
26; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
27; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
28; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
29; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
30; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
31; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
32; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
33;
34; GFX6-FLUSH-LABEL: v_fdiv_f32:
35; GFX6-FLUSH:       ; %bb.0:
36; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
37; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
38; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
39; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
40; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
41; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
42; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
43; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
44; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
45; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
46; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
47; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
48; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
49; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
50; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
51;
52; GFX89-IEEE-LABEL: v_fdiv_f32:
53; GFX89-IEEE:       ; %bb.0:
54; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
55; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
56; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
57; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
58; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
59; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
60; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
61; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
62; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
63; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
64; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
65; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
66; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
67;
68; GFX89-FLUSH-LABEL: v_fdiv_f32:
69; GFX89-FLUSH:       ; %bb.0:
70; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
71; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
72; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
73; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
74; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
75; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
76; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
77; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
78; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v3
79; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
80; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v3
81; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
82; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
83; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
84; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
85;
86; GFX10-IEEE-LABEL: v_fdiv_f32:
87; GFX10-IEEE:       ; %bb.0:
88; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
89; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
90; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
91; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
92; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
93; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
94; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
95; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
96; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
97; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
98; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
99; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
100; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
101; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
102;
103; GFX10-FLUSH-LABEL: v_fdiv_f32:
104; GFX10-FLUSH:       ; %bb.0:
105; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
106; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
107; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
108; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, v0, v1, v0
109; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
110; GFX10-FLUSH-NEXT:    s_denorm_mode 3
111; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
112; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
113; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
114; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
115; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
116; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
117; GFX10-FLUSH-NEXT:    s_denorm_mode 0
118; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
119; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
120; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
121;
122; GFX11-IEEE-LABEL: v_fdiv_f32:
123; GFX11-IEEE:       ; %bb.0:
124; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
125; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
126; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
127; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
128; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
129; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
130; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
131; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
132; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
133; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
134; GFX11-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
135; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
136; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
137; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
138; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
139; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
140; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
141; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
142; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
143;
144; GFX11-FLUSH-LABEL: v_fdiv_f32:
145; GFX11-FLUSH:       ; %bb.0:
146; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
147; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
148; GFX11-FLUSH-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
149; GFX11-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, v0, v1, v0
150; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
151; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
152; GFX11-FLUSH-NEXT:    s_denorm_mode 3
153; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
154; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
155; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
156; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
157; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
158; GFX11-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
159; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
160; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
161; GFX11-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
162; GFX11-FLUSH-NEXT:    s_denorm_mode 0
163; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
164; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
165; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
166; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
167  %fdiv = fdiv float %a, %b
168  ret float %fdiv
169}
170
171define float @v_fdiv_f32_afn(float %a, float %b) {
172; GCN-LABEL: v_fdiv_f32_afn:
173; GCN:       ; %bb.0:
174; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
175; GCN-NEXT:    v_rcp_f32_e32 v1, v1
176; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
177; GCN-NEXT:    s_setpc_b64 s[30:31]
178;
179; GFX10-LABEL: v_fdiv_f32_afn:
180; GFX10:       ; %bb.0:
181; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
182; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
183; GFX10-NEXT:    v_rcp_f32_e32 v1, v1
184; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
185; GFX10-NEXT:    s_setpc_b64 s[30:31]
186;
187; GFX11-LABEL: v_fdiv_f32_afn:
188; GFX11:       ; %bb.0:
189; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
190; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
191; GFX11-NEXT:    v_rcp_f32_e32 v1, v1
192; GFX11-NEXT:    s_waitcnt_depctr 0xfff
193; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
194; GFX11-NEXT:    s_setpc_b64 s[30:31]
195  %fdiv = fdiv afn float %a, %b
196  ret float %fdiv
197}
198
199define float @v_fdiv_f32_ulp25(float %a, float %b) {
200; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:
201; GFX6-IEEE:       ; %bb.0:
202; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
203; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
204; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
205; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
206; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
207; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
208; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
209; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
210; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
211; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
212; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
213; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
214; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
215;
216; GCN-FLUSH-LABEL: v_fdiv_f32_ulp25:
217; GCN-FLUSH:       ; %bb.0:
218; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
219; GCN-FLUSH-NEXT:    v_mov_b32_e32 v2, 0x6f800000
220; GCN-FLUSH-NEXT:    v_mov_b32_e32 v3, 0x2f800000
221; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, v2
222; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
223; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
224; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
225; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
226; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
227; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
228;
229; GFX89-IEEE-LABEL: v_fdiv_f32_ulp25:
230; GFX89-IEEE:       ; %bb.0:
231; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
232; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
233; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
234; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
235; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
236; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
237; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
238; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
239; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
240; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
241; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
242; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
243; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
244;
245; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25:
246; GFX10-IEEE:       ; %bb.0:
247; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
248; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
249; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
250; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
251; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
252; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
253; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
254; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
255; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
256; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
257; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
258; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
259; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
260; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
261;
262; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25:
263; GFX10-FLUSH:       ; %bb.0:
264; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
265; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
266; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
267; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
268; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
269; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
270; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
271; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
272; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
273;
274; GFX11-IEEE-LABEL: v_fdiv_f32_ulp25:
275; GFX11-IEEE:       ; %bb.0:
276; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
277; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
278; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
279; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
280; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
281; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
282; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
283; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
284; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
285; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
286; GFX11-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
287; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
288; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
289; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
290; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
291; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
292; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
293; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
294; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
295;
296; GFX11-FLUSH-LABEL: v_fdiv_f32_ulp25:
297; GFX11-FLUSH:       ; %bb.0:
298; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
299; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
300; GFX11-FLUSH-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
301; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
302; GFX11-FLUSH-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
303; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
304; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
305; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
306; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
307; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
308; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
309; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
310  %fdiv = fdiv float %a, %b, !fpmath !0
311  ret float %fdiv
312}
313
314define float @v_rcp_f32(float %x) {
315; GFX6-IEEE-LABEL: v_rcp_f32:
316; GFX6-IEEE:       ; %bb.0:
317; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
318; GFX6-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
319; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
320; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
321; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
322; GFX6-IEEE-NEXT:    v_fma_f32 v2, v4, v2, v2
323; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v3, v2
324; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v3
325; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v2, v4
326; GFX6-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v3
327; GFX6-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
328; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
329; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
330;
331; GFX6-FLUSH-LABEL: v_rcp_f32:
332; GFX6-FLUSH:       ; %bb.0:
333; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
334; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
335; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
336; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
337; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
338; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
339; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v4, v2, v2
340; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
341; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
342; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v2, v4
343; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
344; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
345; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
346; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
347; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
348;
349; GFX89-IEEE-LABEL: v_rcp_f32:
350; GFX89-IEEE:       ; %bb.0:
351; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
352; GFX89-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
353; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
354; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v3, v1
355; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
356; GFX89-IEEE-NEXT:    v_fma_f32 v3, v4, v3, v3
357; GFX89-IEEE-NEXT:    v_mul_f32_e32 v4, v2, v3
358; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v2
359; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v3, v4
360; GFX89-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v2
361; GFX89-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
362; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
363; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
364;
365; GFX89-FLUSH-LABEL: v_rcp_f32:
366; GFX89-FLUSH:       ; %bb.0:
367; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
368; GFX89-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
369; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
370; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v3, v1
371; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
372; GFX89-FLUSH-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
373; GFX89-FLUSH-NEXT:    v_fma_f32 v3, v4, v3, v3
374; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v3
375; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v2
376; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v3, v4
377; GFX89-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v2
378; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
379; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
380; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
381; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
382;
383; GFX10-IEEE-LABEL: v_rcp_f32:
384; GFX10-IEEE:       ; %bb.0:
385; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
386; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
387; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
388; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
389; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
390; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
391; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
392; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
393; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
394; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
395; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
396; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
397; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
398; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
399;
400; GFX10-FLUSH-LABEL: v_rcp_f32:
401; GFX10-FLUSH:       ; %bb.0:
402; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
403; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
404; GFX10-FLUSH-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
405; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
406; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
407; GFX10-FLUSH-NEXT:    s_denorm_mode 3
408; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
409; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
410; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
411; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
412; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
413; GFX10-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
414; GFX10-FLUSH-NEXT:    s_denorm_mode 0
415; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
416; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
417; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
418;
419; GFX11-IEEE-LABEL: v_rcp_f32:
420; GFX11-IEEE:       ; %bb.0:
421; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
422; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
423; GFX11-IEEE-NEXT:    v_div_scale_f32 v1, null, v0, v0, 1.0
424; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
425; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
426; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
427; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
428; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
429; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
430; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
431; GFX11-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
432; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
433; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
434; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
435; GFX11-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
436; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
437; GFX11-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
438; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
439; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
440;
441; GFX11-FLUSH-LABEL: v_rcp_f32:
442; GFX11-FLUSH:       ; %bb.0:
443; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
444; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
445; GFX11-FLUSH-NEXT:    v_div_scale_f32 v1, null, v0, v0, 1.0
446; GFX11-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
447; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
448; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
449; GFX11-FLUSH-NEXT:    s_denorm_mode 3
450; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
451; GFX11-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
452; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
453; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
454; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
455; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
456; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
457; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
458; GFX11-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
459; GFX11-FLUSH-NEXT:    s_denorm_mode 0
460; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
461; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
462; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
463; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
464  %fdiv = fdiv float 1.0, %x
465  ret float %fdiv
466}
467
468define float @v_rcp_f32_arcp(float %x) {
469; GFX6-IEEE-LABEL: v_rcp_f32_arcp:
470; GFX6-IEEE:       ; %bb.0:
471; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
472; GFX6-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
473; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
474; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
475; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
476; GFX6-IEEE-NEXT:    v_fma_f32 v2, v4, v2, v2
477; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v3, v2
478; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v3
479; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v2, v4
480; GFX6-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v3
481; GFX6-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
482; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
483; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
484;
485; GFX6-FLUSH-LABEL: v_rcp_f32_arcp:
486; GFX6-FLUSH:       ; %bb.0:
487; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
488; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
489; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
490; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
491; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
492; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
493; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v4, v2, v2
494; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
495; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
496; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v2, v4
497; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
498; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
499; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
500; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
501; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
502;
503; GFX89-IEEE-LABEL: v_rcp_f32_arcp:
504; GFX89-IEEE:       ; %bb.0:
505; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
506; GFX89-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
507; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
508; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v3, v1
509; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
510; GFX89-IEEE-NEXT:    v_fma_f32 v3, v4, v3, v3
511; GFX89-IEEE-NEXT:    v_mul_f32_e32 v4, v2, v3
512; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v2
513; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v3, v4
514; GFX89-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v2
515; GFX89-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
516; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
517; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
518;
519; GFX89-FLUSH-LABEL: v_rcp_f32_arcp:
520; GFX89-FLUSH:       ; %bb.0:
521; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
522; GFX89-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
523; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
524; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v3, v1
525; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
526; GFX89-FLUSH-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
527; GFX89-FLUSH-NEXT:    v_fma_f32 v3, v4, v3, v3
528; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v3
529; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v2
530; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v3, v4
531; GFX89-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v2
532; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
533; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
534; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
535; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
536;
537; GFX10-IEEE-LABEL: v_rcp_f32_arcp:
538; GFX10-IEEE:       ; %bb.0:
539; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
540; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
541; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
542; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
543; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
544; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
545; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
546; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
547; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
548; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
549; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
550; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
551; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
552; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
553;
554; GFX10-FLUSH-LABEL: v_rcp_f32_arcp:
555; GFX10-FLUSH:       ; %bb.0:
556; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
557; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
558; GFX10-FLUSH-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
559; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
560; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
561; GFX10-FLUSH-NEXT:    s_denorm_mode 3
562; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
563; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
564; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
565; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
566; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
567; GFX10-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
568; GFX10-FLUSH-NEXT:    s_denorm_mode 0
569; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
570; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
571; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
572;
573; GFX11-IEEE-LABEL: v_rcp_f32_arcp:
574; GFX11-IEEE:       ; %bb.0:
575; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
576; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
577; GFX11-IEEE-NEXT:    v_div_scale_f32 v1, null, v0, v0, 1.0
578; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
579; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
580; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
581; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
582; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
583; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
584; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
585; GFX11-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
586; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
587; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
588; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
589; GFX11-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
590; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
591; GFX11-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
592; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
593; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
594;
595; GFX11-FLUSH-LABEL: v_rcp_f32_arcp:
596; GFX11-FLUSH:       ; %bb.0:
597; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
598; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
599; GFX11-FLUSH-NEXT:    v_div_scale_f32 v1, null, v0, v0, 1.0
600; GFX11-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
601; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
602; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
603; GFX11-FLUSH-NEXT:    s_denorm_mode 3
604; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
605; GFX11-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
606; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
607; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
608; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
609; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
610; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
611; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
612; GFX11-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
613; GFX11-FLUSH-NEXT:    s_denorm_mode 0
614; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
615; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
616; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
617; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
618  %fdiv = fdiv arcp float 1.0, %x
619  ret float %fdiv
620}
621
622define float @v_rcp_f32_arcp_afn(float %x) {
623; GCN-LABEL: v_rcp_f32_arcp_afn:
624; GCN:       ; %bb.0:
625; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
626; GCN-NEXT:    v_rcp_f32_e32 v0, v0
627; GCN-NEXT:    s_setpc_b64 s[30:31]
628;
629; GFX10-LABEL: v_rcp_f32_arcp_afn:
630; GFX10:       ; %bb.0:
631; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
632; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
633; GFX10-NEXT:    v_rcp_f32_e32 v0, v0
634; GFX10-NEXT:    s_setpc_b64 s[30:31]
635;
636; GFX11-LABEL: v_rcp_f32_arcp_afn:
637; GFX11:       ; %bb.0:
638; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
639; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
640; GFX11-NEXT:    v_rcp_f32_e32 v0, v0
641; GFX11-NEXT:    s_setpc_b64 s[30:31]
642  %fdiv = fdiv arcp afn float 1.0, %x
643  ret float %fdiv
644}
645
646define float @v_rcp_f32_ulp25(float %x) {
647; GCN-IEEE-LABEL: v_rcp_f32_ulp25:
648; GCN-IEEE:       ; %bb.0:
649; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
650; GCN-IEEE-NEXT:    v_mov_b32_e32 v1, 0x6f800000
651; GCN-IEEE-NEXT:    v_mov_b32_e32 v2, 0x2f800000
652; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, v1
653; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
654; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
655; GCN-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
656; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
657; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
658; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
659;
660; GCN-FLUSH-LABEL: v_rcp_f32_ulp25:
661; GCN-FLUSH:       ; %bb.0:
662; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
663; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
664; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
665;
666; GFX10-IEEE-LABEL: v_rcp_f32_ulp25:
667; GFX10-IEEE:       ; %bb.0:
668; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
669; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
670; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
671; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s4
672; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
673; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
674; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
675; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
676; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
677;
678; GFX10-FLUSH-LABEL: v_rcp_f32_ulp25:
679; GFX10-FLUSH:       ; %bb.0:
680; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
681; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
682; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
683; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
684;
685; GFX11-IEEE-LABEL: v_rcp_f32_ulp25:
686; GFX11-IEEE:       ; %bb.0:
687; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
688; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
689; GFX11-IEEE-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v0|
690; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
691; GFX11-IEEE-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s0
692; GFX11-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
693; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
694; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
695; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
696; GFX11-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
697; GFX11-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
698; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
699;
700; GFX11-FLUSH-LABEL: v_rcp_f32_ulp25:
701; GFX11-FLUSH:       ; %bb.0:
702; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
703; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
704; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
705; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
706  %fdiv = fdiv float 1.0, %x, !fpmath !0
707  ret float %fdiv
708}
709
710define float @v_fdiv_f32_afn_ulp25(float %a, float %b) {
711; GCN-LABEL: v_fdiv_f32_afn_ulp25:
712; GCN:       ; %bb.0:
713; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
714; GCN-NEXT:    v_rcp_f32_e32 v1, v1
715; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
716; GCN-NEXT:    s_setpc_b64 s[30:31]
717;
718; GFX10-LABEL: v_fdiv_f32_afn_ulp25:
719; GFX10:       ; %bb.0:
720; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
721; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
722; GFX10-NEXT:    v_rcp_f32_e32 v1, v1
723; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
724; GFX10-NEXT:    s_setpc_b64 s[30:31]
725;
726; GFX11-LABEL: v_fdiv_f32_afn_ulp25:
727; GFX11:       ; %bb.0:
728; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
729; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
730; GFX11-NEXT:    v_rcp_f32_e32 v1, v1
731; GFX11-NEXT:    s_waitcnt_depctr 0xfff
732; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
733; GFX11-NEXT:    s_setpc_b64 s[30:31]
734  %fdiv = fdiv afn float %a, %b, !fpmath !0
735  ret float %fdiv
736}
737
738define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
739; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
740; GFX6-IEEE:       ; %bb.0:
741; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
742; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
743; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
744; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
745; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
746; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
747; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
748; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
749; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
750; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
751; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
752; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
753; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
754;
755; GCN-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
756; GCN-FLUSH:       ; %bb.0:
757; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
758; GCN-FLUSH-NEXT:    v_mov_b32_e32 v2, 0x6f800000
759; GCN-FLUSH-NEXT:    v_mov_b32_e32 v3, 0x2f800000
760; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, v2
761; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
762; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
763; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
764; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
765; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
766; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
767;
768; GFX89-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
769; GFX89-IEEE:       ; %bb.0:
770; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
771; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
772; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
773; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
774; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
775; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
776; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
777; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
778; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
779; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
780; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
781; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
782; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
783;
784; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
785; GFX10-IEEE:       ; %bb.0:
786; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
787; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
788; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
789; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
790; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
791; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
792; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
793; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
794; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
795; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
796; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
797; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
798; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
799; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
800;
801; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
802; GFX10-FLUSH:       ; %bb.0:
803; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
804; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
805; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
806; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
807; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
808; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
809; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
810; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
811; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
812;
813; GFX11-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
814; GFX11-IEEE:       ; %bb.0:
815; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
816; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
817; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v1, v1, v0
818; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
819; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
820; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
821; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
822; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
823; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
824; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
825; GFX11-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
826; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
827; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
828; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
829; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
830; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
831; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
832; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
833; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
834;
835; GFX11-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
836; GFX11-FLUSH:       ; %bb.0:
837; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
838; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
839; GFX11-FLUSH-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
840; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
841; GFX11-FLUSH-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
842; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
843; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
844; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
845; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
846; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
847; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
848; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
849  %fdiv = fdiv arcp float %a, %b, !fpmath !0
850  ret float %fdiv
851}
852
853define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
854; GFX6-IEEE-LABEL: v_fdiv_v2f32:
855; GFX6-IEEE:       ; %bb.0:
856; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
857; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
858; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
859; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
860; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
861; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
862; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
863; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
864; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
865; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
866; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
867; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
868; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
869; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
870; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
871; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
872; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
873; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
874; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
875; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
876; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
877; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
878; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
879; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
880;
881; GFX6-FLUSH-LABEL: v_fdiv_v2f32:
882; GFX6-FLUSH:       ; %bb.0:
883; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
884; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
885; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
886; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
887; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
888; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
889; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5
890; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
891; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
892; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
893; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
894; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
895; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
896; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
897; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v5
898; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
899; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
900; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
901; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
902; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v4, v6, v6
903; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v2, v4
904; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v5, v6, v2
905; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
906; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v5, v6, v2
907; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
908; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
909; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
910; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
911;
912; GFX89-IEEE-LABEL: v_fdiv_v2f32:
913; GFX89-IEEE:       ; %bb.0:
914; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
915; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
916; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
917; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
918; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
919; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
920; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
921; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
922; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
923; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
924; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
925; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
926; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
927; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
928; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
929; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
930; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
931; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
932; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
933; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
934; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
935; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
936; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
937; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
938; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
939;
940; GFX89-FLUSH-LABEL: v_fdiv_v2f32:
941; GFX89-FLUSH:       ; %bb.0:
942; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
943; GFX89-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
944; GFX89-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v0, v2, v0
945; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
946; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
947; GFX89-FLUSH-NEXT:    v_fma_f32 v7, -v4, v6, 1.0
948; GFX89-FLUSH-NEXT:    v_fma_f32 v6, v7, v6, v6
949; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v7, v5, v6
950; GFX89-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v5
951; GFX89-FLUSH-NEXT:    v_fma_f32 v7, v8, v6, v7
952; GFX89-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v5
953; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
954; GFX89-FLUSH-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
955; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
956; GFX89-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v1, v3, v1
957; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v7, v5
958; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
959; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
960; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v5, v7, 1.0
961; GFX89-FLUSH-NEXT:    v_fma_f32 v2, v2, v7, v7
962; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v4, v6, v2
963; GFX89-FLUSH-NEXT:    v_fma_f32 v7, -v5, v4, v6
964; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v7, v2, v4
965; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v5, v4, v6
966; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
967; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v5, v2, v4
968; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
969; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
970;
971; GFX10-IEEE-LABEL: v_fdiv_v2f32:
972; GFX10-IEEE:       ; %bb.0:
973; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
974; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
975; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
976; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
977; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
978; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
979; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
980; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
981; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
982; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
983; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
984; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
985; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
986; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
987; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
988; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
989; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
990; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
991; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
992; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
993; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
994; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
995; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
996; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
997; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
998; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
999;
1000; GFX10-FLUSH-LABEL: v_fdiv_v2f32:
1001; GFX10-FLUSH:       ; %bb.0:
1002; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1003; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1004; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
1005; GFX10-FLUSH-NEXT:    v_div_scale_f32 v6, vcc_lo, v0, v2, v0
1006; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
1007; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1008; GFX10-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1009; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v7, v5
1010; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
1011; GFX10-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
1012; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v7, v8, v5
1013; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
1014; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1015; GFX10-FLUSH-NEXT:    v_div_scale_f32 v6, s4, v3, v3, v1
1016; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
1017; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v5, v6
1018; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1019; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, v1, v3, v1
1020; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1021; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v6, v5, 1.0
1022; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v4, v5
1023; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v5
1024; GFX10-FLUSH-NEXT:    v_fma_f32 v7, -v6, v4, v2
1025; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v7, v5
1026; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v6, v4, v2
1027; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1028; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v5, v4
1029; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
1030; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1031;
1032; GFX11-IEEE-LABEL: v_fdiv_v2f32:
1033; GFX11-IEEE:       ; %bb.0:
1034; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1035; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1036; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
1037; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, null, v3, v3, v1
1038; GFX11-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1039; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1040; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1041; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1042; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1043; GFX11-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1044; GFX11-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1045; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1046; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
1047; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, s0, v1, v3, v1
1048; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1049; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1050; GFX11-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1051; GFX11-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1052; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1053; GFX11-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1054; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1055; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1056; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1057; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1058; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1059; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1060; GFX11-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1061; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1062; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1063; GFX11-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1064; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1065; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1066; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1067; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1068;
1069; GFX11-FLUSH-LABEL: v_fdiv_v2f32:
1070; GFX11-FLUSH:       ; %bb.0:
1071; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1072; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1073; GFX11-FLUSH-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
1074; GFX11-FLUSH-NEXT:    v_div_scale_f32 v6, vcc_lo, v0, v2, v0
1075; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1076; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
1077; GFX11-FLUSH-NEXT:    s_denorm_mode 3
1078; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1079; GFX11-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1080; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v7, v5
1081; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1082; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
1083; GFX11-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
1084; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1085; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v7, v8, v5
1086; GFX11-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
1087; GFX11-FLUSH-NEXT:    s_denorm_mode 0
1088; GFX11-FLUSH-NEXT:    v_div_scale_f32 v6, null, v3, v3, v1
1089; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1090; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
1091; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v5, v6
1092; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1093; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1094; GFX11-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, v1, v3, v1
1095; GFX11-FLUSH-NEXT:    s_denorm_mode 3
1096; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1097; GFX11-FLUSH-NEXT:    v_fma_f32 v4, -v6, v5, 1.0
1098; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v4, v5
1099; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1100; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v5
1101; GFX11-FLUSH-NEXT:    v_fma_f32 v7, -v6, v4, v2
1102; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1103; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v4, v7, v5
1104; GFX11-FLUSH-NEXT:    v_fma_f32 v2, -v6, v4, v2
1105; GFX11-FLUSH-NEXT:    s_denorm_mode 0
1106; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1107; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v5, v4
1108; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
1109; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1110  %fdiv = fdiv <2 x float> %a, %b
1111  ret <2 x float> %fdiv
1112}
1113
1114define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {
1115; GCN-LABEL: v_fdiv_v2f32_afn:
1116; GCN:       ; %bb.0:
1117; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1118; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1119; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1120; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
1121; GCN-NEXT:    v_mul_f32_e32 v1, v1, v3
1122; GCN-NEXT:    s_setpc_b64 s[30:31]
1123;
1124; GFX10-LABEL: v_fdiv_v2f32_afn:
1125; GFX10:       ; %bb.0:
1126; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1127; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1128; GFX10-NEXT:    v_rcp_f32_e32 v2, v2
1129; GFX10-NEXT:    v_rcp_f32_e32 v3, v3
1130; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
1131; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v3
1132; GFX10-NEXT:    s_setpc_b64 s[30:31]
1133;
1134; GFX11-LABEL: v_fdiv_v2f32_afn:
1135; GFX11:       ; %bb.0:
1136; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1137; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
1138; GFX11-NEXT:    v_rcp_f32_e32 v2, v2
1139; GFX11-NEXT:    v_rcp_f32_e32 v3, v3
1140; GFX11-NEXT:    s_waitcnt_depctr 0xfff
1141; GFX11-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
1142; GFX11-NEXT:    s_setpc_b64 s[30:31]
1143  %fdiv = fdiv afn <2 x float> %a, %b
1144  ret <2 x float> %fdiv
1145}
1146
1147define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
1148; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1149; GFX6-IEEE:       ; %bb.0:
1150; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1151; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1152; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
1153; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1154; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1155; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
1156; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
1157; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
1158; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
1159; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
1160; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
1161; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1162; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
1163; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1164; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
1165; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
1166; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
1167; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
1168; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
1169; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1170; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
1171; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
1172; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
1173; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1174;
1175; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
1176; GCN-FLUSH:       ; %bb.0:
1177; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1178; GCN-FLUSH-NEXT:    s_mov_b32 s4, 0x6f800000
1179; GCN-FLUSH-NEXT:    v_mov_b32_e32 v4, 0x2f800000
1180; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v2|, s4
1181; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
1182; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v3|, s4
1183; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
1184; GCN-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v5
1185; GCN-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v4
1186; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
1187; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
1188; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
1189; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
1190; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v5, v0
1191; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v4, v1
1192; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1193;
1194; GFX89-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1195; GFX89-IEEE:       ; %bb.0:
1196; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1197; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1198; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1199; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1200; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
1201; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
1202; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
1203; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
1204; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
1205; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
1206; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
1207; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
1208; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
1209; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
1210; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
1211; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
1212; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
1213; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
1214; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
1215; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
1216; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1217; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
1218; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1219; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1220; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1221;
1222; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1223; GFX10-IEEE:       ; %bb.0:
1224; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1225; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1226; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
1227; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
1228; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1229; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1230; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1231; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1232; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1233; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
1234; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
1235; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
1236; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1237; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1238; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1239; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1240; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1241; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1242; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1243; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1244; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1245; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1246; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1247; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1248; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1249; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1250;
1251; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
1252; GFX10-FLUSH:       ; %bb.0:
1253; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1254; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1255; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
1256; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
1257; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
1258; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v4
1259; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
1260; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
1261; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v5
1262; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
1263; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
1264; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v4, v0
1265; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
1266; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v5, v1
1267; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1268;
1269; GFX11-IEEE-LABEL: v_fdiv_v2f32_ulp25:
1270; GFX11-IEEE:       ; %bb.0:
1271; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1272; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1273; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
1274; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, null, v3, v3, v1
1275; GFX11-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1276; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1277; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1278; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1279; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1280; GFX11-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1281; GFX11-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1282; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1283; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
1284; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, s0, v1, v3, v1
1285; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1286; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1287; GFX11-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1288; GFX11-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1289; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1290; GFX11-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1291; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1292; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1293; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1294; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1295; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1296; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1297; GFX11-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1298; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1299; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1300; GFX11-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1301; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1302; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1303; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1304; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1305;
1306; GFX11-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
1307; GFX11-FLUSH:       ; %bb.0:
1308; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1309; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1310; GFX11-FLUSH-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v2|
1311; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
1312; GFX11-FLUSH-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s0
1313; GFX11-FLUSH-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v3|
1314; GFX11-FLUSH-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s0
1315; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1316; GFX11-FLUSH-NEXT:    v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v3, v3, v5
1317; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
1318; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
1319; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
1320; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1321; GFX11-FLUSH-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
1322; GFX11-FLUSH-NEXT:    v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
1323; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1324  %fdiv = fdiv <2 x float> %a, %b, !fpmath !0
1325  ret <2 x float> %fdiv
1326}
1327
1328define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
1329; GFX6-IEEE-LABEL: v_rcp_v2f32:
1330; GFX6-IEEE:       ; %bb.0:
1331; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1332; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1333; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
1334; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1335; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1336; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
1337; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
1338; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
1339; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
1340; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
1341; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1342; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1343; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1344; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1345; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1346; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1347; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
1348; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
1349; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
1350; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
1351; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
1352; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1353; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1354; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1355;
1356; GFX6-FLUSH-LABEL: v_rcp_v2f32:
1357; GFX6-FLUSH:       ; %bb.0:
1358; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1359; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1360; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1361; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1362; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1363; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1364; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
1365; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1366; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1367; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
1368; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1369; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1370; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1371; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1372; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
1373; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1374; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1375; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1376; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1377; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1378; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
1379; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
1380; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1381; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
1382; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1383; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1384; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1385; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1386;
1387; GFX89-IEEE-LABEL: v_rcp_v2f32:
1388; GFX89-IEEE:       ; %bb.0:
1389; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1390; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1391; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1392; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1393; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
1394; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v6, v2
1395; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v7, v3
1396; GFX89-IEEE-NEXT:    v_fma_f32 v8, -v2, v6, 1.0
1397; GFX89-IEEE-NEXT:    v_fma_f32 v6, v8, v6, v6
1398; GFX89-IEEE-NEXT:    v_fma_f32 v9, -v3, v7, 1.0
1399; GFX89-IEEE-NEXT:    v_fma_f32 v7, v9, v7, v7
1400; GFX89-IEEE-NEXT:    v_mul_f32_e32 v8, v4, v6
1401; GFX89-IEEE-NEXT:    v_mul_f32_e32 v9, v5, v7
1402; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v2, v8, v4
1403; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v5
1404; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v6, v8
1405; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v7, v9
1406; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v8, v4
1407; GFX89-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v5
1408; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v6, v8
1409; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1410; GFX89-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v7, v9
1411; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1412; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1413; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1414;
1415; GFX89-FLUSH-LABEL: v_rcp_v2f32:
1416; GFX89-FLUSH:       ; %bb.0:
1417; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1418; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1419; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
1420; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
1421; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1422; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
1423; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1424; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
1425; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v3
1426; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1427; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v3
1428; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1429; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1430; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1431; GFX89-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
1432; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v5, v3
1433; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1434; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1435; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, 1.0
1436; GFX89-FLUSH-NEXT:    v_fma_f32 v2, v2, v5, v5
1437; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v2
1438; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v4
1439; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v2, v5
1440; GFX89-FLUSH-NEXT:    v_fma_f32 v3, -v3, v5, v4
1441; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1442; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v3, v2, v5
1443; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1444; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1445;
1446; GFX10-IEEE-LABEL: v_rcp_v2f32:
1447; GFX10-IEEE:       ; %bb.0:
1448; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1449; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1450; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1451; GFX10-IEEE-NEXT:    v_div_scale_f32 v3, s4, v1, v1, 1.0
1452; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1453; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1454; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1455; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1456; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1457; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
1458; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
1459; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
1460; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1461; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1462; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1463; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1464; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1465; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1466; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1467; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1468; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1469; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1470; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1471; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1472; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1473; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1474;
1475; GFX10-FLUSH-LABEL: v_rcp_v2f32:
1476; GFX10-FLUSH:       ; %bb.0:
1477; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1478; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1479; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1480; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1481; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1482; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1483; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1484; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1485; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1486; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1487; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1488; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1489; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1490; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v1, v1, 1.0
1491; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1492; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
1493; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1494; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
1495; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1496; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
1497; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1498; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
1499; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
1500; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1501; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
1502; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1503; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1504; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1505; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1506;
1507; GFX11-IEEE-LABEL: v_rcp_v2f32:
1508; GFX11-IEEE:       ; %bb.0:
1509; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1510; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1511; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v0, v0, 1.0
1512; GFX11-IEEE-NEXT:    v_div_scale_f32 v3, null, v1, v1, 1.0
1513; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1514; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1515; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1516; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1517; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1518; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1519; GFX11-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1520; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1521; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
1522; GFX11-IEEE-NEXT:    v_div_scale_f32 v6, s0, 1.0, v1, 1.0
1523; GFX11-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1524; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1525; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1526; GFX11-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1527; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1528; GFX11-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1529; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1530; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1531; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1532; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1533; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1534; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1535; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1536; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1537; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1538; GFX11-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1539; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1540; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1541; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1542; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1543;
1544; GFX11-FLUSH-LABEL: v_rcp_v2f32:
1545; GFX11-FLUSH:       ; %bb.0:
1546; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1547; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1548; GFX11-FLUSH-NEXT:    v_div_scale_f32 v2, null, v0, v0, 1.0
1549; GFX11-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1550; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1551; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1552; GFX11-FLUSH-NEXT:    s_denorm_mode 3
1553; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1554; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1555; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1556; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1557; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1558; GFX11-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1559; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1560; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1561; GFX11-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1562; GFX11-FLUSH-NEXT:    s_denorm_mode 0
1563; GFX11-FLUSH-NEXT:    v_div_scale_f32 v4, null, v1, v1, 1.0
1564; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1565; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1566; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
1567; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1568; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1569; GFX11-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
1570; GFX11-FLUSH-NEXT:    s_denorm_mode 3
1571; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1572; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
1573; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1574; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1575; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
1576; GFX11-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
1577; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1578; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1579; GFX11-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
1580; GFX11-FLUSH-NEXT:    s_denorm_mode 0
1581; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1582; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1583; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1584; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1585  %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x
1586  ret <2 x float> %fdiv
1587}
1588
1589define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
1590; GFX6-IEEE-LABEL: v_rcp_v2f32_arcp:
1591; GFX6-IEEE:       ; %bb.0:
1592; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1593; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1594; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
1595; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1596; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1597; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
1598; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
1599; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
1600; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
1601; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
1602; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1603; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1604; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1605; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1606; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1607; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1608; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
1609; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
1610; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
1611; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
1612; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
1613; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1614; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1615; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1616;
1617; GFX6-FLUSH-LABEL: v_rcp_v2f32_arcp:
1618; GFX6-FLUSH:       ; %bb.0:
1619; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1620; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1621; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1622; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1623; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1624; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1625; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
1626; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1627; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1628; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
1629; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1630; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1631; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1632; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1633; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
1634; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1635; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1636; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1637; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1638; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1639; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
1640; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
1641; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1642; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
1643; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1644; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1645; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1646; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1647;
1648; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:
1649; GFX89-IEEE:       ; %bb.0:
1650; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1651; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1652; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1653; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1654; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
1655; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v6, v2
1656; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v7, v3
1657; GFX89-IEEE-NEXT:    v_fma_f32 v8, -v2, v6, 1.0
1658; GFX89-IEEE-NEXT:    v_fma_f32 v6, v8, v6, v6
1659; GFX89-IEEE-NEXT:    v_fma_f32 v9, -v3, v7, 1.0
1660; GFX89-IEEE-NEXT:    v_fma_f32 v7, v9, v7, v7
1661; GFX89-IEEE-NEXT:    v_mul_f32_e32 v8, v4, v6
1662; GFX89-IEEE-NEXT:    v_mul_f32_e32 v9, v5, v7
1663; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v2, v8, v4
1664; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v5
1665; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v6, v8
1666; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v7, v9
1667; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v8, v4
1668; GFX89-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v5
1669; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v6, v8
1670; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1671; GFX89-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v7, v9
1672; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1673; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1674; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1675;
1676; GFX89-FLUSH-LABEL: v_rcp_v2f32_arcp:
1677; GFX89-FLUSH:       ; %bb.0:
1678; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1679; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1680; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
1681; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
1682; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1683; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
1684; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1685; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
1686; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v3
1687; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1688; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v3
1689; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1690; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1691; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1692; GFX89-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
1693; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v5, v3
1694; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1695; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1696; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, 1.0
1697; GFX89-FLUSH-NEXT:    v_fma_f32 v2, v2, v5, v5
1698; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v2
1699; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v4
1700; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v2, v5
1701; GFX89-FLUSH-NEXT:    v_fma_f32 v3, -v3, v5, v4
1702; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1703; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v3, v2, v5
1704; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1705; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1706;
1707; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp:
1708; GFX10-IEEE:       ; %bb.0:
1709; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1710; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1711; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1712; GFX10-IEEE-NEXT:    v_div_scale_f32 v3, s4, v1, v1, 1.0
1713; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1714; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1715; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1716; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1717; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1718; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
1719; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
1720; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
1721; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1722; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1723; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1724; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1725; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1726; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1727; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1728; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1729; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1730; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1731; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1732; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1733; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1734; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1735;
1736; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp:
1737; GFX10-FLUSH:       ; %bb.0:
1738; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1739; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1740; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1741; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1742; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1743; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1744; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1745; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1746; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1747; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1748; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1749; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1750; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1751; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v1, v1, 1.0
1752; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1753; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
1754; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1755; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
1756; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1757; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
1758; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1759; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
1760; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
1761; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1762; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
1763; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1764; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1765; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1766; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1767;
1768; GFX11-IEEE-LABEL: v_rcp_v2f32_arcp:
1769; GFX11-IEEE:       ; %bb.0:
1770; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1771; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1772; GFX11-IEEE-NEXT:    v_div_scale_f32 v2, null, v0, v0, 1.0
1773; GFX11-IEEE-NEXT:    v_div_scale_f32 v3, null, v1, v1, 1.0
1774; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1775; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
1776; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1777; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1778; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1779; GFX11-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1780; GFX11-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1781; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1782; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
1783; GFX11-IEEE-NEXT:    v_div_scale_f32 v6, s0, 1.0, v1, 1.0
1784; GFX11-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1785; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1786; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1787; GFX11-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1788; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1789; GFX11-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1790; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1791; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1792; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1793; GFX11-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1794; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1795; GFX11-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1796; GFX11-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1797; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
1798; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1799; GFX11-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1800; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1801; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
1802; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1803; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1804;
1805; GFX11-FLUSH-LABEL: v_rcp_v2f32_arcp:
1806; GFX11-FLUSH:       ; %bb.0:
1807; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1808; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1809; GFX11-FLUSH-NEXT:    v_div_scale_f32 v2, null, v0, v0, 1.0
1810; GFX11-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1811; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1812; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1813; GFX11-FLUSH-NEXT:    s_denorm_mode 3
1814; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1815; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1816; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1817; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1818; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1819; GFX11-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1820; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1821; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1822; GFX11-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1823; GFX11-FLUSH-NEXT:    s_denorm_mode 0
1824; GFX11-FLUSH-NEXT:    v_div_scale_f32 v4, null, v1, v1, 1.0
1825; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1826; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1827; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
1828; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1829; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1830; GFX11-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
1831; GFX11-FLUSH-NEXT:    s_denorm_mode 3
1832; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
1833; GFX11-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
1834; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1835; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1836; GFX11-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
1837; GFX11-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
1838; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1839; GFX11-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1840; GFX11-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
1841; GFX11-FLUSH-NEXT:    s_denorm_mode 0
1842; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1843; GFX11-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1844; GFX11-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1845; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1846  %fdiv = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x
1847  ret <2 x float> %fdiv
1848}
1849
1850define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) {
1851; GCN-LABEL: v_rcp_v2f32_arcp_afn:
1852; GCN:       ; %bb.0:
1853; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1854; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1855; GCN-NEXT:    v_rcp_f32_e32 v1, v1
1856; GCN-NEXT:    s_setpc_b64 s[30:31]
1857;
1858; GFX10-LABEL: v_rcp_v2f32_arcp_afn:
1859; GFX10:       ; %bb.0:
1860; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1861; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1862; GFX10-NEXT:    v_rcp_f32_e32 v0, v0
1863; GFX10-NEXT:    v_rcp_f32_e32 v1, v1
1864; GFX10-NEXT:    s_setpc_b64 s[30:31]
1865;
1866; GFX11-LABEL: v_rcp_v2f32_arcp_afn:
1867; GFX11:       ; %bb.0:
1868; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1869; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
1870; GFX11-NEXT:    v_rcp_f32_e32 v0, v0
1871; GFX11-NEXT:    v_rcp_f32_e32 v1, v1
1872; GFX11-NEXT:    s_setpc_b64 s[30:31]
1873  %fdiv = fdiv arcp afn <2 x float> <float 1.0, float 1.0>, %x
1874  ret <2 x float> %fdiv
1875}
1876
1877define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) {
1878; GCN-IEEE-LABEL: v_rcp_v2f32_ulp25:
1879; GCN-IEEE:       ; %bb.0:
1880; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1881; GCN-IEEE-NEXT:    s_mov_b32 s4, 0x6f800000
1882; GCN-IEEE-NEXT:    v_mov_b32_e32 v2, 0x2f800000
1883; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, s4
1884; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v3, 1.0, v2, vcc
1885; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, s4
1886; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
1887; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v3
1888; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, v1, v2
1889; GCN-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1890; GCN-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1891; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
1892; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, 1.0, v1
1893; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v3, v0
1894; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, v2, v1
1895; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
1896;
1897; GCN-FLUSH-LABEL: v_rcp_v2f32_ulp25:
1898; GCN-FLUSH:       ; %bb.0:
1899; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1900; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
1901; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
1902; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1903;
1904; GFX10-IEEE-LABEL: v_rcp_v2f32_ulp25:
1905; GFX10-IEEE:       ; %bb.0:
1906; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1907; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1908; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
1909; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
1910; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
1911; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v2
1912; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s4
1913; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1914; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, v1, v3
1915; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1916; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
1917; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v2, v0
1918; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, 1.0, v1
1919; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, v3, v1
1920; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1921;
1922; GFX10-FLUSH-LABEL: v_rcp_v2f32_ulp25:
1923; GFX10-FLUSH:       ; %bb.0:
1924; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1925; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1926; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
1927; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
1928; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1929;
1930; GFX11-IEEE-LABEL: v_rcp_v2f32_ulp25:
1931; GFX11-IEEE:       ; %bb.0:
1932; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1933; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1934; GFX11-IEEE-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v0|
1935; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
1936; GFX11-IEEE-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
1937; GFX11-IEEE-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
1938; GFX11-IEEE-NEXT:    v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s0
1939; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1940; GFX11-IEEE-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
1941; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1942; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
1943; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1944; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
1945; GFX11-IEEE-NEXT:    v_dual_mul_f32 v0, 1.0, v0 :: v_dual_mul_f32 v1, 1.0, v1
1946; GFX11-IEEE-NEXT:    v_dual_mul_f32 v0, v2, v0 :: v_dual_mul_f32 v1, v3, v1
1947; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
1948;
1949; GFX11-FLUSH-LABEL: v_rcp_v2f32_ulp25:
1950; GFX11-FLUSH:       ; %bb.0:
1951; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1952; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1953; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
1954; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
1955; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1956  %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x, !fpmath !0
1957  ret <2 x float> %fdiv
1958}
1959
1960define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) {
1961; GCN-LABEL: v_fdiv_v2f32_afn_ulp25:
1962; GCN:       ; %bb.0:
1963; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1964; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1965; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1966; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
1967; GCN-NEXT:    v_mul_f32_e32 v1, v1, v3
1968; GCN-NEXT:    s_setpc_b64 s[30:31]
1969;
1970; GFX10-LABEL: v_fdiv_v2f32_afn_ulp25:
1971; GFX10:       ; %bb.0:
1972; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1973; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1974; GFX10-NEXT:    v_rcp_f32_e32 v2, v2
1975; GFX10-NEXT:    v_rcp_f32_e32 v3, v3
1976; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
1977; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v3
1978; GFX10-NEXT:    s_setpc_b64 s[30:31]
1979;
1980; GFX11-LABEL: v_fdiv_v2f32_afn_ulp25:
1981; GFX11:       ; %bb.0:
1982; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1983; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
1984; GFX11-NEXT:    v_rcp_f32_e32 v2, v2
1985; GFX11-NEXT:    v_rcp_f32_e32 v3, v3
1986; GFX11-NEXT:    s_waitcnt_depctr 0xfff
1987; GFX11-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
1988; GFX11-NEXT:    s_setpc_b64 s[30:31]
1989  %fdiv = fdiv afn <2 x float> %a, %b, !fpmath !0
1990  ret <2 x float> %fdiv
1991}
1992
1993define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
1994; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
1995; GFX6-IEEE:       ; %bb.0:
1996; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1997; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1998; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
1999; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
2000; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
2001; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
2002; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
2003; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
2004; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
2005; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
2006; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
2007; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
2008; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
2009; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2010; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
2011; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
2012; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
2013; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
2014; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
2015; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
2016; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
2017; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
2018; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
2019; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
2020;
2021; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
2022; GCN-FLUSH:       ; %bb.0:
2023; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2024; GCN-FLUSH-NEXT:    s_mov_b32 s4, 0x6f800000
2025; GCN-FLUSH-NEXT:    v_mov_b32_e32 v4, 0x2f800000
2026; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v2|, s4
2027; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
2028; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v3|, s4
2029; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
2030; GCN-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v5
2031; GCN-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v4
2032; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
2033; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
2034; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
2035; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
2036; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v5, v0
2037; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v4, v1
2038; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
2039;
2040; GFX89-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
2041; GFX89-IEEE:       ; %bb.0:
2042; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2043; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
2044; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
2045; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
2046; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
2047; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
2048; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
2049; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
2050; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
2051; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
2052; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
2053; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
2054; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
2055; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
2056; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
2057; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
2058; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
2059; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
2060; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
2061; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
2062; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
2063; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
2064; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2065; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
2066; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
2067;
2068; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
2069; GFX10-IEEE:       ; %bb.0:
2070; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2071; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
2072; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
2073; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
2074; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
2075; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
2076; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
2077; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
2078; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
2079; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
2080; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
2081; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
2082; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
2083; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
2084; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
2085; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
2086; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
2087; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
2088; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
2089; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
2090; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
2091; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
2092; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
2093; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2094; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
2095; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
2096;
2097; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
2098; GFX10-FLUSH:       ; %bb.0:
2099; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2100; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
2101; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
2102; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
2103; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
2104; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v4
2105; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
2106; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
2107; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v5
2108; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
2109; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
2110; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v4, v0
2111; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
2112; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v5, v1
2113; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
2114;
2115; GFX11-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
2116; GFX11-IEEE:       ; %bb.0:
2117; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2118; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
2119; GFX11-IEEE-NEXT:    v_div_scale_f32 v4, null, v2, v2, v0
2120; GFX11-IEEE-NEXT:    v_div_scale_f32 v5, null, v3, v3, v1
2121; GFX11-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
2122; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
2123; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
2124; GFX11-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
2125; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
2126; GFX11-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
2127; GFX11-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
2128; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
2129; GFX11-IEEE-NEXT:    v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
2130; GFX11-IEEE-NEXT:    v_div_scale_f32 v8, s0, v1, v3, v1
2131; GFX11-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
2132; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2133; GFX11-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
2134; GFX11-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
2135; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2136; GFX11-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
2137; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
2138; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2139; GFX11-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
2140; GFX11-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
2141; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2142; GFX11-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
2143; GFX11-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
2144; GFX11-IEEE-NEXT:    s_mov_b32 vcc_lo, s0
2145; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
2146; GFX11-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
2147; GFX11-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
2148; GFX11-IEEE-NEXT:    s_delay_alu instid0(VALU_DEP_2)
2149; GFX11-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
2150; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
2151;
2152; GFX11-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
2153; GFX11-FLUSH:       ; %bb.0:
2154; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2155; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
2156; GFX11-FLUSH-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v2|
2157; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
2158; GFX11-FLUSH-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s0
2159; GFX11-FLUSH-NEXT:    v_cmp_lt_f32_e64 s0, 0x6f800000, |v3|
2160; GFX11-FLUSH-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s0
2161; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
2162; GFX11-FLUSH-NEXT:    v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v3, v3, v5
2163; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
2164; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
2165; GFX11-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
2166; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
2167; GFX11-FLUSH-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
2168; GFX11-FLUSH-NEXT:    v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
2169; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
2170  %fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
2171  ret <2 x float> %fdiv
2172}
2173
2174define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) {
2175; GCN-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
2176; GCN:       ; %bb.0:
2177; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2178; GCN-NEXT:    v_rcp_f32_e32 v2, v2
2179; GCN-NEXT:    v_rcp_f32_e32 v3, v3
2180; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
2181; GCN-NEXT:    v_mul_f32_e32 v1, v1, v3
2182; GCN-NEXT:    s_setpc_b64 s[30:31]
2183;
2184; GFX10-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
2185; GFX10:       ; %bb.0:
2186; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2187; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
2188; GFX10-NEXT:    v_rcp_f32_e32 v2, v2
2189; GFX10-NEXT:    v_rcp_f32_e32 v3, v3
2190; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
2191; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v3
2192; GFX10-NEXT:    s_setpc_b64 s[30:31]
2193;
2194; GFX11-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
2195; GFX11:       ; %bb.0:
2196; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2197; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
2198; GFX11-NEXT:    v_rcp_f32_e32 v2, v2
2199; GFX11-NEXT:    v_rcp_f32_e32 v3, v3
2200; GFX11-NEXT:    s_waitcnt_depctr 0xfff
2201; GFX11-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
2202; GFX11-NEXT:    s_setpc_b64 s[30:31]
2203  %fdiv = fdiv afn arcp <2 x float> %a, %b, !fpmath !0
2204  ret <2 x float> %fdiv
2205}
2206
2207!0 = !{float 2.500000e+00}
2208