1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE %s
3; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH %s
4
5; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
6; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
7
8; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
9; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
10
11; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s
12; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
13
14define float @v_fdiv_f32(float %a, float %b) {
15; GFX6-IEEE-LABEL: v_fdiv_f32:
16; GFX6-IEEE:       ; %bb.0:
17; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
18; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
19; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
20; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
21; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
22; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
23; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
24; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
25; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
26; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
27; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
28; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
29; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
30;
31; GFX6-FLUSH-LABEL: v_fdiv_f32:
32; GFX6-FLUSH:       ; %bb.0:
33; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
34; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
35; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
36; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
37; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
38; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
39; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
40; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
41; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
42; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
43; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
44; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
45; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
46; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
47; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
48;
49; GFX89-IEEE-LABEL: v_fdiv_f32:
50; GFX89-IEEE:       ; %bb.0:
51; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
52; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
53; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
54; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
55; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
56; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
57; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
58; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
59; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
60; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
61; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
62; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
63; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
64;
65; GFX89-FLUSH-LABEL: v_fdiv_f32:
66; GFX89-FLUSH:       ; %bb.0:
67; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
68; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
69; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
70; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
71; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
72; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
73; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
74; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
75; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v3
76; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
77; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v3
78; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
79; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
80; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
81; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
82;
83; GFX10-IEEE-LABEL: v_fdiv_f32:
84; GFX10-IEEE:       ; %bb.0:
85; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
87; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
88; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
89; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
90; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
91; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
92; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
93; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
94; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
95; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
96; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
97; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
98; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
99;
100; GFX10-FLUSH-LABEL: v_fdiv_f32:
101; GFX10-FLUSH:       ; %bb.0:
102; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
103; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
104; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
105; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, v0, v1, v0
106; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
107; GFX10-FLUSH-NEXT:    s_denorm_mode 3
108; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
109; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
110; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
111; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
112; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
113; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
114; GFX10-FLUSH-NEXT:    s_denorm_mode 0
115; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
116; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
117; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
118  %fdiv = fdiv float %a, %b
119  ret float %fdiv
120}
121
122define float @v_fdiv_f32_afn(float %a, float %b) {
123; GCN-LABEL: v_fdiv_f32_afn:
124; GCN:       ; %bb.0:
125; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
126; GCN-NEXT:    v_rcp_f32_e32 v1, v1
127; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
128; GCN-NEXT:    s_setpc_b64 s[30:31]
129;
130; GFX10-LABEL: v_fdiv_f32_afn:
131; GFX10:       ; %bb.0:
132; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
133; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
134; GFX10-NEXT:    v_rcp_f32_e32 v1, v1
135; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
136; GFX10-NEXT:    s_setpc_b64 s[30:31]
137  %fdiv = fdiv afn float %a, %b
138  ret float %fdiv
139}
140
141define float @v_fdiv_f32_ulp25(float %a, float %b) {
142; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:
143; GFX6-IEEE:       ; %bb.0:
144; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
145; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
146; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
147; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
148; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
149; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
150; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
151; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
152; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
153; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
154; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
155; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
156; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
157;
158; GCN-FLUSH-LABEL: v_fdiv_f32_ulp25:
159; GCN-FLUSH:       ; %bb.0:
160; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
161; GCN-FLUSH-NEXT:    v_mov_b32_e32 v2, 0x6f800000
162; GCN-FLUSH-NEXT:    v_mov_b32_e32 v3, 0x2f800000
163; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, v2
164; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
165; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
166; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
167; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
168; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
169; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
170;
171; GFX89-IEEE-LABEL: v_fdiv_f32_ulp25:
172; GFX89-IEEE:       ; %bb.0:
173; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
174; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
175; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
176; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
177; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
178; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
179; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
180; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
181; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
182; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
183; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
184; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
185; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
186;
187; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25:
188; GFX10-IEEE:       ; %bb.0:
189; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
190; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
191; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
192; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
193; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
194; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
195; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
196; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
197; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
198; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
199; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
200; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
201; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
202; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
203;
204; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25:
205; GFX10-FLUSH:       ; %bb.0:
206; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
207; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
208; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
209; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
210; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
211; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
212; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
213; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
214; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
215  %fdiv = fdiv float %a, %b, !fpmath !0
216  ret float %fdiv
217}
218
219define float @v_rcp_f32(float %x) {
220; GFX6-IEEE-LABEL: v_rcp_f32:
221; GFX6-IEEE:       ; %bb.0:
222; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
223; GFX6-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
224; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
225; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
226; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
227; GFX6-IEEE-NEXT:    v_fma_f32 v2, v4, v2, v2
228; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v3, v2
229; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v3
230; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v2, v4
231; GFX6-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v3
232; GFX6-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
233; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
234; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
235;
236; GFX6-FLUSH-LABEL: v_rcp_f32:
237; GFX6-FLUSH:       ; %bb.0:
238; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
239; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
240; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
241; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
242; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
243; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
244; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v4, v2, v2
245; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
246; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
247; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v2, v4
248; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
249; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
250; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
251; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
252; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
253;
254; GFX89-IEEE-LABEL: v_rcp_f32:
255; GFX89-IEEE:       ; %bb.0:
256; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
257; GFX89-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
258; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
259; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v3, v1
260; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
261; GFX89-IEEE-NEXT:    v_fma_f32 v3, v4, v3, v3
262; GFX89-IEEE-NEXT:    v_mul_f32_e32 v4, v2, v3
263; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v2
264; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v3, v4
265; GFX89-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v2
266; GFX89-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
267; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
268; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
269;
270; GFX89-FLUSH-LABEL: v_rcp_f32:
271; GFX89-FLUSH:       ; %bb.0:
272; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
273; GFX89-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
274; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
275; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v3, v1
276; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
277; GFX89-FLUSH-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
278; GFX89-FLUSH-NEXT:    v_fma_f32 v3, v4, v3, v3
279; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v3
280; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v2
281; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v3, v4
282; GFX89-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v2
283; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
284; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
285; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
286; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
287;
288; GFX10-IEEE-LABEL: v_rcp_f32:
289; GFX10-IEEE:       ; %bb.0:
290; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
291; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
292; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
293; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
294; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
295; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
296; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
297; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
298; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
299; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
300; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
301; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
302; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
303; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
304;
305; GFX10-FLUSH-LABEL: v_rcp_f32:
306; GFX10-FLUSH:       ; %bb.0:
307; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
308; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
309; GFX10-FLUSH-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
310; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
311; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
312; GFX10-FLUSH-NEXT:    s_denorm_mode 3
313; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
314; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
315; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
316; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
317; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
318; GFX10-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
319; GFX10-FLUSH-NEXT:    s_denorm_mode 0
320; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
321; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
322; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
323  %fdiv = fdiv float 1.0, %x
324  ret float %fdiv
325}
326
327define float @v_rcp_f32_arcp(float %x) {
328; GFX6-IEEE-LABEL: v_rcp_f32_arcp:
329; GFX6-IEEE:       ; %bb.0:
330; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
331; GFX6-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
332; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
333; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
334; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
335; GFX6-IEEE-NEXT:    v_fma_f32 v2, v4, v2, v2
336; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v3, v2
337; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v3
338; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v2, v4
339; GFX6-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v3
340; GFX6-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
341; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
342; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
343;
344; GFX6-FLUSH-LABEL: v_rcp_f32_arcp:
345; GFX6-FLUSH:       ; %bb.0:
346; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
347; GFX6-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
348; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
349; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
350; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
351; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
352; GFX6-FLUSH-NEXT:    v_fma_f32 v2, v4, v2, v2
353; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
354; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
355; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v2, v4
356; GFX6-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
357; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
358; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
359; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
360; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
361;
362; GFX89-IEEE-LABEL: v_rcp_f32_arcp:
363; GFX89-IEEE:       ; %bb.0:
364; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
365; GFX89-IEEE-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
366; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
367; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v3, v1
368; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
369; GFX89-IEEE-NEXT:    v_fma_f32 v3, v4, v3, v3
370; GFX89-IEEE-NEXT:    v_mul_f32_e32 v4, v2, v3
371; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v1, v4, v2
372; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v3, v4
373; GFX89-IEEE-NEXT:    v_fma_f32 v1, -v1, v4, v2
374; GFX89-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
375; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
376; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
377;
378; GFX89-FLUSH-LABEL: v_rcp_f32_arcp:
379; GFX89-FLUSH:       ; %bb.0:
380; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
381; GFX89-FLUSH-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
382; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
383; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v3, v1
384; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
385; GFX89-FLUSH-NEXT:    v_fma_f32 v4, -v1, v3, 1.0
386; GFX89-FLUSH-NEXT:    v_fma_f32 v3, v4, v3, v3
387; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v3
388; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v2
389; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v3, v4
390; GFX89-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v2
391; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
392; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
393; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
394; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
395;
396; GFX10-IEEE-LABEL: v_rcp_f32_arcp:
397; GFX10-IEEE:       ; %bb.0:
398; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
399; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
400; GFX10-IEEE-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
401; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
402; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v2, v1
403; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
404; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v2, v3, v2
405; GFX10-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v2
406; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v1, v3, v4
407; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v5, v2
408; GFX10-IEEE-NEXT:    v_fma_f32 v1, -v1, v3, v4
409; GFX10-IEEE-NEXT:    v_div_fmas_f32 v1, v1, v2, v3
410; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
411; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
412;
413; GFX10-FLUSH-LABEL: v_rcp_f32_arcp:
414; GFX10-FLUSH:       ; %bb.0:
415; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
416; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
417; GFX10-FLUSH-NEXT:    v_div_scale_f32 v1, s4, v0, v0, 1.0
418; GFX10-FLUSH-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
419; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v1
420; GFX10-FLUSH-NEXT:    s_denorm_mode 3
421; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
422; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v2, v4, v2
423; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v3, v2
424; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v1, v4, v3
425; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v5, v2
426; GFX10-FLUSH-NEXT:    v_fma_f32 v1, -v1, v4, v3
427; GFX10-FLUSH-NEXT:    s_denorm_mode 0
428; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
429; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
430; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
431  %fdiv = fdiv arcp float 1.0, %x
432  ret float %fdiv
433}
434
435define float @v_rcp_f32_arcp_afn(float %x) {
436; GCN-LABEL: v_rcp_f32_arcp_afn:
437; GCN:       ; %bb.0:
438; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
439; GCN-NEXT:    v_rcp_f32_e32 v0, v0
440; GCN-NEXT:    s_setpc_b64 s[30:31]
441;
442; GFX10-LABEL: v_rcp_f32_arcp_afn:
443; GFX10:       ; %bb.0:
444; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
445; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
446; GFX10-NEXT:    v_rcp_f32_e32 v0, v0
447; GFX10-NEXT:    s_setpc_b64 s[30:31]
448  %fdiv = fdiv arcp afn float 1.0, %x
449  ret float %fdiv
450}
451
452define float @v_rcp_f32_ulp25(float %x) {
453; GCN-IEEE-LABEL: v_rcp_f32_ulp25:
454; GCN-IEEE:       ; %bb.0:
455; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
456; GCN-IEEE-NEXT:    v_mov_b32_e32 v1, 0x6f800000
457; GCN-IEEE-NEXT:    v_mov_b32_e32 v2, 0x2f800000
458; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, v1
459; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
460; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
461; GCN-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
462; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
463; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
464; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
465;
466; GCN-FLUSH-LABEL: v_rcp_f32_ulp25:
467; GCN-FLUSH:       ; %bb.0:
468; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
469; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
470; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
471;
472; GFX10-IEEE-LABEL: v_rcp_f32_ulp25:
473; GFX10-IEEE:       ; %bb.0:
474; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
475; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
476; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
477; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s4
478; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v1
479; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
480; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
481; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v1, v0
482; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
483;
484; GFX10-FLUSH-LABEL: v_rcp_f32_ulp25:
485; GFX10-FLUSH:       ; %bb.0:
486; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
487; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
488; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
489; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
490  %fdiv = fdiv float 1.0, %x, !fpmath !0
491  ret float %fdiv
492}
493
494define float @v_fdiv_f32_afn_ulp25(float %a, float %b) {
495; GCN-LABEL: v_fdiv_f32_afn_ulp25:
496; GCN:       ; %bb.0:
497; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
498; GCN-NEXT:    v_rcp_f32_e32 v1, v1
499; GCN-NEXT:    v_mul_f32_e32 v0, v0, v1
500; GCN-NEXT:    s_setpc_b64 s[30:31]
501;
502; GFX10-LABEL: v_fdiv_f32_afn_ulp25:
503; GFX10:       ; %bb.0:
504; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
505; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
506; GFX10-NEXT:    v_rcp_f32_e32 v1, v1
507; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v1
508; GFX10-NEXT:    s_setpc_b64 s[30:31]
509  %fdiv = fdiv afn float %a, %b, !fpmath !0
510  ret float %fdiv
511}
512
513define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
514; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
515; GFX6-IEEE:       ; %bb.0:
516; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
517; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
518; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
519; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v0
520; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
521; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
522; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
523; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
524; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
525; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
526; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
527; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
528; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
529;
530; GCN-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
531; GCN-FLUSH:       ; %bb.0:
532; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
533; GCN-FLUSH-NEXT:    v_mov_b32_e32 v2, 0x6f800000
534; GCN-FLUSH-NEXT:    v_mov_b32_e32 v3, 0x2f800000
535; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, v2
536; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc
537; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
538; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
539; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
540; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
541; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
542;
543; GFX89-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
544; GFX89-IEEE:       ; %bb.0:
545; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
546; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0
547; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
548; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
549; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
550; GFX89-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
551; GFX89-IEEE-NEXT:    v_mul_f32_e32 v5, v3, v4
552; GFX89-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v3
553; GFX89-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
554; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v3
555; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
556; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
557; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
558;
559; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
560; GFX10-IEEE:       ; %bb.0:
561; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
562; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
563; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v1, v1, v0
564; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v1, v0
565; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
566; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v2, v3, 1.0
567; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v3, v4, v3
568; GFX10-IEEE-NEXT:    v_mul_f32_e32 v4, v5, v3
569; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, v5
570; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v3
571; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v4, v5
572; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v4
573; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v1, v0
574; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
575;
576; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
577; GFX10-FLUSH:       ; %bb.0:
578; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
579; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
580; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
581; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
582; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v2
583; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
584; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v1
585; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v2, v0
586; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
587  %fdiv = fdiv arcp float %a, %b, !fpmath !0
588  ret float %fdiv
589}
590
591define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
592; GFX6-IEEE-LABEL: v_fdiv_v2f32:
593; GFX6-IEEE:       ; %bb.0:
594; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
595; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
596; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
597; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
598; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
599; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
600; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
601; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
602; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
603; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
604; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
605; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
606; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
607; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
608; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
609; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
610; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
611; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
612; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
613; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
614; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
615; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
616; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
617; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
618;
619; GFX6-FLUSH-LABEL: v_fdiv_v2f32:
620; GFX6-FLUSH:       ; %bb.0:
621; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
622; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
623; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
624; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
625; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
626; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
627; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5
628; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
629; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
630; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
631; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
632; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
633; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
634; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
635; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v5
636; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
637; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
638; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
639; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
640; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v4, v6, v6
641; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v2, v4
642; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v5, v6, v2
643; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
644; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v5, v6, v2
645; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
646; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
647; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
648; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
649;
650; GFX89-IEEE-LABEL: v_fdiv_v2f32:
651; GFX89-IEEE:       ; %bb.0:
652; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
653; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
654; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
655; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
656; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
657; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
658; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
659; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
660; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
661; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
662; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
663; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
664; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
665; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
666; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
667; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
668; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
669; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
670; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
671; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
672; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
673; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
674; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
675; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
676; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
677;
678; GFX89-FLUSH-LABEL: v_fdiv_v2f32:
679; GFX89-FLUSH:       ; %bb.0:
680; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
681; GFX89-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
682; GFX89-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v0, v2, v0
683; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
684; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
685; GFX89-FLUSH-NEXT:    v_fma_f32 v7, -v4, v6, 1.0
686; GFX89-FLUSH-NEXT:    v_fma_f32 v6, v7, v6, v6
687; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v7, v5, v6
688; GFX89-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v5
689; GFX89-FLUSH-NEXT:    v_fma_f32 v7, v8, v6, v7
690; GFX89-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v5
691; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
692; GFX89-FLUSH-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
693; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
694; GFX89-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v1, v3, v1
695; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v7, v5
696; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
697; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
698; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v5, v7, 1.0
699; GFX89-FLUSH-NEXT:    v_fma_f32 v2, v2, v7, v7
700; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v4, v6, v2
701; GFX89-FLUSH-NEXT:    v_fma_f32 v7, -v5, v4, v6
702; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v7, v2, v4
703; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v5, v4, v6
704; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
705; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v5, v2, v4
706; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
707; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
708;
709; GFX10-IEEE-LABEL: v_fdiv_v2f32:
710; GFX10-IEEE:       ; %bb.0:
711; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
712; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
713; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
714; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
715; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
716; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
717; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
718; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
719; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
720; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
721; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
722; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
723; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
724; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
725; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
726; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
727; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
728; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
729; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
730; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
731; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
732; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
733; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
734; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
735; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
736; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
737;
738; GFX10-FLUSH-LABEL: v_fdiv_v2f32:
739; GFX10-FLUSH:       ; %bb.0:
740; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
741; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
742; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
743; GFX10-FLUSH-NEXT:    v_div_scale_f32 v6, vcc_lo, v0, v2, v0
744; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
745; GFX10-FLUSH-NEXT:    s_denorm_mode 3
746; GFX10-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
747; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v7, v5
748; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
749; GFX10-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
750; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v7, v8, v5
751; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
752; GFX10-FLUSH-NEXT:    s_denorm_mode 0
753; GFX10-FLUSH-NEXT:    v_div_scale_f32 v6, s4, v3, v3, v1
754; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
755; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v5, v6
756; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
757; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, v1, v3, v1
758; GFX10-FLUSH-NEXT:    s_denorm_mode 3
759; GFX10-FLUSH-NEXT:    v_fma_f32 v4, -v6, v5, 1.0
760; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v4, v5
761; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v4, v2, v5
762; GFX10-FLUSH-NEXT:    v_fma_f32 v7, -v6, v4, v2
763; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v4, v7, v5
764; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v6, v4, v2
765; GFX10-FLUSH-NEXT:    s_denorm_mode 0
766; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v5, v4
767; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
768; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
769  %fdiv = fdiv <2 x float> %a, %b
770  ret <2 x float> %fdiv
771}
772
773define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {
774; GCN-LABEL: v_fdiv_v2f32_afn:
775; GCN:       ; %bb.0:
776; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
777; GCN-NEXT:    v_rcp_f32_e32 v2, v2
778; GCN-NEXT:    v_rcp_f32_e32 v3, v3
779; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
780; GCN-NEXT:    v_mul_f32_e32 v1, v1, v3
781; GCN-NEXT:    s_setpc_b64 s[30:31]
782;
783; GFX10-LABEL: v_fdiv_v2f32_afn:
784; GFX10:       ; %bb.0:
785; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
786; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
787; GFX10-NEXT:    v_rcp_f32_e32 v2, v2
788; GFX10-NEXT:    v_rcp_f32_e32 v3, v3
789; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
790; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v3
791; GFX10-NEXT:    s_setpc_b64 s[30:31]
792  %fdiv = fdiv afn <2 x float> %a, %b
793  ret <2 x float> %fdiv
794}
795
796define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
797; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:
798; GFX6-IEEE:       ; %bb.0:
799; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
800; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
801; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
802; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
803; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
804; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
805; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
806; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
807; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
808; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
809; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
810; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
811; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
812; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
813; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
814; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
815; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
816; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
817; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
818; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
819; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
820; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
821; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
822; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
823;
824; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
825; GCN-FLUSH:       ; %bb.0:
826; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
827; GCN-FLUSH-NEXT:    s_mov_b32 s4, 0x6f800000
828; GCN-FLUSH-NEXT:    v_mov_b32_e32 v4, 0x2f800000
829; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v2|, s4
830; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
831; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v3|, s4
832; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
833; GCN-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v5
834; GCN-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v4
835; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
836; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
837; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
838; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
839; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v5, v0
840; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v4, v1
841; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
842;
843; GFX89-IEEE-LABEL: v_fdiv_v2f32_ulp25:
844; GFX89-IEEE:       ; %bb.0:
845; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
846; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
847; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
848; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
849; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
850; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
851; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
852; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
853; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
854; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
855; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
856; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
857; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
858; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
859; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
860; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
861; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
862; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
863; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
864; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
865; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
866; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
867; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
868; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
869; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
870;
871; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25:
872; GFX10-IEEE:       ; %bb.0:
873; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
874; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
875; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
876; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
877; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
878; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
879; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
880; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
881; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
882; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
883; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
884; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
885; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
886; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
887; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
888; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
889; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
890; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
891; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
892; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
893; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
894; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
895; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
896; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
897; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
898; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
899;
900; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
901; GFX10-FLUSH:       ; %bb.0:
902; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
903; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
904; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
905; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
906; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
907; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v4
908; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
909; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
910; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v5
911; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
912; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
913; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v4, v0
914; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
915; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v5, v1
916; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
917  %fdiv = fdiv <2 x float> %a, %b, !fpmath !0
918  ret <2 x float> %fdiv
919}
920
921define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
922; GFX6-IEEE-LABEL: v_rcp_v2f32:
923; GFX6-IEEE:       ; %bb.0:
924; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
925; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
926; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
927; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
928; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
929; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
930; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
931; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
932; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
933; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
934; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
935; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
936; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
937; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
938; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
939; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
940; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
941; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
942; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
943; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
944; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
945; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
946; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
947; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
948;
949; GFX6-FLUSH-LABEL: v_rcp_v2f32:
950; GFX6-FLUSH:       ; %bb.0:
951; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
952; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
953; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
954; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
955; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
956; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
957; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
958; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
959; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
960; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
961; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
962; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
963; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
964; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
965; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
966; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
967; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
968; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
969; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
970; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
971; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
972; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
973; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
974; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
975; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
976; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
977; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
978; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
979;
980; GFX89-IEEE-LABEL: v_rcp_v2f32:
981; GFX89-IEEE:       ; %bb.0:
982; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
983; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
984; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
985; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
986; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
987; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v6, v2
988; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v7, v3
989; GFX89-IEEE-NEXT:    v_fma_f32 v8, -v2, v6, 1.0
990; GFX89-IEEE-NEXT:    v_fma_f32 v6, v8, v6, v6
991; GFX89-IEEE-NEXT:    v_fma_f32 v9, -v3, v7, 1.0
992; GFX89-IEEE-NEXT:    v_fma_f32 v7, v9, v7, v7
993; GFX89-IEEE-NEXT:    v_mul_f32_e32 v8, v4, v6
994; GFX89-IEEE-NEXT:    v_mul_f32_e32 v9, v5, v7
995; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v2, v8, v4
996; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v5
997; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v6, v8
998; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v7, v9
999; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v8, v4
1000; GFX89-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v5
1001; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v6, v8
1002; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1003; GFX89-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v7, v9
1004; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1005; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1006; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1007;
1008; GFX89-FLUSH-LABEL: v_rcp_v2f32:
1009; GFX89-FLUSH:       ; %bb.0:
1010; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1011; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1012; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
1013; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
1014; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1015; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
1016; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1017; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
1018; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v3
1019; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1020; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v3
1021; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1022; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1023; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1024; GFX89-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
1025; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v5, v3
1026; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1027; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1028; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, 1.0
1029; GFX89-FLUSH-NEXT:    v_fma_f32 v2, v2, v5, v5
1030; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v2
1031; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v4
1032; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v2, v5
1033; GFX89-FLUSH-NEXT:    v_fma_f32 v3, -v3, v5, v4
1034; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1035; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v3, v2, v5
1036; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1037; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1038;
1039; GFX10-IEEE-LABEL: v_rcp_v2f32:
1040; GFX10-IEEE:       ; %bb.0:
1041; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1042; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1043; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1044; GFX10-IEEE-NEXT:    v_div_scale_f32 v3, s4, v1, v1, 1.0
1045; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1046; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1047; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1048; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1049; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1050; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
1051; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
1052; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
1053; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1054; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1055; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1056; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1057; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1058; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1059; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1060; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1061; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1062; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1063; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1064; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1065; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1066; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1067;
1068; GFX10-FLUSH-LABEL: v_rcp_v2f32:
1069; GFX10-FLUSH:       ; %bb.0:
1070; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1071; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1072; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1073; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1074; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1075; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1076; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1077; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1078; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1079; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1080; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1081; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1082; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1083; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v1, v1, 1.0
1084; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1085; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
1086; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1087; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
1088; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1089; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
1090; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1091; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
1092; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
1093; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1094; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
1095; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1096; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1097; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1098; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1099  %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x
1100  ret <2 x float> %fdiv
1101}
1102
1103define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
1104; GFX6-IEEE-LABEL: v_rcp_v2f32_arcp:
1105; GFX6-IEEE:       ; %bb.0:
1106; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1107; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1108; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
1109; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1110; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1111; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
1112; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
1113; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
1114; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
1115; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
1116; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1117; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1118; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
1119; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1120; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1121; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1122; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
1123; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
1124; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
1125; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
1126; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
1127; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1128; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1129; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1130;
1131; GFX6-FLUSH-LABEL: v_rcp_v2f32_arcp:
1132; GFX6-FLUSH:       ; %bb.0:
1133; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1134; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1135; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1136; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1137; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1138; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1139; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
1140; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1141; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1142; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
1143; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1144; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1145; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1146; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1147; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
1148; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1149; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
1150; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1151; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
1152; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1153; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
1154; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
1155; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1156; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
1157; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1158; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1159; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1160; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1161;
1162; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:
1163; GFX89-IEEE:       ; %bb.0:
1164; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1165; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1166; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1167; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1168; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
1169; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v6, v2
1170; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v7, v3
1171; GFX89-IEEE-NEXT:    v_fma_f32 v8, -v2, v6, 1.0
1172; GFX89-IEEE-NEXT:    v_fma_f32 v6, v8, v6, v6
1173; GFX89-IEEE-NEXT:    v_fma_f32 v9, -v3, v7, 1.0
1174; GFX89-IEEE-NEXT:    v_fma_f32 v7, v9, v7, v7
1175; GFX89-IEEE-NEXT:    v_mul_f32_e32 v8, v4, v6
1176; GFX89-IEEE-NEXT:    v_mul_f32_e32 v9, v5, v7
1177; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v2, v8, v4
1178; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v5
1179; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v6, v8
1180; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v7, v9
1181; GFX89-IEEE-NEXT:    v_fma_f32 v2, -v2, v8, v4
1182; GFX89-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v5
1183; GFX89-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v6, v8
1184; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1185; GFX89-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v7, v9
1186; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1187; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1188; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1189;
1190; GFX89-FLUSH-LABEL: v_rcp_v2f32_arcp:
1191; GFX89-FLUSH:       ; %bb.0:
1192; GFX89-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1193; GFX89-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
1194; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
1195; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v4, v2
1196; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1197; GFX89-FLUSH-NEXT:    v_fma_f32 v5, -v2, v4, 1.0
1198; GFX89-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
1199; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v3, v4
1200; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v3
1201; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
1202; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v3
1203; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1204; GFX89-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
1205; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
1206; GFX89-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
1207; GFX89-FLUSH-NEXT:    v_rcp_f32_e32 v5, v3
1208; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1209; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
1210; GFX89-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, 1.0
1211; GFX89-FLUSH-NEXT:    v_fma_f32 v2, v2, v5, v5
1212; GFX89-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v2
1213; GFX89-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v4
1214; GFX89-FLUSH-NEXT:    v_fma_f32 v5, v6, v2, v5
1215; GFX89-FLUSH-NEXT:    v_fma_f32 v3, -v3, v5, v4
1216; GFX89-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
1217; GFX89-FLUSH-NEXT:    v_div_fmas_f32 v2, v3, v2, v5
1218; GFX89-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1219; GFX89-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1220;
1221; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp:
1222; GFX10-IEEE:       ; %bb.0:
1223; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1224; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1225; GFX10-IEEE-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1226; GFX10-IEEE-NEXT:    v_div_scale_f32 v3, s4, v1, v1, 1.0
1227; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.0
1228; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v4, v2
1229; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v5, v3
1230; GFX10-IEEE-NEXT:    v_fma_f32 v6, -v2, v4, 1.0
1231; GFX10-IEEE-NEXT:    v_fma_f32 v7, -v3, v5, 1.0
1232; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v4, v6, v4
1233; GFX10-IEEE-NEXT:    v_div_scale_f32 v6, s4, 1.0, v1, 1.0
1234; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v5, v7, v5
1235; GFX10-IEEE-NEXT:    v_mul_f32_e32 v7, v8, v4
1236; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v6, v5
1237; GFX10-IEEE-NEXT:    v_fma_f32 v10, -v2, v7, v8
1238; GFX10-IEEE-NEXT:    v_fma_f32 v11, -v3, v9, v6
1239; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v10, v4
1240; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v11, v5
1241; GFX10-IEEE-NEXT:    v_fma_f32 v2, -v2, v7, v8
1242; GFX10-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v6
1243; GFX10-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v7
1244; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1245; GFX10-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v9
1246; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1247; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, 1.0
1248; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1249;
1250; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp:
1251; GFX10-FLUSH:       ; %bb.0:
1252; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1253; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1254; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, s4, v0, v0, 1.0
1255; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1256; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
1257; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1258; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
1259; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1260; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
1261; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
1262; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1263; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
1264; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1265; GFX10-FLUSH-NEXT:    v_div_scale_f32 v4, s4, v1, v1, 1.0
1266; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1267; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v4
1268; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
1269; GFX10-FLUSH-NEXT:    v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
1270; GFX10-FLUSH-NEXT:    s_denorm_mode 3
1271; GFX10-FLUSH-NEXT:    v_fma_f32 v5, -v4, v3, 1.0
1272; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v3, v5, v3
1273; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
1274; GFX10-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
1275; GFX10-FLUSH-NEXT:    v_fmac_f32_e32 v5, v6, v3
1276; GFX10-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
1277; GFX10-FLUSH-NEXT:    s_denorm_mode 0
1278; GFX10-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
1279; GFX10-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
1280; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1281  %fdiv = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x
1282  ret <2 x float> %fdiv
1283}
1284
1285define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) {
1286; GCN-LABEL: v_rcp_v2f32_arcp_afn:
1287; GCN:       ; %bb.0:
1288; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1289; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1290; GCN-NEXT:    v_rcp_f32_e32 v1, v1
1291; GCN-NEXT:    s_setpc_b64 s[30:31]
1292;
1293; GFX10-LABEL: v_rcp_v2f32_arcp_afn:
1294; GFX10:       ; %bb.0:
1295; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1296; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1297; GFX10-NEXT:    v_rcp_f32_e32 v0, v0
1298; GFX10-NEXT:    v_rcp_f32_e32 v1, v1
1299; GFX10-NEXT:    s_setpc_b64 s[30:31]
1300  %fdiv = fdiv arcp afn <2 x float> <float 1.0, float 1.0>, %x
1301  ret <2 x float> %fdiv
1302}
1303
1304define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) {
1305; GCN-IEEE-LABEL: v_rcp_v2f32_ulp25:
1306; GCN-IEEE:       ; %bb.0:
1307; GCN-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1308; GCN-IEEE-NEXT:    s_mov_b32 s4, 0x6f800000
1309; GCN-IEEE-NEXT:    v_mov_b32_e32 v2, 0x2f800000
1310; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v0|, s4
1311; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v3, 1.0, v2, vcc
1312; GCN-IEEE-NEXT:    v_cmp_gt_f32_e64 vcc, |v1|, s4
1313; GCN-IEEE-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc
1314; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v3
1315; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, v1, v2
1316; GCN-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1317; GCN-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1318; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
1319; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, 1.0, v1
1320; GCN-IEEE-NEXT:    v_mul_f32_e32 v0, v3, v0
1321; GCN-IEEE-NEXT:    v_mul_f32_e32 v1, v2, v1
1322; GCN-IEEE-NEXT:    s_setpc_b64 s[30:31]
1323;
1324; GCN-FLUSH-LABEL: v_rcp_v2f32_ulp25:
1325; GCN-FLUSH:       ; %bb.0:
1326; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1327; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
1328; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
1329; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1330;
1331; GFX10-IEEE-LABEL: v_rcp_v2f32_ulp25:
1332; GFX10-IEEE:       ; %bb.0:
1333; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1334; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1335; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
1336; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
1337; GFX10-IEEE-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
1338; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v0, v2
1339; GFX10-IEEE-NEXT:    v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s4
1340; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v0, v0
1341; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, v1, v3
1342; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v1, v1
1343; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, 1.0, v0
1344; GFX10-IEEE-NEXT:    v_mul_f32_e32 v0, v2, v0
1345; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, 1.0, v1
1346; GFX10-IEEE-NEXT:    v_mul_f32_e32 v1, v3, v1
1347; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1348;
1349; GFX10-FLUSH-LABEL: v_rcp_v2f32_ulp25:
1350; GFX10-FLUSH:       ; %bb.0:
1351; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1352; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1353; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v0, v0
1354; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v1, v1
1355; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1356  %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x, !fpmath !0
1357  ret <2 x float> %fdiv
1358}
1359
1360define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) {
1361; GCN-LABEL: v_fdiv_v2f32_afn_ulp25:
1362; GCN:       ; %bb.0:
1363; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1364; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1365; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1366; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
1367; GCN-NEXT:    v_mul_f32_e32 v1, v1, v3
1368; GCN-NEXT:    s_setpc_b64 s[30:31]
1369;
1370; GFX10-LABEL: v_fdiv_v2f32_afn_ulp25:
1371; GFX10:       ; %bb.0:
1372; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1373; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1374; GFX10-NEXT:    v_rcp_f32_e32 v2, v2
1375; GFX10-NEXT:    v_rcp_f32_e32 v3, v3
1376; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
1377; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v3
1378; GFX10-NEXT:    s_setpc_b64 s[30:31]
1379  %fdiv = fdiv afn <2 x float> %a, %b, !fpmath !0
1380  ret <2 x float> %fdiv
1381}
1382
1383define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
1384; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
1385; GFX6-IEEE:       ; %bb.0:
1386; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1387; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1388; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
1389; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1390; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1391; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
1392; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
1393; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
1394; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
1395; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
1396; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
1397; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1398; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
1399; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1400; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
1401; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
1402; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
1403; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
1404; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
1405; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
1406; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
1407; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
1408; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
1409; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
1410;
1411; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
1412; GCN-FLUSH:       ; %bb.0:
1413; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1414; GCN-FLUSH-NEXT:    s_mov_b32 s4, 0x6f800000
1415; GCN-FLUSH-NEXT:    v_mov_b32_e32 v4, 0x2f800000
1416; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v2|, s4
1417; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v5, 1.0, v4, vcc
1418; GCN-FLUSH-NEXT:    v_cmp_gt_f32_e64 vcc, |v3|, s4
1419; GCN-FLUSH-NEXT:    v_cndmask_b32_e32 v4, 1.0, v4, vcc
1420; GCN-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v5
1421; GCN-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v4
1422; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
1423; GCN-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
1424; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
1425; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
1426; GCN-FLUSH-NEXT:    v_mul_f32_e32 v0, v5, v0
1427; GCN-FLUSH-NEXT:    v_mul_f32_e32 v1, v4, v1
1428; GCN-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1429;
1430; GFX89-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
1431; GFX89-IEEE:       ; %bb.0:
1432; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1433; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1434; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1435; GFX89-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
1436; GFX89-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v1, v3, v1
1437; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v8, v4
1438; GFX89-IEEE-NEXT:    v_rcp_f32_e32 v9, v5
1439; GFX89-IEEE-NEXT:    v_fma_f32 v10, -v4, v8, 1.0
1440; GFX89-IEEE-NEXT:    v_fma_f32 v8, v10, v8, v8
1441; GFX89-IEEE-NEXT:    v_fma_f32 v11, -v5, v9, 1.0
1442; GFX89-IEEE-NEXT:    v_fma_f32 v9, v11, v9, v9
1443; GFX89-IEEE-NEXT:    v_mul_f32_e32 v10, v6, v8
1444; GFX89-IEEE-NEXT:    v_mul_f32_e32 v11, v7, v9
1445; GFX89-IEEE-NEXT:    v_fma_f32 v12, -v4, v10, v6
1446; GFX89-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v7
1447; GFX89-IEEE-NEXT:    v_fma_f32 v10, v12, v8, v10
1448; GFX89-IEEE-NEXT:    v_fma_f32 v11, v13, v9, v11
1449; GFX89-IEEE-NEXT:    v_fma_f32 v4, -v4, v10, v6
1450; GFX89-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v7
1451; GFX89-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v8, v10
1452; GFX89-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]
1453; GFX89-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v9, v11
1454; GFX89-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1455; GFX89-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1456; GFX89-IEEE-NEXT:    s_setpc_b64 s[30:31]
1457;
1458; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
1459; GFX10-IEEE:       ; %bb.0:
1460; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1461; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
1462; GFX10-IEEE-NEXT:    v_div_scale_f32 v4, s4, v2, v2, v0
1463; GFX10-IEEE-NEXT:    v_div_scale_f32 v5, s4, v3, v3, v1
1464; GFX10-IEEE-NEXT:    v_div_scale_f32 v10, vcc_lo, v0, v2, v0
1465; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
1466; GFX10-IEEE-NEXT:    v_rcp_f32_e32 v7, v5
1467; GFX10-IEEE-NEXT:    v_fma_f32 v8, -v4, v6, 1.0
1468; GFX10-IEEE-NEXT:    v_fma_f32 v9, -v5, v7, 1.0
1469; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v6, v8, v6
1470; GFX10-IEEE-NEXT:    v_div_scale_f32 v8, s4, v1, v3, v1
1471; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v7, v9, v7
1472; GFX10-IEEE-NEXT:    v_mul_f32_e32 v9, v10, v6
1473; GFX10-IEEE-NEXT:    v_mul_f32_e32 v11, v8, v7
1474; GFX10-IEEE-NEXT:    v_fma_f32 v12, -v4, v9, v10
1475; GFX10-IEEE-NEXT:    v_fma_f32 v13, -v5, v11, v8
1476; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v9, v12, v6
1477; GFX10-IEEE-NEXT:    v_fmac_f32_e32 v11, v13, v7
1478; GFX10-IEEE-NEXT:    v_fma_f32 v4, -v4, v9, v10
1479; GFX10-IEEE-NEXT:    v_fma_f32 v5, -v5, v11, v8
1480; GFX10-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v6, v9
1481; GFX10-IEEE-NEXT:    s_mov_b32 vcc_lo, s4
1482; GFX10-IEEE-NEXT:    v_div_fmas_f32 v5, v5, v7, v11
1483; GFX10-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
1484; GFX10-IEEE-NEXT:    v_div_fixup_f32 v1, v5, v3, v1
1485; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
1486;
1487; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
1488; GFX10-FLUSH:       ; %bb.0:
1489; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1490; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
1491; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|
1492; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
1493; GFX10-FLUSH-NEXT:    v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|
1494; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v2, v2, v4
1495; GFX10-FLUSH-NEXT:    v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s4
1496; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v2, v2
1497; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v3, v3, v5
1498; GFX10-FLUSH-NEXT:    v_rcp_f32_e32 v3, v3
1499; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v0, v2
1500; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v0, v4, v0
1501; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v1, v3
1502; GFX10-FLUSH-NEXT:    v_mul_f32_e32 v1, v5, v1
1503; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
1504  %fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
1505  ret <2 x float> %fdiv
1506}
1507
1508define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) {
1509; GCN-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
1510; GCN:       ; %bb.0:
1511; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1512; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1513; GCN-NEXT:    v_rcp_f32_e32 v3, v3
1514; GCN-NEXT:    v_mul_f32_e32 v0, v0, v2
1515; GCN-NEXT:    v_mul_f32_e32 v1, v1, v3
1516; GCN-NEXT:    s_setpc_b64 s[30:31]
1517;
1518; GFX10-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:
1519; GFX10:       ; %bb.0:
1520; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1521; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1522; GFX10-NEXT:    v_rcp_f32_e32 v2, v2
1523; GFX10-NEXT:    v_rcp_f32_e32 v3, v3
1524; GFX10-NEXT:    v_mul_f32_e32 v0, v0, v2
1525; GFX10-NEXT:    v_mul_f32_e32 v1, v1, v3
1526; GFX10-NEXT:    s_setpc_b64 s[30:31]
1527  %fdiv = fdiv afn arcp <2 x float> %a, %b, !fpmath !0
1528  ret <2 x float> %fdiv
1529}
1530
1531!0 = !{float 2.500000e+00}
1532