1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Denormal mode shouldn't matter for f16, check with and without flushing. 3; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-IEEE %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-FLUSH %s 5 6; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s 7; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s 8 9; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s 10; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s 11 12; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s 13; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s 14 15; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s 16; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s 17 18define half @v_fdiv_f16(half %a, half %b) { 19; GFX6-IEEE-LABEL: v_fdiv_f16: 20; GFX6-IEEE: ; %bb.0: 21; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 22; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 23; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 24; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 25; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 26; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 27; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 28; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 29; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 30; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 31; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 32; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 33; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 34; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 35; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 36; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 37; 38; GFX6-FLUSH-LABEL: v_fdiv_f16: 39; GFX6-FLUSH: ; %bb.0: 40; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 41; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 42; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 43; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 44; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 45; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 46; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 47; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 48; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 49; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 50; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 51; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 52; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 53; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 54; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 55; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 56; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 57; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 58; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 59; 60; GFX89-LABEL: v_fdiv_f16: 61; GFX89: ; %bb.0: 62; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 63; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 64; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 65; GFX89-NEXT: v_rcp_f32_e32 v2, v2 66; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 67; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 68; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 69; GFX89-NEXT: s_setpc_b64 s[30:31] 70; 71; GFX10-LABEL: v_fdiv_f16: 72; GFX10: ; %bb.0: 73; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 74; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 75; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 76; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 77; GFX10-NEXT: v_rcp_f32_e32 v2, v2 78; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2 79; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 80; GFX10-NEXT: v_div_fixup_f16 v0, v2, v1, v0 81; GFX10-NEXT: s_setpc_b64 s[30:31] 82; 83; GFX11-LABEL: v_fdiv_f16: 84; GFX11: ; %bb.0: 85; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 86; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 87; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 88; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 89; GFX11-NEXT: v_rcp_f32_e32 v2, v2 90; GFX11-NEXT: s_waitcnt_depctr 0xfff 91; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2 92; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2 93; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0 94; GFX11-NEXT: s_setpc_b64 s[30:31] 95 %fdiv = fdiv half %a, %b 96 ret half %fdiv 97} 98 99define half @v_fdiv_f16_afn(half %a, half %b) { 100; GFX6-LABEL: v_fdiv_f16_afn: 101; GFX6: ; %bb.0: 102; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 103; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 104; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 105; GFX6-NEXT: v_rcp_f32_e32 v1, v1 106; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 107; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 108; GFX6-NEXT: s_setpc_b64 s[30:31] 109; 110; GFX89-LABEL: v_fdiv_f16_afn: 111; GFX89: ; %bb.0: 112; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 113; GFX89-NEXT: v_rcp_f16_e32 v1, v1 114; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 115; GFX89-NEXT: s_setpc_b64 s[30:31] 116; 117; GFX10-LABEL: v_fdiv_f16_afn: 118; GFX10: ; %bb.0: 119; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 120; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 121; GFX10-NEXT: v_rcp_f16_e32 v1, v1 122; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1 123; GFX10-NEXT: s_setpc_b64 s[30:31] 124; 125; GFX11-LABEL: v_fdiv_f16_afn: 126; GFX11: ; %bb.0: 127; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 128; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 129; GFX11-NEXT: v_rcp_f16_e32 v1, v1 130; GFX11-NEXT: s_waitcnt_depctr 0xfff 131; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 132; GFX11-NEXT: s_setpc_b64 s[30:31] 133 %fdiv = fdiv afn half %a, %b 134 ret half %fdiv 135} 136 137define half @v_fdiv_f16_ulp25(half %a, half %b) { 138; GFX6-IEEE-LABEL: v_fdiv_f16_ulp25: 139; GFX6-IEEE: ; %bb.0: 140; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 141; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 142; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 143; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 144; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 145; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 146; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 147; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 148; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 149; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 150; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 151; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 152; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 153; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 154; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 155; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 156; 157; GFX6-FLUSH-LABEL: v_fdiv_f16_ulp25: 158; GFX6-FLUSH: ; %bb.0: 159; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 160; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 161; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 162; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 163; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 164; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 165; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 166; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 167; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 168; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 169; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 170; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 171; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 172; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 173; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 174; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 175; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 176; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 177; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 178; 179; GFX89-LABEL: v_fdiv_f16_ulp25: 180; GFX89: ; %bb.0: 181; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 182; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 183; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 184; GFX89-NEXT: v_rcp_f32_e32 v2, v2 185; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 186; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 187; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 188; GFX89-NEXT: s_setpc_b64 s[30:31] 189; 190; GFX10-LABEL: v_fdiv_f16_ulp25: 191; GFX10: ; %bb.0: 192; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 193; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 194; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 195; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 196; GFX10-NEXT: v_rcp_f32_e32 v2, v2 197; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2 198; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 199; GFX10-NEXT: v_div_fixup_f16 v0, v2, v1, v0 200; GFX10-NEXT: s_setpc_b64 s[30:31] 201; 202; GFX11-LABEL: v_fdiv_f16_ulp25: 203; GFX11: ; %bb.0: 204; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 205; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 206; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 207; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 208; GFX11-NEXT: v_rcp_f32_e32 v2, v2 209; GFX11-NEXT: s_waitcnt_depctr 0xfff 210; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2 211; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2 212; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0 213; GFX11-NEXT: s_setpc_b64 s[30:31] 214 %fdiv = fdiv half %a, %b, !fpmath !0 215 ret half %fdiv 216} 217 218define half @v_rcp_f16(half %x) { 219; GFX6-IEEE-LABEL: v_rcp_f16: 220; GFX6-IEEE: ; %bb.0: 221; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 222; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 223; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 224; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 225; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 226; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 227; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 228; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 229; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 230; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 231; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 232; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 233; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 234; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 235; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 236; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 237; 238; GFX6-FLUSH-LABEL: v_rcp_f16: 239; GFX6-FLUSH: ; %bb.0: 240; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 241; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 242; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 243; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 244; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 245; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 246; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 247; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 248; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 249; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 250; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 251; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 252; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 253; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 254; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 255; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 256; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 257; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 258; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 259; 260; GFX89-LABEL: v_rcp_f16: 261; GFX89: ; %bb.0: 262; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 263; GFX89-NEXT: v_cvt_f32_f16_e32 v1, v0 264; GFX89-NEXT: v_cvt_f32_f16_e32 v2, 1.0 265; GFX89-NEXT: v_rcp_f32_e32 v1, v1 266; GFX89-NEXT: v_mul_f32_e32 v1, v2, v1 267; GFX89-NEXT: v_cvt_f16_f32_e32 v1, v1 268; GFX89-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 269; GFX89-NEXT: s_setpc_b64 s[30:31] 270; 271; GFX10-LABEL: v_rcp_f16: 272; GFX10: ; %bb.0: 273; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 274; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 275; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v0 276; GFX10-NEXT: v_cvt_f32_f16_e32 v2, 1.0 277; GFX10-NEXT: v_rcp_f32_e32 v1, v1 278; GFX10-NEXT: v_mul_f32_e32 v1, v2, v1 279; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 280; GFX10-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 281; GFX10-NEXT: s_setpc_b64 s[30:31] 282; 283; GFX11-LABEL: v_rcp_f16: 284; GFX11: ; %bb.0: 285; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 286; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 287; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v0 288; GFX11-NEXT: v_cvt_f32_f16_e32 v2, 1.0 289; GFX11-NEXT: v_rcp_f32_e32 v1, v1 290; GFX11-NEXT: s_waitcnt_depctr 0xfff 291; GFX11-NEXT: v_mul_f32_e32 v1, v2, v1 292; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1 293; GFX11-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 294; GFX11-NEXT: s_setpc_b64 s[30:31] 295 %fdiv = fdiv half 1.0, %x 296 ret half %fdiv 297} 298 299define half @v_rcp_f16_arcp(half %x) { 300; GFX6-IEEE-LABEL: v_rcp_f16_arcp: 301; GFX6-IEEE: ; %bb.0: 302; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 303; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 304; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 305; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 306; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 307; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 308; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 309; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 310; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 311; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 312; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 313; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 314; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 315; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 316; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 317; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 318; 319; GFX6-FLUSH-LABEL: v_rcp_f16_arcp: 320; GFX6-FLUSH: ; %bb.0: 321; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 322; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 323; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 324; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 325; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 326; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 327; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 328; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 329; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 330; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 331; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 332; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 333; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 334; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 335; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 336; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 337; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 338; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 339; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 340; 341; GFX89-LABEL: v_rcp_f16_arcp: 342; GFX89: ; %bb.0: 343; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 344; GFX89-NEXT: v_cvt_f32_f16_e32 v1, v0 345; GFX89-NEXT: v_cvt_f32_f16_e32 v2, 1.0 346; GFX89-NEXT: v_rcp_f32_e32 v1, v1 347; GFX89-NEXT: v_mul_f32_e32 v1, v2, v1 348; GFX89-NEXT: v_cvt_f16_f32_e32 v1, v1 349; GFX89-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 350; GFX89-NEXT: s_setpc_b64 s[30:31] 351; 352; GFX10-LABEL: v_rcp_f16_arcp: 353; GFX10: ; %bb.0: 354; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 355; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 356; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v0 357; GFX10-NEXT: v_cvt_f32_f16_e32 v2, 1.0 358; GFX10-NEXT: v_rcp_f32_e32 v1, v1 359; GFX10-NEXT: v_mul_f32_e32 v1, v2, v1 360; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 361; GFX10-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 362; GFX10-NEXT: s_setpc_b64 s[30:31] 363; 364; GFX11-LABEL: v_rcp_f16_arcp: 365; GFX11: ; %bb.0: 366; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 367; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 368; GFX11-NEXT: v_cvt_f32_f16_e32 v1, v0 369; GFX11-NEXT: v_cvt_f32_f16_e32 v2, 1.0 370; GFX11-NEXT: v_rcp_f32_e32 v1, v1 371; GFX11-NEXT: s_waitcnt_depctr 0xfff 372; GFX11-NEXT: v_mul_f32_e32 v1, v2, v1 373; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1 374; GFX11-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 375; GFX11-NEXT: s_setpc_b64 s[30:31] 376 %fdiv = fdiv arcp half 1.0, %x 377 ret half %fdiv 378} 379 380define half @v_rcp_f16_arcp_afn(half %x) { 381; GFX6-LABEL: v_rcp_f16_arcp_afn: 382; GFX6: ; %bb.0: 383; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 384; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 385; GFX6-NEXT: v_cvt_f32_f16_e32 v1, 1.0 386; GFX6-NEXT: v_rcp_f32_e32 v0, v0 387; GFX6-NEXT: v_mul_f32_e32 v0, v1, v0 388; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 389; GFX6-NEXT: s_setpc_b64 s[30:31] 390; 391; GFX89-LABEL: v_rcp_f16_arcp_afn: 392; GFX89: ; %bb.0: 393; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 394; GFX89-NEXT: v_rcp_f16_e32 v0, v0 395; GFX89-NEXT: s_setpc_b64 s[30:31] 396; 397; GFX10PLUS-LABEL: v_rcp_f16_arcp_afn: 398; GFX10PLUS: ; %bb.0: 399; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 400; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 401; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0 402; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 403 %fdiv = fdiv arcp afn half 1.0, %x 404 ret half %fdiv 405} 406 407define half @v_rcp_f16_ulp25(half %x) { 408; GFX6-IEEE-LABEL: v_rcp_f16_ulp25: 409; GFX6-IEEE: ; %bb.0: 410; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 411; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 412; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 413; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 414; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 415; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 416; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 417; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 418; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 419; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 420; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 421; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 422; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 423; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 424; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 425; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 426; 427; GFX6-FLUSH-LABEL: v_rcp_f16_ulp25: 428; GFX6-FLUSH: ; %bb.0: 429; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 430; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 431; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 432; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 433; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 434; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 435; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 436; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 437; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 438; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 439; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 440; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 441; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 442; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 443; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 444; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 445; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 446; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 447; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 448; 449; GFX89-LABEL: v_rcp_f16_ulp25: 450; GFX89: ; %bb.0: 451; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 452; GFX89-NEXT: v_rcp_f16_e32 v0, v0 453; GFX89-NEXT: s_setpc_b64 s[30:31] 454; 455; GFX10PLUS-LABEL: v_rcp_f16_ulp25: 456; GFX10PLUS: ; %bb.0: 457; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 458; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 459; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0 460; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 461 %fdiv = fdiv half 1.0, %x, !fpmath !0 462 ret half %fdiv 463} 464 465define half @v_fdiv_f16_afn_ulp25(half %a, half %b) { 466; GFX6-LABEL: v_fdiv_f16_afn_ulp25: 467; GFX6: ; %bb.0: 468; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 469; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 470; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 471; GFX6-NEXT: v_rcp_f32_e32 v1, v1 472; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 473; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 474; GFX6-NEXT: s_setpc_b64 s[30:31] 475; 476; GFX89-LABEL: v_fdiv_f16_afn_ulp25: 477; GFX89: ; %bb.0: 478; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 479; GFX89-NEXT: v_rcp_f16_e32 v1, v1 480; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 481; GFX89-NEXT: s_setpc_b64 s[30:31] 482; 483; GFX10-LABEL: v_fdiv_f16_afn_ulp25: 484; GFX10: ; %bb.0: 485; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 486; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 487; GFX10-NEXT: v_rcp_f16_e32 v1, v1 488; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1 489; GFX10-NEXT: s_setpc_b64 s[30:31] 490; 491; GFX11-LABEL: v_fdiv_f16_afn_ulp25: 492; GFX11: ; %bb.0: 493; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 494; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 495; GFX11-NEXT: v_rcp_f16_e32 v1, v1 496; GFX11-NEXT: s_waitcnt_depctr 0xfff 497; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 498; GFX11-NEXT: s_setpc_b64 s[30:31] 499 %fdiv = fdiv afn half %a, %b, !fpmath !0 500 ret half %fdiv 501} 502 503define half @v_fdiv_f16_arcp_ulp25(half %a, half %b) { 504; GFX6-IEEE-LABEL: v_fdiv_f16_arcp_ulp25: 505; GFX6-IEEE: ; %bb.0: 506; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 507; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 508; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 509; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 510; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 511; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 512; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 513; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 514; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 515; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 516; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 517; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 518; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 519; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 520; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 521; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 522; 523; GFX6-FLUSH-LABEL: v_fdiv_f16_arcp_ulp25: 524; GFX6-FLUSH: ; %bb.0: 525; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 526; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 527; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 528; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 529; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 530; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 531; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 532; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 533; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 534; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 535; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 536; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 537; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 538; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 539; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 540; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 541; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 542; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 543; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 544; 545; GFX89-LABEL: v_fdiv_f16_arcp_ulp25: 546; GFX89: ; %bb.0: 547; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 548; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 549; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 550; GFX89-NEXT: v_rcp_f32_e32 v2, v2 551; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 552; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 553; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 554; GFX89-NEXT: s_setpc_b64 s[30:31] 555; 556; GFX10-LABEL: v_fdiv_f16_arcp_ulp25: 557; GFX10: ; %bb.0: 558; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 559; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 560; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 561; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 562; GFX10-NEXT: v_rcp_f32_e32 v2, v2 563; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2 564; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 565; GFX10-NEXT: v_div_fixup_f16 v0, v2, v1, v0 566; GFX10-NEXT: s_setpc_b64 s[30:31] 567; 568; GFX11-LABEL: v_fdiv_f16_arcp_ulp25: 569; GFX11: ; %bb.0: 570; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 571; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 572; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 573; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 574; GFX11-NEXT: v_rcp_f32_e32 v2, v2 575; GFX11-NEXT: s_waitcnt_depctr 0xfff 576; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2 577; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2 578; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0 579; GFX11-NEXT: s_setpc_b64 s[30:31] 580 %fdiv = fdiv arcp half %a, %b, !fpmath !0 581 ret half %fdiv 582} 583 584define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { 585; GFX6-IEEE-LABEL: v_fdiv_v2f16: 586; GFX6-IEEE: ; %bb.0: 587; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 588; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 589; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 590; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 591; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 592; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 593; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 594; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 595; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 596; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 597; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 598; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 599; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 600; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 601; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 602; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 603; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 604; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 605; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 606; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 607; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 608; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 609; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 610; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 611; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 612; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 613; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 614; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 615; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 616; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 617; 618; GFX6-FLUSH-LABEL: v_fdiv_v2f16: 619; GFX6-FLUSH: ; %bb.0: 620; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 621; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 622; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 623; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 624; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 625; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 626; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 627; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 628; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 629; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 630; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 631; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 632; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 633; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 634; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 635; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 636; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 637; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 638; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 639; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 640; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 641; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 642; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 643; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 644; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 645; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 646; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 647; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 648; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 649; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 650; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 651; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 652; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 653; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 654; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 655; 656; GFX8-LABEL: v_fdiv_v2f16: 657; GFX8: ; %bb.0: 658; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 659; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 660; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 661; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 662; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 663; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 664; GFX8-NEXT: v_rcp_f32_e32 v2, v2 665; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 666; GFX8-NEXT: v_rcp_f32_e32 v5, v5 667; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 668; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 669; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 670; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 671; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 672; GFX8-NEXT: v_mov_b32_e32 v2, 16 673; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 674; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 675; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 676; GFX8-NEXT: s_setpc_b64 s[30:31] 677; 678; GFX9-LABEL: v_fdiv_v2f16: 679; GFX9: ; %bb.0: 680; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 681; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 682; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 683; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 684; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 685; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 686; GFX9-NEXT: v_rcp_f32_e32 v2, v2 687; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 688; GFX9-NEXT: v_rcp_f32_e32 v5, v5 689; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 690; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 691; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 692; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 693; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 694; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 695; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 696; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 697; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 698; GFX9-NEXT: s_setpc_b64 s[30:31] 699; 700; GFX10-LABEL: v_fdiv_v2f16: 701; GFX10: ; %bb.0: 702; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 703; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 704; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 705; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 706; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 707; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v0 708; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 709; GFX10-NEXT: v_rcp_f32_e32 v4, v4 710; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v5 711; GFX10-NEXT: v_rcp_f32_e32 v3, v3 712; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 713; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 714; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 715; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 716; GFX10-NEXT: v_div_fixup_f16 v0, v4, v1, v0 717; GFX10-NEXT: v_div_fixup_f16 v2, v3, v2, v5 718; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v2 719; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 720; GFX10-NEXT: s_setpc_b64 s[30:31] 721; 722; GFX11-LABEL: v_fdiv_v2f16: 723; GFX11: ; %bb.0: 724; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 725; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 726; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 727; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v1 728; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 729; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v0 730; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v2 731; GFX11-NEXT: v_rcp_f32_e32 v4, v4 732; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v5 733; GFX11-NEXT: v_rcp_f32_e32 v3, v3 734; GFX11-NEXT: s_waitcnt_depctr 0xfff 735; GFX11-NEXT: v_dual_mul_f32 v4, v7, v4 :: v_dual_mul_f32 v3, v6, v3 736; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4 737; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 738; GFX11-NEXT: v_div_fixup_f16 v0, v4, v1, v0 739; GFX11-NEXT: v_div_fixup_f16 v2, v3, v2, v5 740; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2 741; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 742; GFX11-NEXT: s_setpc_b64 s[30:31] 743 %fdiv = fdiv <2 x half> %a, %b 744 ret <2 x half> %fdiv 745} 746 747define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) { 748; GFX6-LABEL: v_fdiv_v2f16_afn: 749; GFX6: ; %bb.0: 750; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 751; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 752; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 753; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 754; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 755; GFX6-NEXT: v_rcp_f32_e32 v2, v2 756; GFX6-NEXT: v_rcp_f32_e32 v3, v3 757; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 758; GFX6-NEXT: v_mul_f32_e32 v1, v1, v3 759; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 760; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 761; GFX6-NEXT: s_setpc_b64 s[30:31] 762; 763; GFX8-LABEL: v_fdiv_v2f16_afn: 764; GFX8: ; %bb.0: 765; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 766; GFX8-NEXT: v_rcp_f16_e32 v2, v1 767; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 768; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 769; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 770; GFX8-NEXT: v_mov_b32_e32 v1, 16 771; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 772; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 773; GFX8-NEXT: s_setpc_b64 s[30:31] 774; 775; GFX9-LABEL: v_fdiv_v2f16_afn: 776; GFX9: ; %bb.0: 777; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 778; GFX9-NEXT: v_rcp_f16_e32 v2, v1 779; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 780; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 781; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 782; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff 783; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 784; GFX9-NEXT: s_setpc_b64 s[30:31] 785; 786; GFX10-LABEL: v_fdiv_v2f16_afn: 787; GFX10: ; %bb.0: 788; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 789; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 790; GFX10-NEXT: v_rcp_f16_e32 v2, v1 791; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 792; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 793; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 794; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v2, v0 795; GFX10-NEXT: s_setpc_b64 s[30:31] 796; 797; GFX11-LABEL: v_fdiv_v2f16_afn: 798; GFX11: ; %bb.0: 799; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 800; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 801; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 802; GFX11-NEXT: v_rcp_f16_e32 v1, v1 803; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 804; GFX11-NEXT: v_rcp_f16_e32 v2, v2 805; GFX11-NEXT: s_waitcnt_depctr 0xfff 806; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 807; GFX11-NEXT: v_mul_f16_e32 v2, v3, v2 808; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2 809; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 810; GFX11-NEXT: s_setpc_b64 s[30:31] 811 %fdiv = fdiv afn <2 x half> %a, %b 812 ret <2 x half> %fdiv 813} 814 815define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { 816; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25: 817; GFX6-IEEE: ; %bb.0: 818; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 819; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 820; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 821; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 822; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 823; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 824; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 825; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 826; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 827; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 828; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 829; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 830; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 831; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 832; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 833; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 834; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 835; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 836; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 837; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 838; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 839; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 840; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 841; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 842; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 843; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 844; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 845; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 846; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 847; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 848; 849; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25: 850; GFX6-FLUSH: ; %bb.0: 851; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 852; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 853; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 854; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 855; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 856; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 857; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 858; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 859; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 860; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 861; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 862; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 863; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 864; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 865; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 866; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 867; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 868; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 869; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 870; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 871; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 872; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 873; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 874; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 875; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 876; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 877; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 878; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 879; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 880; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 881; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 882; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 883; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 884; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 885; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 886; 887; GFX8-LABEL: v_fdiv_v2f16_ulp25: 888; GFX8: ; %bb.0: 889; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 890; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 891; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 892; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 893; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 894; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 895; GFX8-NEXT: v_rcp_f32_e32 v2, v2 896; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 897; GFX8-NEXT: v_rcp_f32_e32 v5, v5 898; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 899; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 900; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 901; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 902; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 903; GFX8-NEXT: v_mov_b32_e32 v2, 16 904; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 905; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 906; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 907; GFX8-NEXT: s_setpc_b64 s[30:31] 908; 909; GFX9-LABEL: v_fdiv_v2f16_ulp25: 910; GFX9: ; %bb.0: 911; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 912; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 913; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 914; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 915; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 916; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 917; GFX9-NEXT: v_rcp_f32_e32 v2, v2 918; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 919; GFX9-NEXT: v_rcp_f32_e32 v5, v5 920; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 921; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 922; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 923; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 924; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 925; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 926; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 927; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 928; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 929; GFX9-NEXT: s_setpc_b64 s[30:31] 930; 931; GFX10-LABEL: v_fdiv_v2f16_ulp25: 932; GFX10: ; %bb.0: 933; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 934; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 935; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 936; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 937; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 938; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v0 939; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 940; GFX10-NEXT: v_rcp_f32_e32 v4, v4 941; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v5 942; GFX10-NEXT: v_rcp_f32_e32 v3, v3 943; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 944; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 945; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 946; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 947; GFX10-NEXT: v_div_fixup_f16 v0, v4, v1, v0 948; GFX10-NEXT: v_div_fixup_f16 v2, v3, v2, v5 949; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v2 950; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 951; GFX10-NEXT: s_setpc_b64 s[30:31] 952; 953; GFX11-LABEL: v_fdiv_v2f16_ulp25: 954; GFX11: ; %bb.0: 955; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 956; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 957; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 958; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v1 959; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 960; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v0 961; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v2 962; GFX11-NEXT: v_rcp_f32_e32 v4, v4 963; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v5 964; GFX11-NEXT: v_rcp_f32_e32 v3, v3 965; GFX11-NEXT: s_waitcnt_depctr 0xfff 966; GFX11-NEXT: v_dual_mul_f32 v4, v7, v4 :: v_dual_mul_f32 v3, v6, v3 967; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4 968; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 969; GFX11-NEXT: v_div_fixup_f16 v0, v4, v1, v0 970; GFX11-NEXT: v_div_fixup_f16 v2, v3, v2, v5 971; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2 972; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 973; GFX11-NEXT: s_setpc_b64 s[30:31] 974 %fdiv = fdiv <2 x half> %a, %b, !fpmath !0 975 ret <2 x half> %fdiv 976} 977 978define <2 x half> @v_rcp_v2f16(<2 x half> %x) { 979; GFX6-IEEE-LABEL: v_rcp_v2f16: 980; GFX6-IEEE: ; %bb.0: 981; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 982; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, 1.0 983; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 984; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 985; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 986; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 987; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 988; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 989; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 990; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 991; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 992; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 993; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 994; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 995; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v2 996; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2 997; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 998; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v1, v2 999; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1000; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1001; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1002; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1003; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1004; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1005; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1006; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1007; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, v2 1008; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 1009; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1010; 1011; GFX6-FLUSH-LABEL: v_rcp_v2f16: 1012; GFX6-FLUSH: ; %bb.0: 1013; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1014; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1015; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1016; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 1017; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 1018; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 1019; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1020; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1021; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1022; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1023; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 1024; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1025; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 1026; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1027; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1028; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1029; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 1030; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2 1031; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1032; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1033; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v4 1034; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 1035; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v1, v4 1036; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1037; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 1038; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 1039; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 1040; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 1041; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 1042; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 1043; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1044; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 1045; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v4 1046; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 1047; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1048; 1049; GFX8-LABEL: v_rcp_v2f16: 1050; GFX8: ; %bb.0: 1051; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1052; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1053; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0 1054; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2 1055; GFX8-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1056; GFX8-NEXT: v_rcp_f32_e32 v1, v1 1057; GFX8-NEXT: v_rcp_f32_e32 v3, v3 1058; GFX8-NEXT: v_mul_f32_e32 v1, v4, v1 1059; GFX8-NEXT: v_mul_f32_e32 v3, v4, v3 1060; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1 1061; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 1062; GFX8-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 1063; GFX8-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 1064; GFX8-NEXT: v_mov_b32_e32 v2, 16 1065; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1066; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1067; GFX8-NEXT: s_setpc_b64 s[30:31] 1068; 1069; GFX9-LABEL: v_rcp_v2f16: 1070; GFX9: ; %bb.0: 1071; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1072; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1073; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0 1074; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 1075; GFX9-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1076; GFX9-NEXT: v_rcp_f32_e32 v1, v1 1077; GFX9-NEXT: v_rcp_f32_e32 v3, v3 1078; GFX9-NEXT: v_mul_f32_e32 v1, v4, v1 1079; GFX9-NEXT: v_mul_f32_e32 v3, v4, v3 1080; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 1081; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 1082; GFX9-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 1083; GFX9-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 1084; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1085; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1086; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 1087; GFX9-NEXT: s_setpc_b64 s[30:31] 1088; 1089; GFX10-LABEL: v_rcp_v2f16: 1090; GFX10: ; %bb.0: 1091; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1092; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1093; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1094; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 1095; GFX10-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1096; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 1097; GFX10-NEXT: v_rcp_f32_e32 v3, v3 1098; GFX10-NEXT: v_rcp_f32_e32 v2, v2 1099; GFX10-NEXT: v_mul_f32_e32 v3, v4, v3 1100; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2 1101; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 1102; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 1103; GFX10-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0 1104; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0 1105; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1106; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1107; GFX10-NEXT: s_setpc_b64 s[30:31] 1108; 1109; GFX11-LABEL: v_rcp_v2f16: 1110; GFX11: ; %bb.0: 1111; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1112; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1113; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1114; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 1115; GFX11-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1116; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 1117; GFX11-NEXT: v_rcp_f32_e32 v3, v3 1118; GFX11-NEXT: v_rcp_f32_e32 v2, v2 1119; GFX11-NEXT: s_waitcnt_depctr 0xfff 1120; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3 1121; GFX11-NEXT: v_mul_f32_e32 v2, v4, v2 1122; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 1123; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2 1124; GFX11-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0 1125; GFX11-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0 1126; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1127; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1128; GFX11-NEXT: s_setpc_b64 s[30:31] 1129 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x 1130 ret <2 x half> %fdiv 1131} 1132 1133define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) { 1134; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp: 1135; GFX6-IEEE: ; %bb.0: 1136; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1137; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1138; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 1139; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 1140; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 1141; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1142; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 1143; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1144; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1145; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1146; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1147; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1148; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1149; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1150; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v2 1151; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2 1152; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1153; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v1, v2 1154; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1155; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1156; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1157; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1158; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1159; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1160; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1161; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1162; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, v2 1163; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 1164; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1165; 1166; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp: 1167; GFX6-FLUSH: ; %bb.0: 1168; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1169; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1170; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1171; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 1172; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 1173; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 1174; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1175; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1176; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1177; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1178; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 1179; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1180; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 1181; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1182; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1183; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1184; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 1185; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2 1186; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1187; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1188; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v4 1189; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 1190; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v1, v4 1191; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1192; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 1193; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 1194; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 1195; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 1196; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 1197; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 1198; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1199; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 1200; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v4 1201; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 1202; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1203; 1204; GFX8-LABEL: v_rcp_v2f16_arcp: 1205; GFX8: ; %bb.0: 1206; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1207; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1208; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0 1209; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2 1210; GFX8-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1211; GFX8-NEXT: v_rcp_f32_e32 v1, v1 1212; GFX8-NEXT: v_rcp_f32_e32 v3, v3 1213; GFX8-NEXT: v_mul_f32_e32 v1, v4, v1 1214; GFX8-NEXT: v_mul_f32_e32 v3, v4, v3 1215; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1 1216; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 1217; GFX8-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 1218; GFX8-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 1219; GFX8-NEXT: v_mov_b32_e32 v2, 16 1220; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1221; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1222; GFX8-NEXT: s_setpc_b64 s[30:31] 1223; 1224; GFX9-LABEL: v_rcp_v2f16_arcp: 1225; GFX9: ; %bb.0: 1226; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1227; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1228; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0 1229; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 1230; GFX9-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1231; GFX9-NEXT: v_rcp_f32_e32 v1, v1 1232; GFX9-NEXT: v_rcp_f32_e32 v3, v3 1233; GFX9-NEXT: v_mul_f32_e32 v1, v4, v1 1234; GFX9-NEXT: v_mul_f32_e32 v3, v4, v3 1235; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 1236; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 1237; GFX9-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 1238; GFX9-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 1239; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1240; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1241; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 1242; GFX9-NEXT: s_setpc_b64 s[30:31] 1243; 1244; GFX10-LABEL: v_rcp_v2f16_arcp: 1245; GFX10: ; %bb.0: 1246; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1247; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1248; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1249; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 1250; GFX10-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1251; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 1252; GFX10-NEXT: v_rcp_f32_e32 v3, v3 1253; GFX10-NEXT: v_rcp_f32_e32 v2, v2 1254; GFX10-NEXT: v_mul_f32_e32 v3, v4, v3 1255; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2 1256; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 1257; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 1258; GFX10-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0 1259; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0 1260; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1261; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1262; GFX10-NEXT: s_setpc_b64 s[30:31] 1263; 1264; GFX11-LABEL: v_rcp_v2f16_arcp: 1265; GFX11: ; %bb.0: 1266; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1267; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1268; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1269; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 1270; GFX11-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1271; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 1272; GFX11-NEXT: v_rcp_f32_e32 v3, v3 1273; GFX11-NEXT: v_rcp_f32_e32 v2, v2 1274; GFX11-NEXT: s_waitcnt_depctr 0xfff 1275; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3 1276; GFX11-NEXT: v_mul_f32_e32 v2, v4, v2 1277; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 1278; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2 1279; GFX11-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0 1280; GFX11-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0 1281; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1282; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1283; GFX11-NEXT: s_setpc_b64 s[30:31] 1284 %fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x 1285 ret <2 x half> %fdiv 1286} 1287 1288define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) { 1289; GFX6-LABEL: v_rcp_v2f16_arcp_afn: 1290; GFX6: ; %bb.0: 1291; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1292; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 1293; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 1294; GFX6-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1295; GFX6-NEXT: v_rcp_f32_e32 v0, v0 1296; GFX6-NEXT: v_rcp_f32_e32 v1, v1 1297; GFX6-NEXT: v_mul_f32_e32 v0, v2, v0 1298; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 1299; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 1300; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 1301; GFX6-NEXT: s_setpc_b64 s[30:31] 1302; 1303; GFX8-LABEL: v_rcp_v2f16_arcp_afn: 1304; GFX8: ; %bb.0: 1305; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1306; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1307; GFX8-NEXT: v_rcp_f16_e32 v0, v0 1308; GFX8-NEXT: v_mov_b32_e32 v2, 16 1309; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1310; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1311; GFX8-NEXT: s_setpc_b64 s[30:31] 1312; 1313; GFX9-LABEL: v_rcp_v2f16_arcp_afn: 1314; GFX9: ; %bb.0: 1315; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1316; GFX9-NEXT: v_rcp_f16_e32 v1, v0 1317; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1318; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1319; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 1320; GFX9-NEXT: s_setpc_b64 s[30:31] 1321; 1322; GFX10-LABEL: v_rcp_v2f16_arcp_afn: 1323; GFX10: ; %bb.0: 1324; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1325; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1326; GFX10-NEXT: v_rcp_f16_e32 v1, v0 1327; GFX10-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1328; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 1329; GFX10-NEXT: s_setpc_b64 s[30:31] 1330; 1331; GFX11-LABEL: v_rcp_v2f16_arcp_afn: 1332; GFX11: ; %bb.0: 1333; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1334; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1335; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1336; GFX11-NEXT: v_rcp_f16_e32 v0, v0 1337; GFX11-NEXT: v_rcp_f16_e32 v1, v1 1338; GFX11-NEXT: s_waitcnt_depctr 0xfff 1339; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1340; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1341; GFX11-NEXT: s_setpc_b64 s[30:31] 1342 %fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x 1343 ret <2 x half> %fdiv 1344} 1345 1346define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) { 1347; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25: 1348; GFX6-IEEE: ; %bb.0: 1349; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1350; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1351; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 1352; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 1353; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 1354; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1355; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 1356; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1357; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1358; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1359; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1360; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1361; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1362; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1363; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v2 1364; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v2 1365; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1366; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v2, v1, v2 1367; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1368; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1369; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1370; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1371; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1372; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1373; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1374; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1375; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, v2 1376; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 1377; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1378; 1379; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25: 1380; GFX6-FLUSH: ; %bb.0: 1381; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1382; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1383; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1384; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v2 1385; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 1386; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v2, v0, v2 1387; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1388; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1389; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1390; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1391; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 1392; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1393; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 1394; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1395; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1396; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1397; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 1398; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v0, v2 1399; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1400; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1401; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v4 1402; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 1403; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v1, v4 1404; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1405; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 1406; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 1407; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 1408; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 1409; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 1410; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 1411; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1412; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 1413; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, v4 1414; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 1415; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1416; 1417; GFX8-LABEL: v_rcp_v2f16_ulp25: 1418; GFX8: ; %bb.0: 1419; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1420; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1421; GFX8-NEXT: v_rcp_f16_e32 v0, v0 1422; GFX8-NEXT: v_mov_b32_e32 v2, 16 1423; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1424; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1425; GFX8-NEXT: s_setpc_b64 s[30:31] 1426; 1427; GFX9-LABEL: v_rcp_v2f16_ulp25: 1428; GFX9: ; %bb.0: 1429; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1430; GFX9-NEXT: v_rcp_f16_e32 v1, v0 1431; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1432; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1433; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 1434; GFX9-NEXT: s_setpc_b64 s[30:31] 1435; 1436; GFX10-LABEL: v_rcp_v2f16_ulp25: 1437; GFX10: ; %bb.0: 1438; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1439; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1440; GFX10-NEXT: v_rcp_f16_e32 v1, v0 1441; GFX10-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1442; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 1443; GFX10-NEXT: s_setpc_b64 s[30:31] 1444; 1445; GFX11-LABEL: v_rcp_v2f16_ulp25: 1446; GFX11: ; %bb.0: 1447; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1448; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1449; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1450; GFX11-NEXT: v_rcp_f16_e32 v0, v0 1451; GFX11-NEXT: v_rcp_f16_e32 v1, v1 1452; GFX11-NEXT: s_waitcnt_depctr 0xfff 1453; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1454; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1455; GFX11-NEXT: s_setpc_b64 s[30:31] 1456 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x, !fpmath !0 1457 ret <2 x half> %fdiv 1458} 1459 1460define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) { 1461; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25: 1462; GFX6: ; %bb.0: 1463; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1464; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 1465; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 1466; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 1467; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 1468; GFX6-NEXT: v_rcp_f32_e32 v2, v2 1469; GFX6-NEXT: v_rcp_f32_e32 v3, v3 1470; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 1471; GFX6-NEXT: v_mul_f32_e32 v1, v1, v3 1472; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 1473; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 1474; GFX6-NEXT: s_setpc_b64 s[30:31] 1475; 1476; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25: 1477; GFX8: ; %bb.0: 1478; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1479; GFX8-NEXT: v_rcp_f16_e32 v2, v1 1480; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1481; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 1482; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1483; GFX8-NEXT: v_mov_b32_e32 v1, 16 1484; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1485; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1486; GFX8-NEXT: s_setpc_b64 s[30:31] 1487; 1488; GFX9-LABEL: v_fdiv_v2f16_afn_ulp25: 1489; GFX9: ; %bb.0: 1490; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1491; GFX9-NEXT: v_rcp_f16_e32 v2, v1 1492; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1493; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 1494; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1495; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff 1496; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 1497; GFX9-NEXT: s_setpc_b64 s[30:31] 1498; 1499; GFX10-LABEL: v_fdiv_v2f16_afn_ulp25: 1500; GFX10: ; %bb.0: 1501; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1502; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1503; GFX10-NEXT: v_rcp_f16_e32 v2, v1 1504; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1505; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 1506; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1507; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v2, v0 1508; GFX10-NEXT: s_setpc_b64 s[30:31] 1509; 1510; GFX11-LABEL: v_fdiv_v2f16_afn_ulp25: 1511; GFX11: ; %bb.0: 1512; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1513; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1514; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 1515; GFX11-NEXT: v_rcp_f16_e32 v1, v1 1516; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 1517; GFX11-NEXT: v_rcp_f16_e32 v2, v2 1518; GFX11-NEXT: s_waitcnt_depctr 0xfff 1519; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 1520; GFX11-NEXT: v_mul_f16_e32 v2, v3, v2 1521; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2 1522; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1523; GFX11-NEXT: s_setpc_b64 s[30:31] 1524 %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0 1525 ret <2 x half> %fdiv 1526} 1527 1528define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) { 1529; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25: 1530; GFX6-IEEE: ; %bb.0: 1531; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1532; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 1533; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2 1534; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 1535; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3 1536; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 1537; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 1538; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 1539; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 1540; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 1541; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 1542; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 1543; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 1544; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 1545; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 1546; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0 1547; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 1548; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2 1549; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 1550; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1551; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0 1552; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1553; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1554; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5 1555; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1556; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5 1557; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6 1558; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1 1559; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 1560; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1561; 1562; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25: 1563; GFX6-FLUSH: ; %bb.0: 1564; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1565; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1566; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 1567; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0 1568; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 1569; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0 1570; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1571; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 1572; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 1573; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 1574; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 1575; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 1576; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 1577; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1578; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 1579; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 1580; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 1581; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0 1582; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1583; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1584; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1 1585; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2 1586; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1 1587; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1588; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0 1589; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1590; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1591; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 1592; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1593; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 1594; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1595; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6 1596; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1 1597; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 1598; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1599; 1600; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25: 1601; GFX8: ; %bb.0: 1602; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1603; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 1604; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 1605; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 1606; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 1607; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 1608; GFX8-NEXT: v_rcp_f32_e32 v2, v2 1609; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 1610; GFX8-NEXT: v_rcp_f32_e32 v5, v5 1611; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 1612; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 1613; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 1614; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 1615; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 1616; GFX8-NEXT: v_mov_b32_e32 v2, 16 1617; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 1618; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1619; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1620; GFX8-NEXT: s_setpc_b64 s[30:31] 1621; 1622; GFX9-LABEL: v_fdiv_v2f16_arcp_ulp25: 1623; GFX9: ; %bb.0: 1624; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1625; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 1626; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 1627; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 1628; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 1629; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 1630; GFX9-NEXT: v_rcp_f32_e32 v2, v2 1631; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 1632; GFX9-NEXT: v_rcp_f32_e32 v5, v5 1633; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 1634; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 1635; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 1636; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 1637; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 1638; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1639; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 1640; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1641; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 1642; GFX9-NEXT: s_setpc_b64 s[30:31] 1643; 1644; GFX10-LABEL: v_fdiv_v2f16_arcp_ulp25: 1645; GFX10: ; %bb.0: 1646; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1647; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1648; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 1649; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 1650; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 1651; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v0 1652; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 1653; GFX10-NEXT: v_rcp_f32_e32 v4, v4 1654; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v5 1655; GFX10-NEXT: v_rcp_f32_e32 v3, v3 1656; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 1657; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 1658; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 1659; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 1660; GFX10-NEXT: v_div_fixup_f16 v0, v4, v1, v0 1661; GFX10-NEXT: v_div_fixup_f16 v2, v3, v2, v5 1662; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v2 1663; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1664; GFX10-NEXT: s_setpc_b64 s[30:31] 1665; 1666; GFX11-LABEL: v_fdiv_v2f16_arcp_ulp25: 1667; GFX11: ; %bb.0: 1668; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1669; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1670; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 1671; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v1 1672; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 1673; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v0 1674; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v2 1675; GFX11-NEXT: v_rcp_f32_e32 v4, v4 1676; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v5 1677; GFX11-NEXT: v_rcp_f32_e32 v3, v3 1678; GFX11-NEXT: s_waitcnt_depctr 0xfff 1679; GFX11-NEXT: v_dual_mul_f32 v4, v7, v4 :: v_dual_mul_f32 v3, v6, v3 1680; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4 1681; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 1682; GFX11-NEXT: v_div_fixup_f16 v0, v4, v1, v0 1683; GFX11-NEXT: v_div_fixup_f16 v2, v3, v2, v5 1684; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2 1685; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1686; GFX11-NEXT: s_setpc_b64 s[30:31] 1687 %fdiv = fdiv arcp <2 x half> %a, %b, !fpmath !0 1688 ret <2 x half> %fdiv 1689} 1690 1691define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) { 1692; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1693; GFX6: ; %bb.0: 1694; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1695; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 1696; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 1697; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 1698; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 1699; GFX6-NEXT: v_rcp_f32_e32 v2, v2 1700; GFX6-NEXT: v_rcp_f32_e32 v3, v3 1701; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 1702; GFX6-NEXT: v_mul_f32_e32 v1, v1, v3 1703; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 1704; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 1705; GFX6-NEXT: s_setpc_b64 s[30:31] 1706; 1707; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1708; GFX8: ; %bb.0: 1709; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1710; GFX8-NEXT: v_rcp_f16_e32 v2, v1 1711; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1712; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 1713; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1714; GFX8-NEXT: v_mov_b32_e32 v1, 16 1715; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1716; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1717; GFX8-NEXT: s_setpc_b64 s[30:31] 1718; 1719; GFX9-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1720; GFX9: ; %bb.0: 1721; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1722; GFX9-NEXT: v_rcp_f16_e32 v2, v1 1723; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1724; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 1725; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1726; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff 1727; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 1728; GFX9-NEXT: s_setpc_b64 s[30:31] 1729; 1730; GFX10-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1731; GFX10: ; %bb.0: 1732; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1733; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1734; GFX10-NEXT: v_rcp_f16_e32 v2, v1 1735; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1736; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 1737; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1738; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v2, v0 1739; GFX10-NEXT: s_setpc_b64 s[30:31] 1740; 1741; GFX11-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1742; GFX11: ; %bb.0: 1743; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1744; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1745; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 1746; GFX11-NEXT: v_rcp_f16_e32 v1, v1 1747; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 1748; GFX11-NEXT: v_rcp_f16_e32 v2, v2 1749; GFX11-NEXT: s_waitcnt_depctr 0xfff 1750; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 1751; GFX11-NEXT: v_mul_f16_e32 v2, v3, v2 1752; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2 1753; GFX11-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1754; GFX11-NEXT: s_setpc_b64 s[30:31] 1755 %fdiv = fdiv afn arcp <2 x half> %a, %b, !fpmath !0 1756 ret <2 x half> %fdiv 1757} 1758 1759!0 = !{float 2.500000e+00} 1760