1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Denormal mode shouldn't matter for f16, check with and without flushing. 3; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-IEEE %s 4; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-FLUSH %s 5 6; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s 7; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s 8 9; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s 10; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s 11 12; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s 13; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s 14 15define half @v_fdiv_f16(half %a, half %b) { 16; GFX6-IEEE-LABEL: v_fdiv_f16: 17; GFX6-IEEE: ; %bb.0: 18; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 20; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 21; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 22; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 23; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 24; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 25; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 26; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 27; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 28; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 29; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 30; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 31; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 32; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 33; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 34; 35; GFX6-FLUSH-LABEL: v_fdiv_f16: 36; GFX6-FLUSH: ; %bb.0: 37; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 38; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 39; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 40; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 41; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 42; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 43; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 44; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 45; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 46; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 47; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 48; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 49; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 50; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 51; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 52; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 53; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 54; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 55; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 56; 57; GFX89-LABEL: v_fdiv_f16: 58; GFX89: ; %bb.0: 59; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 60; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 61; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 62; GFX89-NEXT: v_rcp_f32_e32 v2, v2 63; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 64; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 65; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 66; GFX89-NEXT: s_setpc_b64 s[30:31] 67; 68; GFX10-LABEL: v_fdiv_f16: 69; GFX10: ; %bb.0: 70; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 71; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 72; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 73; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 74; GFX10-NEXT: v_rcp_f32_e32 v2, v2 75; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2 76; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 77; GFX10-NEXT: v_div_fixup_f16 v0, v2, v1, v0 78; GFX10-NEXT: s_setpc_b64 s[30:31] 79 %fdiv = fdiv half %a, %b 80 ret half %fdiv 81} 82 83define half @v_fdiv_f16_afn(half %a, half %b) { 84; GFX6-LABEL: v_fdiv_f16_afn: 85; GFX6: ; %bb.0: 86; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 87; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 88; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 89; GFX6-NEXT: v_rcp_f32_e32 v1, v1 90; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 91; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 92; GFX6-NEXT: s_setpc_b64 s[30:31] 93; 94; GFX89-LABEL: v_fdiv_f16_afn: 95; GFX89: ; %bb.0: 96; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 97; GFX89-NEXT: v_rcp_f16_e32 v1, v1 98; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 99; GFX89-NEXT: s_setpc_b64 s[30:31] 100; 101; GFX10-LABEL: v_fdiv_f16_afn: 102; GFX10: ; %bb.0: 103; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 104; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 105; GFX10-NEXT: v_rcp_f16_e32 v1, v1 106; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1 107; GFX10-NEXT: s_setpc_b64 s[30:31] 108 %fdiv = fdiv afn half %a, %b 109 ret half %fdiv 110} 111 112define half @v_fdiv_f16_ulp25(half %a, half %b) { 113; GFX6-IEEE-LABEL: v_fdiv_f16_ulp25: 114; GFX6-IEEE: ; %bb.0: 115; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 116; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 117; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 118; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 119; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 120; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 121; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 122; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 123; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 124; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 125; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 126; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 127; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 128; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 129; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 130; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 131; 132; GFX6-FLUSH-LABEL: v_fdiv_f16_ulp25: 133; GFX6-FLUSH: ; %bb.0: 134; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 135; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 136; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 137; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 138; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 139; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 140; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 141; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 142; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 143; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 144; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 145; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 146; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 147; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 148; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 149; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 150; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 151; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 152; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 153; 154; GFX89-LABEL: v_fdiv_f16_ulp25: 155; GFX89: ; %bb.0: 156; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 157; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 158; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 159; GFX89-NEXT: v_rcp_f32_e32 v2, v2 160; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 161; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 162; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 163; GFX89-NEXT: s_setpc_b64 s[30:31] 164; 165; GFX10-LABEL: v_fdiv_f16_ulp25: 166; GFX10: ; %bb.0: 167; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 168; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 169; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 170; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 171; GFX10-NEXT: v_rcp_f32_e32 v2, v2 172; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2 173; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 174; GFX10-NEXT: v_div_fixup_f16 v0, v2, v1, v0 175; GFX10-NEXT: s_setpc_b64 s[30:31] 176 %fdiv = fdiv half %a, %b, !fpmath !0 177 ret half %fdiv 178} 179 180define half @v_rcp_f16(half %x) { 181; GFX6-IEEE-LABEL: v_rcp_f16: 182; GFX6-IEEE: ; %bb.0: 183; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 184; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 185; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 186; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 187; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 188; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 189; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 190; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 191; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 192; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 193; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 194; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 195; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 196; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 197; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 198; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 199; 200; GFX6-FLUSH-LABEL: v_rcp_f16: 201; GFX6-FLUSH: ; %bb.0: 202; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 203; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 204; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 205; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 206; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 207; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 208; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 209; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 210; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 211; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 212; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 213; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 214; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 215; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 216; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 217; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 218; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 219; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 220; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 221; 222; GFX89-LABEL: v_rcp_f16: 223; GFX89: ; %bb.0: 224; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 225; GFX89-NEXT: v_cvt_f32_f16_e32 v1, v0 226; GFX89-NEXT: v_cvt_f32_f16_e32 v2, 1.0 227; GFX89-NEXT: v_rcp_f32_e32 v1, v1 228; GFX89-NEXT: v_mul_f32_e32 v1, v2, v1 229; GFX89-NEXT: v_cvt_f16_f32_e32 v1, v1 230; GFX89-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 231; GFX89-NEXT: s_setpc_b64 s[30:31] 232; 233; GFX10-LABEL: v_rcp_f16: 234; GFX10: ; %bb.0: 235; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 236; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 237; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v0 238; GFX10-NEXT: v_cvt_f32_f16_e32 v2, 1.0 239; GFX10-NEXT: v_rcp_f32_e32 v1, v1 240; GFX10-NEXT: v_mul_f32_e32 v1, v2, v1 241; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 242; GFX10-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 243; GFX10-NEXT: s_setpc_b64 s[30:31] 244 %fdiv = fdiv half 1.0, %x 245 ret half %fdiv 246} 247 248define half @v_rcp_f16_arcp(half %x) { 249; GFX6-IEEE-LABEL: v_rcp_f16_arcp: 250; GFX6-IEEE: ; %bb.0: 251; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 252; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 253; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 254; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 255; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 256; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 257; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 258; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 259; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 260; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 261; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 262; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 263; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 264; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 265; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 266; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 267; 268; GFX6-FLUSH-LABEL: v_rcp_f16_arcp: 269; GFX6-FLUSH: ; %bb.0: 270; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 271; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 272; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 273; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 274; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 275; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 276; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 277; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 278; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 279; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 280; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 281; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 282; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 283; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 284; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 285; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 286; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 287; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 288; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 289; 290; GFX89-LABEL: v_rcp_f16_arcp: 291; GFX89: ; %bb.0: 292; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 293; GFX89-NEXT: v_cvt_f32_f16_e32 v1, v0 294; GFX89-NEXT: v_cvt_f32_f16_e32 v2, 1.0 295; GFX89-NEXT: v_rcp_f32_e32 v1, v1 296; GFX89-NEXT: v_mul_f32_e32 v1, v2, v1 297; GFX89-NEXT: v_cvt_f16_f32_e32 v1, v1 298; GFX89-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 299; GFX89-NEXT: s_setpc_b64 s[30:31] 300; 301; GFX10-LABEL: v_rcp_f16_arcp: 302; GFX10: ; %bb.0: 303; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 304; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 305; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v0 306; GFX10-NEXT: v_cvt_f32_f16_e32 v2, 1.0 307; GFX10-NEXT: v_rcp_f32_e32 v1, v1 308; GFX10-NEXT: v_mul_f32_e32 v1, v2, v1 309; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 310; GFX10-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 311; GFX10-NEXT: s_setpc_b64 s[30:31] 312 %fdiv = fdiv arcp half 1.0, %x 313 ret half %fdiv 314} 315 316define half @v_rcp_f16_arcp_afn(half %x) { 317; GFX6-LABEL: v_rcp_f16_arcp_afn: 318; GFX6: ; %bb.0: 319; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 320; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 321; GFX6-NEXT: v_cvt_f32_f16_e32 v1, 1.0 322; GFX6-NEXT: v_rcp_f32_e32 v0, v0 323; GFX6-NEXT: v_mul_f32_e32 v0, v1, v0 324; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 325; GFX6-NEXT: s_setpc_b64 s[30:31] 326; 327; GFX89-LABEL: v_rcp_f16_arcp_afn: 328; GFX89: ; %bb.0: 329; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 330; GFX89-NEXT: v_rcp_f16_e32 v0, v0 331; GFX89-NEXT: s_setpc_b64 s[30:31] 332; 333; GFX10-LABEL: v_rcp_f16_arcp_afn: 334; GFX10: ; %bb.0: 335; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 336; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 337; GFX10-NEXT: v_rcp_f16_e32 v0, v0 338; GFX10-NEXT: s_setpc_b64 s[30:31] 339 %fdiv = fdiv arcp afn half 1.0, %x 340 ret half %fdiv 341} 342 343define half @v_rcp_f16_ulp25(half %x) { 344; GFX6-IEEE-LABEL: v_rcp_f16_ulp25: 345; GFX6-IEEE: ; %bb.0: 346; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 347; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 348; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 349; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 350; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 351; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 352; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 353; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 354; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 355; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 356; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 357; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 358; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 359; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v1 360; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 361; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 362; 363; GFX6-FLUSH-LABEL: v_rcp_f16_ulp25: 364; GFX6-FLUSH: ; %bb.0: 365; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 366; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, 1.0 367; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 368; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v1 369; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 370; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v1 371; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 372; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 373; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 374; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 375; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 376; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 377; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 378; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 379; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 380; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v1 381; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 382; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 383; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 384; 385; GFX89-LABEL: v_rcp_f16_ulp25: 386; GFX89: ; %bb.0: 387; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 388; GFX89-NEXT: v_rcp_f16_e32 v0, v0 389; GFX89-NEXT: s_setpc_b64 s[30:31] 390; 391; GFX10-LABEL: v_rcp_f16_ulp25: 392; GFX10: ; %bb.0: 393; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 394; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 395; GFX10-NEXT: v_rcp_f16_e32 v0, v0 396; GFX10-NEXT: s_setpc_b64 s[30:31] 397 %fdiv = fdiv half 1.0, %x, !fpmath !0 398 ret half %fdiv 399} 400 401define half @v_fdiv_f16_afn_ulp25(half %a, half %b) { 402; GFX6-LABEL: v_fdiv_f16_afn_ulp25: 403; GFX6: ; %bb.0: 404; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 405; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 406; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 407; GFX6-NEXT: v_rcp_f32_e32 v1, v1 408; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 409; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 410; GFX6-NEXT: s_setpc_b64 s[30:31] 411; 412; GFX89-LABEL: v_fdiv_f16_afn_ulp25: 413; GFX89: ; %bb.0: 414; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 415; GFX89-NEXT: v_rcp_f16_e32 v1, v1 416; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1 417; GFX89-NEXT: s_setpc_b64 s[30:31] 418; 419; GFX10-LABEL: v_fdiv_f16_afn_ulp25: 420; GFX10: ; %bb.0: 421; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 422; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 423; GFX10-NEXT: v_rcp_f16_e32 v1, v1 424; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1 425; GFX10-NEXT: s_setpc_b64 s[30:31] 426 %fdiv = fdiv afn half %a, %b, !fpmath !0 427 ret half %fdiv 428} 429 430define half @v_fdiv_f16_arcp_ulp25(half %a, half %b) { 431; GFX6-IEEE-LABEL: v_fdiv_f16_arcp_ulp25: 432; GFX6-IEEE: ; %bb.0: 433; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 434; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 435; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 436; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 437; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2 438; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 439; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0 440; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3 441; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 442; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4 443; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5 444; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4 445; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5 446; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0 447; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 448; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 449; 450; GFX6-FLUSH-LABEL: v_fdiv_f16_arcp_ulp25: 451; GFX6-FLUSH: ; %bb.0: 452; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 453; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 454; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 455; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0 456; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 457; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0 458; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 459; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0 460; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3 461; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 462; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4 463; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5 464; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4 465; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 466; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5 467; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0 468; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 469; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 470; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 471; 472; GFX89-LABEL: v_fdiv_f16_arcp_ulp25: 473; GFX89: ; %bb.0: 474; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 475; GFX89-NEXT: v_cvt_f32_f16_e32 v2, v1 476; GFX89-NEXT: v_cvt_f32_f16_e32 v3, v0 477; GFX89-NEXT: v_rcp_f32_e32 v2, v2 478; GFX89-NEXT: v_mul_f32_e32 v2, v3, v2 479; GFX89-NEXT: v_cvt_f16_f32_e32 v2, v2 480; GFX89-NEXT: v_div_fixup_f16 v0, v2, v1, v0 481; GFX89-NEXT: s_setpc_b64 s[30:31] 482; 483; GFX10-LABEL: v_fdiv_f16_arcp_ulp25: 484; GFX10: ; %bb.0: 485; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 486; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 487; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 488; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 489; GFX10-NEXT: v_rcp_f32_e32 v2, v2 490; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2 491; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 492; GFX10-NEXT: v_div_fixup_f16 v0, v2, v1, v0 493; GFX10-NEXT: s_setpc_b64 s[30:31] 494 %fdiv = fdiv arcp half %a, %b, !fpmath !0 495 ret half %fdiv 496} 497 498define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { 499; GFX6-IEEE-LABEL: v_fdiv_v2f16: 500; GFX6-IEEE: ; %bb.0: 501; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 502; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 503; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 504; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0 505; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1 506; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 507; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2 508; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 509; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2 510; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 511; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 512; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 513; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 514; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 515; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 516; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 517; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 518; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2 519; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0 520; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 521; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0 522; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 523; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 524; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 525; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 526; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 527; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 528; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 529; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 530; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0 531; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 532; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16 533; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16 534; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0 535; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0 536; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 537; 538; GFX6-FLUSH-LABEL: v_fdiv_v2f16: 539; GFX6-FLUSH: ; %bb.0: 540; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 541; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0 542; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1 543; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0 544; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1 545; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2 546; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 547; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2 548; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 549; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 550; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 551; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 552; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 553; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 554; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 555; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 556; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 557; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 558; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 559; GFX6-FLUSH-NEXT: v_div_fixup_f32 v2, v4, v3, v2 560; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 561; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2 562; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0 563; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 564; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0 565; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 566; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 567; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 568; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 569; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 570; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 571; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 572; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 573; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 574; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v1, v0 575; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 576; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v2, 0, 16 577; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16 578; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0 579; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0 580; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 581; 582; GFX8-LABEL: v_fdiv_v2f16: 583; GFX8: ; %bb.0: 584; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 585; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 586; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 587; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 588; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 589; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 590; GFX8-NEXT: v_rcp_f32_e32 v2, v2 591; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 592; GFX8-NEXT: v_rcp_f32_e32 v5, v5 593; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 594; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 595; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 596; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 597; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 598; GFX8-NEXT: v_mov_b32_e32 v2, 16 599; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 600; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 601; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 602; GFX8-NEXT: s_setpc_b64 s[30:31] 603; 604; GFX9-LABEL: v_fdiv_v2f16: 605; GFX9: ; %bb.0: 606; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 607; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 608; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 609; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 610; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 611; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 612; GFX9-NEXT: v_rcp_f32_e32 v2, v2 613; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 614; GFX9-NEXT: v_rcp_f32_e32 v5, v5 615; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 616; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 617; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 618; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 619; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 620; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 621; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 622; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 623; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 624; GFX9-NEXT: s_setpc_b64 s[30:31] 625; 626; GFX10-LABEL: v_fdiv_v2f16: 627; GFX10: ; %bb.0: 628; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 629; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 630; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 631; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 632; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 633; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v0 634; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 635; GFX10-NEXT: v_rcp_f32_e32 v4, v4 636; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v5 637; GFX10-NEXT: v_rcp_f32_e32 v3, v3 638; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 639; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 640; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 641; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 642; GFX10-NEXT: v_div_fixup_f16 v0, v4, v1, v0 643; GFX10-NEXT: v_div_fixup_f16 v2, v3, v2, v5 644; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v2 645; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 646; GFX10-NEXT: s_setpc_b64 s[30:31] 647 %fdiv = fdiv <2 x half> %a, %b 648 ret <2 x half> %fdiv 649} 650 651define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) { 652; GFX6-LABEL: v_fdiv_v2f16_afn: 653; GFX6: ; %bb.0: 654; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 655; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1 656; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 657; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 658; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 659; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 660; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 661; GFX6-NEXT: v_rcp_f32_e32 v1, v1 662; GFX6-NEXT: v_rcp_f32_e32 v3, v3 663; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 664; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3 665; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 666; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 667; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 668; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 669; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 670; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 671; GFX6-NEXT: s_setpc_b64 s[30:31] 672; 673; GFX8-LABEL: v_fdiv_v2f16_afn: 674; GFX8: ; %bb.0: 675; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 676; GFX8-NEXT: v_rcp_f16_e32 v2, v1 677; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 678; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 679; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 680; GFX8-NEXT: v_mov_b32_e32 v1, 16 681; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 682; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 683; GFX8-NEXT: s_setpc_b64 s[30:31] 684; 685; GFX9-LABEL: v_fdiv_v2f16_afn: 686; GFX9: ; %bb.0: 687; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 688; GFX9-NEXT: v_rcp_f16_e32 v2, v1 689; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 690; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 691; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 692; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff 693; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 694; GFX9-NEXT: s_setpc_b64 s[30:31] 695; 696; GFX10-LABEL: v_fdiv_v2f16_afn: 697; GFX10: ; %bb.0: 698; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 699; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 700; GFX10-NEXT: v_rcp_f16_e32 v2, v1 701; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 702; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 703; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 704; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v2, v0 705; GFX10-NEXT: s_setpc_b64 s[30:31] 706 %fdiv = fdiv afn <2 x half> %a, %b 707 ret <2 x half> %fdiv 708} 709 710define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { 711; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25: 712; GFX6-IEEE: ; %bb.0: 713; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 714; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 715; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 716; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0 717; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1 718; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 719; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2 720; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 721; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2 722; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 723; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 724; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 725; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 726; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 727; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 728; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 729; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 730; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2 731; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0 732; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 733; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0 734; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 735; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 736; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 737; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 738; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 739; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 740; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 741; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 742; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0 743; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 744; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16 745; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16 746; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0 747; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0 748; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 749; 750; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25: 751; GFX6-FLUSH: ; %bb.0: 752; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 753; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0 754; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1 755; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0 756; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1 757; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2 758; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 759; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2 760; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 761; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 762; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 763; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 764; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 765; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 766; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 767; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 768; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 769; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 770; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 771; GFX6-FLUSH-NEXT: v_div_fixup_f32 v2, v4, v3, v2 772; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 773; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2 774; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0 775; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 776; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0 777; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 778; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 779; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 780; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 781; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 782; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 783; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 784; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 785; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 786; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v1, v0 787; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 788; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v2, 0, 16 789; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16 790; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0 791; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0 792; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 793; 794; GFX8-LABEL: v_fdiv_v2f16_ulp25: 795; GFX8: ; %bb.0: 796; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 797; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 798; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 799; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 800; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 801; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 802; GFX8-NEXT: v_rcp_f32_e32 v2, v2 803; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 804; GFX8-NEXT: v_rcp_f32_e32 v5, v5 805; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 806; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 807; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 808; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 809; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 810; GFX8-NEXT: v_mov_b32_e32 v2, 16 811; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 812; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 813; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 814; GFX8-NEXT: s_setpc_b64 s[30:31] 815; 816; GFX9-LABEL: v_fdiv_v2f16_ulp25: 817; GFX9: ; %bb.0: 818; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 819; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 820; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 821; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 822; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 823; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 824; GFX9-NEXT: v_rcp_f32_e32 v2, v2 825; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 826; GFX9-NEXT: v_rcp_f32_e32 v5, v5 827; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 828; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 829; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 830; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 831; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 832; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 833; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 834; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 835; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 836; GFX9-NEXT: s_setpc_b64 s[30:31] 837; 838; GFX10-LABEL: v_fdiv_v2f16_ulp25: 839; GFX10: ; %bb.0: 840; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 841; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 842; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 843; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 844; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 845; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v0 846; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 847; GFX10-NEXT: v_rcp_f32_e32 v4, v4 848; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v5 849; GFX10-NEXT: v_rcp_f32_e32 v3, v3 850; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 851; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 852; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 853; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 854; GFX10-NEXT: v_div_fixup_f16 v0, v4, v1, v0 855; GFX10-NEXT: v_div_fixup_f16 v2, v3, v2, v5 856; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v2 857; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 858; GFX10-NEXT: s_setpc_b64 s[30:31] 859 %fdiv = fdiv <2 x half> %a, %b, !fpmath !0 860 ret <2 x half> %fdiv 861} 862 863define <2 x half> @v_rcp_v2f16(<2 x half> %x) { 864; GFX6-IEEE-LABEL: v_rcp_v2f16: 865; GFX6-IEEE: ; %bb.0: 866; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 867; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 868; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 869; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0 870; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 871; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1 872; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 873; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1 874; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 875; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 876; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 877; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 878; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 879; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 880; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 881; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v3, v2, v1 882; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v1 883; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 884; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v0, v1 885; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 886; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 887; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 888; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 889; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 890; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 891; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 892; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 893; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v1 894; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 895; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16 896; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16 897; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0 898; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0 899; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 900; 901; GFX6-FLUSH-LABEL: v_rcp_v2f16: 902; GFX6-FLUSH: ; %bb.0: 903; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 904; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00 905; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0 906; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6 907; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0 908; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1 909; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 910; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1 911; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 912; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 913; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 914; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 915; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 916; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 917; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 918; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 919; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 920; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6 921; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 922; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v3, v2, v1 923; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 924; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 925; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v4 926; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 927; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v0, v4 928; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 929; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 930; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 931; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 932; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 933; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 934; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 935; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 936; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 937; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v4 938; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 939; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v1, 0, 16 940; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16 941; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0 942; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0 943; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 944; 945; GFX8-LABEL: v_rcp_v2f16: 946; GFX8: ; %bb.0: 947; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 948; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0 949; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0 950; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2 951; GFX8-NEXT: v_cvt_f32_f16_e32 v4, 1.0 952; GFX8-NEXT: v_rcp_f32_e32 v1, v1 953; GFX8-NEXT: v_rcp_f32_e32 v3, v3 954; GFX8-NEXT: v_mul_f32_e32 v1, v4, v1 955; GFX8-NEXT: v_mul_f32_e32 v3, v4, v3 956; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1 957; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 958; GFX8-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 959; GFX8-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 960; GFX8-NEXT: v_mov_b32_e32 v2, 16 961; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 962; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 963; GFX8-NEXT: s_setpc_b64 s[30:31] 964; 965; GFX9-LABEL: v_rcp_v2f16: 966; GFX9: ; %bb.0: 967; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 968; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 969; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0 970; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 971; GFX9-NEXT: v_cvt_f32_f16_e32 v4, 1.0 972; GFX9-NEXT: v_rcp_f32_e32 v1, v1 973; GFX9-NEXT: v_rcp_f32_e32 v3, v3 974; GFX9-NEXT: v_mul_f32_e32 v1, v4, v1 975; GFX9-NEXT: v_mul_f32_e32 v3, v4, v3 976; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 977; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 978; GFX9-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 979; GFX9-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 980; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 981; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 982; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 983; GFX9-NEXT: s_setpc_b64 s[30:31] 984; 985; GFX10-LABEL: v_rcp_v2f16: 986; GFX10: ; %bb.0: 987; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 988; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 989; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0 990; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 991; GFX10-NEXT: v_cvt_f32_f16_e32 v4, 1.0 992; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 993; GFX10-NEXT: v_rcp_f32_e32 v3, v3 994; GFX10-NEXT: v_rcp_f32_e32 v2, v2 995; GFX10-NEXT: v_mul_f32_e32 v3, v4, v3 996; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2 997; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 998; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 999; GFX10-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0 1000; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0 1001; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1002; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1003; GFX10-NEXT: s_setpc_b64 s[30:31] 1004 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x 1005 ret <2 x half> %fdiv 1006} 1007 1008define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) { 1009; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp: 1010; GFX6-IEEE: ; %bb.0: 1011; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1012; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 1013; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 1014; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1015; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 1016; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1 1017; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1018; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1 1019; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1020; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1021; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1022; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1023; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1024; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1025; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1026; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v3, v2, v1 1027; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v1 1028; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1029; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v0, v1 1030; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 1031; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1032; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1033; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1034; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1035; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1036; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1037; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1038; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v1 1039; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1040; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16 1041; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16 1042; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1043; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0 1044; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1045; 1046; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp: 1047; GFX6-FLUSH: ; %bb.0: 1048; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1049; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00 1050; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0 1051; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6 1052; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1053; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1 1054; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 1055; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1 1056; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1057; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1058; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1059; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1060; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 1061; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1062; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 1063; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1064; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1065; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6 1066; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1067; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v3, v2, v1 1068; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1069; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 1070; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v4 1071; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 1072; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v0, v4 1073; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1074; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 1075; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 1076; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 1077; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 1078; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 1079; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 1080; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1081; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 1082; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v4 1083; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1084; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v1, 0, 16 1085; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16 1086; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1087; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0 1088; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1089; 1090; GFX8-LABEL: v_rcp_v2f16_arcp: 1091; GFX8: ; %bb.0: 1092; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1093; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1094; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v0 1095; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v2 1096; GFX8-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1097; GFX8-NEXT: v_rcp_f32_e32 v1, v1 1098; GFX8-NEXT: v_rcp_f32_e32 v3, v3 1099; GFX8-NEXT: v_mul_f32_e32 v1, v4, v1 1100; GFX8-NEXT: v_mul_f32_e32 v3, v4, v3 1101; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1 1102; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 1103; GFX8-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 1104; GFX8-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 1105; GFX8-NEXT: v_mov_b32_e32 v2, 16 1106; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1107; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1108; GFX8-NEXT: s_setpc_b64 s[30:31] 1109; 1110; GFX9-LABEL: v_rcp_v2f16_arcp: 1111; GFX9: ; %bb.0: 1112; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1113; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1114; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v0 1115; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 1116; GFX9-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1117; GFX9-NEXT: v_rcp_f32_e32 v1, v1 1118; GFX9-NEXT: v_rcp_f32_e32 v3, v3 1119; GFX9-NEXT: v_mul_f32_e32 v1, v4, v1 1120; GFX9-NEXT: v_mul_f32_e32 v3, v4, v3 1121; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 1122; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 1123; GFX9-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0 1124; GFX9-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0 1125; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1126; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1127; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 1128; GFX9-NEXT: s_setpc_b64 s[30:31] 1129; 1130; GFX10-LABEL: v_rcp_v2f16_arcp: 1131; GFX10: ; %bb.0: 1132; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1133; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1134; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0 1135; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v0 1136; GFX10-NEXT: v_cvt_f32_f16_e32 v4, 1.0 1137; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v1 1138; GFX10-NEXT: v_rcp_f32_e32 v3, v3 1139; GFX10-NEXT: v_rcp_f32_e32 v2, v2 1140; GFX10-NEXT: v_mul_f32_e32 v3, v4, v3 1141; GFX10-NEXT: v_mul_f32_e32 v2, v4, v2 1142; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 1143; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2 1144; GFX10-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0 1145; GFX10-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0 1146; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1147; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1148; GFX10-NEXT: s_setpc_b64 s[30:31] 1149 %fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x 1150 ret <2 x half> %fdiv 1151} 1152 1153define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) { 1154; GFX6-LABEL: v_rcp_v2f16_arcp_afn: 1155; GFX6: ; %bb.0: 1156; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1157; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0 1158; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1159; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 1160; GFX6-NEXT: v_cvt_f32_f16_e32 v2, 1.0 1161; GFX6-NEXT: v_rcp_f32_e32 v1, v1 1162; GFX6-NEXT: v_rcp_f32_e32 v0, v0 1163; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 1164; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 1165; GFX6-NEXT: v_mul_f32_e32 v0, v2, v0 1166; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 1167; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 1168; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 1169; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1170; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 1171; GFX6-NEXT: s_setpc_b64 s[30:31] 1172; 1173; GFX8-LABEL: v_rcp_v2f16_arcp_afn: 1174; GFX8: ; %bb.0: 1175; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1176; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1177; GFX8-NEXT: v_rcp_f16_e32 v0, v0 1178; GFX8-NEXT: v_mov_b32_e32 v2, 16 1179; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1180; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1181; GFX8-NEXT: s_setpc_b64 s[30:31] 1182; 1183; GFX9-LABEL: v_rcp_v2f16_arcp_afn: 1184; GFX9: ; %bb.0: 1185; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1186; GFX9-NEXT: v_rcp_f16_e32 v1, v0 1187; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1188; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1189; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 1190; GFX9-NEXT: s_setpc_b64 s[30:31] 1191; 1192; GFX10-LABEL: v_rcp_v2f16_arcp_afn: 1193; GFX10: ; %bb.0: 1194; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1195; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1196; GFX10-NEXT: v_rcp_f16_e32 v1, v0 1197; GFX10-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1198; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 1199; GFX10-NEXT: s_setpc_b64 s[30:31] 1200 %fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x 1201 ret <2 x half> %fdiv 1202} 1203 1204define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) { 1205; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25: 1206; GFX6-IEEE: ; %bb.0: 1207; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1208; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 1209; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, 1.0 1210; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1211; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 1212; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1 1213; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1214; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1 1215; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1216; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1217; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1218; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1219; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1220; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1221; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1222; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v3, v2, v1 1223; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, v1 1224; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1225; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v0, v1 1226; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 1227; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1228; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1229; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1230; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1231; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1232; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1233; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1234; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v0, v1 1235; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1236; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16 1237; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16 1238; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1239; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0 1240; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1241; 1242; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25: 1243; GFX6-FLUSH: ; %bb.0: 1244; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1245; GFX6-FLUSH-NEXT: s_movk_i32 s6, 0x3c00 1246; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0 1247; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s6 1248; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1249; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v1 1250; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 1251; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v2, v1 1252; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1253; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1254; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1255; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1256; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 1257; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1258; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 1259; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1260; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1261; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s6 1262; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1263; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v3, v2, v1 1264; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1265; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 1266; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v4 1267; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 1268; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v4, v0, v4 1269; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1270; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v3, 1.0 1271; GFX6-FLUSH-NEXT: v_fma_f32 v3, v6, v3, v3 1272; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v3 1273; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5 1274; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v3, v6 1275; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5 1276; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1277; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v6 1278; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v4 1279; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1280; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v1, 0, 16 1281; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16 1282; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1283; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0 1284; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1285; 1286; GFX8-LABEL: v_rcp_v2f16_ulp25: 1287; GFX8: ; %bb.0: 1288; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1289; GFX8-NEXT: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1290; GFX8-NEXT: v_rcp_f16_e32 v0, v0 1291; GFX8-NEXT: v_mov_b32_e32 v2, 16 1292; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1293; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1294; GFX8-NEXT: s_setpc_b64 s[30:31] 1295; 1296; GFX9-LABEL: v_rcp_v2f16_ulp25: 1297; GFX9: ; %bb.0: 1298; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1299; GFX9-NEXT: v_rcp_f16_e32 v1, v0 1300; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1301; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1302; GFX9-NEXT: v_and_or_b32 v0, v1, v2, v0 1303; GFX9-NEXT: s_setpc_b64 s[30:31] 1304; 1305; GFX10-LABEL: v_rcp_v2f16_ulp25: 1306; GFX10: ; %bb.0: 1307; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1308; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1309; GFX10-NEXT: v_rcp_f16_e32 v1, v0 1310; GFX10-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 1311; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v1, v0 1312; GFX10-NEXT: s_setpc_b64 s[30:31] 1313 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x, !fpmath !0 1314 ret <2 x half> %fdiv 1315} 1316 1317define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) { 1318; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25: 1319; GFX6: ; %bb.0: 1320; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1321; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1 1322; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 1323; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 1324; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1325; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 1326; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 1327; GFX6-NEXT: v_rcp_f32_e32 v1, v1 1328; GFX6-NEXT: v_rcp_f32_e32 v3, v3 1329; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 1330; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3 1331; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 1332; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 1333; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 1334; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 1335; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1336; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1337; GFX6-NEXT: s_setpc_b64 s[30:31] 1338; 1339; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25: 1340; GFX8: ; %bb.0: 1341; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1342; GFX8-NEXT: v_rcp_f16_e32 v2, v1 1343; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1344; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 1345; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1346; GFX8-NEXT: v_mov_b32_e32 v1, 16 1347; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1348; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1349; GFX8-NEXT: s_setpc_b64 s[30:31] 1350; 1351; GFX9-LABEL: v_fdiv_v2f16_afn_ulp25: 1352; GFX9: ; %bb.0: 1353; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1354; GFX9-NEXT: v_rcp_f16_e32 v2, v1 1355; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1356; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 1357; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1358; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff 1359; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 1360; GFX9-NEXT: s_setpc_b64 s[30:31] 1361; 1362; GFX10-LABEL: v_fdiv_v2f16_afn_ulp25: 1363; GFX10: ; %bb.0: 1364; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1365; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1366; GFX10-NEXT: v_rcp_f16_e32 v2, v1 1367; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1368; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 1369; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1370; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v2, v0 1371; GFX10-NEXT: s_setpc_b64 s[30:31] 1372 %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0 1373 ret <2 x half> %fdiv 1374} 1375 1376define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) { 1377; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25: 1378; GFX6-IEEE: ; %bb.0: 1379; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1380; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 1381; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 1382; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1383; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v1 1384; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0 1385; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2 1386; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4 1387; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2 1388; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1 1389; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0 1390; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5 1391; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5 1392; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6 1393; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7 1394; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6 1395; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7 1396; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2 1397; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0 1398; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3 1399; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0 1400; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 1401; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1402; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4 1403; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4 1404; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v6, v5 1405; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6 1406; GFX6-IEEE-NEXT: v_fma_f32 v3, -v3, v6, v5 1407; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1408; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0 1409; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 1410; GFX6-IEEE-NEXT: v_bfe_u32 v1, v2, 0, 16 1411; GFX6-IEEE-NEXT: v_bfe_u32 v0, v0, 0, 16 1412; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1413; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v0 1414; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31] 1415; 1416; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25: 1417; GFX6-FLUSH: ; %bb.0: 1418; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1419; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v0 1420; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1 1421; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v0 1422; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v1 1423; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v3, v3, v2 1424; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4 1425; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v2, v3, v2 1426; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1427; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0 1428; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5 1429; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5 1430; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6 1431; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7 1432; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6 1433; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1434; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0 1435; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1 1436; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7 1437; GFX6-FLUSH-NEXT: v_div_fixup_f32 v2, v4, v3, v2 1438; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 1439; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2 1440; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0 1441; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3 1442; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0 1443; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 1444; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v4, 1.0 1445; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4 1446; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4 1447; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v3, v6, v5 1448; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6 1449; GFX6-FLUSH-NEXT: v_fma_f32 v3, -v3, v6, v5 1450; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 1451; GFX6-FLUSH-NEXT: v_div_fmas_f32 v3, v3, v4, v6 1452; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v3, v1, v0 1453; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 1454; GFX6-FLUSH-NEXT: v_bfe_u32 v1, v2, 0, 16 1455; GFX6-FLUSH-NEXT: v_bfe_u32 v0, v0, 0, 16 1456; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1457; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0 1458; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31] 1459; 1460; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25: 1461; GFX8: ; %bb.0: 1462; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1463; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 1464; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v1 1465; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v4 1466; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 1467; GFX8-NEXT: v_cvt_f32_f16_e32 v3, v0 1468; GFX8-NEXT: v_rcp_f32_e32 v2, v2 1469; GFX8-NEXT: v_cvt_f32_f16_e32 v7, v6 1470; GFX8-NEXT: v_rcp_f32_e32 v5, v5 1471; GFX8-NEXT: v_mul_f32_e32 v2, v3, v2 1472; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v2 1473; GFX8-NEXT: v_mul_f32_e32 v3, v7, v5 1474; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v3 1475; GFX8-NEXT: v_div_fixup_f16 v0, v2, v1, v0 1476; GFX8-NEXT: v_mov_b32_e32 v2, 16 1477; GFX8-NEXT: v_div_fixup_f16 v1, v3, v4, v6 1478; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1479; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1480; GFX8-NEXT: s_setpc_b64 s[30:31] 1481; 1482; GFX9-LABEL: v_fdiv_v2f16_arcp_ulp25: 1483; GFX9: ; %bb.0: 1484; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1485; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1 1486; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v1 1487; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v4 1488; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v0 1489; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v0 1490; GFX9-NEXT: v_rcp_f32_e32 v2, v2 1491; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v6 1492; GFX9-NEXT: v_rcp_f32_e32 v5, v5 1493; GFX9-NEXT: v_mul_f32_e32 v2, v3, v2 1494; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2 1495; GFX9-NEXT: v_mul_f32_e32 v3, v7, v5 1496; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 1497; GFX9-NEXT: v_div_fixup_f16 v0, v2, v1, v0 1498; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff 1499; GFX9-NEXT: v_div_fixup_f16 v1, v3, v4, v6 1500; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1501; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1 1502; GFX9-NEXT: s_setpc_b64 s[30:31] 1503; 1504; GFX10-LABEL: v_fdiv_v2f16_arcp_ulp25: 1505; GFX10: ; %bb.0: 1506; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1507; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1508; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1 1509; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v1 1510; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v0 1511; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v0 1512; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 1513; GFX10-NEXT: v_rcp_f32_e32 v4, v4 1514; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v5 1515; GFX10-NEXT: v_rcp_f32_e32 v3, v3 1516; GFX10-NEXT: v_mul_f32_e32 v4, v7, v4 1517; GFX10-NEXT: v_mul_f32_e32 v3, v6, v3 1518; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4 1519; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 1520; GFX10-NEXT: v_div_fixup_f16 v0, v4, v1, v0 1521; GFX10-NEXT: v_div_fixup_f16 v2, v3, v2, v5 1522; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v2 1523; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v0, v1 1524; GFX10-NEXT: s_setpc_b64 s[30:31] 1525 %fdiv = fdiv arcp <2 x half> %a, %b, !fpmath !0 1526 ret <2 x half> %fdiv 1527} 1528 1529define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) { 1530; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1531; GFX6: ; %bb.0: 1532; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1533; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v1 1534; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1 1535; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 1536; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 1537; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 1538; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 1539; GFX6-NEXT: v_rcp_f32_e32 v1, v1 1540; GFX6-NEXT: v_rcp_f32_e32 v3, v3 1541; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 1542; GFX6-NEXT: v_mul_f32_e32 v0, v0, v3 1543; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 1544; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 1545; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 1546; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 1547; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1548; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1549; GFX6-NEXT: s_setpc_b64 s[30:31] 1550; 1551; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1552; GFX8: ; %bb.0: 1553; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1554; GFX8-NEXT: v_rcp_f16_e32 v2, v1 1555; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1556; GFX8-NEXT: v_mul_f16_e32 v2, v0, v2 1557; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1558; GFX8-NEXT: v_mov_b32_e32 v1, 16 1559; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 1560; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1561; GFX8-NEXT: s_setpc_b64 s[30:31] 1562; 1563; GFX9-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1564; GFX9: ; %bb.0: 1565; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1566; GFX9-NEXT: v_rcp_f16_e32 v2, v1 1567; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1568; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 1569; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1570; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff 1571; GFX9-NEXT: v_and_or_b32 v0, v2, v1, v0 1572; GFX9-NEXT: s_setpc_b64 s[30:31] 1573; 1574; GFX10-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: 1575; GFX10: ; %bb.0: 1576; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1577; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1578; GFX10-NEXT: v_rcp_f16_e32 v2, v1 1579; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 1580; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 1581; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1582; GFX10-NEXT: v_and_or_b32 v0, 0xffff, v2, v0 1583; GFX10-NEXT: s_setpc_b64 s[30:31] 1584 %fdiv = fdiv afn arcp <2 x half> %a, %b, !fpmath !0 1585 ret <2 x half> %fdiv 1586} 1587 1588!0 = !{float 2.500000e+00} 1589