1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MOVREL %s
4
5define float @dyn_extract_v8f32_const_s_v(i32 %sel) {
6; GCN-LABEL: dyn_extract_v8f32_const_s_v:
7; GCN:       ; %bb.0: ; %entry
8; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
10; GCN-NEXT:    v_cndmask_b32_e64 v6, 1.0, 2.0, vcc
11; GCN-NEXT:    v_mov_b32_e32 v1, 0x40400000
12; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
13; GCN-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
14; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
15; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, 4.0, vcc
16; GCN-NEXT:    v_mov_b32_e32 v2, 0x40a00000
17; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
18; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
19; GCN-NEXT:    v_mov_b32_e32 v3, 0x40c00000
20; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
21; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
22; GCN-NEXT:    v_mov_b32_e32 v4, 0x40e00000
23; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
24; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
25; GCN-NEXT:    v_mov_b32_e32 v5, 0x41000000
26; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
27; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v5, vcc
28; GCN-NEXT:    s_setpc_b64 s[30:31]
29entry:
30  %ext = extractelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, i32 %sel
31  ret float %ext
32}
33
34define amdgpu_ps float @dyn_extract_v8f32_const_s_s(i32 inreg %sel) {
35; GCN-LABEL: dyn_extract_v8f32_const_s_s:
36; GCN:       ; %bb.0: ; %entry
37; GCN-NEXT:    s_cmp_eq_u32 s2, 1
38; GCN-NEXT:    s_cselect_b32 s0, 2.0, 1.0
39; GCN-NEXT:    s_cmp_eq_u32 s2, 2
40; GCN-NEXT:    s_cselect_b32 s0, 0x40400000, s0
41; GCN-NEXT:    s_cmp_eq_u32 s2, 3
42; GCN-NEXT:    s_cselect_b32 s0, 4.0, s0
43; GCN-NEXT:    s_cmp_eq_u32 s2, 4
44; GCN-NEXT:    s_cselect_b32 s0, 0x40a00000, s0
45; GCN-NEXT:    s_cmp_eq_u32 s2, 5
46; GCN-NEXT:    s_cselect_b32 s0, 0x40c00000, s0
47; GCN-NEXT:    s_cmp_eq_u32 s2, 6
48; GCN-NEXT:    s_cselect_b32 s0, 0x40e00000, s0
49; GCN-NEXT:    s_cmp_eq_u32 s2, 7
50; GCN-NEXT:    s_cselect_b32 s0, 0x41000000, s0
51; GCN-NEXT:    v_mov_b32_e32 v0, s0
52; GCN-NEXT:    ; return to shader part epilog
53entry:
54  %ext = extractelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, i32 %sel
55  ret float %ext
56}
57
58define amdgpu_ps float @dyn_extract_v8f32_s_v(<8 x float> inreg %vec, i32 %sel) {
59; GCN-LABEL: dyn_extract_v8f32_s_v:
60; GCN:       ; %bb.0: ; %entry
61; GCN-NEXT:    s_mov_b32 s0, s2
62; GCN-NEXT:    s_mov_b32 s1, s3
63; GCN-NEXT:    s_mov_b32 s2, s4
64; GCN-NEXT:    v_mov_b32_e32 v1, s0
65; GCN-NEXT:    v_mov_b32_e32 v2, s1
66; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
67; GCN-NEXT:    s_mov_b32 s3, s5
68; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
69; GCN-NEXT:    v_mov_b32_e32 v3, s2
70; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
71; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
72; GCN-NEXT:    v_mov_b32_e32 v4, s3
73; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
74; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
75; GCN-NEXT:    v_mov_b32_e32 v5, s6
76; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
77; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
78; GCN-NEXT:    v_mov_b32_e32 v6, s7
79; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
80; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
81; GCN-NEXT:    v_mov_b32_e32 v7, s8
82; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
83; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
84; GCN-NEXT:    v_mov_b32_e32 v8, s9
85; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
86; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v8, vcc
87; GCN-NEXT:    ; return to shader part epilog
88entry:
89  %ext = extractelement <8 x float> %vec, i32 %sel
90  ret float %ext
91}
92
93define float @dyn_extract_v8f32_v_v(<8 x float> %vec, i32 %sel) {
94; GCN-LABEL: dyn_extract_v8f32_v_v:
95; GCN:       ; %bb.0: ; %entry
96; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
97; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v8
98; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
99; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v8
100; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
101; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
102; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
103; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v8
104; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
105; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v8
106; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
107; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v8
108; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
109; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v8
110; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
111; GCN-NEXT:    s_setpc_b64 s[30:31]
112entry:
113  %ext = extractelement <8 x float> %vec, i32 %sel
114  ret float %ext
115}
116
117define amdgpu_ps float @dyn_extract_v8f32_v_s(<8 x float> %vec, i32 inreg %sel) {
118; GCN-LABEL: dyn_extract_v8f32_v_s:
119; GCN:       ; %bb.0: ; %entry
120; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 1
121; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
122; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 2
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 3
125; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
126; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 4
127; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
128; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 5
129; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
130; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 6
131; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
132; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 7
133; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
134; GCN-NEXT:    ; return to shader part epilog
135entry:
136  %ext = extractelement <8 x float> %vec, i32 %sel
137  ret float %ext
138}
139
140define amdgpu_ps float @dyn_extract_v8f32_s_s(<8 x float> inreg %vec, i32 inreg %sel) {
141; GCN-LABEL: dyn_extract_v8f32_s_s:
142; GCN:       ; %bb.0: ; %entry
143; GCN-NEXT:    s_cmp_eq_u32 s10, 1
144; GCN-NEXT:    s_cselect_b32 s0, s3, s2
145; GCN-NEXT:    s_cmp_eq_u32 s10, 2
146; GCN-NEXT:    s_cselect_b32 s0, s4, s0
147; GCN-NEXT:    s_cmp_eq_u32 s10, 3
148; GCN-NEXT:    s_cselect_b32 s0, s5, s0
149; GCN-NEXT:    s_cmp_eq_u32 s10, 4
150; GCN-NEXT:    s_cselect_b32 s0, s6, s0
151; GCN-NEXT:    s_cmp_eq_u32 s10, 5
152; GCN-NEXT:    s_cselect_b32 s0, s7, s0
153; GCN-NEXT:    s_cmp_eq_u32 s10, 6
154; GCN-NEXT:    s_cselect_b32 s0, s8, s0
155; GCN-NEXT:    s_cmp_eq_u32 s10, 7
156; GCN-NEXT:    s_cselect_b32 s0, s9, s0
157; GCN-NEXT:    v_mov_b32_e32 v0, s0
158; GCN-NEXT:    ; return to shader part epilog
159entry:
160  %ext = extractelement <8 x float> %vec, i32 %sel
161  ret float %ext
162}
163
164define i64 @dyn_extract_v8i64_const_s_v(i32 %sel) {
165; GCN-LABEL: dyn_extract_v8i64_const_s_v:
166; GCN:       ; %bb.0: ; %entry
167; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
168; GCN-NEXT:    s_mov_b64 s[4:5], 1
169; GCN-NEXT:    s_mov_b64 s[6:7], 2
170; GCN-NEXT:    s_mov_b64 s[8:9], 3
171; GCN-NEXT:    v_mov_b32_e32 v1, s4
172; GCN-NEXT:    v_mov_b32_e32 v2, s5
173; GCN-NEXT:    v_mov_b32_e32 v3, s6
174; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
175; GCN-NEXT:    v_mov_b32_e32 v4, s7
176; GCN-NEXT:    s_mov_b64 s[10:11], 4
177; GCN-NEXT:    v_mov_b32_e32 v5, s8
178; GCN-NEXT:    v_mov_b32_e32 v6, s9
179; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
180; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
181; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
182; GCN-NEXT:    s_mov_b64 s[12:13], 5
183; GCN-NEXT:    v_mov_b32_e32 v7, s10
184; GCN-NEXT:    v_mov_b32_e32 v8, s11
185; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
186; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
187; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
188; GCN-NEXT:    s_mov_b64 s[14:15], 6
189; GCN-NEXT:    v_mov_b32_e32 v9, s12
190; GCN-NEXT:    v_mov_b32_e32 v10, s13
191; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
192; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
193; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
194; GCN-NEXT:    s_mov_b64 s[16:17], 7
195; GCN-NEXT:    v_mov_b32_e32 v11, s14
196; GCN-NEXT:    v_mov_b32_e32 v12, s15
197; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
198; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
199; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
200; GCN-NEXT:    s_mov_b64 s[18:19], 8
201; GCN-NEXT:    v_mov_b32_e32 v13, s16
202; GCN-NEXT:    v_mov_b32_e32 v14, s17
203; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
204; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v12, vcc
205; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
206; GCN-NEXT:    v_mov_b32_e32 v15, s18
207; GCN-NEXT:    v_mov_b32_e32 v16, s19
208; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
209; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v14, vcc
210; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
211; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v15, vcc
212; GCN-NEXT:    v_cndmask_b32_e32 v1, v2, v16, vcc
213; GCN-NEXT:    s_setpc_b64 s[30:31]
214entry:
215  %ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel
216  ret i64 %ext
217}
218
219define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
220; GPRIDX-LABEL: dyn_extract_v8i64_const_s_s:
221; GPRIDX:       ; %bb.0: ; %entry
222; GPRIDX-NEXT:    s_mov_b64 s[4:5], 1
223; GPRIDX-NEXT:    s_mov_b32 m0, s2
224; GPRIDX-NEXT:    s_mov_b64 s[18:19], 8
225; GPRIDX-NEXT:    s_mov_b64 s[16:17], 7
226; GPRIDX-NEXT:    s_mov_b64 s[14:15], 6
227; GPRIDX-NEXT:    s_mov_b64 s[12:13], 5
228; GPRIDX-NEXT:    s_mov_b64 s[10:11], 4
229; GPRIDX-NEXT:    s_mov_b64 s[8:9], 3
230; GPRIDX-NEXT:    s_mov_b64 s[6:7], 2
231; GPRIDX-NEXT:    s_movrels_b64 s[0:1], s[4:5]
232; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
233; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
234; GPRIDX-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
235; GPRIDX-NEXT:    s_endpgm
236;
237; MOVREL-LABEL: dyn_extract_v8i64_const_s_s:
238; MOVREL:       ; %bb.0: ; %entry
239; MOVREL-NEXT:    s_mov_b64 s[4:5], 1
240; MOVREL-NEXT:    s_mov_b32 m0, s2
241; MOVREL-NEXT:    s_mov_b64 s[18:19], 8
242; MOVREL-NEXT:    s_mov_b64 s[16:17], 7
243; MOVREL-NEXT:    s_mov_b64 s[14:15], 6
244; MOVREL-NEXT:    s_mov_b64 s[12:13], 5
245; MOVREL-NEXT:    s_mov_b64 s[10:11], 4
246; MOVREL-NEXT:    s_mov_b64 s[8:9], 3
247; MOVREL-NEXT:    s_mov_b64 s[6:7], 2
248; MOVREL-NEXT:    s_movrels_b64 s[0:1], s[4:5]
249; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
250; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
251; MOVREL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
252; MOVREL-NEXT:    s_endpgm
253entry:
254  %ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel
255  store i64 %ext, i64 addrspace(1)* undef
256  ret void
257}
258
259define amdgpu_ps void @dyn_extract_v8i64_s_v(<8 x i64> inreg %vec, i32 %sel) {
260; GPRIDX-LABEL: dyn_extract_v8i64_s_v:
261; GPRIDX:       ; %bb.0: ; %entry
262; GPRIDX-NEXT:    s_mov_b32 s0, s2
263; GPRIDX-NEXT:    s_mov_b32 s1, s3
264; GPRIDX-NEXT:    s_mov_b32 s2, s4
265; GPRIDX-NEXT:    s_mov_b32 s3, s5
266; GPRIDX-NEXT:    s_mov_b32 s4, s6
267; GPRIDX-NEXT:    s_mov_b32 s5, s7
268; GPRIDX-NEXT:    v_mov_b32_e32 v1, s0
269; GPRIDX-NEXT:    v_mov_b32_e32 v2, s1
270; GPRIDX-NEXT:    v_mov_b32_e32 v3, s2
271; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
272; GPRIDX-NEXT:    v_mov_b32_e32 v4, s3
273; GPRIDX-NEXT:    s_mov_b32 s6, s8
274; GPRIDX-NEXT:    s_mov_b32 s7, s9
275; GPRIDX-NEXT:    v_mov_b32_e32 v5, s4
276; GPRIDX-NEXT:    v_mov_b32_e32 v6, s5
277; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
278; GPRIDX-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
279; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
280; GPRIDX-NEXT:    s_mov_b32 s8, s10
281; GPRIDX-NEXT:    s_mov_b32 s9, s11
282; GPRIDX-NEXT:    v_mov_b32_e32 v7, s6
283; GPRIDX-NEXT:    v_mov_b32_e32 v8, s7
284; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
285; GPRIDX-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
286; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
287; GPRIDX-NEXT:    s_mov_b32 s10, s12
288; GPRIDX-NEXT:    s_mov_b32 s11, s13
289; GPRIDX-NEXT:    v_mov_b32_e32 v9, s8
290; GPRIDX-NEXT:    v_mov_b32_e32 v10, s9
291; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
292; GPRIDX-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
293; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
294; GPRIDX-NEXT:    v_mov_b32_e32 v11, s10
295; GPRIDX-NEXT:    v_mov_b32_e32 v12, s11
296; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
297; GPRIDX-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
298; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
299; GPRIDX-NEXT:    v_mov_b32_e32 v13, s14
300; GPRIDX-NEXT:    v_mov_b32_e32 v14, s15
301; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
302; GPRIDX-NEXT:    v_cndmask_b32_e32 v2, v2, v12, vcc
303; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
304; GPRIDX-NEXT:    v_mov_b32_e32 v15, s16
305; GPRIDX-NEXT:    v_mov_b32_e32 v16, s17
306; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
307; GPRIDX-NEXT:    v_cndmask_b32_e32 v2, v2, v14, vcc
308; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
309; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v1, v15, vcc
310; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v2, v16, vcc
311; GPRIDX-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
312; GPRIDX-NEXT:    s_endpgm
313;
314; MOVREL-LABEL: dyn_extract_v8i64_s_v:
315; MOVREL:       ; %bb.0: ; %entry
316; MOVREL-NEXT:    s_mov_b32 s0, s2
317; MOVREL-NEXT:    s_mov_b32 s1, s3
318; MOVREL-NEXT:    s_mov_b32 s2, s4
319; MOVREL-NEXT:    s_mov_b32 s3, s5
320; MOVREL-NEXT:    s_mov_b32 s4, s6
321; MOVREL-NEXT:    s_mov_b32 s5, s7
322; MOVREL-NEXT:    v_mov_b32_e32 v1, s0
323; MOVREL-NEXT:    v_mov_b32_e32 v2, s1
324; MOVREL-NEXT:    v_mov_b32_e32 v3, s2
325; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
326; MOVREL-NEXT:    v_mov_b32_e32 v4, s3
327; MOVREL-NEXT:    s_mov_b32 s6, s8
328; MOVREL-NEXT:    s_mov_b32 s7, s9
329; MOVREL-NEXT:    v_mov_b32_e32 v5, s4
330; MOVREL-NEXT:    v_mov_b32_e32 v6, s5
331; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
332; MOVREL-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
333; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
334; MOVREL-NEXT:    s_mov_b32 s8, s10
335; MOVREL-NEXT:    s_mov_b32 s9, s11
336; MOVREL-NEXT:    v_mov_b32_e32 v7, s6
337; MOVREL-NEXT:    v_mov_b32_e32 v8, s7
338; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
339; MOVREL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
340; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
341; MOVREL-NEXT:    s_mov_b32 s10, s12
342; MOVREL-NEXT:    s_mov_b32 s11, s13
343; MOVREL-NEXT:    v_mov_b32_e32 v9, s8
344; MOVREL-NEXT:    v_mov_b32_e32 v10, s9
345; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
346; MOVREL-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
347; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
348; MOVREL-NEXT:    v_mov_b32_e32 v11, s10
349; MOVREL-NEXT:    v_mov_b32_e32 v12, s11
350; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
351; MOVREL-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
352; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
353; MOVREL-NEXT:    v_mov_b32_e32 v13, s14
354; MOVREL-NEXT:    v_mov_b32_e32 v14, s15
355; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
356; MOVREL-NEXT:    v_cndmask_b32_e32 v2, v2, v12, vcc
357; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
358; MOVREL-NEXT:    v_mov_b32_e32 v15, s16
359; MOVREL-NEXT:    v_mov_b32_e32 v16, s17
360; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
361; MOVREL-NEXT:    v_cndmask_b32_e32 v2, v2, v14, vcc
362; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
363; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v1, v15, vcc
364; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v2, v16, vcc
365; MOVREL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
366; MOVREL-NEXT:    s_endpgm
367entry:
368  %ext = extractelement <8 x i64> %vec, i32 %sel
369  store i64 %ext, i64 addrspace(1)* undef
370  ret void
371}
372
373define i64 @dyn_extract_v8i64_v_v(<8 x i64> %vec, i32 %sel) {
374; GCN-LABEL: dyn_extract_v8i64_v_v:
375; GCN:       ; %bb.0: ; %entry
376; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
377; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v16
378; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
379; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
380; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v16
381; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
382; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
383; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v16
384; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
385; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
386; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v16
387; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
388; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
389; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v16
390; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
391; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
392; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v16
393; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
394; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
395; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v16
396; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
397; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v15, vcc
398; GCN-NEXT:    s_setpc_b64 s[30:31]
399entry:
400  %ext = extractelement <8 x i64> %vec, i32 %sel
401  ret i64 %ext
402}
403
404define amdgpu_ps void @dyn_extract_v8i64_v_s(<8 x i64> %vec, i32 inreg %sel) {
405; GPRIDX-LABEL: dyn_extract_v8i64_v_s:
406; GPRIDX:       ; %bb.0: ; %entry
407; GPRIDX-NEXT:    s_lshl_b32 s0, s2, 1
408; GPRIDX-NEXT:    s_set_gpr_idx_on s0, gpr_idx(SRC0)
409; GPRIDX-NEXT:    v_mov_b32_e32 v16, v0
410; GPRIDX-NEXT:    v_mov_b32_e32 v17, v1
411; GPRIDX-NEXT:    s_set_gpr_idx_off
412; GPRIDX-NEXT:    global_store_dwordx2 v[0:1], v[16:17], off
413; GPRIDX-NEXT:    s_endpgm
414;
415; MOVREL-LABEL: dyn_extract_v8i64_v_s:
416; MOVREL:       ; %bb.0: ; %entry
417; MOVREL-NEXT:    s_lshl_b32 m0, s2, 1
418; MOVREL-NEXT:    v_movrels_b32_e32 v16, v0
419; MOVREL-NEXT:    v_movrels_b32_e32 v17, v1
420; MOVREL-NEXT:    flat_store_dwordx2 v[0:1], v[16:17]
421; MOVREL-NEXT:    s_endpgm
422entry:
423  %ext = extractelement <8 x i64> %vec, i32 %sel
424  store i64 %ext, i64 addrspace(1)* undef
425  ret void
426}
427
428define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %sel) {
429; GPRIDX-LABEL: dyn_extract_v8i64_s_s:
430; GPRIDX:       ; %bb.0: ; %entry
431; GPRIDX-NEXT:    s_mov_b32 s0, s2
432; GPRIDX-NEXT:    s_mov_b32 s1, s3
433; GPRIDX-NEXT:    s_mov_b32 m0, s18
434; GPRIDX-NEXT:    s_mov_b32 s2, s4
435; GPRIDX-NEXT:    s_mov_b32 s3, s5
436; GPRIDX-NEXT:    s_mov_b32 s4, s6
437; GPRIDX-NEXT:    s_mov_b32 s5, s7
438; GPRIDX-NEXT:    s_mov_b32 s6, s8
439; GPRIDX-NEXT:    s_mov_b32 s7, s9
440; GPRIDX-NEXT:    s_mov_b32 s8, s10
441; GPRIDX-NEXT:    s_mov_b32 s9, s11
442; GPRIDX-NEXT:    s_mov_b32 s10, s12
443; GPRIDX-NEXT:    s_mov_b32 s11, s13
444; GPRIDX-NEXT:    s_mov_b32 s12, s14
445; GPRIDX-NEXT:    s_mov_b32 s13, s15
446; GPRIDX-NEXT:    s_mov_b32 s14, s16
447; GPRIDX-NEXT:    s_mov_b32 s15, s17
448; GPRIDX-NEXT:    s_movrels_b64 s[0:1], s[0:1]
449; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
450; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
451; GPRIDX-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
452; GPRIDX-NEXT:    s_endpgm
453;
454; MOVREL-LABEL: dyn_extract_v8i64_s_s:
455; MOVREL:       ; %bb.0: ; %entry
456; MOVREL-NEXT:    s_mov_b32 s0, s2
457; MOVREL-NEXT:    s_mov_b32 s1, s3
458; MOVREL-NEXT:    s_mov_b32 m0, s18
459; MOVREL-NEXT:    s_mov_b32 s2, s4
460; MOVREL-NEXT:    s_mov_b32 s3, s5
461; MOVREL-NEXT:    s_mov_b32 s4, s6
462; MOVREL-NEXT:    s_mov_b32 s5, s7
463; MOVREL-NEXT:    s_mov_b32 s6, s8
464; MOVREL-NEXT:    s_mov_b32 s7, s9
465; MOVREL-NEXT:    s_mov_b32 s8, s10
466; MOVREL-NEXT:    s_mov_b32 s9, s11
467; MOVREL-NEXT:    s_mov_b32 s10, s12
468; MOVREL-NEXT:    s_mov_b32 s11, s13
469; MOVREL-NEXT:    s_mov_b32 s12, s14
470; MOVREL-NEXT:    s_mov_b32 s13, s15
471; MOVREL-NEXT:    s_mov_b32 s14, s16
472; MOVREL-NEXT:    s_mov_b32 s15, s17
473; MOVREL-NEXT:    s_movrels_b64 s[0:1], s[0:1]
474; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
475; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
476; MOVREL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
477; MOVREL-NEXT:    s_endpgm
478entry:
479  %ext = extractelement <8 x i64> %vec, i32 %sel
480  store i64 %ext, i64 addrspace(1)* undef
481  ret void
482}
483
484define amdgpu_ps float @dyn_extract_v8f32_s_s_offset3(<8 x float> inreg %vec, i32 inreg %sel) {
485; GCN-LABEL: dyn_extract_v8f32_s_s_offset3:
486; GCN:       ; %bb.0: ; %entry
487; GCN-NEXT:    s_add_i32 s10, s10, 3
488; GCN-NEXT:    s_cmp_eq_u32 s10, 1
489; GCN-NEXT:    s_cselect_b32 s0, s3, s2
490; GCN-NEXT:    s_cmp_eq_u32 s10, 2
491; GCN-NEXT:    s_cselect_b32 s0, s4, s0
492; GCN-NEXT:    s_cmp_eq_u32 s10, 3
493; GCN-NEXT:    s_cselect_b32 s0, s5, s0
494; GCN-NEXT:    s_cmp_eq_u32 s10, 4
495; GCN-NEXT:    s_cselect_b32 s0, s6, s0
496; GCN-NEXT:    s_cmp_eq_u32 s10, 5
497; GCN-NEXT:    s_cselect_b32 s0, s7, s0
498; GCN-NEXT:    s_cmp_eq_u32 s10, 6
499; GCN-NEXT:    s_cselect_b32 s0, s8, s0
500; GCN-NEXT:    s_cmp_eq_u32 s10, 7
501; GCN-NEXT:    s_cselect_b32 s0, s9, s0
502; GCN-NEXT:    v_mov_b32_e32 v0, s0
503; GCN-NEXT:    ; return to shader part epilog
504entry:
505  %add = add i32 %sel, 3
506  %ext = extractelement <8 x float> %vec, i32 %add
507  ret float %ext
508}
509
510define float @dyn_extract_v8f32_v_v_offset3(<8 x float> %vec, i32 %sel) {
511; GPRIDX-LABEL: dyn_extract_v8f32_v_v_offset3:
512; GPRIDX:       ; %bb.0: ; %entry
513; GPRIDX-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
514; GPRIDX-NEXT:    v_add_u32_e32 v8, 3, v8
515; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v8
516; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
517; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v8
518; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
519; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
520; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
521; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v8
522; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
523; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v8
524; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
525; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v8
526; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
527; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v8
528; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
529; GPRIDX-NEXT:    s_setpc_b64 s[30:31]
530;
531; MOVREL-LABEL: dyn_extract_v8f32_v_v_offset3:
532; MOVREL:       ; %bb.0: ; %entry
533; MOVREL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
534; MOVREL-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
535; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v8
536; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
537; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v8
538; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
539; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
540; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
541; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v8
542; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
543; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v8
544; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
545; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v8
546; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
547; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v8
548; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
549; MOVREL-NEXT:    s_setpc_b64 s[30:31]
550entry:
551  %add = add i32 %sel, 3
552  %ext = extractelement <8 x float> %vec, i32 %add
553  ret float %ext
554}
555
556define amdgpu_ps double @dyn_extract_v8f64_s_s_offset1(<8 x double> inreg %vec, i32 inreg %sel) {
557; GCN-LABEL: dyn_extract_v8f64_s_s_offset1:
558; GCN:       ; %bb.0: ; %entry
559; GCN-NEXT:    s_mov_b32 s0, s2
560; GCN-NEXT:    s_mov_b32 s1, s3
561; GCN-NEXT:    s_mov_b32 s2, s4
562; GCN-NEXT:    s_mov_b32 s3, s5
563; GCN-NEXT:    s_mov_b32 m0, s18
564; GCN-NEXT:    s_mov_b32 s4, s6
565; GCN-NEXT:    s_mov_b32 s5, s7
566; GCN-NEXT:    s_mov_b32 s6, s8
567; GCN-NEXT:    s_mov_b32 s7, s9
568; GCN-NEXT:    s_mov_b32 s8, s10
569; GCN-NEXT:    s_mov_b32 s9, s11
570; GCN-NEXT:    s_mov_b32 s10, s12
571; GCN-NEXT:    s_mov_b32 s11, s13
572; GCN-NEXT:    s_mov_b32 s12, s14
573; GCN-NEXT:    s_mov_b32 s13, s15
574; GCN-NEXT:    s_mov_b32 s14, s16
575; GCN-NEXT:    s_mov_b32 s15, s17
576; GCN-NEXT:    s_movrels_b64 s[0:1], s[2:3]
577; GCN-NEXT:    ; return to shader part epilog
578entry:
579  %add = add i32 %sel, 1
580  %ext = extractelement <8 x double> %vec, i32 %add
581  ret double %ext
582}
583
584define amdgpu_ps double @dyn_extract_v8f64_s_s_offset2(<8 x double> inreg %vec, i32 inreg %sel) {
585; GCN-LABEL: dyn_extract_v8f64_s_s_offset2:
586; GCN:       ; %bb.0: ; %entry
587; GCN-NEXT:    s_mov_b32 s0, s2
588; GCN-NEXT:    s_mov_b32 s1, s3
589; GCN-NEXT:    s_mov_b32 s2, s4
590; GCN-NEXT:    s_mov_b32 s3, s5
591; GCN-NEXT:    s_mov_b32 s4, s6
592; GCN-NEXT:    s_mov_b32 s5, s7
593; GCN-NEXT:    s_mov_b32 m0, s18
594; GCN-NEXT:    s_mov_b32 s6, s8
595; GCN-NEXT:    s_mov_b32 s7, s9
596; GCN-NEXT:    s_mov_b32 s8, s10
597; GCN-NEXT:    s_mov_b32 s9, s11
598; GCN-NEXT:    s_mov_b32 s10, s12
599; GCN-NEXT:    s_mov_b32 s11, s13
600; GCN-NEXT:    s_mov_b32 s12, s14
601; GCN-NEXT:    s_mov_b32 s13, s15
602; GCN-NEXT:    s_mov_b32 s14, s16
603; GCN-NEXT:    s_mov_b32 s15, s17
604; GCN-NEXT:    s_movrels_b64 s[0:1], s[4:5]
605; GCN-NEXT:    ; return to shader part epilog
606entry:
607  %add = add i32 %sel, 2
608  %ext = extractelement <8 x double> %vec, i32 %add
609  ret double %ext
610}
611
612define amdgpu_ps double @dyn_extract_v8f64_s_s_offset3(<8 x double> inreg %vec, i32 inreg %sel) {
613; GCN-LABEL: dyn_extract_v8f64_s_s_offset3:
614; GCN:       ; %bb.0: ; %entry
615; GCN-NEXT:    s_mov_b32 s0, s2
616; GCN-NEXT:    s_mov_b32 s1, s3
617; GCN-NEXT:    s_mov_b32 s2, s4
618; GCN-NEXT:    s_mov_b32 s3, s5
619; GCN-NEXT:    s_mov_b32 s4, s6
620; GCN-NEXT:    s_mov_b32 s5, s7
621; GCN-NEXT:    s_mov_b32 s6, s8
622; GCN-NEXT:    s_mov_b32 s7, s9
623; GCN-NEXT:    s_mov_b32 m0, s18
624; GCN-NEXT:    s_mov_b32 s8, s10
625; GCN-NEXT:    s_mov_b32 s9, s11
626; GCN-NEXT:    s_mov_b32 s10, s12
627; GCN-NEXT:    s_mov_b32 s11, s13
628; GCN-NEXT:    s_mov_b32 s12, s14
629; GCN-NEXT:    s_mov_b32 s13, s15
630; GCN-NEXT:    s_mov_b32 s14, s16
631; GCN-NEXT:    s_mov_b32 s15, s17
632; GCN-NEXT:    s_movrels_b64 s[0:1], s[6:7]
633; GCN-NEXT:    ; return to shader part epilog
634entry:
635  %add = add i32 %sel, 3
636  %ext = extractelement <8 x double> %vec, i32 %add
637  ret double %ext
638}
639
640define amdgpu_ps double @dyn_extract_v8f64_s_s_offset4(<8 x double> inreg %vec, i32 inreg %sel) {
641; GCN-LABEL: dyn_extract_v8f64_s_s_offset4:
642; GCN:       ; %bb.0: ; %entry
643; GCN-NEXT:    s_mov_b32 s0, s2
644; GCN-NEXT:    s_mov_b32 s1, s3
645; GCN-NEXT:    s_mov_b32 s2, s4
646; GCN-NEXT:    s_mov_b32 s3, s5
647; GCN-NEXT:    s_mov_b32 s4, s6
648; GCN-NEXT:    s_mov_b32 s5, s7
649; GCN-NEXT:    s_mov_b32 s6, s8
650; GCN-NEXT:    s_mov_b32 s7, s9
651; GCN-NEXT:    s_mov_b32 s8, s10
652; GCN-NEXT:    s_mov_b32 s9, s11
653; GCN-NEXT:    s_mov_b32 m0, s18
654; GCN-NEXT:    s_mov_b32 s10, s12
655; GCN-NEXT:    s_mov_b32 s11, s13
656; GCN-NEXT:    s_mov_b32 s12, s14
657; GCN-NEXT:    s_mov_b32 s13, s15
658; GCN-NEXT:    s_mov_b32 s14, s16
659; GCN-NEXT:    s_mov_b32 s15, s17
660; GCN-NEXT:    s_movrels_b64 s[0:1], s[8:9]
661; GCN-NEXT:    ; return to shader part epilog
662entry:
663  %add = add i32 %sel, 4
664  %ext = extractelement <8 x double> %vec, i32 %add
665  ret double %ext
666}
667
668define amdgpu_ps double @dyn_extract_v8f64_s_s_offset5(<8 x double> inreg %vec, i32 inreg %sel) {
669; GCN-LABEL: dyn_extract_v8f64_s_s_offset5:
670; GCN:       ; %bb.0: ; %entry
671; GCN-NEXT:    s_mov_b32 s0, s2
672; GCN-NEXT:    s_mov_b32 s1, s3
673; GCN-NEXT:    s_mov_b32 s2, s4
674; GCN-NEXT:    s_mov_b32 s3, s5
675; GCN-NEXT:    s_mov_b32 s4, s6
676; GCN-NEXT:    s_mov_b32 s5, s7
677; GCN-NEXT:    s_mov_b32 s6, s8
678; GCN-NEXT:    s_mov_b32 s7, s9
679; GCN-NEXT:    s_mov_b32 s8, s10
680; GCN-NEXT:    s_mov_b32 s9, s11
681; GCN-NEXT:    s_mov_b32 s10, s12
682; GCN-NEXT:    s_mov_b32 s11, s13
683; GCN-NEXT:    s_mov_b32 m0, s18
684; GCN-NEXT:    s_mov_b32 s12, s14
685; GCN-NEXT:    s_mov_b32 s13, s15
686; GCN-NEXT:    s_mov_b32 s14, s16
687; GCN-NEXT:    s_mov_b32 s15, s17
688; GCN-NEXT:    s_movrels_b64 s[0:1], s[10:11]
689; GCN-NEXT:    ; return to shader part epilog
690entry:
691  %add = add i32 %sel, 5
692  %ext = extractelement <8 x double> %vec, i32 %add
693  ret double %ext
694}
695
696define amdgpu_ps double @dyn_extract_v8f64_s_s_offset6(<8 x double> inreg %vec, i32 inreg %sel) {
697; GCN-LABEL: dyn_extract_v8f64_s_s_offset6:
698; GCN:       ; %bb.0: ; %entry
699; GCN-NEXT:    s_mov_b32 s0, s2
700; GCN-NEXT:    s_mov_b32 s1, s3
701; GCN-NEXT:    s_mov_b32 s2, s4
702; GCN-NEXT:    s_mov_b32 s3, s5
703; GCN-NEXT:    s_mov_b32 s4, s6
704; GCN-NEXT:    s_mov_b32 s5, s7
705; GCN-NEXT:    s_mov_b32 s6, s8
706; GCN-NEXT:    s_mov_b32 s7, s9
707; GCN-NEXT:    s_mov_b32 s8, s10
708; GCN-NEXT:    s_mov_b32 s9, s11
709; GCN-NEXT:    s_mov_b32 s10, s12
710; GCN-NEXT:    s_mov_b32 s11, s13
711; GCN-NEXT:    s_mov_b32 s12, s14
712; GCN-NEXT:    s_mov_b32 s13, s15
713; GCN-NEXT:    s_mov_b32 m0, s18
714; GCN-NEXT:    s_mov_b32 s14, s16
715; GCN-NEXT:    s_mov_b32 s15, s17
716; GCN-NEXT:    s_movrels_b64 s[0:1], s[12:13]
717; GCN-NEXT:    ; return to shader part epilog
718entry:
719  %add = add i32 %sel, 6
720  %ext = extractelement <8 x double> %vec, i32 %add
721  ret double %ext
722}
723
724define amdgpu_ps double @dyn_extract_v8f64_s_s_offset7(<8 x double> inreg %vec, i32 inreg %sel) {
725; GPRIDX-LABEL: dyn_extract_v8f64_s_s_offset7:
726; GPRIDX:       ; %bb.0: ; %entry
727; GPRIDX-NEXT:    s_mov_b32 s0, s2
728; GPRIDX-NEXT:    s_mov_b32 s1, s3
729; GPRIDX-NEXT:    s_mov_b32 s2, s4
730; GPRIDX-NEXT:    s_mov_b32 s3, s5
731; GPRIDX-NEXT:    s_mov_b32 s4, s6
732; GPRIDX-NEXT:    s_mov_b32 s5, s7
733; GPRIDX-NEXT:    s_mov_b32 s6, s8
734; GPRIDX-NEXT:    s_mov_b32 s7, s9
735; GPRIDX-NEXT:    s_mov_b32 s8, s10
736; GPRIDX-NEXT:    s_mov_b32 s9, s11
737; GPRIDX-NEXT:    s_mov_b32 s10, s12
738; GPRIDX-NEXT:    s_mov_b32 s11, s13
739; GPRIDX-NEXT:    s_mov_b32 s12, s14
740; GPRIDX-NEXT:    s_mov_b32 s13, s15
741; GPRIDX-NEXT:    s_mov_b32 s14, s16
742; GPRIDX-NEXT:    s_mov_b32 s15, s17
743; GPRIDX-NEXT:    s_mov_b32 m0, s18
744; GPRIDX-NEXT:    s_nop 0
745; GPRIDX-NEXT:    s_movrels_b64 s[0:1], s[14:15]
746; GPRIDX-NEXT:    ; return to shader part epilog
747;
748; MOVREL-LABEL: dyn_extract_v8f64_s_s_offset7:
749; MOVREL:       ; %bb.0: ; %entry
750; MOVREL-NEXT:    s_mov_b32 s0, s2
751; MOVREL-NEXT:    s_mov_b32 s1, s3
752; MOVREL-NEXT:    s_mov_b32 s2, s4
753; MOVREL-NEXT:    s_mov_b32 s3, s5
754; MOVREL-NEXT:    s_mov_b32 s4, s6
755; MOVREL-NEXT:    s_mov_b32 s5, s7
756; MOVREL-NEXT:    s_mov_b32 s6, s8
757; MOVREL-NEXT:    s_mov_b32 s7, s9
758; MOVREL-NEXT:    s_mov_b32 s8, s10
759; MOVREL-NEXT:    s_mov_b32 s9, s11
760; MOVREL-NEXT:    s_mov_b32 s10, s12
761; MOVREL-NEXT:    s_mov_b32 s11, s13
762; MOVREL-NEXT:    s_mov_b32 s12, s14
763; MOVREL-NEXT:    s_mov_b32 s13, s15
764; MOVREL-NEXT:    s_mov_b32 s14, s16
765; MOVREL-NEXT:    s_mov_b32 s15, s17
766; MOVREL-NEXT:    s_mov_b32 m0, s18
767; MOVREL-NEXT:    s_movrels_b64 s[0:1], s[14:15]
768; MOVREL-NEXT:    ; return to shader part epilog
769entry:
770  %add = add i32 %sel, 7
771  %ext = extractelement <8 x double> %vec, i32 %add
772  ret double %ext
773}
774
775define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec, i32 inreg %sel) {
776; GCN-LABEL: dyn_extract_v8f64_s_s_offsetm1:
777; GCN:       ; %bb.0: ; %entry
778; GCN-NEXT:    s_mov_b32 s0, s2
779; GCN-NEXT:    s_mov_b32 s1, s3
780; GCN-NEXT:    s_add_i32 m0, s18, -1
781; GCN-NEXT:    s_mov_b32 s2, s4
782; GCN-NEXT:    s_mov_b32 s3, s5
783; GCN-NEXT:    s_mov_b32 s4, s6
784; GCN-NEXT:    s_mov_b32 s5, s7
785; GCN-NEXT:    s_mov_b32 s6, s8
786; GCN-NEXT:    s_mov_b32 s7, s9
787; GCN-NEXT:    s_mov_b32 s8, s10
788; GCN-NEXT:    s_mov_b32 s9, s11
789; GCN-NEXT:    s_mov_b32 s10, s12
790; GCN-NEXT:    s_mov_b32 s11, s13
791; GCN-NEXT:    s_mov_b32 s12, s14
792; GCN-NEXT:    s_mov_b32 s13, s15
793; GCN-NEXT:    s_mov_b32 s14, s16
794; GCN-NEXT:    s_mov_b32 s15, s17
795; GCN-NEXT:    s_movrels_b64 s[0:1], s[0:1]
796; GCN-NEXT:    ; return to shader part epilog
797entry:
798  %add = add i32 %sel, -1
799  %ext = extractelement <8 x double> %vec, i32 %add
800  ret double %ext
801}
802
803define double @dyn_extract_v8f64_v_v_offset3(<8 x double> %vec, i32 %sel) {
804; GPRIDX-LABEL: dyn_extract_v8f64_v_v_offset3:
805; GPRIDX:       ; %bb.0: ; %entry
806; GPRIDX-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
807; GPRIDX-NEXT:    v_add_u32_e32 v16, 3, v16
808; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v16
809; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
810; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
811; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v16
812; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
813; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
814; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v16
815; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
816; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
817; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v16
818; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
819; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
820; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v16
821; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
822; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
823; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v16
824; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
825; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
826; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v16
827; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
828; GPRIDX-NEXT:    v_cndmask_b32_e32 v1, v1, v15, vcc
829; GPRIDX-NEXT:    s_setpc_b64 s[30:31]
830;
831; MOVREL-LABEL: dyn_extract_v8f64_v_v_offset3:
832; MOVREL:       ; %bb.0: ; %entry
833; MOVREL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
834; MOVREL-NEXT:    v_add_u32_e32 v16, vcc, 3, v16
835; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v16
836; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
837; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
838; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v16
839; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
840; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
841; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v16
842; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
843; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
844; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v16
845; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
846; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
847; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v16
848; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
849; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
850; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v16
851; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
852; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
853; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v16
854; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
855; MOVREL-NEXT:    v_cndmask_b32_e32 v1, v1, v15, vcc
856; MOVREL-NEXT:    s_setpc_b64 s[30:31]
857entry:
858  %add = add i32 %sel, 3
859  %ext = extractelement <8 x double> %vec, i32 %add
860  ret double %ext
861}
862
863define i8 addrspace(3)* @dyn_extract_v8p3_v_v(<8 x i8 addrspace(3)*> %vec, i32 %idx) {
864; GCN-LABEL: dyn_extract_v8p3_v_v:
865; GCN:       ; %bb.0: ; %entry
866; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
867; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v8
868; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
869; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v8
870; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
871; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
872; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
873; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v8
874; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
875; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v8
876; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
877; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v8
878; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
879; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v8
880; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
881; GCN-NEXT:    s_setpc_b64 s[30:31]
882entry:
883  %ext = extractelement <8 x i8 addrspace(3)*> %vec, i32 %idx
884  ret i8 addrspace(3)* %ext
885}
886
887define amdgpu_ps void @dyn_extract_v8p3_s_s(<8 x i8 addrspace(3)*> inreg %vec, i32 inreg %idx) {
888; GPRIDX-LABEL: dyn_extract_v8p3_s_s:
889; GPRIDX:       ; %bb.0: ; %entry
890; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 1
891; GPRIDX-NEXT:    s_cselect_b32 s0, s3, s2
892; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 2
893; GPRIDX-NEXT:    s_cselect_b32 s0, s4, s0
894; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 3
895; GPRIDX-NEXT:    s_cselect_b32 s0, s5, s0
896; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 4
897; GPRIDX-NEXT:    s_cselect_b32 s0, s6, s0
898; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 5
899; GPRIDX-NEXT:    s_cselect_b32 s0, s7, s0
900; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 6
901; GPRIDX-NEXT:    s_cselect_b32 s0, s8, s0
902; GPRIDX-NEXT:    s_cmp_eq_u32 s10, 7
903; GPRIDX-NEXT:    s_cselect_b32 s0, s9, s0
904; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
905; GPRIDX-NEXT:    ds_write_b32 v0, v0
906; GPRIDX-NEXT:    s_endpgm
907;
908; MOVREL-LABEL: dyn_extract_v8p3_s_s:
909; MOVREL:       ; %bb.0: ; %entry
910; MOVREL-NEXT:    s_cmp_eq_u32 s10, 1
911; MOVREL-NEXT:    s_cselect_b32 s0, s3, s2
912; MOVREL-NEXT:    s_cmp_eq_u32 s10, 2
913; MOVREL-NEXT:    s_cselect_b32 s0, s4, s0
914; MOVREL-NEXT:    s_cmp_eq_u32 s10, 3
915; MOVREL-NEXT:    s_cselect_b32 s0, s5, s0
916; MOVREL-NEXT:    s_cmp_eq_u32 s10, 4
917; MOVREL-NEXT:    s_cselect_b32 s0, s6, s0
918; MOVREL-NEXT:    s_cmp_eq_u32 s10, 5
919; MOVREL-NEXT:    s_cselect_b32 s0, s7, s0
920; MOVREL-NEXT:    s_cmp_eq_u32 s10, 6
921; MOVREL-NEXT:    s_cselect_b32 s0, s8, s0
922; MOVREL-NEXT:    s_cmp_eq_u32 s10, 7
923; MOVREL-NEXT:    s_cselect_b32 s0, s9, s0
924; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
925; MOVREL-NEXT:    s_mov_b32 m0, -1
926; MOVREL-NEXT:    ds_write_b32 v0, v0
927; MOVREL-NEXT:    s_endpgm
928entry:
929  %ext = extractelement <8 x i8 addrspace(3)*> %vec, i32 %idx
930  store i8 addrspace(3)* %ext, i8 addrspace(3)* addrspace(3)* undef
931  ret void
932}
933
934define i8 addrspace(1)* @dyn_extract_v8p1_v_v(<8 x i8 addrspace(1)*> %vec, i32 %idx) {
935; GCN-LABEL: dyn_extract_v8p1_v_v:
936; GCN:       ; %bb.0: ; %entry
937; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
938; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v16
939; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
940; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
941; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v16
942; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
943; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
944; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v16
945; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
946; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
947; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v16
948; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
949; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
950; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v16
951; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
952; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
953; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v16
954; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
955; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
956; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v16
957; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
958; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v15, vcc
959; GCN-NEXT:    s_setpc_b64 s[30:31]
960entry:
961  %ext = extractelement <8 x i8 addrspace(1)*> %vec, i32 %idx
962  ret i8 addrspace(1)* %ext
963}
964
965define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x i8 addrspace(1)*> inreg %vec, i32 inreg %idx) {
966; GPRIDX-LABEL: dyn_extract_v8p1_s_s:
967; GPRIDX:       ; %bb.0: ; %entry
968; GPRIDX-NEXT:    s_mov_b32 s0, s2
969; GPRIDX-NEXT:    s_mov_b32 s1, s3
970; GPRIDX-NEXT:    s_mov_b32 m0, s18
971; GPRIDX-NEXT:    s_mov_b32 s2, s4
972; GPRIDX-NEXT:    s_mov_b32 s3, s5
973; GPRIDX-NEXT:    s_mov_b32 s4, s6
974; GPRIDX-NEXT:    s_mov_b32 s5, s7
975; GPRIDX-NEXT:    s_mov_b32 s6, s8
976; GPRIDX-NEXT:    s_mov_b32 s7, s9
977; GPRIDX-NEXT:    s_mov_b32 s8, s10
978; GPRIDX-NEXT:    s_mov_b32 s9, s11
979; GPRIDX-NEXT:    s_mov_b32 s10, s12
980; GPRIDX-NEXT:    s_mov_b32 s11, s13
981; GPRIDX-NEXT:    s_mov_b32 s12, s14
982; GPRIDX-NEXT:    s_mov_b32 s13, s15
983; GPRIDX-NEXT:    s_mov_b32 s14, s16
984; GPRIDX-NEXT:    s_mov_b32 s15, s17
985; GPRIDX-NEXT:    s_movrels_b64 s[0:1], s[0:1]
986; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
987; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
988; GPRIDX-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
989; GPRIDX-NEXT:    s_endpgm
990;
991; MOVREL-LABEL: dyn_extract_v8p1_s_s:
992; MOVREL:       ; %bb.0: ; %entry
993; MOVREL-NEXT:    s_mov_b32 s0, s2
994; MOVREL-NEXT:    s_mov_b32 s1, s3
995; MOVREL-NEXT:    s_mov_b32 m0, s18
996; MOVREL-NEXT:    s_mov_b32 s2, s4
997; MOVREL-NEXT:    s_mov_b32 s3, s5
998; MOVREL-NEXT:    s_mov_b32 s4, s6
999; MOVREL-NEXT:    s_mov_b32 s5, s7
1000; MOVREL-NEXT:    s_mov_b32 s6, s8
1001; MOVREL-NEXT:    s_mov_b32 s7, s9
1002; MOVREL-NEXT:    s_mov_b32 s8, s10
1003; MOVREL-NEXT:    s_mov_b32 s9, s11
1004; MOVREL-NEXT:    s_mov_b32 s10, s12
1005; MOVREL-NEXT:    s_mov_b32 s11, s13
1006; MOVREL-NEXT:    s_mov_b32 s12, s14
1007; MOVREL-NEXT:    s_mov_b32 s13, s15
1008; MOVREL-NEXT:    s_mov_b32 s14, s16
1009; MOVREL-NEXT:    s_mov_b32 s15, s17
1010; MOVREL-NEXT:    s_movrels_b64 s[0:1], s[0:1]
1011; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
1012; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
1013; MOVREL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
1014; MOVREL-NEXT:    s_endpgm
1015entry:
1016  %ext = extractelement <8 x i8 addrspace(1)*> %vec, i32 %idx
1017  store i8 addrspace(1)* %ext, i8 addrspace(1)* addrspace(1)* undef
1018  ret void
1019}
1020
1021define amdgpu_ps float @dyn_extract_v16f32_v_s(<16 x float> %vec, i32 inreg %sel) {
1022; GPRIDX-LABEL: dyn_extract_v16f32_v_s:
1023; GPRIDX:       ; %bb.0: ; %entry
1024; GPRIDX-NEXT:    s_set_gpr_idx_on s2, gpr_idx(SRC0)
1025; GPRIDX-NEXT:    v_mov_b32_e32 v0, v0
1026; GPRIDX-NEXT:    s_set_gpr_idx_off
1027; GPRIDX-NEXT:    ; return to shader part epilog
1028;
1029; MOVREL-LABEL: dyn_extract_v16f32_v_s:
1030; MOVREL:       ; %bb.0: ; %entry
1031; MOVREL-NEXT:    s_mov_b32 m0, s2
1032; MOVREL-NEXT:    v_movrels_b32_e32 v0, v0
1033; MOVREL-NEXT:    ; return to shader part epilog
1034entry:
1035  %ext = extractelement <16 x float> %vec, i32 %sel
1036  ret float %ext
1037}
1038
1039define amdgpu_ps float @dyn_extract_v32f32_v_s(<32 x float> %vec, i32 inreg %sel) {
1040; GPRIDX-LABEL: dyn_extract_v32f32_v_s:
1041; GPRIDX:       ; %bb.0: ; %entry
1042; GPRIDX-NEXT:    s_set_gpr_idx_on s2, gpr_idx(SRC0)
1043; GPRIDX-NEXT:    v_mov_b32_e32 v0, v0
1044; GPRIDX-NEXT:    s_set_gpr_idx_off
1045; GPRIDX-NEXT:    ; return to shader part epilog
1046;
1047; MOVREL-LABEL: dyn_extract_v32f32_v_s:
1048; MOVREL:       ; %bb.0: ; %entry
1049; MOVREL-NEXT:    s_mov_b32 m0, s2
1050; MOVREL-NEXT:    v_movrels_b32_e32 v0, v0
1051; MOVREL-NEXT:    ; return to shader part epilog
1052entry:
1053  %ext = extractelement <32 x float> %vec, i32 %sel
1054  ret float %ext
1055}
1056
1057define amdgpu_ps double @dyn_extract_v16f64_v_s(<16 x double> %vec, i32 inreg %sel) {
1058; GPRIDX-LABEL: dyn_extract_v16f64_v_s:
1059; GPRIDX:       ; %bb.0: ; %entry
1060; GPRIDX-NEXT:    s_lshl_b32 s0, s2, 1
1061; GPRIDX-NEXT:    s_set_gpr_idx_on s0, gpr_idx(SRC0)
1062; GPRIDX-NEXT:    v_mov_b32_e32 v32, v0
1063; GPRIDX-NEXT:    v_mov_b32_e32 v0, v1
1064; GPRIDX-NEXT:    s_set_gpr_idx_off
1065; GPRIDX-NEXT:    v_readfirstlane_b32 s0, v32
1066; GPRIDX-NEXT:    v_readfirstlane_b32 s1, v0
1067; GPRIDX-NEXT:    ; return to shader part epilog
1068;
1069; MOVREL-LABEL: dyn_extract_v16f64_v_s:
1070; MOVREL:       ; %bb.0: ; %entry
1071; MOVREL-NEXT:    s_lshl_b32 m0, s2, 1
1072; MOVREL-NEXT:    v_movrels_b32_e32 v32, v0
1073; MOVREL-NEXT:    v_movrels_b32_e32 v0, v1
1074; MOVREL-NEXT:    v_readfirstlane_b32 s0, v32
1075; MOVREL-NEXT:    v_readfirstlane_b32 s1, v0
1076; MOVREL-NEXT:    ; return to shader part epilog
1077entry:
1078  %ext = extractelement <16 x double> %vec, i32 %sel
1079  ret double %ext
1080}
1081
1082define amdgpu_ps float @dyn_extract_v16f32_s_s(i32 inreg %sel) {
1083; GCN-LABEL: dyn_extract_v16f32_s_s:
1084; GCN:       ; %bb.0: ; %entry
1085; GCN-NEXT:    s_mov_b32 s4, 1.0
1086; GCN-NEXT:    s_mov_b32 m0, s2
1087; GCN-NEXT:    s_mov_b32 s19, 0x41800000
1088; GCN-NEXT:    s_mov_b32 s18, 0x41700000
1089; GCN-NEXT:    s_mov_b32 s17, 0x41600000
1090; GCN-NEXT:    s_mov_b32 s16, 0x41500000
1091; GCN-NEXT:    s_mov_b32 s15, 0x41400000
1092; GCN-NEXT:    s_mov_b32 s14, 0x41300000
1093; GCN-NEXT:    s_mov_b32 s13, 0x41200000
1094; GCN-NEXT:    s_mov_b32 s12, 0x41100000
1095; GCN-NEXT:    s_mov_b32 s11, 0x41000000
1096; GCN-NEXT:    s_mov_b32 s10, 0x40e00000
1097; GCN-NEXT:    s_mov_b32 s9, 0x40c00000
1098; GCN-NEXT:    s_mov_b32 s8, 0x40a00000
1099; GCN-NEXT:    s_mov_b32 s7, 4.0
1100; GCN-NEXT:    s_mov_b32 s6, 0x40400000
1101; GCN-NEXT:    s_mov_b32 s5, 2.0
1102; GCN-NEXT:    s_movrels_b32 s0, s4
1103; GCN-NEXT:    v_mov_b32_e32 v0, s0
1104; GCN-NEXT:    ; return to shader part epilog
1105entry:
1106  %ext = extractelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, i32 %sel
1107  ret float %ext
1108}
1109
1110define amdgpu_ps float @dyn_extract_v32f32_s_s(i32 inreg %sel) {
1111; GCN-LABEL: dyn_extract_v32f32_s_s:
1112; GCN:       ; %bb.0: ; %entry
1113; GCN-NEXT:    s_mov_b32 s36, 1.0
1114; GCN-NEXT:    s_mov_b32 m0, s2
1115; GCN-NEXT:    s_mov_b32 s67, 0x42000000
1116; GCN-NEXT:    s_mov_b32 s66, 0x41f80000
1117; GCN-NEXT:    s_mov_b32 s65, 0x41f00000
1118; GCN-NEXT:    s_mov_b32 s64, 0x41e80000
1119; GCN-NEXT:    s_mov_b32 s63, 0x41e00000
1120; GCN-NEXT:    s_mov_b32 s62, 0x41d80000
1121; GCN-NEXT:    s_mov_b32 s61, 0x41d00000
1122; GCN-NEXT:    s_mov_b32 s60, 0x41c80000
1123; GCN-NEXT:    s_mov_b32 s59, 0x41c00000
1124; GCN-NEXT:    s_mov_b32 s58, 0x41b80000
1125; GCN-NEXT:    s_mov_b32 s57, 0x41b00000
1126; GCN-NEXT:    s_mov_b32 s56, 0x41a80000
1127; GCN-NEXT:    s_mov_b32 s55, 0x41a00000
1128; GCN-NEXT:    s_mov_b32 s54, 0x41980000
1129; GCN-NEXT:    s_mov_b32 s53, 0x41900000
1130; GCN-NEXT:    s_mov_b32 s52, 0x41880000
1131; GCN-NEXT:    s_mov_b32 s51, 0x41800000
1132; GCN-NEXT:    s_mov_b32 s50, 0x41700000
1133; GCN-NEXT:    s_mov_b32 s49, 0x41600000
1134; GCN-NEXT:    s_mov_b32 s48, 0x41500000
1135; GCN-NEXT:    s_mov_b32 s47, 0x41400000
1136; GCN-NEXT:    s_mov_b32 s46, 0x41300000
1137; GCN-NEXT:    s_mov_b32 s45, 0x41200000
1138; GCN-NEXT:    s_mov_b32 s44, 0x41100000
1139; GCN-NEXT:    s_mov_b32 s43, 0x41000000
1140; GCN-NEXT:    s_mov_b32 s42, 0x40e00000
1141; GCN-NEXT:    s_mov_b32 s41, 0x40c00000
1142; GCN-NEXT:    s_mov_b32 s40, 0x40a00000
1143; GCN-NEXT:    s_mov_b32 s39, 4.0
1144; GCN-NEXT:    s_mov_b32 s38, 0x40400000
1145; GCN-NEXT:    s_mov_b32 s37, 2.0
1146; GCN-NEXT:    s_movrels_b32 s0, s36
1147; GCN-NEXT:    v_mov_b32_e32 v0, s0
1148; GCN-NEXT:    ; return to shader part epilog
1149entry:
1150  %ext = extractelement <32 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0, float 17.0, float 18.0, float 19.0, float 20.0, float 21.0, float 22.0, float 23.0, float 24.0, float 25.0, float 26.0, float 27.0, float 28.0, float 29.0, float 30.0, float 31.0, float 32.0>, i32 %sel
1151  ret float %ext
1152}
1153
1154define amdgpu_ps double @dyn_extract_v16f64_s_s(i32 inreg %sel) {
1155; GCN-LABEL: dyn_extract_v16f64_s_s:
1156; GCN:       ; %bb.0: ; %entry
1157; GCN-NEXT:    s_mov_b32 s66, 0
1158; GCN-NEXT:    s_mov_b64 s[36:37], 1.0
1159; GCN-NEXT:    s_mov_b32 m0, s2
1160; GCN-NEXT:    s_mov_b32 s67, 0x40300000
1161; GCN-NEXT:    s_mov_b32 s65, 0x402e0000
1162; GCN-NEXT:    s_mov_b32 s64, s66
1163; GCN-NEXT:    s_mov_b32 s63, 0x402c0000
1164; GCN-NEXT:    s_mov_b32 s62, s66
1165; GCN-NEXT:    s_mov_b32 s61, 0x402a0000
1166; GCN-NEXT:    s_mov_b32 s60, s66
1167; GCN-NEXT:    s_mov_b32 s59, 0x40280000
1168; GCN-NEXT:    s_mov_b32 s58, s66
1169; GCN-NEXT:    s_mov_b32 s57, 0x40260000
1170; GCN-NEXT:    s_mov_b32 s56, s66
1171; GCN-NEXT:    s_mov_b32 s55, 0x40240000
1172; GCN-NEXT:    s_mov_b32 s54, s66
1173; GCN-NEXT:    s_mov_b32 s53, 0x40220000
1174; GCN-NEXT:    s_mov_b32 s52, s66
1175; GCN-NEXT:    s_mov_b32 s51, 0x40200000
1176; GCN-NEXT:    s_mov_b32 s50, s66
1177; GCN-NEXT:    s_mov_b32 s49, 0x401c0000
1178; GCN-NEXT:    s_mov_b32 s48, s66
1179; GCN-NEXT:    s_mov_b32 s47, 0x40180000
1180; GCN-NEXT:    s_mov_b32 s46, s66
1181; GCN-NEXT:    s_mov_b32 s45, 0x40140000
1182; GCN-NEXT:    s_mov_b32 s44, s66
1183; GCN-NEXT:    s_mov_b64 s[42:43], 4.0
1184; GCN-NEXT:    s_mov_b32 s41, 0x40080000
1185; GCN-NEXT:    s_mov_b32 s40, s66
1186; GCN-NEXT:    s_mov_b64 s[38:39], 2.0
1187; GCN-NEXT:    s_movrels_b64 s[0:1], s[36:37]
1188; GCN-NEXT:    ; return to shader part epilog
1189entry:
1190  %ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel
1191  ret double %ext
1192}
1193
1194define amdgpu_ps float @dyn_extract_v6f32_s_v(<6 x float> inreg %vec, i32 %sel) {
1195; GCN-LABEL: dyn_extract_v6f32_s_v:
1196; GCN:       ; %bb.0: ; %entry
1197; GCN-NEXT:    s_mov_b32 s0, s2
1198; GCN-NEXT:    s_mov_b32 s1, s3
1199; GCN-NEXT:    v_mov_b32_e32 v1, s0
1200; GCN-NEXT:    v_mov_b32_e32 v2, s1
1201; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
1202; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1203; GCN-NEXT:    v_mov_b32_e32 v3, s4
1204; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
1205; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1206; GCN-NEXT:    v_mov_b32_e32 v4, s5
1207; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
1208; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1209; GCN-NEXT:    v_mov_b32_e32 v5, s6
1210; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
1211; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1212; GCN-NEXT:    v_mov_b32_e32 v6, s7
1213; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
1214; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v6, vcc
1215; GCN-NEXT:    ; return to shader part epilog
1216entry:
1217  %ext = extractelement <6 x float> %vec, i32 %sel
1218  ret float %ext
1219}
1220
1221define float @dyn_extract_v6f32_v_v(<6 x float> %vec, i32 %sel) {
1222; GCN-LABEL: dyn_extract_v6f32_v_v:
1223; GCN:       ; %bb.0: ; %entry
1224; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1225; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v6
1226; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1227; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v6
1228; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1229; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
1230; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1231; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v6
1232; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1233; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v6
1234; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
1235; GCN-NEXT:    s_setpc_b64 s[30:31]
1236entry:
1237  %ext = extractelement <6 x float> %vec, i32 %sel
1238  ret float %ext
1239}
1240
1241define amdgpu_ps float @dyn_extract_v6f32_v_s(<6 x float> %vec, i32 inreg %sel) {
1242; GCN-LABEL: dyn_extract_v6f32_v_s:
1243; GCN:       ; %bb.0: ; %entry
1244; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 1
1245; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1246; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 2
1247; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1248; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 3
1249; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1250; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 4
1251; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1252; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 5
1253; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
1254; GCN-NEXT:    ; return to shader part epilog
1255entry:
1256  %ext = extractelement <6 x float> %vec, i32 %sel
1257  ret float %ext
1258}
1259
1260define amdgpu_ps float @dyn_extract_v6f32_s_s(<6 x float> inreg %vec, i32 inreg %sel) {
1261; GCN-LABEL: dyn_extract_v6f32_s_s:
1262; GCN:       ; %bb.0: ; %entry
1263; GCN-NEXT:    s_cmp_eq_u32 s8, 1
1264; GCN-NEXT:    s_cselect_b32 s0, s3, s2
1265; GCN-NEXT:    s_cmp_eq_u32 s8, 2
1266; GCN-NEXT:    s_cselect_b32 s0, s4, s0
1267; GCN-NEXT:    s_cmp_eq_u32 s8, 3
1268; GCN-NEXT:    s_cselect_b32 s0, s5, s0
1269; GCN-NEXT:    s_cmp_eq_u32 s8, 4
1270; GCN-NEXT:    s_cselect_b32 s0, s6, s0
1271; GCN-NEXT:    s_cmp_eq_u32 s8, 5
1272; GCN-NEXT:    s_cselect_b32 s0, s7, s0
1273; GCN-NEXT:    v_mov_b32_e32 v0, s0
1274; GCN-NEXT:    ; return to shader part epilog
1275entry:
1276  %ext = extractelement <6 x float> %vec, i32 %sel
1277  ret float %ext
1278}
1279
1280define amdgpu_ps float @dyn_extract_v7f32_s_v(<7 x float> inreg %vec, i32 %sel) {
1281; GCN-LABEL: dyn_extract_v7f32_s_v:
1282; GCN:       ; %bb.0: ; %entry
1283; GCN-NEXT:    s_mov_b32 s0, s2
1284; GCN-NEXT:    s_mov_b32 s1, s3
1285; GCN-NEXT:    s_mov_b32 s2, s4
1286; GCN-NEXT:    v_mov_b32_e32 v1, s0
1287; GCN-NEXT:    v_mov_b32_e32 v2, s1
1288; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
1289; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1290; GCN-NEXT:    v_mov_b32_e32 v3, s2
1291; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
1292; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1293; GCN-NEXT:    v_mov_b32_e32 v4, s5
1294; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
1295; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1296; GCN-NEXT:    v_mov_b32_e32 v5, s6
1297; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
1298; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1299; GCN-NEXT:    v_mov_b32_e32 v6, s7
1300; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
1301; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1302; GCN-NEXT:    v_mov_b32_e32 v7, s8
1303; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
1304; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v7, vcc
1305; GCN-NEXT:    ; return to shader part epilog
1306entry:
1307  %ext = extractelement <7 x float> %vec, i32 %sel
1308  ret float %ext
1309}
1310
1311define float @dyn_extract_v7f32_v_v(<7 x float> %vec, i32 %sel) {
1312; GCN-LABEL: dyn_extract_v7f32_v_v:
1313; GCN:       ; %bb.0: ; %entry
1314; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1315; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v7
1316; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1317; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v7
1318; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1319; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v7
1320; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1321; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v7
1322; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1323; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v7
1324; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
1325; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v7
1326; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1327; GCN-NEXT:    s_setpc_b64 s[30:31]
1328entry:
1329  %ext = extractelement <7 x float> %vec, i32 %sel
1330  ret float %ext
1331}
1332
1333define amdgpu_ps float @dyn_extract_v7f32_v_s(<7 x float> %vec, i32 inreg %sel) {
1334; GCN-LABEL: dyn_extract_v7f32_v_s:
1335; GCN:       ; %bb.0: ; %entry
1336; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 1
1337; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1338; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 2
1339; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1340; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 3
1341; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1342; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 4
1343; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1344; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 5
1345; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
1346; GCN-NEXT:    v_cmp_eq_u32_e64 vcc, s2, 6
1347; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1348; GCN-NEXT:    ; return to shader part epilog
1349entry:
1350  %ext = extractelement <7 x float> %vec, i32 %sel
1351  ret float %ext
1352}
1353
1354define amdgpu_ps float @dyn_extract_v7f32_s_s(<7 x float> inreg %vec, i32 inreg %sel) {
1355; GCN-LABEL: dyn_extract_v7f32_s_s:
1356; GCN:       ; %bb.0: ; %entry
1357; GCN-NEXT:    s_cmp_eq_u32 s9, 1
1358; GCN-NEXT:    s_cselect_b32 s0, s3, s2
1359; GCN-NEXT:    s_cmp_eq_u32 s9, 2
1360; GCN-NEXT:    s_cselect_b32 s0, s4, s0
1361; GCN-NEXT:    s_cmp_eq_u32 s9, 3
1362; GCN-NEXT:    s_cselect_b32 s0, s5, s0
1363; GCN-NEXT:    s_cmp_eq_u32 s9, 4
1364; GCN-NEXT:    s_cselect_b32 s0, s6, s0
1365; GCN-NEXT:    s_cmp_eq_u32 s9, 5
1366; GCN-NEXT:    s_cselect_b32 s0, s7, s0
1367; GCN-NEXT:    s_cmp_eq_u32 s9, 6
1368; GCN-NEXT:    s_cselect_b32 s0, s8, s0
1369; GCN-NEXT:    v_mov_b32_e32 v0, s0
1370; GCN-NEXT:    ; return to shader part epilog
1371entry:
1372  %ext = extractelement <7 x float> %vec, i32 %sel
1373  ret float %ext
1374}
1375
1376define amdgpu_ps double @dyn_extract_v6f64_s_v(<6 x double> inreg %vec, i32 %sel) {
1377; GCN-LABEL: dyn_extract_v6f64_s_v:
1378; GCN:       ; %bb.0: ; %entry
1379; GCN-NEXT:    s_mov_b32 s0, s2
1380; GCN-NEXT:    s_mov_b32 s1, s3
1381; GCN-NEXT:    s_mov_b32 s2, s4
1382; GCN-NEXT:    s_mov_b32 s3, s5
1383; GCN-NEXT:    s_mov_b32 s4, s6
1384; GCN-NEXT:    s_mov_b32 s5, s7
1385; GCN-NEXT:    v_mov_b32_e32 v1, s0
1386; GCN-NEXT:    v_mov_b32_e32 v2, s1
1387; GCN-NEXT:    v_mov_b32_e32 v3, s2
1388; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
1389; GCN-NEXT:    v_mov_b32_e32 v4, s3
1390; GCN-NEXT:    s_mov_b32 s6, s8
1391; GCN-NEXT:    s_mov_b32 s7, s9
1392; GCN-NEXT:    v_mov_b32_e32 v5, s4
1393; GCN-NEXT:    v_mov_b32_e32 v6, s5
1394; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1395; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1396; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
1397; GCN-NEXT:    v_mov_b32_e32 v7, s6
1398; GCN-NEXT:    v_mov_b32_e32 v8, s7
1399; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1400; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1401; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
1402; GCN-NEXT:    v_mov_b32_e32 v9, s10
1403; GCN-NEXT:    v_mov_b32_e32 v10, s11
1404; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1405; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
1406; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
1407; GCN-NEXT:    v_mov_b32_e32 v11, s12
1408; GCN-NEXT:    v_mov_b32_e32 v12, s13
1409; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
1410; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
1411; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
1412; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v11, vcc
1413; GCN-NEXT:    v_cndmask_b32_e32 v1, v2, v12, vcc
1414; GCN-NEXT:    v_readfirstlane_b32 s0, v0
1415; GCN-NEXT:    v_readfirstlane_b32 s1, v1
1416; GCN-NEXT:    ; return to shader part epilog
1417entry:
1418  %ext = extractelement <6 x double> %vec, i32 %sel
1419  ret double %ext
1420}
1421
1422define double @dyn_extract_v6f64_v_v(<6 x double> %vec, i32 %sel) {
1423; GCN-LABEL: dyn_extract_v6f64_v_v:
1424; GCN:       ; %bb.0: ; %entry
1425; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1426; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v12
1427; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1428; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1429; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v12
1430; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1431; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1432; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v12
1433; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1434; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1435; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v12
1436; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
1437; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
1438; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v12
1439; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
1440; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
1441; GCN-NEXT:    s_setpc_b64 s[30:31]
1442entry:
1443  %ext = extractelement <6 x double> %vec, i32 %sel
1444  ret double %ext
1445}
1446
1447define amdgpu_ps double @dyn_extract_v6f64_v_s(<6 x double> %vec, i32 inreg %sel) {
1448; GPRIDX-LABEL: dyn_extract_v6f64_v_s:
1449; GPRIDX:       ; %bb.0: ; %entry
1450; GPRIDX-NEXT:    s_lshl_b32 s0, s2, 1
1451; GPRIDX-NEXT:    s_set_gpr_idx_on s0, gpr_idx(SRC0)
1452; GPRIDX-NEXT:    v_mov_b32_e32 v12, v0
1453; GPRIDX-NEXT:    v_mov_b32_e32 v0, v1
1454; GPRIDX-NEXT:    s_set_gpr_idx_off
1455; GPRIDX-NEXT:    v_readfirstlane_b32 s0, v12
1456; GPRIDX-NEXT:    v_readfirstlane_b32 s1, v0
1457; GPRIDX-NEXT:    ; return to shader part epilog
1458;
1459; MOVREL-LABEL: dyn_extract_v6f64_v_s:
1460; MOVREL:       ; %bb.0: ; %entry
1461; MOVREL-NEXT:    s_lshl_b32 m0, s2, 1
1462; MOVREL-NEXT:    v_movrels_b32_e32 v12, v0
1463; MOVREL-NEXT:    v_movrels_b32_e32 v0, v1
1464; MOVREL-NEXT:    v_readfirstlane_b32 s0, v12
1465; MOVREL-NEXT:    v_readfirstlane_b32 s1, v0
1466; MOVREL-NEXT:    ; return to shader part epilog
1467entry:
1468  %ext = extractelement <6 x double> %vec, i32 %sel
1469  ret double %ext
1470}
1471
1472define amdgpu_ps double @dyn_extract_v6f64_s_s(<6 x double> inreg %vec, i32 inreg %sel) {
1473; GCN-LABEL: dyn_extract_v6f64_s_s:
1474; GCN:       ; %bb.0: ; %entry
1475; GCN-NEXT:    s_mov_b32 s0, s2
1476; GCN-NEXT:    s_mov_b32 s1, s3
1477; GCN-NEXT:    s_mov_b32 m0, s14
1478; GCN-NEXT:    s_mov_b32 s2, s4
1479; GCN-NEXT:    s_mov_b32 s3, s5
1480; GCN-NEXT:    s_mov_b32 s4, s6
1481; GCN-NEXT:    s_mov_b32 s5, s7
1482; GCN-NEXT:    s_mov_b32 s6, s8
1483; GCN-NEXT:    s_mov_b32 s7, s9
1484; GCN-NEXT:    s_mov_b32 s8, s10
1485; GCN-NEXT:    s_mov_b32 s9, s11
1486; GCN-NEXT:    s_mov_b32 s10, s12
1487; GCN-NEXT:    s_mov_b32 s11, s13
1488; GCN-NEXT:    s_movrels_b64 s[0:1], s[0:1]
1489; GCN-NEXT:    ; return to shader part epilog
1490entry:
1491  %ext = extractelement <6 x double> %vec, i32 %sel
1492  ret double %ext
1493}
1494
1495define amdgpu_ps double @dyn_extract_v7f64_s_v(<7 x double> inreg %vec, i32 %sel) {
1496; GCN-LABEL: dyn_extract_v7f64_s_v:
1497; GCN:       ; %bb.0: ; %entry
1498; GCN-NEXT:    s_mov_b32 s0, s2
1499; GCN-NEXT:    s_mov_b32 s1, s3
1500; GCN-NEXT:    s_mov_b32 s2, s4
1501; GCN-NEXT:    s_mov_b32 s3, s5
1502; GCN-NEXT:    s_mov_b32 s4, s6
1503; GCN-NEXT:    s_mov_b32 s5, s7
1504; GCN-NEXT:    v_mov_b32_e32 v1, s0
1505; GCN-NEXT:    v_mov_b32_e32 v2, s1
1506; GCN-NEXT:    v_mov_b32_e32 v3, s2
1507; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
1508; GCN-NEXT:    v_mov_b32_e32 v4, s3
1509; GCN-NEXT:    s_mov_b32 s6, s8
1510; GCN-NEXT:    s_mov_b32 s7, s9
1511; GCN-NEXT:    v_mov_b32_e32 v5, s4
1512; GCN-NEXT:    v_mov_b32_e32 v6, s5
1513; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1514; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1515; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
1516; GCN-NEXT:    s_mov_b32 s8, s10
1517; GCN-NEXT:    s_mov_b32 s9, s11
1518; GCN-NEXT:    v_mov_b32_e32 v7, s6
1519; GCN-NEXT:    v_mov_b32_e32 v8, s7
1520; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1521; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
1522; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
1523; GCN-NEXT:    v_mov_b32_e32 v9, s8
1524; GCN-NEXT:    v_mov_b32_e32 v10, s9
1525; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1526; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
1527; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
1528; GCN-NEXT:    v_mov_b32_e32 v11, s12
1529; GCN-NEXT:    v_mov_b32_e32 v12, s13
1530; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
1531; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
1532; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
1533; GCN-NEXT:    v_mov_b32_e32 v13, s14
1534; GCN-NEXT:    v_mov_b32_e32 v14, s15
1535; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
1536; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v12, vcc
1537; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
1538; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v13, vcc
1539; GCN-NEXT:    v_cndmask_b32_e32 v1, v2, v14, vcc
1540; GCN-NEXT:    v_readfirstlane_b32 s0, v0
1541; GCN-NEXT:    v_readfirstlane_b32 s1, v1
1542; GCN-NEXT:    ; return to shader part epilog
1543entry:
1544  %ext = extractelement <7 x double> %vec, i32 %sel
1545  ret double %ext
1546}
1547
1548define double @dyn_extract_v7f64_v_v(<7 x double> %vec, i32 %sel) {
1549; GCN-LABEL: dyn_extract_v7f64_v_v:
1550; GCN:       ; %bb.0: ; %entry
1551; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1552; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v14
1553; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1554; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1555; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v14
1556; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1557; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1558; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v14
1559; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1560; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1561; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v14
1562; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
1563; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
1564; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v14
1565; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
1566; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
1567; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v14
1568; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
1569; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
1570; GCN-NEXT:    s_setpc_b64 s[30:31]
1571entry:
1572  %ext = extractelement <7 x double> %vec, i32 %sel
1573  ret double %ext
1574}
1575
1576define amdgpu_ps double @dyn_extract_v7f64_v_s(<7 x double> %vec, i32 inreg %sel) {
1577; GPRIDX-LABEL: dyn_extract_v7f64_v_s:
1578; GPRIDX:       ; %bb.0: ; %entry
1579; GPRIDX-NEXT:    s_lshl_b32 s0, s2, 1
1580; GPRIDX-NEXT:    s_set_gpr_idx_on s0, gpr_idx(SRC0)
1581; GPRIDX-NEXT:    v_mov_b32_e32 v14, v0
1582; GPRIDX-NEXT:    v_mov_b32_e32 v0, v1
1583; GPRIDX-NEXT:    s_set_gpr_idx_off
1584; GPRIDX-NEXT:    v_readfirstlane_b32 s0, v14
1585; GPRIDX-NEXT:    v_readfirstlane_b32 s1, v0
1586; GPRIDX-NEXT:    ; return to shader part epilog
1587;
1588; MOVREL-LABEL: dyn_extract_v7f64_v_s:
1589; MOVREL:       ; %bb.0: ; %entry
1590; MOVREL-NEXT:    s_lshl_b32 m0, s2, 1
1591; MOVREL-NEXT:    v_movrels_b32_e32 v14, v0
1592; MOVREL-NEXT:    v_movrels_b32_e32 v0, v1
1593; MOVREL-NEXT:    v_readfirstlane_b32 s0, v14
1594; MOVREL-NEXT:    v_readfirstlane_b32 s1, v0
1595; MOVREL-NEXT:    ; return to shader part epilog
1596entry:
1597  %ext = extractelement <7 x double> %vec, i32 %sel
1598  ret double %ext
1599}
1600
1601define amdgpu_ps double @dyn_extract_v7f64_s_s(<7 x double> inreg %vec, i32 inreg %sel) {
1602; GCN-LABEL: dyn_extract_v7f64_s_s:
1603; GCN:       ; %bb.0: ; %entry
1604; GCN-NEXT:    s_mov_b32 s0, s2
1605; GCN-NEXT:    s_mov_b32 s1, s3
1606; GCN-NEXT:    s_mov_b32 m0, s16
1607; GCN-NEXT:    s_mov_b32 s2, s4
1608; GCN-NEXT:    s_mov_b32 s3, s5
1609; GCN-NEXT:    s_mov_b32 s4, s6
1610; GCN-NEXT:    s_mov_b32 s5, s7
1611; GCN-NEXT:    s_mov_b32 s6, s8
1612; GCN-NEXT:    s_mov_b32 s7, s9
1613; GCN-NEXT:    s_mov_b32 s8, s10
1614; GCN-NEXT:    s_mov_b32 s9, s11
1615; GCN-NEXT:    s_mov_b32 s10, s12
1616; GCN-NEXT:    s_mov_b32 s11, s13
1617; GCN-NEXT:    s_mov_b32 s12, s14
1618; GCN-NEXT:    s_mov_b32 s13, s15
1619; GCN-NEXT:    s_movrels_b64 s[0:1], s[0:1]
1620; GCN-NEXT:    ; return to shader part epilog
1621entry:
1622  %ext = extractelement <7 x double> %vec, i32 %sel
1623  ret double %ext
1624}
1625
1626define amdgpu_kernel void @dyn_extract_v5f64_s_s(double addrspace(1)* %out, i32 %sel) {
1627; GPRIDX-LABEL: dyn_extract_v5f64_s_s:
1628; GPRIDX:         .amd_kernel_code_t
1629; GPRIDX-NEXT:     amd_code_version_major = 1
1630; GPRIDX-NEXT:     amd_code_version_minor = 2
1631; GPRIDX-NEXT:     amd_machine_kind = 1
1632; GPRIDX-NEXT:     amd_machine_version_major = 9
1633; GPRIDX-NEXT:     amd_machine_version_minor = 0
1634; GPRIDX-NEXT:     amd_machine_version_stepping = 0
1635; GPRIDX-NEXT:     kernel_code_entry_byte_offset = 256
1636; GPRIDX-NEXT:     kernel_code_prefetch_byte_size = 0
1637; GPRIDX-NEXT:     granulated_workitem_vgpr_count = 0
1638; GPRIDX-NEXT:     granulated_wavefront_sgpr_count = 1
1639; GPRIDX-NEXT:     priority = 0
1640; GPRIDX-NEXT:     float_mode = 240
1641; GPRIDX-NEXT:     priv = 0
1642; GPRIDX-NEXT:     enable_dx10_clamp = 1
1643; GPRIDX-NEXT:     debug_mode = 0
1644; GPRIDX-NEXT:     enable_ieee_mode = 1
1645; GPRIDX-NEXT:     enable_wgp_mode = 0
1646; GPRIDX-NEXT:     enable_mem_ordered = 0
1647; GPRIDX-NEXT:     enable_fwd_progress = 0
1648; GPRIDX-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
1649; GPRIDX-NEXT:     user_sgpr_count = 6
1650; GPRIDX-NEXT:     enable_trap_handler = 0
1651; GPRIDX-NEXT:     enable_sgpr_workgroup_id_x = 1
1652; GPRIDX-NEXT:     enable_sgpr_workgroup_id_y = 0
1653; GPRIDX-NEXT:     enable_sgpr_workgroup_id_z = 0
1654; GPRIDX-NEXT:     enable_sgpr_workgroup_info = 0
1655; GPRIDX-NEXT:     enable_vgpr_workitem_id = 0
1656; GPRIDX-NEXT:     enable_exception_msb = 0
1657; GPRIDX-NEXT:     granulated_lds_size = 0
1658; GPRIDX-NEXT:     enable_exception = 0
1659; GPRIDX-NEXT:     enable_sgpr_private_segment_buffer = 1
1660; GPRIDX-NEXT:     enable_sgpr_dispatch_ptr = 0
1661; GPRIDX-NEXT:     enable_sgpr_queue_ptr = 0
1662; GPRIDX-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
1663; GPRIDX-NEXT:     enable_sgpr_dispatch_id = 0
1664; GPRIDX-NEXT:     enable_sgpr_flat_scratch_init = 0
1665; GPRIDX-NEXT:     enable_sgpr_private_segment_size = 0
1666; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
1667; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
1668; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
1669; GPRIDX-NEXT:     enable_wavefront_size32 = 0
1670; GPRIDX-NEXT:     enable_ordered_append_gds = 0
1671; GPRIDX-NEXT:     private_element_size = 1
1672; GPRIDX-NEXT:     is_ptr64 = 1
1673; GPRIDX-NEXT:     is_dynamic_callstack = 0
1674; GPRIDX-NEXT:     is_debug_enabled = 0
1675; GPRIDX-NEXT:     is_xnack_enabled = 0
1676; GPRIDX-NEXT:     workitem_private_segment_byte_size = 0
1677; GPRIDX-NEXT:     workgroup_group_segment_byte_size = 0
1678; GPRIDX-NEXT:     gds_segment_byte_size = 0
1679; GPRIDX-NEXT:     kernarg_segment_byte_size = 28
1680; GPRIDX-NEXT:     workgroup_fbarrier_count = 0
1681; GPRIDX-NEXT:     wavefront_sgpr_count = 9
1682; GPRIDX-NEXT:     workitem_vgpr_count = 4
1683; GPRIDX-NEXT:     reserved_vgpr_first = 0
1684; GPRIDX-NEXT:     reserved_vgpr_count = 0
1685; GPRIDX-NEXT:     reserved_sgpr_first = 0
1686; GPRIDX-NEXT:     reserved_sgpr_count = 0
1687; GPRIDX-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
1688; GPRIDX-NEXT:     debug_private_segment_buffer_sgpr = 0
1689; GPRIDX-NEXT:     kernarg_segment_alignment = 4
1690; GPRIDX-NEXT:     group_segment_alignment = 4
1691; GPRIDX-NEXT:     private_segment_alignment = 4
1692; GPRIDX-NEXT:     wavefront_size = 6
1693; GPRIDX-NEXT:     call_convention = -1
1694; GPRIDX-NEXT:     runtime_loader_kernel_symbol = 0
1695; GPRIDX-NEXT:    .end_amd_kernel_code_t
1696; GPRIDX-NEXT:  ; %bb.0: ; %entry
1697; GPRIDX-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x0
1698; GPRIDX-NEXT:    s_load_dword s8, s[4:5], 0x8
1699; GPRIDX-NEXT:    s_mov_b32 s0, 0
1700; GPRIDX-NEXT:    s_mov_b32 s3, 0x40080000
1701; GPRIDX-NEXT:    s_mov_b32 s2, s0
1702; GPRIDX-NEXT:    s_mov_b32 s1, 0x40140000
1703; GPRIDX-NEXT:    s_waitcnt lgkmcnt(0)
1704; GPRIDX-NEXT:    s_cmp_eq_u32 s8, 1
1705; GPRIDX-NEXT:    s_cselect_b64 s[4:5], 2.0, 1.0
1706; GPRIDX-NEXT:    s_cmp_eq_u32 s8, 2
1707; GPRIDX-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[4:5]
1708; GPRIDX-NEXT:    s_cmp_eq_u32 s8, 3
1709; GPRIDX-NEXT:    s_cselect_b64 s[2:3], 4.0, s[2:3]
1710; GPRIDX-NEXT:    s_cmp_eq_u32 s8, 4
1711; GPRIDX-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
1712; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
1713; GPRIDX-NEXT:    v_mov_b32_e32 v2, s6
1714; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
1715; GPRIDX-NEXT:    v_mov_b32_e32 v3, s7
1716; GPRIDX-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
1717; GPRIDX-NEXT:    s_endpgm
1718;
1719; MOVREL-LABEL: dyn_extract_v5f64_s_s:
1720; MOVREL:         .amd_kernel_code_t
1721; MOVREL-NEXT:     amd_code_version_major = 1
1722; MOVREL-NEXT:     amd_code_version_minor = 2
1723; MOVREL-NEXT:     amd_machine_kind = 1
1724; MOVREL-NEXT:     amd_machine_version_major = 8
1725; MOVREL-NEXT:     amd_machine_version_minor = 0
1726; MOVREL-NEXT:     amd_machine_version_stepping = 3
1727; MOVREL-NEXT:     kernel_code_entry_byte_offset = 256
1728; MOVREL-NEXT:     kernel_code_prefetch_byte_size = 0
1729; MOVREL-NEXT:     granulated_workitem_vgpr_count = 0
1730; MOVREL-NEXT:     granulated_wavefront_sgpr_count = 1
1731; MOVREL-NEXT:     priority = 0
1732; MOVREL-NEXT:     float_mode = 240
1733; MOVREL-NEXT:     priv = 0
1734; MOVREL-NEXT:     enable_dx10_clamp = 1
1735; MOVREL-NEXT:     debug_mode = 0
1736; MOVREL-NEXT:     enable_ieee_mode = 1
1737; MOVREL-NEXT:     enable_wgp_mode = 0
1738; MOVREL-NEXT:     enable_mem_ordered = 0
1739; MOVREL-NEXT:     enable_fwd_progress = 0
1740; MOVREL-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
1741; MOVREL-NEXT:     user_sgpr_count = 6
1742; MOVREL-NEXT:     enable_trap_handler = 0
1743; MOVREL-NEXT:     enable_sgpr_workgroup_id_x = 1
1744; MOVREL-NEXT:     enable_sgpr_workgroup_id_y = 0
1745; MOVREL-NEXT:     enable_sgpr_workgroup_id_z = 0
1746; MOVREL-NEXT:     enable_sgpr_workgroup_info = 0
1747; MOVREL-NEXT:     enable_vgpr_workitem_id = 0
1748; MOVREL-NEXT:     enable_exception_msb = 0
1749; MOVREL-NEXT:     granulated_lds_size = 0
1750; MOVREL-NEXT:     enable_exception = 0
1751; MOVREL-NEXT:     enable_sgpr_private_segment_buffer = 1
1752; MOVREL-NEXT:     enable_sgpr_dispatch_ptr = 0
1753; MOVREL-NEXT:     enable_sgpr_queue_ptr = 0
1754; MOVREL-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
1755; MOVREL-NEXT:     enable_sgpr_dispatch_id = 0
1756; MOVREL-NEXT:     enable_sgpr_flat_scratch_init = 0
1757; MOVREL-NEXT:     enable_sgpr_private_segment_size = 0
1758; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
1759; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
1760; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
1761; MOVREL-NEXT:     enable_wavefront_size32 = 0
1762; MOVREL-NEXT:     enable_ordered_append_gds = 0
1763; MOVREL-NEXT:     private_element_size = 1
1764; MOVREL-NEXT:     is_ptr64 = 1
1765; MOVREL-NEXT:     is_dynamic_callstack = 0
1766; MOVREL-NEXT:     is_debug_enabled = 0
1767; MOVREL-NEXT:     is_xnack_enabled = 0
1768; MOVREL-NEXT:     workitem_private_segment_byte_size = 0
1769; MOVREL-NEXT:     workgroup_group_segment_byte_size = 0
1770; MOVREL-NEXT:     gds_segment_byte_size = 0
1771; MOVREL-NEXT:     kernarg_segment_byte_size = 28
1772; MOVREL-NEXT:     workgroup_fbarrier_count = 0
1773; MOVREL-NEXT:     wavefront_sgpr_count = 9
1774; MOVREL-NEXT:     workitem_vgpr_count = 4
1775; MOVREL-NEXT:     reserved_vgpr_first = 0
1776; MOVREL-NEXT:     reserved_vgpr_count = 0
1777; MOVREL-NEXT:     reserved_sgpr_first = 0
1778; MOVREL-NEXT:     reserved_sgpr_count = 0
1779; MOVREL-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
1780; MOVREL-NEXT:     debug_private_segment_buffer_sgpr = 0
1781; MOVREL-NEXT:     kernarg_segment_alignment = 4
1782; MOVREL-NEXT:     group_segment_alignment = 4
1783; MOVREL-NEXT:     private_segment_alignment = 4
1784; MOVREL-NEXT:     wavefront_size = 6
1785; MOVREL-NEXT:     call_convention = -1
1786; MOVREL-NEXT:     runtime_loader_kernel_symbol = 0
1787; MOVREL-NEXT:    .end_amd_kernel_code_t
1788; MOVREL-NEXT:  ; %bb.0: ; %entry
1789; MOVREL-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x0
1790; MOVREL-NEXT:    s_load_dword s8, s[4:5], 0x8
1791; MOVREL-NEXT:    s_mov_b32 s0, 0
1792; MOVREL-NEXT:    s_mov_b32 s3, 0x40080000
1793; MOVREL-NEXT:    s_mov_b32 s2, s0
1794; MOVREL-NEXT:    s_mov_b32 s1, 0x40140000
1795; MOVREL-NEXT:    s_waitcnt lgkmcnt(0)
1796; MOVREL-NEXT:    s_cmp_eq_u32 s8, 1
1797; MOVREL-NEXT:    s_cselect_b64 s[4:5], 2.0, 1.0
1798; MOVREL-NEXT:    s_cmp_eq_u32 s8, 2
1799; MOVREL-NEXT:    s_cselect_b64 s[2:3], s[2:3], s[4:5]
1800; MOVREL-NEXT:    s_cmp_eq_u32 s8, 3
1801; MOVREL-NEXT:    s_cselect_b64 s[2:3], 4.0, s[2:3]
1802; MOVREL-NEXT:    s_cmp_eq_u32 s8, 4
1803; MOVREL-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[2:3]
1804; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
1805; MOVREL-NEXT:    v_mov_b32_e32 v2, s6
1806; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
1807; MOVREL-NEXT:    v_mov_b32_e32 v3, s7
1808; MOVREL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
1809; MOVREL-NEXT:    s_endpgm
1810entry:
1811  %ext = extractelement <5 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0>, i32 %sel
1812  store double %ext, double addrspace(1)* %out
1813  ret void
1814}
1815
1816define float @dyn_extract_v15f32_const_s_v(i32 %sel) {
1817; GCN-LABEL: dyn_extract_v15f32_const_s_v:
1818; GCN:       ; %bb.0: ; %entry
1819; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1820; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
1821; GCN-NEXT:    v_cndmask_b32_e64 v13, 1.0, 2.0, vcc
1822; GCN-NEXT:    v_mov_b32_e32 v1, 0x40400000
1823; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
1824; GCN-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc
1825; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
1826; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, 4.0, vcc
1827; GCN-NEXT:    v_mov_b32_e32 v2, 0x40a00000
1828; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
1829; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1830; GCN-NEXT:    v_mov_b32_e32 v3, 0x40c00000
1831; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
1832; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1833; GCN-NEXT:    v_mov_b32_e32 v4, 0x40e00000
1834; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
1835; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1836; GCN-NEXT:    v_mov_b32_e32 v5, 0x41000000
1837; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
1838; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1839; GCN-NEXT:    v_mov_b32_e32 v6, 0x41100000
1840; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 8, v0
1841; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1842; GCN-NEXT:    v_mov_b32_e32 v7, 0x41200000
1843; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 9, v0
1844; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1845; GCN-NEXT:    v_mov_b32_e32 v8, 0x41300000
1846; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 10, v0
1847; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
1848; GCN-NEXT:    v_mov_b32_e32 v9, 0x41400000
1849; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 11, v0
1850; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
1851; GCN-NEXT:    v_mov_b32_e32 v10, 0x41500000
1852; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 12, v0
1853; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v10, vcc
1854; GCN-NEXT:    v_mov_b32_e32 v11, 0x41600000
1855; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 13, v0
1856; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
1857; GCN-NEXT:    v_mov_b32_e32 v12, 0x41700000
1858; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 14, v0
1859; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v12, vcc
1860; GCN-NEXT:    s_setpc_b64 s[30:31]
1861entry:
1862  %ext = extractelement <15 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0>, i32 %sel
1863  ret float %ext
1864}
1865
1866define amdgpu_ps float @dyn_extract_v15f32_const_s_s(i32 inreg %sel) {
1867; GCN-LABEL: dyn_extract_v15f32_const_s_s:
1868; GCN:       ; %bb.0: ; %entry
1869; GCN-NEXT:    s_mov_b32 s4, 1.0
1870; GCN-NEXT:    s_mov_b32 m0, s2
1871; GCN-NEXT:    s_mov_b32 s18, 0x41700000
1872; GCN-NEXT:    s_mov_b32 s17, 0x41600000
1873; GCN-NEXT:    s_mov_b32 s16, 0x41500000
1874; GCN-NEXT:    s_mov_b32 s15, 0x41400000
1875; GCN-NEXT:    s_mov_b32 s14, 0x41300000
1876; GCN-NEXT:    s_mov_b32 s13, 0x41200000
1877; GCN-NEXT:    s_mov_b32 s12, 0x41100000
1878; GCN-NEXT:    s_mov_b32 s11, 0x41000000
1879; GCN-NEXT:    s_mov_b32 s10, 0x40e00000
1880; GCN-NEXT:    s_mov_b32 s9, 0x40c00000
1881; GCN-NEXT:    s_mov_b32 s8, 0x40a00000
1882; GCN-NEXT:    s_mov_b32 s7, 4.0
1883; GCN-NEXT:    s_mov_b32 s6, 0x40400000
1884; GCN-NEXT:    s_mov_b32 s5, 2.0
1885; GCN-NEXT:    s_movrels_b32 s0, s4
1886; GCN-NEXT:    v_mov_b32_e32 v0, s0
1887; GCN-NEXT:    ; return to shader part epilog
1888entry:
1889  %ext = extractelement <15 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0>, i32 %sel
1890  ret float %ext
1891}
1892
1893define amdgpu_ps float @dyn_extract_v15f32_s_v(<15 x float> inreg %vec, i32 %sel) {
1894; GCN-LABEL: dyn_extract_v15f32_s_v:
1895; GCN:       ; %bb.0: ; %entry
1896; GCN-NEXT:    s_mov_b32 s0, s2
1897; GCN-NEXT:    s_mov_b32 s1, s3
1898; GCN-NEXT:    s_mov_b32 s2, s4
1899; GCN-NEXT:    v_mov_b32_e32 v1, s0
1900; GCN-NEXT:    v_mov_b32_e32 v2, s1
1901; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
1902; GCN-NEXT:    s_mov_b32 s3, s5
1903; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1904; GCN-NEXT:    v_mov_b32_e32 v3, s2
1905; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v0
1906; GCN-NEXT:    s_mov_b32 s4, s6
1907; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1908; GCN-NEXT:    v_mov_b32_e32 v4, s3
1909; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
1910; GCN-NEXT:    s_mov_b32 s5, s7
1911; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1912; GCN-NEXT:    v_mov_b32_e32 v5, s4
1913; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v0
1914; GCN-NEXT:    s_mov_b32 s6, s8
1915; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
1916; GCN-NEXT:    v_mov_b32_e32 v6, s5
1917; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v0
1918; GCN-NEXT:    s_mov_b32 s7, s9
1919; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
1920; GCN-NEXT:    v_mov_b32_e32 v7, s6
1921; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v0
1922; GCN-NEXT:    s_mov_b32 s8, s10
1923; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
1924; GCN-NEXT:    v_mov_b32_e32 v8, s7
1925; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v0
1926; GCN-NEXT:    s_mov_b32 s9, s11
1927; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
1928; GCN-NEXT:    v_mov_b32_e32 v9, s8
1929; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 8, v0
1930; GCN-NEXT:    s_mov_b32 s10, s12
1931; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
1932; GCN-NEXT:    v_mov_b32_e32 v10, s9
1933; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 9, v0
1934; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v10, vcc
1935; GCN-NEXT:    v_mov_b32_e32 v11, s10
1936; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 10, v0
1937; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
1938; GCN-NEXT:    v_mov_b32_e32 v12, s13
1939; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 11, v0
1940; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v12, vcc
1941; GCN-NEXT:    v_mov_b32_e32 v13, s14
1942; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 12, v0
1943; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v13, vcc
1944; GCN-NEXT:    v_mov_b32_e32 v14, s15
1945; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 13, v0
1946; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v14, vcc
1947; GCN-NEXT:    v_mov_b32_e32 v15, s16
1948; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 14, v0
1949; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v15, vcc
1950; GCN-NEXT:    ; return to shader part epilog
1951entry:
1952  %ext = extractelement <15 x float> %vec, i32 %sel
1953  ret float %ext
1954}
1955
1956define float @dyn_extract_v15f32_v_v(<15 x float> %vec, i32 %sel) {
1957; GCN-LABEL: dyn_extract_v15f32_v_v:
1958; GCN:       ; %bb.0: ; %entry
1959; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1960; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v15
1961; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
1962; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v15
1963; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1964; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v15
1965; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
1966; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v15
1967; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
1968; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v15
1969; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
1970; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v15
1971; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
1972; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v15
1973; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
1974; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 8, v15
1975; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
1976; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 9, v15
1977; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
1978; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 10, v15
1979; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
1980; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 11, v15
1981; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v11, vcc
1982; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 12, v15
1983; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
1984; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 13, v15
1985; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v13, vcc
1986; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 14, v15
1987; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
1988; GCN-NEXT:    s_setpc_b64 s[30:31]
1989entry:
1990  %ext = extractelement <15 x float> %vec, i32 %sel
1991  ret float %ext
1992}
1993
1994define amdgpu_ps float @dyn_extract_v15f32_v_s(<15 x float> %vec, i32 inreg %sel) {
1995; GPRIDX-LABEL: dyn_extract_v15f32_v_s:
1996; GPRIDX:       ; %bb.0: ; %entry
1997; GPRIDX-NEXT:    s_set_gpr_idx_on s2, gpr_idx(SRC0)
1998; GPRIDX-NEXT:    v_mov_b32_e32 v0, v0
1999; GPRIDX-NEXT:    s_set_gpr_idx_off
2000; GPRIDX-NEXT:    ; return to shader part epilog
2001;
2002; MOVREL-LABEL: dyn_extract_v15f32_v_s:
2003; MOVREL:       ; %bb.0: ; %entry
2004; MOVREL-NEXT:    s_mov_b32 m0, s2
2005; MOVREL-NEXT:    v_movrels_b32_e32 v0, v0
2006; MOVREL-NEXT:    ; return to shader part epilog
2007entry:
2008  %ext = extractelement <15 x float> %vec, i32 %sel
2009  ret float %ext
2010}
2011
2012define amdgpu_ps float @dyn_extract_v15f32_s_s(<15 x float> inreg %vec, i32 inreg %sel) {
2013; GCN-LABEL: dyn_extract_v15f32_s_s:
2014; GCN:       ; %bb.0: ; %entry
2015; GCN-NEXT:    s_mov_b32 s0, s2
2016; GCN-NEXT:    s_mov_b32 m0, s17
2017; GCN-NEXT:    s_mov_b32 s1, s3
2018; GCN-NEXT:    s_mov_b32 s2, s4
2019; GCN-NEXT:    s_mov_b32 s3, s5
2020; GCN-NEXT:    s_mov_b32 s4, s6
2021; GCN-NEXT:    s_mov_b32 s5, s7
2022; GCN-NEXT:    s_mov_b32 s6, s8
2023; GCN-NEXT:    s_mov_b32 s7, s9
2024; GCN-NEXT:    s_mov_b32 s8, s10
2025; GCN-NEXT:    s_mov_b32 s9, s11
2026; GCN-NEXT:    s_mov_b32 s10, s12
2027; GCN-NEXT:    s_mov_b32 s11, s13
2028; GCN-NEXT:    s_mov_b32 s12, s14
2029; GCN-NEXT:    s_mov_b32 s13, s15
2030; GCN-NEXT:    s_mov_b32 s14, s16
2031; GCN-NEXT:    s_movrels_b32 s0, s0
2032; GCN-NEXT:    v_mov_b32_e32 v0, s0
2033; GCN-NEXT:    ; return to shader part epilog
2034entry:
2035  %ext = extractelement <15 x float> %vec, i32 %sel
2036  ret float %ext
2037}
2038
2039define amdgpu_ps float @dyn_extract_v15f32_s_s_offset3(<15 x float> inreg %vec, i32 inreg %sel) {
2040; GCN-LABEL: dyn_extract_v15f32_s_s_offset3:
2041; GCN:       ; %bb.0: ; %entry
2042; GCN-NEXT:    s_mov_b32 s0, s2
2043; GCN-NEXT:    s_mov_b32 s1, s3
2044; GCN-NEXT:    s_mov_b32 s3, s5
2045; GCN-NEXT:    s_mov_b32 m0, s17
2046; GCN-NEXT:    s_mov_b32 s2, s4
2047; GCN-NEXT:    s_mov_b32 s4, s6
2048; GCN-NEXT:    s_mov_b32 s5, s7
2049; GCN-NEXT:    s_mov_b32 s6, s8
2050; GCN-NEXT:    s_mov_b32 s7, s9
2051; GCN-NEXT:    s_mov_b32 s8, s10
2052; GCN-NEXT:    s_mov_b32 s9, s11
2053; GCN-NEXT:    s_mov_b32 s10, s12
2054; GCN-NEXT:    s_mov_b32 s11, s13
2055; GCN-NEXT:    s_mov_b32 s12, s14
2056; GCN-NEXT:    s_mov_b32 s13, s15
2057; GCN-NEXT:    s_mov_b32 s14, s16
2058; GCN-NEXT:    s_movrels_b32 s0, s3
2059; GCN-NEXT:    v_mov_b32_e32 v0, s0
2060; GCN-NEXT:    ; return to shader part epilog
2061entry:
2062  %add = add i32 %sel, 3
2063  %ext = extractelement <15 x float> %vec, i32 %add
2064  ret float %ext
2065}
2066
2067define float @dyn_extract_v15f32_v_v_offset3(<15 x float> %vec, i32 %sel) {
2068; GPRIDX-LABEL: dyn_extract_v15f32_v_v_offset3:
2069; GPRIDX:       ; %bb.0: ; %entry
2070; GPRIDX-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2071; GPRIDX-NEXT:    v_add_u32_e32 v15, 3, v15
2072; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v15
2073; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
2074; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v15
2075; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2076; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v15
2077; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2078; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v15
2079; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
2080; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v15
2081; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
2082; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v15
2083; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
2084; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v15
2085; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
2086; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 8, v15
2087; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
2088; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 9, v15
2089; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
2090; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 10, v15
2091; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
2092; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 11, v15
2093; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v11, vcc
2094; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 12, v15
2095; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
2096; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 13, v15
2097; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v13, vcc
2098; GPRIDX-NEXT:    v_cmp_eq_u32_e32 vcc, 14, v15
2099; GPRIDX-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
2100; GPRIDX-NEXT:    s_setpc_b64 s[30:31]
2101;
2102; MOVREL-LABEL: dyn_extract_v15f32_v_v_offset3:
2103; MOVREL:       ; %bb.0: ; %entry
2104; MOVREL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2105; MOVREL-NEXT:    v_add_u32_e32 v15, vcc, 3, v15
2106; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v15
2107; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
2108; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v15
2109; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
2110; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v15
2111; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
2112; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v15
2113; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
2114; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v15
2115; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
2116; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 6, v15
2117; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
2118; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 7, v15
2119; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
2120; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 8, v15
2121; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
2122; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 9, v15
2123; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
2124; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 10, v15
2125; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
2126; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 11, v15
2127; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v11, vcc
2128; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 12, v15
2129; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
2130; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 13, v15
2131; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v13, vcc
2132; MOVREL-NEXT:    v_cmp_eq_u32_e32 vcc, 14, v15
2133; MOVREL-NEXT:    v_cndmask_b32_e32 v0, v0, v14, vcc
2134; MOVREL-NEXT:    s_setpc_b64 s[30:31]
2135entry:
2136  %add = add i32 %sel, 3
2137  %ext = extractelement <15 x float> %vec, i32 %add
2138  ret float %ext
2139}
2140
2141define amdgpu_kernel void @dyn_extract_v4f32_s_s_s(float addrspace(1)* %out, i32 %sel) {
2142; GPRIDX-LABEL: dyn_extract_v4f32_s_s_s:
2143; GPRIDX:         .amd_kernel_code_t
2144; GPRIDX-NEXT:     amd_code_version_major = 1
2145; GPRIDX-NEXT:     amd_code_version_minor = 2
2146; GPRIDX-NEXT:     amd_machine_kind = 1
2147; GPRIDX-NEXT:     amd_machine_version_major = 9
2148; GPRIDX-NEXT:     amd_machine_version_minor = 0
2149; GPRIDX-NEXT:     amd_machine_version_stepping = 0
2150; GPRIDX-NEXT:     kernel_code_entry_byte_offset = 256
2151; GPRIDX-NEXT:     kernel_code_prefetch_byte_size = 0
2152; GPRIDX-NEXT:     granulated_workitem_vgpr_count = 0
2153; GPRIDX-NEXT:     granulated_wavefront_sgpr_count = 0
2154; GPRIDX-NEXT:     priority = 0
2155; GPRIDX-NEXT:     float_mode = 240
2156; GPRIDX-NEXT:     priv = 0
2157; GPRIDX-NEXT:     enable_dx10_clamp = 1
2158; GPRIDX-NEXT:     debug_mode = 0
2159; GPRIDX-NEXT:     enable_ieee_mode = 1
2160; GPRIDX-NEXT:     enable_wgp_mode = 0
2161; GPRIDX-NEXT:     enable_mem_ordered = 0
2162; GPRIDX-NEXT:     enable_fwd_progress = 0
2163; GPRIDX-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
2164; GPRIDX-NEXT:     user_sgpr_count = 6
2165; GPRIDX-NEXT:     enable_trap_handler = 0
2166; GPRIDX-NEXT:     enable_sgpr_workgroup_id_x = 1
2167; GPRIDX-NEXT:     enable_sgpr_workgroup_id_y = 0
2168; GPRIDX-NEXT:     enable_sgpr_workgroup_id_z = 0
2169; GPRIDX-NEXT:     enable_sgpr_workgroup_info = 0
2170; GPRIDX-NEXT:     enable_vgpr_workitem_id = 0
2171; GPRIDX-NEXT:     enable_exception_msb = 0
2172; GPRIDX-NEXT:     granulated_lds_size = 0
2173; GPRIDX-NEXT:     enable_exception = 0
2174; GPRIDX-NEXT:     enable_sgpr_private_segment_buffer = 1
2175; GPRIDX-NEXT:     enable_sgpr_dispatch_ptr = 0
2176; GPRIDX-NEXT:     enable_sgpr_queue_ptr = 0
2177; GPRIDX-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
2178; GPRIDX-NEXT:     enable_sgpr_dispatch_id = 0
2179; GPRIDX-NEXT:     enable_sgpr_flat_scratch_init = 0
2180; GPRIDX-NEXT:     enable_sgpr_private_segment_size = 0
2181; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
2182; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
2183; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
2184; GPRIDX-NEXT:     enable_wavefront_size32 = 0
2185; GPRIDX-NEXT:     enable_ordered_append_gds = 0
2186; GPRIDX-NEXT:     private_element_size = 1
2187; GPRIDX-NEXT:     is_ptr64 = 1
2188; GPRIDX-NEXT:     is_dynamic_callstack = 0
2189; GPRIDX-NEXT:     is_debug_enabled = 0
2190; GPRIDX-NEXT:     is_xnack_enabled = 0
2191; GPRIDX-NEXT:     workitem_private_segment_byte_size = 0
2192; GPRIDX-NEXT:     workgroup_group_segment_byte_size = 0
2193; GPRIDX-NEXT:     gds_segment_byte_size = 0
2194; GPRIDX-NEXT:     kernarg_segment_byte_size = 28
2195; GPRIDX-NEXT:     workgroup_fbarrier_count = 0
2196; GPRIDX-NEXT:     wavefront_sgpr_count = 6
2197; GPRIDX-NEXT:     workitem_vgpr_count = 3
2198; GPRIDX-NEXT:     reserved_vgpr_first = 0
2199; GPRIDX-NEXT:     reserved_vgpr_count = 0
2200; GPRIDX-NEXT:     reserved_sgpr_first = 0
2201; GPRIDX-NEXT:     reserved_sgpr_count = 0
2202; GPRIDX-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
2203; GPRIDX-NEXT:     debug_private_segment_buffer_sgpr = 0
2204; GPRIDX-NEXT:     kernarg_segment_alignment = 4
2205; GPRIDX-NEXT:     group_segment_alignment = 4
2206; GPRIDX-NEXT:     private_segment_alignment = 4
2207; GPRIDX-NEXT:     wavefront_size = 6
2208; GPRIDX-NEXT:     call_convention = -1
2209; GPRIDX-NEXT:     runtime_loader_kernel_symbol = 0
2210; GPRIDX-NEXT:    .end_amd_kernel_code_t
2211; GPRIDX-NEXT:  ; %bb.0: ; %entry
2212; GPRIDX-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
2213; GPRIDX-NEXT:    s_load_dword s2, s[4:5], 0x8
2214; GPRIDX-NEXT:    s_waitcnt lgkmcnt(0)
2215; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
2216; GPRIDX-NEXT:    s_cmp_eq_u32 s2, 1
2217; GPRIDX-NEXT:    s_cselect_b32 s3, 2.0, 1.0
2218; GPRIDX-NEXT:    s_cmp_eq_u32 s2, 2
2219; GPRIDX-NEXT:    s_cselect_b32 s3, 0x40400000, s3
2220; GPRIDX-NEXT:    s_cmp_eq_u32 s2, 3
2221; GPRIDX-NEXT:    s_cselect_b32 s2, 4.0, s3
2222; GPRIDX-NEXT:    v_mov_b32_e32 v2, s2
2223; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
2224; GPRIDX-NEXT:    global_store_dword v[0:1], v2, off
2225; GPRIDX-NEXT:    s_endpgm
2226;
2227; MOVREL-LABEL: dyn_extract_v4f32_s_s_s:
2228; MOVREL:         .amd_kernel_code_t
2229; MOVREL-NEXT:     amd_code_version_major = 1
2230; MOVREL-NEXT:     amd_code_version_minor = 2
2231; MOVREL-NEXT:     amd_machine_kind = 1
2232; MOVREL-NEXT:     amd_machine_version_major = 8
2233; MOVREL-NEXT:     amd_machine_version_minor = 0
2234; MOVREL-NEXT:     amd_machine_version_stepping = 3
2235; MOVREL-NEXT:     kernel_code_entry_byte_offset = 256
2236; MOVREL-NEXT:     kernel_code_prefetch_byte_size = 0
2237; MOVREL-NEXT:     granulated_workitem_vgpr_count = 0
2238; MOVREL-NEXT:     granulated_wavefront_sgpr_count = 0
2239; MOVREL-NEXT:     priority = 0
2240; MOVREL-NEXT:     float_mode = 240
2241; MOVREL-NEXT:     priv = 0
2242; MOVREL-NEXT:     enable_dx10_clamp = 1
2243; MOVREL-NEXT:     debug_mode = 0
2244; MOVREL-NEXT:     enable_ieee_mode = 1
2245; MOVREL-NEXT:     enable_wgp_mode = 0
2246; MOVREL-NEXT:     enable_mem_ordered = 0
2247; MOVREL-NEXT:     enable_fwd_progress = 0
2248; MOVREL-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
2249; MOVREL-NEXT:     user_sgpr_count = 6
2250; MOVREL-NEXT:     enable_trap_handler = 0
2251; MOVREL-NEXT:     enable_sgpr_workgroup_id_x = 1
2252; MOVREL-NEXT:     enable_sgpr_workgroup_id_y = 0
2253; MOVREL-NEXT:     enable_sgpr_workgroup_id_z = 0
2254; MOVREL-NEXT:     enable_sgpr_workgroup_info = 0
2255; MOVREL-NEXT:     enable_vgpr_workitem_id = 0
2256; MOVREL-NEXT:     enable_exception_msb = 0
2257; MOVREL-NEXT:     granulated_lds_size = 0
2258; MOVREL-NEXT:     enable_exception = 0
2259; MOVREL-NEXT:     enable_sgpr_private_segment_buffer = 1
2260; MOVREL-NEXT:     enable_sgpr_dispatch_ptr = 0
2261; MOVREL-NEXT:     enable_sgpr_queue_ptr = 0
2262; MOVREL-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
2263; MOVREL-NEXT:     enable_sgpr_dispatch_id = 0
2264; MOVREL-NEXT:     enable_sgpr_flat_scratch_init = 0
2265; MOVREL-NEXT:     enable_sgpr_private_segment_size = 0
2266; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
2267; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
2268; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
2269; MOVREL-NEXT:     enable_wavefront_size32 = 0
2270; MOVREL-NEXT:     enable_ordered_append_gds = 0
2271; MOVREL-NEXT:     private_element_size = 1
2272; MOVREL-NEXT:     is_ptr64 = 1
2273; MOVREL-NEXT:     is_dynamic_callstack = 0
2274; MOVREL-NEXT:     is_debug_enabled = 0
2275; MOVREL-NEXT:     is_xnack_enabled = 0
2276; MOVREL-NEXT:     workitem_private_segment_byte_size = 0
2277; MOVREL-NEXT:     workgroup_group_segment_byte_size = 0
2278; MOVREL-NEXT:     gds_segment_byte_size = 0
2279; MOVREL-NEXT:     kernarg_segment_byte_size = 28
2280; MOVREL-NEXT:     workgroup_fbarrier_count = 0
2281; MOVREL-NEXT:     wavefront_sgpr_count = 6
2282; MOVREL-NEXT:     workitem_vgpr_count = 3
2283; MOVREL-NEXT:     reserved_vgpr_first = 0
2284; MOVREL-NEXT:     reserved_vgpr_count = 0
2285; MOVREL-NEXT:     reserved_sgpr_first = 0
2286; MOVREL-NEXT:     reserved_sgpr_count = 0
2287; MOVREL-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
2288; MOVREL-NEXT:     debug_private_segment_buffer_sgpr = 0
2289; MOVREL-NEXT:     kernarg_segment_alignment = 4
2290; MOVREL-NEXT:     group_segment_alignment = 4
2291; MOVREL-NEXT:     private_segment_alignment = 4
2292; MOVREL-NEXT:     wavefront_size = 6
2293; MOVREL-NEXT:     call_convention = -1
2294; MOVREL-NEXT:     runtime_loader_kernel_symbol = 0
2295; MOVREL-NEXT:    .end_amd_kernel_code_t
2296; MOVREL-NEXT:  ; %bb.0: ; %entry
2297; MOVREL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
2298; MOVREL-NEXT:    s_load_dword s2, s[4:5], 0x8
2299; MOVREL-NEXT:    s_waitcnt lgkmcnt(0)
2300; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
2301; MOVREL-NEXT:    s_cmp_eq_u32 s2, 1
2302; MOVREL-NEXT:    s_cselect_b32 s3, 2.0, 1.0
2303; MOVREL-NEXT:    s_cmp_eq_u32 s2, 2
2304; MOVREL-NEXT:    s_cselect_b32 s3, 0x40400000, s3
2305; MOVREL-NEXT:    s_cmp_eq_u32 s2, 3
2306; MOVREL-NEXT:    s_cselect_b32 s2, 4.0, s3
2307; MOVREL-NEXT:    v_mov_b32_e32 v2, s2
2308; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
2309; MOVREL-NEXT:    flat_store_dword v[0:1], v2
2310; MOVREL-NEXT:    s_endpgm
2311entry:
2312  %ext = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %sel
2313  store float %ext, float addrspace(1)* %out
2314  ret void
2315}
2316
2317define amdgpu_kernel void @dyn_extract_v4f64_s_s_s(double addrspace(1)* %out, i32 %sel) {
2318; GPRIDX-LABEL: dyn_extract_v4f64_s_s_s:
2319; GPRIDX:         .amd_kernel_code_t
2320; GPRIDX-NEXT:     amd_code_version_major = 1
2321; GPRIDX-NEXT:     amd_code_version_minor = 2
2322; GPRIDX-NEXT:     amd_machine_kind = 1
2323; GPRIDX-NEXT:     amd_machine_version_major = 9
2324; GPRIDX-NEXT:     amd_machine_version_minor = 0
2325; GPRIDX-NEXT:     amd_machine_version_stepping = 0
2326; GPRIDX-NEXT:     kernel_code_entry_byte_offset = 256
2327; GPRIDX-NEXT:     kernel_code_prefetch_byte_size = 0
2328; GPRIDX-NEXT:     granulated_workitem_vgpr_count = 0
2329; GPRIDX-NEXT:     granulated_wavefront_sgpr_count = 0
2330; GPRIDX-NEXT:     priority = 0
2331; GPRIDX-NEXT:     float_mode = 240
2332; GPRIDX-NEXT:     priv = 0
2333; GPRIDX-NEXT:     enable_dx10_clamp = 1
2334; GPRIDX-NEXT:     debug_mode = 0
2335; GPRIDX-NEXT:     enable_ieee_mode = 1
2336; GPRIDX-NEXT:     enable_wgp_mode = 0
2337; GPRIDX-NEXT:     enable_mem_ordered = 0
2338; GPRIDX-NEXT:     enable_fwd_progress = 0
2339; GPRIDX-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
2340; GPRIDX-NEXT:     user_sgpr_count = 6
2341; GPRIDX-NEXT:     enable_trap_handler = 0
2342; GPRIDX-NEXT:     enable_sgpr_workgroup_id_x = 1
2343; GPRIDX-NEXT:     enable_sgpr_workgroup_id_y = 0
2344; GPRIDX-NEXT:     enable_sgpr_workgroup_id_z = 0
2345; GPRIDX-NEXT:     enable_sgpr_workgroup_info = 0
2346; GPRIDX-NEXT:     enable_vgpr_workitem_id = 0
2347; GPRIDX-NEXT:     enable_exception_msb = 0
2348; GPRIDX-NEXT:     granulated_lds_size = 0
2349; GPRIDX-NEXT:     enable_exception = 0
2350; GPRIDX-NEXT:     enable_sgpr_private_segment_buffer = 1
2351; GPRIDX-NEXT:     enable_sgpr_dispatch_ptr = 0
2352; GPRIDX-NEXT:     enable_sgpr_queue_ptr = 0
2353; GPRIDX-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
2354; GPRIDX-NEXT:     enable_sgpr_dispatch_id = 0
2355; GPRIDX-NEXT:     enable_sgpr_flat_scratch_init = 0
2356; GPRIDX-NEXT:     enable_sgpr_private_segment_size = 0
2357; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
2358; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
2359; GPRIDX-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
2360; GPRIDX-NEXT:     enable_wavefront_size32 = 0
2361; GPRIDX-NEXT:     enable_ordered_append_gds = 0
2362; GPRIDX-NEXT:     private_element_size = 1
2363; GPRIDX-NEXT:     is_ptr64 = 1
2364; GPRIDX-NEXT:     is_dynamic_callstack = 0
2365; GPRIDX-NEXT:     is_debug_enabled = 0
2366; GPRIDX-NEXT:     is_xnack_enabled = 0
2367; GPRIDX-NEXT:     workitem_private_segment_byte_size = 0
2368; GPRIDX-NEXT:     workgroup_group_segment_byte_size = 0
2369; GPRIDX-NEXT:     gds_segment_byte_size = 0
2370; GPRIDX-NEXT:     kernarg_segment_byte_size = 28
2371; GPRIDX-NEXT:     workgroup_fbarrier_count = 0
2372; GPRIDX-NEXT:     wavefront_sgpr_count = 7
2373; GPRIDX-NEXT:     workitem_vgpr_count = 4
2374; GPRIDX-NEXT:     reserved_vgpr_first = 0
2375; GPRIDX-NEXT:     reserved_vgpr_count = 0
2376; GPRIDX-NEXT:     reserved_sgpr_first = 0
2377; GPRIDX-NEXT:     reserved_sgpr_count = 0
2378; GPRIDX-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
2379; GPRIDX-NEXT:     debug_private_segment_buffer_sgpr = 0
2380; GPRIDX-NEXT:     kernarg_segment_alignment = 4
2381; GPRIDX-NEXT:     group_segment_alignment = 4
2382; GPRIDX-NEXT:     private_segment_alignment = 4
2383; GPRIDX-NEXT:     wavefront_size = 6
2384; GPRIDX-NEXT:     call_convention = -1
2385; GPRIDX-NEXT:     runtime_loader_kernel_symbol = 0
2386; GPRIDX-NEXT:    .end_amd_kernel_code_t
2387; GPRIDX-NEXT:  ; %bb.0: ; %entry
2388; GPRIDX-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x0
2389; GPRIDX-NEXT:    s_load_dword s6, s[4:5], 0x8
2390; GPRIDX-NEXT:    s_mov_b32 s0, 0
2391; GPRIDX-NEXT:    s_mov_b32 s1, 0x40080000
2392; GPRIDX-NEXT:    s_waitcnt lgkmcnt(0)
2393; GPRIDX-NEXT:    v_mov_b32_e32 v2, s2
2394; GPRIDX-NEXT:    s_cmp_eq_u32 s6, 1
2395; GPRIDX-NEXT:    s_cselect_b64 s[4:5], 2.0, 1.0
2396; GPRIDX-NEXT:    s_cmp_eq_u32 s6, 2
2397; GPRIDX-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
2398; GPRIDX-NEXT:    s_cmp_eq_u32 s6, 3
2399; GPRIDX-NEXT:    s_cselect_b64 s[0:1], 4.0, s[0:1]
2400; GPRIDX-NEXT:    v_mov_b32_e32 v0, s0
2401; GPRIDX-NEXT:    v_mov_b32_e32 v1, s1
2402; GPRIDX-NEXT:    v_mov_b32_e32 v3, s3
2403; GPRIDX-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
2404; GPRIDX-NEXT:    s_endpgm
2405;
2406; MOVREL-LABEL: dyn_extract_v4f64_s_s_s:
2407; MOVREL:         .amd_kernel_code_t
2408; MOVREL-NEXT:     amd_code_version_major = 1
2409; MOVREL-NEXT:     amd_code_version_minor = 2
2410; MOVREL-NEXT:     amd_machine_kind = 1
2411; MOVREL-NEXT:     amd_machine_version_major = 8
2412; MOVREL-NEXT:     amd_machine_version_minor = 0
2413; MOVREL-NEXT:     amd_machine_version_stepping = 3
2414; MOVREL-NEXT:     kernel_code_entry_byte_offset = 256
2415; MOVREL-NEXT:     kernel_code_prefetch_byte_size = 0
2416; MOVREL-NEXT:     granulated_workitem_vgpr_count = 0
2417; MOVREL-NEXT:     granulated_wavefront_sgpr_count = 0
2418; MOVREL-NEXT:     priority = 0
2419; MOVREL-NEXT:     float_mode = 240
2420; MOVREL-NEXT:     priv = 0
2421; MOVREL-NEXT:     enable_dx10_clamp = 1
2422; MOVREL-NEXT:     debug_mode = 0
2423; MOVREL-NEXT:     enable_ieee_mode = 1
2424; MOVREL-NEXT:     enable_wgp_mode = 0
2425; MOVREL-NEXT:     enable_mem_ordered = 0
2426; MOVREL-NEXT:     enable_fwd_progress = 0
2427; MOVREL-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
2428; MOVREL-NEXT:     user_sgpr_count = 6
2429; MOVREL-NEXT:     enable_trap_handler = 0
2430; MOVREL-NEXT:     enable_sgpr_workgroup_id_x = 1
2431; MOVREL-NEXT:     enable_sgpr_workgroup_id_y = 0
2432; MOVREL-NEXT:     enable_sgpr_workgroup_id_z = 0
2433; MOVREL-NEXT:     enable_sgpr_workgroup_info = 0
2434; MOVREL-NEXT:     enable_vgpr_workitem_id = 0
2435; MOVREL-NEXT:     enable_exception_msb = 0
2436; MOVREL-NEXT:     granulated_lds_size = 0
2437; MOVREL-NEXT:     enable_exception = 0
2438; MOVREL-NEXT:     enable_sgpr_private_segment_buffer = 1
2439; MOVREL-NEXT:     enable_sgpr_dispatch_ptr = 0
2440; MOVREL-NEXT:     enable_sgpr_queue_ptr = 0
2441; MOVREL-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
2442; MOVREL-NEXT:     enable_sgpr_dispatch_id = 0
2443; MOVREL-NEXT:     enable_sgpr_flat_scratch_init = 0
2444; MOVREL-NEXT:     enable_sgpr_private_segment_size = 0
2445; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
2446; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
2447; MOVREL-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
2448; MOVREL-NEXT:     enable_wavefront_size32 = 0
2449; MOVREL-NEXT:     enable_ordered_append_gds = 0
2450; MOVREL-NEXT:     private_element_size = 1
2451; MOVREL-NEXT:     is_ptr64 = 1
2452; MOVREL-NEXT:     is_dynamic_callstack = 0
2453; MOVREL-NEXT:     is_debug_enabled = 0
2454; MOVREL-NEXT:     is_xnack_enabled = 0
2455; MOVREL-NEXT:     workitem_private_segment_byte_size = 0
2456; MOVREL-NEXT:     workgroup_group_segment_byte_size = 0
2457; MOVREL-NEXT:     gds_segment_byte_size = 0
2458; MOVREL-NEXT:     kernarg_segment_byte_size = 28
2459; MOVREL-NEXT:     workgroup_fbarrier_count = 0
2460; MOVREL-NEXT:     wavefront_sgpr_count = 7
2461; MOVREL-NEXT:     workitem_vgpr_count = 4
2462; MOVREL-NEXT:     reserved_vgpr_first = 0
2463; MOVREL-NEXT:     reserved_vgpr_count = 0
2464; MOVREL-NEXT:     reserved_sgpr_first = 0
2465; MOVREL-NEXT:     reserved_sgpr_count = 0
2466; MOVREL-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
2467; MOVREL-NEXT:     debug_private_segment_buffer_sgpr = 0
2468; MOVREL-NEXT:     kernarg_segment_alignment = 4
2469; MOVREL-NEXT:     group_segment_alignment = 4
2470; MOVREL-NEXT:     private_segment_alignment = 4
2471; MOVREL-NEXT:     wavefront_size = 6
2472; MOVREL-NEXT:     call_convention = -1
2473; MOVREL-NEXT:     runtime_loader_kernel_symbol = 0
2474; MOVREL-NEXT:    .end_amd_kernel_code_t
2475; MOVREL-NEXT:  ; %bb.0: ; %entry
2476; MOVREL-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x0
2477; MOVREL-NEXT:    s_load_dword s6, s[4:5], 0x8
2478; MOVREL-NEXT:    s_mov_b32 s0, 0
2479; MOVREL-NEXT:    s_mov_b32 s1, 0x40080000
2480; MOVREL-NEXT:    s_waitcnt lgkmcnt(0)
2481; MOVREL-NEXT:    v_mov_b32_e32 v2, s2
2482; MOVREL-NEXT:    s_cmp_eq_u32 s6, 1
2483; MOVREL-NEXT:    s_cselect_b64 s[4:5], 2.0, 1.0
2484; MOVREL-NEXT:    s_cmp_eq_u32 s6, 2
2485; MOVREL-NEXT:    s_cselect_b64 s[0:1], s[0:1], s[4:5]
2486; MOVREL-NEXT:    s_cmp_eq_u32 s6, 3
2487; MOVREL-NEXT:    s_cselect_b64 s[0:1], 4.0, s[0:1]
2488; MOVREL-NEXT:    v_mov_b32_e32 v0, s0
2489; MOVREL-NEXT:    v_mov_b32_e32 v1, s1
2490; MOVREL-NEXT:    v_mov_b32_e32 v3, s3
2491; MOVREL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
2492; MOVREL-NEXT:    s_endpgm
2493entry:
2494  %ext = extractelement <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, i32 %sel
2495  store double %ext, double addrspace(1)* %out
2496  ret void
2497}
2498