1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3; RUN: opt -S -mtriple=amdgcn-- -amdgpu-atomic-optimizer -verify-machineinstrs %s | FileCheck -check-prefix=IR %s
4; RUN: llc -global-isel -mtriple=amdgcn-- -amdgpu-atomic-optimizations -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
5
6declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
7declare i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
8declare i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)
9declare void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32 immarg)
10
11define amdgpu_cs void @atomic_add(<4 x i32> inreg %arg)  {
12; IR-LABEL: @atomic_add(
13; IR-NEXT:  .entry:
14; IR-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
15; IR-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
16; IR-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
17; IR-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
18; IR-NEXT:    [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
19; IR-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
20; IR-NEXT:    [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
21; IR-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
22; IR-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
23; IR-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
24; IR:       9:
25; IR-NEXT:    [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
26; IR-NEXT:    br label [[TMP11]]
27; IR:       11:
28; IR-NEXT:    ret void
29;
30; GCN-LABEL: atomic_add:
31; GCN:       ; %bb.0: ; %.entry
32; GCN-NEXT:    s_mov_b64 s[4:5], exec
33; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
34; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
35; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
36; GCN-NEXT:    s_and_saveexec_b64 s[6:7], vcc
37; GCN-NEXT:    s_cbranch_execz .LBB0_2
38; GCN-NEXT:  ; %bb.1:
39; GCN-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
40; GCN-NEXT:    v_mov_b32_e32 v0, 0
41; GCN-NEXT:    v_mov_b32_e32 v1, s4
42; GCN-NEXT:    buffer_atomic_add v1, v0, s[0:3], 0 idxen
43; GCN-NEXT:  .LBB0_2:
44; GCN-NEXT:    s_endpgm
45.entry:
46  call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
47  ret void
48}
49
50define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
51; IR-LABEL: @atomic_add_and_format(
52; IR-NEXT:  .entry:
53; IR-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
54; IR-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
55; IR-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
56; IR-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
57; IR-NEXT:    [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
58; IR-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
59; IR-NEXT:    [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
60; IR-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
61; IR-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
62; IR-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
63; IR:       9:
64; IR-NEXT:    [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
65; IR-NEXT:    br label [[TMP11]]
66; IR:       11:
67; IR-NEXT:    [[TMP12:%.*]] = phi i32 [ undef, [[DOTENTRY:%.*]] ], [ [[TMP10]], [[TMP9]] ]
68; IR-NEXT:    [[TMP13:%.*]] = call i32 @llvm.amdgcn.readfirstlane(i32 [[TMP12]])
69; IR-NEXT:    [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP5]]
70; IR-NEXT:    call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> [[ARG]], <4 x i32> [[ARG]], i32 [[TMP14]], i32 0, i32 0, i32 0)
71; IR-NEXT:    ret void
72;
73; GCN-LABEL: atomic_add_and_format:
74; GCN:       ; %bb.0: ; %.entry
75; GCN-NEXT:    s_mov_b64 s[6:7], exec
76; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
77; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s7, v0
78; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
79; GCN-NEXT:    ; implicit-def: $vgpr1
80; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
81; GCN-NEXT:    s_cbranch_execz .LBB1_2
82; GCN-NEXT:  ; %bb.1:
83; GCN-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
84; GCN-NEXT:    v_mov_b32_e32 v1, s6
85; GCN-NEXT:    v_mov_b32_e32 v2, 0
86; GCN-NEXT:    buffer_atomic_add v1, v2, s[0:3], 0 idxen glc
87; GCN-NEXT:  .LBB1_2:
88; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
89; GCN-NEXT:    s_waitcnt vmcnt(0)
90; GCN-NEXT:    v_readfirstlane_b32 s4, v1
91; GCN-NEXT:    v_add_i32_e32 v4, vcc, s4, v0
92; GCN-NEXT:    s_waitcnt expcnt(0)
93; GCN-NEXT:    v_mov_b32_e32 v0, s0
94; GCN-NEXT:    v_mov_b32_e32 v1, s1
95; GCN-NEXT:    v_mov_b32_e32 v2, s2
96; GCN-NEXT:    v_mov_b32_e32 v3, s3
97; GCN-NEXT:    buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
98; GCN-NEXT:    s_endpgm
99.entry:
100  %a = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
101  call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> %arg, <4 x i32> %arg, i32 %a, i32 0, i32 0, i32 0)
102  ret void
103}
104
105define amdgpu_cs void @atomic_sub(<4 x i32> inreg %arg)  {
106; IR-LABEL: @atomic_sub(
107; IR-NEXT:  .entry:
108; IR-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
109; IR-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
110; IR-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
111; IR-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
112; IR-NEXT:    [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
113; IR-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
114; IR-NEXT:    [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
115; IR-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
116; IR-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
117; IR-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
118; IR:       9:
119; IR-NEXT:    [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
120; IR-NEXT:    br label [[TMP11]]
121; IR:       11:
122; IR-NEXT:    ret void
123;
124; GCN-LABEL: atomic_sub:
125; GCN:       ; %bb.0: ; %.entry
126; GCN-NEXT:    s_mov_b64 s[4:5], exec
127; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
128; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
129; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
130; GCN-NEXT:    s_and_saveexec_b64 s[6:7], vcc
131; GCN-NEXT:    s_cbranch_execz .LBB2_2
132; GCN-NEXT:  ; %bb.1:
133; GCN-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
134; GCN-NEXT:    v_mov_b32_e32 v0, 0
135; GCN-NEXT:    v_mov_b32_e32 v1, s4
136; GCN-NEXT:    buffer_atomic_sub v1, v0, s[0:3], 0 idxen
137; GCN-NEXT:  .LBB2_2:
138; GCN-NEXT:    s_endpgm
139.entry:
140  call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
141  ret void
142}
143
144define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
145; IR-LABEL: @atomic_sub_and_format(
146; IR-NEXT:  .entry:
147; IR-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
148; IR-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
149; IR-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
150; IR-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
151; IR-NEXT:    [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
152; IR-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
153; IR-NEXT:    [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
154; IR-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
155; IR-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
156; IR-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
157; IR:       9:
158; IR-NEXT:    [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
159; IR-NEXT:    br label [[TMP11]]
160; IR:       11:
161; IR-NEXT:    [[TMP12:%.*]] = phi i32 [ undef, [[DOTENTRY:%.*]] ], [ [[TMP10]], [[TMP9]] ]
162; IR-NEXT:    [[TMP13:%.*]] = call i32 @llvm.amdgcn.readfirstlane(i32 [[TMP12]])
163; IR-NEXT:    [[TMP14:%.*]] = sub i32 [[TMP13]], [[TMP5]]
164; IR-NEXT:    call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> [[ARG]], <4 x i32> [[ARG]], i32 [[TMP14]], i32 0, i32 0, i32 0)
165; IR-NEXT:    ret void
166;
167; GCN-LABEL: atomic_sub_and_format:
168; GCN:       ; %bb.0: ; %.entry
169; GCN-NEXT:    s_mov_b64 s[6:7], exec
170; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
171; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s7, v0
172; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
173; GCN-NEXT:    ; implicit-def: $vgpr1
174; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
175; GCN-NEXT:    s_cbranch_execz .LBB3_2
176; GCN-NEXT:  ; %bb.1:
177; GCN-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
178; GCN-NEXT:    v_mov_b32_e32 v1, s6
179; GCN-NEXT:    v_mov_b32_e32 v2, 0
180; GCN-NEXT:    buffer_atomic_sub v1, v2, s[0:3], 0 idxen glc
181; GCN-NEXT:  .LBB3_2:
182; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
183; GCN-NEXT:    s_waitcnt vmcnt(0)
184; GCN-NEXT:    v_readfirstlane_b32 s4, v1
185; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s4, v0
186; GCN-NEXT:    s_waitcnt expcnt(0)
187; GCN-NEXT:    v_mov_b32_e32 v0, s0
188; GCN-NEXT:    v_mov_b32_e32 v1, s1
189; GCN-NEXT:    v_mov_b32_e32 v2, s2
190; GCN-NEXT:    v_mov_b32_e32 v3, s3
191; GCN-NEXT:    buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
192; GCN-NEXT:    s_endpgm
193.entry:
194  %a = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
195  call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> %arg, <4 x i32> %arg, i32 %a, i32 0, i32 0, i32 0)
196  ret void
197}
198
199define amdgpu_cs void @atomic_xor(<4 x i32> inreg %arg)  {
200; IR-LABEL: @atomic_xor(
201; IR-NEXT:  .entry:
202; IR-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
203; IR-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
204; IR-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
205; IR-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
206; IR-NEXT:    [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
207; IR-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
208; IR-NEXT:    [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
209; IR-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
210; IR-NEXT:    [[TMP8:%.*]] = and i32 [[TMP7]], 1
211; IR-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
212; IR-NEXT:    br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
213; IR:       10:
214; IR-NEXT:    [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
215; IR-NEXT:    br label [[TMP12]]
216; IR:       12:
217; IR-NEXT:    ret void
218;
219; GCN-LABEL: atomic_xor:
220; GCN:       ; %bb.0: ; %.entry
221; GCN-NEXT:    s_mov_b64 s[4:5], exec
222; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
223; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s5, v0
224; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
225; GCN-NEXT:    s_and_saveexec_b64 s[6:7], vcc
226; GCN-NEXT:    s_cbranch_execz .LBB4_2
227; GCN-NEXT:  ; %bb.1:
228; GCN-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
229; GCN-NEXT:    s_and_b32 s4, s4, 1
230; GCN-NEXT:    v_mov_b32_e32 v0, 0
231; GCN-NEXT:    v_mov_b32_e32 v1, s4
232; GCN-NEXT:    buffer_atomic_xor v1, v0, s[0:3], 0 idxen
233; GCN-NEXT:  .LBB4_2:
234; GCN-NEXT:    s_endpgm
235.entry:
236  call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
237  ret void
238}
239
240define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {
241; IR-LABEL: @atomic_xor_and_format(
242; IR-NEXT:  .entry:
243; IR-NEXT:    [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
244; IR-NEXT:    [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
245; IR-NEXT:    [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
246; IR-NEXT:    [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
247; IR-NEXT:    [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
248; IR-NEXT:    [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
249; IR-NEXT:    [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
250; IR-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
251; IR-NEXT:    [[TMP8:%.*]] = and i32 [[TMP7]], 1
252; IR-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
253; IR-NEXT:    br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
254; IR:       10:
255; IR-NEXT:    [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
256; IR-NEXT:    br label [[TMP12]]
257; IR:       12:
258; IR-NEXT:    [[TMP13:%.*]] = phi i32 [ undef, [[DOTENTRY:%.*]] ], [ [[TMP11]], [[TMP10]] ]
259; IR-NEXT:    [[TMP14:%.*]] = call i32 @llvm.amdgcn.readfirstlane(i32 [[TMP13]])
260; IR-NEXT:    [[TMP15:%.*]] = and i32 [[TMP5]], 1
261; IR-NEXT:    [[TMP16:%.*]] = xor i32 [[TMP14]], [[TMP15]]
262; IR-NEXT:    call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> [[ARG]], <4 x i32> [[ARG]], i32 [[TMP16]], i32 0, i32 0, i32 0)
263; IR-NEXT:    ret void
264;
265; GCN-LABEL: atomic_xor_and_format:
266; GCN:       ; %bb.0: ; %.entry
267; GCN-NEXT:    s_mov_b64 s[6:7], exec
268; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
269; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, s7, v0
270; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
271; GCN-NEXT:    ; implicit-def: $vgpr1
272; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
273; GCN-NEXT:    s_cbranch_execz .LBB5_2
274; GCN-NEXT:  ; %bb.1:
275; GCN-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
276; GCN-NEXT:    s_and_b32 s6, s6, 1
277; GCN-NEXT:    v_mov_b32_e32 v1, s6
278; GCN-NEXT:    v_mov_b32_e32 v2, 0
279; GCN-NEXT:    buffer_atomic_xor v1, v2, s[0:3], 0 idxen glc
280; GCN-NEXT:  .LBB5_2:
281; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
282; GCN-NEXT:    s_waitcnt vmcnt(0)
283; GCN-NEXT:    v_readfirstlane_b32 s4, v1
284; GCN-NEXT:    v_and_b32_e32 v0, 1, v0
285; GCN-NEXT:    v_xor_b32_e32 v4, s4, v0
286; GCN-NEXT:    s_waitcnt expcnt(0)
287; GCN-NEXT:    v_mov_b32_e32 v0, s0
288; GCN-NEXT:    v_mov_b32_e32 v1, s1
289; GCN-NEXT:    v_mov_b32_e32 v2, s2
290; GCN-NEXT:    v_mov_b32_e32 v3, s3
291; GCN-NEXT:    buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
292; GCN-NEXT:    s_endpgm
293.entry:
294  %a = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)
295  call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> %arg, <4 x i32> %arg, i32 %a, i32 0, i32 0, i32 0)
296  ret void
297}
298