1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s 6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s 7 8define i8 @v_ashr_i8(i8 %value, i8 %amount) { 9; GFX6-LABEL: v_ashr_i8: 10; GFX6: ; %bb.0: 11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 12; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 13; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 14; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0 15; GFX6-NEXT: s_setpc_b64 s[30:31] 16; 17; GFX8-LABEL: v_ashr_i8: 18; GFX8: ; %bb.0: 19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 20; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 21; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1 22; GFX8-NEXT: s_setpc_b64 s[30:31] 23; 24; GFX9-LABEL: v_ashr_i8: 25; GFX9: ; %bb.0: 26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 27; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 28; GFX9-NEXT: s_setpc_b64 s[30:31] 29; 30; GFX10PLUS-LABEL: v_ashr_i8: 31; GFX10PLUS: ; %bb.0: 32; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 33; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 34; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xff, v1 35; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 8 36; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v1, v0 37; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 38 %result = ashr i8 %value, %amount 39 ret i8 %result 40} 41 42define i8 @v_ashr_i8_7(i8 %value) { 43; GFX6-LABEL: v_ashr_i8_7: 44; GFX6: ; %bb.0: 45; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 46; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 47; GFX6-NEXT: v_ashrrev_i32_e32 v0, 7, v0 48; GFX6-NEXT: s_setpc_b64 s[30:31] 49; 50; GFX8-LABEL: v_ashr_i8_7: 51; GFX8: ; %bb.0: 52; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 53; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 54; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v0 55; GFX8-NEXT: s_setpc_b64 s[30:31] 56; 57; GFX9-LABEL: v_ashr_i8_7: 58; GFX9: ; %bb.0: 59; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 60; GFX9-NEXT: v_mov_b32_e32 v1, 7 61; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 62; GFX9-NEXT: s_setpc_b64 s[30:31] 63; 64; GFX10PLUS-LABEL: v_ashr_i8_7: 65; GFX10PLUS: ; %bb.0: 66; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 67; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 68; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 8 69; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 7, v0 70; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 71 %result = ashr i8 %value, 7 72 ret i8 %result 73} 74 75define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) { 76; GFX6-LABEL: s_ashr_i8: 77; GFX6: ; %bb.0: 78; GFX6-NEXT: s_sext_i32_i8 s0, s0 79; GFX6-NEXT: s_ashr_i32 s0, s0, s1 80; GFX6-NEXT: ; return to shader part epilog 81; 82; GFX8-LABEL: s_ashr_i8: 83; GFX8: ; %bb.0: 84; GFX8-NEXT: s_sext_i32_i8 s0, s0 85; GFX8-NEXT: s_sext_i32_i8 s1, s1 86; GFX8-NEXT: s_ashr_i32 s0, s0, s1 87; GFX8-NEXT: ; return to shader part epilog 88; 89; GFX9-LABEL: s_ashr_i8: 90; GFX9: ; %bb.0: 91; GFX9-NEXT: s_sext_i32_i8 s0, s0 92; GFX9-NEXT: s_sext_i32_i8 s1, s1 93; GFX9-NEXT: s_ashr_i32 s0, s0, s1 94; GFX9-NEXT: ; return to shader part epilog 95; 96; GFX10PLUS-LABEL: s_ashr_i8: 97; GFX10PLUS: ; %bb.0: 98; GFX10PLUS-NEXT: s_sext_i32_i8 s0, s0 99; GFX10PLUS-NEXT: s_sext_i32_i8 s1, s1 100; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1 101; GFX10PLUS-NEXT: ; return to shader part epilog 102 %result = ashr i8 %value, %amount 103 ret i8 %result 104} 105 106define amdgpu_ps i8 @s_ashr_i8_7(i8 inreg %value) { 107; GCN-LABEL: s_ashr_i8_7: 108; GCN: ; %bb.0: 109; GCN-NEXT: s_sext_i32_i8 s0, s0 110; GCN-NEXT: s_ashr_i32 s0, s0, 7 111; GCN-NEXT: ; return to shader part epilog 112; 113; GFX10PLUS-LABEL: s_ashr_i8_7: 114; GFX10PLUS: ; %bb.0: 115; GFX10PLUS-NEXT: s_sext_i32_i8 s0, s0 116; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 7 117; GFX10PLUS-NEXT: ; return to shader part epilog 118 %result = ashr i8 %value, 7 119 ret i8 %result 120} 121 122 123define i24 @v_ashr_i24(i24 %value, i24 %amount) { 124; GCN-LABEL: v_ashr_i24: 125; GCN: ; %bb.0: 126; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 127; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1 128; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 129; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0 130; GCN-NEXT: s_setpc_b64 s[30:31] 131; 132; GFX10PLUS-LABEL: v_ashr_i24: 133; GFX10PLUS: ; %bb.0: 134; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 135; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 136; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1 137; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 24 138; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v1, v0 139; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 140 %result = ashr i24 %value, %amount 141 ret i24 %result 142} 143 144define i24 @v_ashr_i24_7(i24 %value) { 145; GCN-LABEL: v_ashr_i24_7: 146; GCN: ; %bb.0: 147; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 148; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 149; GCN-NEXT: v_ashrrev_i32_e32 v0, 7, v0 150; GCN-NEXT: s_setpc_b64 s[30:31] 151; 152; GFX10PLUS-LABEL: v_ashr_i24_7: 153; GFX10PLUS: ; %bb.0: 154; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 155; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 156; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 24 157; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 7, v0 158; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 159 %result = ashr i24 %value, 7 160 ret i24 %result 161} 162 163define amdgpu_ps i24 @s_ashr_i24(i24 inreg %value, i24 inreg %amount) { 164; GCN-LABEL: s_ashr_i24: 165; GCN: ; %bb.0: 166; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000 167; GCN-NEXT: s_ashr_i32 s0, s0, s1 168; GCN-NEXT: ; return to shader part epilog 169; 170; GFX10PLUS-LABEL: s_ashr_i24: 171; GFX10PLUS: ; %bb.0: 172; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x180000 173; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1 174; GFX10PLUS-NEXT: ; return to shader part epilog 175 %result = ashr i24 %value, %amount 176 ret i24 %result 177} 178 179define amdgpu_ps i24 @s_ashr_i24_7(i24 inreg %value) { 180; GCN-LABEL: s_ashr_i24_7: 181; GCN: ; %bb.0: 182; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000 183; GCN-NEXT: s_ashr_i32 s0, s0, 7 184; GCN-NEXT: ; return to shader part epilog 185; 186; GFX10PLUS-LABEL: s_ashr_i24_7: 187; GFX10PLUS: ; %bb.0: 188; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x180000 189; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 7 190; GFX10PLUS-NEXT: ; return to shader part epilog 191 %result = ashr i24 %value, 7 192 ret i24 %result 193} 194 195define i32 @v_ashr_i32(i32 %value, i32 %amount) { 196; GCN-LABEL: v_ashr_i32: 197; GCN: ; %bb.0: 198; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 199; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0 200; GCN-NEXT: s_setpc_b64 s[30:31] 201; 202; GFX10PLUS-LABEL: v_ashr_i32: 203; GFX10PLUS: ; %bb.0: 204; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 205; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 206; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v1, v0 207; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 208 %result = ashr i32 %value, %amount 209 ret i32 %result 210} 211 212define i32 @v_ashr_i32_31(i32 %value) { 213; GCN-LABEL: v_ashr_i32_31: 214; GCN: ; %bb.0: 215; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 216; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0 217; GCN-NEXT: s_setpc_b64 s[30:31] 218; 219; GFX10PLUS-LABEL: v_ashr_i32_31: 220; GFX10PLUS: ; %bb.0: 221; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 222; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 223; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v0 224; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 225 %result = ashr i32 %value, 31 226 ret i32 %result 227} 228 229define amdgpu_ps i32 @s_ashr_i32(i32 inreg %value, i32 inreg %amount) { 230; GCN-LABEL: s_ashr_i32: 231; GCN: ; %bb.0: 232; GCN-NEXT: s_ashr_i32 s0, s0, s1 233; GCN-NEXT: ; return to shader part epilog 234; 235; GFX10PLUS-LABEL: s_ashr_i32: 236; GFX10PLUS: ; %bb.0: 237; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1 238; GFX10PLUS-NEXT: ; return to shader part epilog 239 %result = ashr i32 %value, %amount 240 ret i32 %result 241} 242 243define amdgpu_ps i32 @s_ashr_i32_31(i32 inreg %value) { 244; GCN-LABEL: s_ashr_i32_31: 245; GCN: ; %bb.0: 246; GCN-NEXT: s_ashr_i32 s0, s0, 31 247; GCN-NEXT: ; return to shader part epilog 248; 249; GFX10PLUS-LABEL: s_ashr_i32_31: 250; GFX10PLUS: ; %bb.0: 251; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 31 252; GFX10PLUS-NEXT: ; return to shader part epilog 253 %result = ashr i32 %value, 31 254 ret i32 %result 255} 256 257define amdgpu_ps float @ashr_i32_sv(i32 inreg %value, i32 %amount) { 258; GFX6-LABEL: ashr_i32_sv: 259; GFX6: ; %bb.0: 260; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0 261; GFX6-NEXT: ; return to shader part epilog 262; 263; GFX8-LABEL: ashr_i32_sv: 264; GFX8: ; %bb.0: 265; GFX8-NEXT: v_ashrrev_i32_e64 v0, v0, s0 266; GFX8-NEXT: ; return to shader part epilog 267; 268; GFX9-LABEL: ashr_i32_sv: 269; GFX9: ; %bb.0: 270; GFX9-NEXT: v_ashrrev_i32_e64 v0, v0, s0 271; GFX9-NEXT: ; return to shader part epilog 272; 273; GFX10PLUS-LABEL: ashr_i32_sv: 274; GFX10PLUS: ; %bb.0: 275; GFX10PLUS-NEXT: v_ashrrev_i32_e64 v0, v0, s0 276; GFX10PLUS-NEXT: ; return to shader part epilog 277 %result = ashr i32 %value, %amount 278 %cast = bitcast i32 %result to float 279 ret float %cast 280} 281 282define amdgpu_ps float @ashr_i32_vs(i32 %value, i32 inreg %amount) { 283; GCN-LABEL: ashr_i32_vs: 284; GCN: ; %bb.0: 285; GCN-NEXT: v_ashrrev_i32_e32 v0, s0, v0 286; GCN-NEXT: ; return to shader part epilog 287; 288; GFX10PLUS-LABEL: ashr_i32_vs: 289; GFX10PLUS: ; %bb.0: 290; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, s0, v0 291; GFX10PLUS-NEXT: ; return to shader part epilog 292 %result = ashr i32 %value, %amount 293 %cast = bitcast i32 %result to float 294 ret float %cast 295} 296 297define <2 x i32> @v_ashr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 298; GCN-LABEL: v_ashr_v2i32: 299; GCN: ; %bb.0: 300; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 301; GCN-NEXT: v_ashrrev_i32_e32 v0, v2, v0 302; GCN-NEXT: v_ashrrev_i32_e32 v1, v3, v1 303; GCN-NEXT: s_setpc_b64 s[30:31] 304; 305; GFX10PLUS-LABEL: v_ashr_v2i32: 306; GFX10PLUS: ; %bb.0: 307; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 308; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 309; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v2, v0 310; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v3, v1 311; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 312 %result = ashr <2 x i32> %value, %amount 313 ret <2 x i32> %result 314} 315 316define <2 x i32> @v_ashr_v2i32_31(<2 x i32> %value) { 317; GCN-LABEL: v_ashr_v2i32_31: 318; GCN: ; %bb.0: 319; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 320; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0 321; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v1 322; GCN-NEXT: s_setpc_b64 s[30:31] 323; 324; GFX10PLUS-LABEL: v_ashr_v2i32_31: 325; GFX10PLUS: ; %bb.0: 326; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 327; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 328; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v0 329; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v1 330; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 331 %result = ashr <2 x i32> %value, <i32 31, i32 31> 332 ret <2 x i32> %result 333} 334 335define amdgpu_ps <2 x i32> @s_ashr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 336; GCN-LABEL: s_ashr_v2i32: 337; GCN: ; %bb.0: 338; GCN-NEXT: s_ashr_i32 s0, s0, s2 339; GCN-NEXT: s_ashr_i32 s1, s1, s3 340; GCN-NEXT: ; return to shader part epilog 341; 342; GFX10PLUS-LABEL: s_ashr_v2i32: 343; GFX10PLUS: ; %bb.0: 344; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s2 345; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s3 346; GFX10PLUS-NEXT: ; return to shader part epilog 347 %result = ashr <2 x i32> %value, %amount 348 ret <2 x i32> %result 349} 350 351define <3 x i32> @v_ashr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 352; GCN-LABEL: v_ashr_v3i32: 353; GCN: ; %bb.0: 354; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 355; GCN-NEXT: v_ashrrev_i32_e32 v0, v3, v0 356; GCN-NEXT: v_ashrrev_i32_e32 v1, v4, v1 357; GCN-NEXT: v_ashrrev_i32_e32 v2, v5, v2 358; GCN-NEXT: s_setpc_b64 s[30:31] 359; 360; GFX10PLUS-LABEL: v_ashr_v3i32: 361; GFX10PLUS: ; %bb.0: 362; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 363; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 364; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v3, v0 365; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v4, v1 366; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, v5, v2 367; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 368 %result = ashr <3 x i32> %value, %amount 369 ret <3 x i32> %result 370} 371 372define amdgpu_ps <3 x i32> @s_ashr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 373; GCN-LABEL: s_ashr_v3i32: 374; GCN: ; %bb.0: 375; GCN-NEXT: s_ashr_i32 s0, s0, s3 376; GCN-NEXT: s_ashr_i32 s1, s1, s4 377; GCN-NEXT: s_ashr_i32 s2, s2, s5 378; GCN-NEXT: ; return to shader part epilog 379; 380; GFX10PLUS-LABEL: s_ashr_v3i32: 381; GFX10PLUS: ; %bb.0: 382; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s3 383; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s4 384; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s5 385; GFX10PLUS-NEXT: ; return to shader part epilog 386 %result = ashr <3 x i32> %value, %amount 387 ret <3 x i32> %result 388} 389 390define <4 x i32> @v_ashr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 391; GCN-LABEL: v_ashr_v4i32: 392; GCN: ; %bb.0: 393; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 394; GCN-NEXT: v_ashrrev_i32_e32 v0, v4, v0 395; GCN-NEXT: v_ashrrev_i32_e32 v1, v5, v1 396; GCN-NEXT: v_ashrrev_i32_e32 v2, v6, v2 397; GCN-NEXT: v_ashrrev_i32_e32 v3, v7, v3 398; GCN-NEXT: s_setpc_b64 s[30:31] 399; 400; GFX10PLUS-LABEL: v_ashr_v4i32: 401; GFX10PLUS: ; %bb.0: 402; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 403; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 404; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v4, v0 405; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v5, v1 406; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, v6, v2 407; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, v7, v3 408; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 409 %result = ashr <4 x i32> %value, %amount 410 ret <4 x i32> %result 411} 412 413define amdgpu_ps <4 x i32> @s_ashr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 414; GCN-LABEL: s_ashr_v4i32: 415; GCN: ; %bb.0: 416; GCN-NEXT: s_ashr_i32 s0, s0, s4 417; GCN-NEXT: s_ashr_i32 s1, s1, s5 418; GCN-NEXT: s_ashr_i32 s2, s2, s6 419; GCN-NEXT: s_ashr_i32 s3, s3, s7 420; GCN-NEXT: ; return to shader part epilog 421; 422; GFX10PLUS-LABEL: s_ashr_v4i32: 423; GFX10PLUS: ; %bb.0: 424; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4 425; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5 426; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s6 427; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s7 428; GFX10PLUS-NEXT: ; return to shader part epilog 429 %result = ashr <4 x i32> %value, %amount 430 ret <4 x i32> %result 431} 432 433define <5 x i32> @v_ashr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 434; GCN-LABEL: v_ashr_v5i32: 435; GCN: ; %bb.0: 436; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 437; GCN-NEXT: v_ashrrev_i32_e32 v0, v5, v0 438; GCN-NEXT: v_ashrrev_i32_e32 v1, v6, v1 439; GCN-NEXT: v_ashrrev_i32_e32 v2, v7, v2 440; GCN-NEXT: v_ashrrev_i32_e32 v3, v8, v3 441; GCN-NEXT: v_ashrrev_i32_e32 v4, v9, v4 442; GCN-NEXT: s_setpc_b64 s[30:31] 443; 444; GFX10PLUS-LABEL: v_ashr_v5i32: 445; GFX10PLUS: ; %bb.0: 446; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 447; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 448; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v5, v0 449; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v6, v1 450; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, v7, v2 451; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, v8, v3 452; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v4, v9, v4 453; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 454 %result = ashr <5 x i32> %value, %amount 455 ret <5 x i32> %result 456} 457 458define amdgpu_ps <5 x i32> @s_ashr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 459; GCN-LABEL: s_ashr_v5i32: 460; GCN: ; %bb.0: 461; GCN-NEXT: s_ashr_i32 s0, s0, s5 462; GCN-NEXT: s_ashr_i32 s1, s1, s6 463; GCN-NEXT: s_ashr_i32 s2, s2, s7 464; GCN-NEXT: s_ashr_i32 s3, s3, s8 465; GCN-NEXT: s_ashr_i32 s4, s4, s9 466; GCN-NEXT: ; return to shader part epilog 467; 468; GFX10PLUS-LABEL: s_ashr_v5i32: 469; GFX10PLUS: ; %bb.0: 470; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s5 471; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s6 472; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s7 473; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s8 474; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s9 475; GFX10PLUS-NEXT: ; return to shader part epilog 476 %result = ashr <5 x i32> %value, %amount 477 ret <5 x i32> %result 478} 479 480define <16 x i32> @v_ashr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 481; GCN-LABEL: v_ashr_v16i32: 482; GCN: ; %bb.0: 483; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 484; GCN-NEXT: v_ashrrev_i32_e32 v0, v16, v0 485; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32 486; GCN-NEXT: v_ashrrev_i32_e32 v1, v17, v1 487; GCN-NEXT: v_ashrrev_i32_e32 v2, v18, v2 488; GCN-NEXT: v_ashrrev_i32_e32 v3, v19, v3 489; GCN-NEXT: v_ashrrev_i32_e32 v4, v20, v4 490; GCN-NEXT: v_ashrrev_i32_e32 v5, v21, v5 491; GCN-NEXT: v_ashrrev_i32_e32 v6, v22, v6 492; GCN-NEXT: v_ashrrev_i32_e32 v7, v23, v7 493; GCN-NEXT: v_ashrrev_i32_e32 v8, v24, v8 494; GCN-NEXT: v_ashrrev_i32_e32 v9, v25, v9 495; GCN-NEXT: v_ashrrev_i32_e32 v10, v26, v10 496; GCN-NEXT: v_ashrrev_i32_e32 v11, v27, v11 497; GCN-NEXT: v_ashrrev_i32_e32 v12, v28, v12 498; GCN-NEXT: v_ashrrev_i32_e32 v13, v29, v13 499; GCN-NEXT: v_ashrrev_i32_e32 v14, v30, v14 500; GCN-NEXT: s_waitcnt vmcnt(0) 501; GCN-NEXT: v_ashrrev_i32_e32 v15, v16, v15 502; GCN-NEXT: s_setpc_b64 s[30:31] 503; 504; GFX10-LABEL: v_ashr_v16i32: 505; GFX10: ; %bb.0: 506; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 507; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 508; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 509; GFX10-NEXT: v_ashrrev_i32_e32 v0, v16, v0 510; GFX10-NEXT: v_ashrrev_i32_e32 v1, v17, v1 511; GFX10-NEXT: v_ashrrev_i32_e32 v2, v18, v2 512; GFX10-NEXT: v_ashrrev_i32_e32 v3, v19, v3 513; GFX10-NEXT: v_ashrrev_i32_e32 v4, v20, v4 514; GFX10-NEXT: v_ashrrev_i32_e32 v5, v21, v5 515; GFX10-NEXT: v_ashrrev_i32_e32 v6, v22, v6 516; GFX10-NEXT: v_ashrrev_i32_e32 v7, v23, v7 517; GFX10-NEXT: v_ashrrev_i32_e32 v8, v24, v8 518; GFX10-NEXT: v_ashrrev_i32_e32 v9, v25, v9 519; GFX10-NEXT: v_ashrrev_i32_e32 v10, v26, v10 520; GFX10-NEXT: v_ashrrev_i32_e32 v11, v27, v11 521; GFX10-NEXT: v_ashrrev_i32_e32 v12, v28, v12 522; GFX10-NEXT: v_ashrrev_i32_e32 v13, v29, v13 523; GFX10-NEXT: v_ashrrev_i32_e32 v14, v30, v14 524; GFX10-NEXT: s_waitcnt vmcnt(0) 525; GFX10-NEXT: v_ashrrev_i32_e32 v15, v31, v15 526; GFX10-NEXT: s_setpc_b64 s[30:31] 527; 528; GFX11-LABEL: v_ashr_v16i32: 529; GFX11: ; %bb.0: 530; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 531; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 532; GFX11-NEXT: scratch_load_b32 v31, off, s32 533; GFX11-NEXT: v_ashrrev_i32_e32 v0, v16, v0 534; GFX11-NEXT: v_ashrrev_i32_e32 v1, v17, v1 535; GFX11-NEXT: v_ashrrev_i32_e32 v2, v18, v2 536; GFX11-NEXT: v_ashrrev_i32_e32 v3, v19, v3 537; GFX11-NEXT: v_ashrrev_i32_e32 v4, v20, v4 538; GFX11-NEXT: v_ashrrev_i32_e32 v5, v21, v5 539; GFX11-NEXT: v_ashrrev_i32_e32 v6, v22, v6 540; GFX11-NEXT: v_ashrrev_i32_e32 v7, v23, v7 541; GFX11-NEXT: v_ashrrev_i32_e32 v8, v24, v8 542; GFX11-NEXT: v_ashrrev_i32_e32 v9, v25, v9 543; GFX11-NEXT: v_ashrrev_i32_e32 v10, v26, v10 544; GFX11-NEXT: v_ashrrev_i32_e32 v11, v27, v11 545; GFX11-NEXT: v_ashrrev_i32_e32 v12, v28, v12 546; GFX11-NEXT: v_ashrrev_i32_e32 v13, v29, v13 547; GFX11-NEXT: v_ashrrev_i32_e32 v14, v30, v14 548; GFX11-NEXT: s_waitcnt vmcnt(0) 549; GFX11-NEXT: v_ashrrev_i32_e32 v15, v31, v15 550; GFX11-NEXT: s_setpc_b64 s[30:31] 551 %result = ashr <16 x i32> %value, %amount 552 ret <16 x i32> %result 553} 554 555define amdgpu_ps <16 x i32> @s_ashr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 556; GCN-LABEL: s_ashr_v16i32: 557; GCN: ; %bb.0: 558; GCN-NEXT: s_ashr_i32 s0, s0, s16 559; GCN-NEXT: s_ashr_i32 s1, s1, s17 560; GCN-NEXT: s_ashr_i32 s2, s2, s18 561; GCN-NEXT: s_ashr_i32 s3, s3, s19 562; GCN-NEXT: s_ashr_i32 s4, s4, s20 563; GCN-NEXT: s_ashr_i32 s5, s5, s21 564; GCN-NEXT: s_ashr_i32 s6, s6, s22 565; GCN-NEXT: s_ashr_i32 s7, s7, s23 566; GCN-NEXT: s_ashr_i32 s8, s8, s24 567; GCN-NEXT: s_ashr_i32 s9, s9, s25 568; GCN-NEXT: s_ashr_i32 s10, s10, s26 569; GCN-NEXT: s_ashr_i32 s11, s11, s27 570; GCN-NEXT: s_ashr_i32 s12, s12, s28 571; GCN-NEXT: s_ashr_i32 s13, s13, s29 572; GCN-NEXT: s_ashr_i32 s14, s14, s30 573; GCN-NEXT: s_ashr_i32 s15, s15, s31 574; GCN-NEXT: ; return to shader part epilog 575; 576; GFX10PLUS-LABEL: s_ashr_v16i32: 577; GFX10PLUS: ; %bb.0: 578; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s16 579; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s17 580; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s18 581; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s19 582; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s20 583; GFX10PLUS-NEXT: s_ashr_i32 s5, s5, s21 584; GFX10PLUS-NEXT: s_ashr_i32 s6, s6, s22 585; GFX10PLUS-NEXT: s_ashr_i32 s7, s7, s23 586; GFX10PLUS-NEXT: s_ashr_i32 s8, s8, s24 587; GFX10PLUS-NEXT: s_ashr_i32 s9, s9, s25 588; GFX10PLUS-NEXT: s_ashr_i32 s10, s10, s26 589; GFX10PLUS-NEXT: s_ashr_i32 s11, s11, s27 590; GFX10PLUS-NEXT: s_ashr_i32 s12, s12, s28 591; GFX10PLUS-NEXT: s_ashr_i32 s13, s13, s29 592; GFX10PLUS-NEXT: s_ashr_i32 s14, s14, s30 593; GFX10PLUS-NEXT: s_ashr_i32 s15, s15, s31 594; GFX10PLUS-NEXT: ; return to shader part epilog 595 %result = ashr <16 x i32> %value, %amount 596 ret <16 x i32> %result 597} 598 599define i16 @v_ashr_i16(i16 %value, i16 %amount) { 600; GFX6-LABEL: v_ashr_i16: 601; GFX6: ; %bb.0: 602; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 603; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 604; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 605; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0 606; GFX6-NEXT: s_setpc_b64 s[30:31] 607; 608; GFX8-LABEL: v_ashr_i16: 609; GFX8: ; %bb.0: 610; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 611; GFX8-NEXT: v_ashrrev_i16_e32 v0, v1, v0 612; GFX8-NEXT: s_setpc_b64 s[30:31] 613; 614; GFX9-LABEL: v_ashr_i16: 615; GFX9: ; %bb.0: 616; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 617; GFX9-NEXT: v_ashrrev_i16_e32 v0, v1, v0 618; GFX9-NEXT: s_setpc_b64 s[30:31] 619; 620; GFX10PLUS-LABEL: v_ashr_i16: 621; GFX10PLUS: ; %bb.0: 622; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 623; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 624; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v1, v0 625; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 626 %result = ashr i16 %value, %amount 627 ret i16 %result 628} 629 630define i16 @v_ashr_i16_31(i16 %value) { 631; GCN-LABEL: v_ashr_i16_31: 632; GCN: ; %bb.0: 633; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 634; GCN-NEXT: s_setpc_b64 s[30:31] 635; 636; GFX10PLUS-LABEL: v_ashr_i16_31: 637; GFX10PLUS: ; %bb.0: 638; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 639; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 640; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 641 %result = ashr i16 %value, 31 642 ret i16 %result 643} 644 645define amdgpu_ps i16 @s_ashr_i16(i16 inreg %value, i16 inreg %amount) { 646; GFX6-LABEL: s_ashr_i16: 647; GFX6: ; %bb.0: 648; GFX6-NEXT: s_sext_i32_i16 s0, s0 649; GFX6-NEXT: s_ashr_i32 s0, s0, s1 650; GFX6-NEXT: ; return to shader part epilog 651; 652; GFX8-LABEL: s_ashr_i16: 653; GFX8: ; %bb.0: 654; GFX8-NEXT: s_sext_i32_i16 s0, s0 655; GFX8-NEXT: s_sext_i32_i16 s1, s1 656; GFX8-NEXT: s_ashr_i32 s0, s0, s1 657; GFX8-NEXT: ; return to shader part epilog 658; 659; GFX9-LABEL: s_ashr_i16: 660; GFX9: ; %bb.0: 661; GFX9-NEXT: s_sext_i32_i16 s0, s0 662; GFX9-NEXT: s_sext_i32_i16 s1, s1 663; GFX9-NEXT: s_ashr_i32 s0, s0, s1 664; GFX9-NEXT: ; return to shader part epilog 665; 666; GFX10PLUS-LABEL: s_ashr_i16: 667; GFX10PLUS: ; %bb.0: 668; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0 669; GFX10PLUS-NEXT: s_sext_i32_i16 s1, s1 670; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1 671; GFX10PLUS-NEXT: ; return to shader part epilog 672 %result = ashr i16 %value, %amount 673 ret i16 %result 674} 675 676define amdgpu_ps i16 @s_ashr_i16_15(i16 inreg %value) { 677; GCN-LABEL: s_ashr_i16_15: 678; GCN: ; %bb.0: 679; GCN-NEXT: s_sext_i32_i16 s0, s0 680; GCN-NEXT: s_ashr_i32 s0, s0, 15 681; GCN-NEXT: ; return to shader part epilog 682; 683; GFX10PLUS-LABEL: s_ashr_i16_15: 684; GFX10PLUS: ; %bb.0: 685; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0 686; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 15 687; GFX10PLUS-NEXT: ; return to shader part epilog 688 %result = ashr i16 %value, 15 689 ret i16 %result 690} 691 692define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) { 693; GFX6-LABEL: ashr_i16_sv: 694; GFX6: ; %bb.0: 695; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 696; GFX6-NEXT: s_sext_i32_i16 s0, s0 697; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0 698; GFX6-NEXT: ; return to shader part epilog 699; 700; GFX8-LABEL: ashr_i16_sv: 701; GFX8: ; %bb.0: 702; GFX8-NEXT: v_ashrrev_i16_e64 v0, v0, s0 703; GFX8-NEXT: ; return to shader part epilog 704; 705; GFX9-LABEL: ashr_i16_sv: 706; GFX9: ; %bb.0: 707; GFX9-NEXT: v_ashrrev_i16_e64 v0, v0, s0 708; GFX9-NEXT: ; return to shader part epilog 709; 710; GFX10PLUS-LABEL: ashr_i16_sv: 711; GFX10PLUS: ; %bb.0: 712; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v0, s0 713; GFX10PLUS-NEXT: ; return to shader part epilog 714 %result = ashr i16 %value, %amount 715 %cast = bitcast i16 %result to half 716 ret half %cast 717} 718 719define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) { 720; GFX6-LABEL: ashr_i16_vs: 721; GFX6: ; %bb.0: 722; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 723; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 724; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0 725; GFX6-NEXT: ; return to shader part epilog 726; 727; GFX8-LABEL: ashr_i16_vs: 728; GFX8: ; %bb.0: 729; GFX8-NEXT: v_ashrrev_i16_e32 v0, s0, v0 730; GFX8-NEXT: ; return to shader part epilog 731; 732; GFX9-LABEL: ashr_i16_vs: 733; GFX9: ; %bb.0: 734; GFX9-NEXT: v_ashrrev_i16_e32 v0, s0, v0 735; GFX9-NEXT: ; return to shader part epilog 736; 737; GFX10PLUS-LABEL: ashr_i16_vs: 738; GFX10PLUS: ; %bb.0: 739; GFX10PLUS-NEXT: v_ashrrev_i16 v0, s0, v0 740; GFX10PLUS-NEXT: ; return to shader part epilog 741 %result = ashr i16 %value, %amount 742 %cast = bitcast i16 %result to half 743 ret half %cast 744} 745 746define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 747; GFX6-LABEL: v_ashr_v2i16: 748; GFX6: ; %bb.0: 749; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 750; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 751; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 752; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0 753; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3 754; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 755; GFX6-NEXT: v_ashrrev_i32_e32 v1, v2, v1 756; GFX6-NEXT: s_setpc_b64 s[30:31] 757; 758; GFX8-LABEL: v_ashr_v2i16: 759; GFX8: ; %bb.0: 760; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 761; GFX8-NEXT: v_ashrrev_i16_e32 v2, v1, v0 762; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 763; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 764; GFX8-NEXT: s_setpc_b64 s[30:31] 765; 766; GFX9-LABEL: v_ashr_v2i16: 767; GFX9: ; %bb.0: 768; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 769; GFX9-NEXT: v_pk_ashrrev_i16 v0, v1, v0 770; GFX9-NEXT: s_setpc_b64 s[30:31] 771; 772; GFX10PLUS-LABEL: v_ashr_v2i16: 773; GFX10PLUS: ; %bb.0: 774; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 775; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 776; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v1, v0 777; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 778 %result = ashr <2 x i16> %value, %amount 779 ret <2 x i16> %result 780} 781 782define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) { 783; GFX6-LABEL: v_ashr_v2i16_15: 784; GFX6: ; %bb.0: 785; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 786; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 787; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 788; GFX6-NEXT: v_ashrrev_i32_e32 v0, 15, v0 789; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v1 790; GFX6-NEXT: s_setpc_b64 s[30:31] 791; 792; GFX8-LABEL: v_ashr_v2i16_15: 793; GFX8: ; %bb.0: 794; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 795; GFX8-NEXT: v_mov_b32_e32 v2, 15 796; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v0 797; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 798; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 799; GFX8-NEXT: s_setpc_b64 s[30:31] 800; 801; GFX9-LABEL: v_ashr_v2i16_15: 802; GFX9: ; %bb.0: 803; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 804; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1] 805; GFX9-NEXT: s_setpc_b64 s[30:31] 806; 807; GFX10PLUS-LABEL: v_ashr_v2i16_15: 808; GFX10PLUS: ; %bb.0: 809; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 810; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 811; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1] 812; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 813 %result = ashr <2 x i16> %value, <i16 15, i16 15> 814 ret <2 x i16> %result 815} 816 817define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 818; GFX6-LABEL: s_ashr_v2i16: 819; GFX6: ; %bb.0: 820; GFX6-NEXT: s_sext_i32_i16 s1, s1 821; GFX6-NEXT: s_sext_i32_i16 s0, s0 822; GFX6-NEXT: s_ashr_i32 s1, s1, s3 823; GFX6-NEXT: s_ashr_i32 s0, s0, s2 824; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 825; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 826; GFX6-NEXT: s_lshl_b32 s1, s1, 16 827; GFX6-NEXT: s_or_b32 s0, s0, s1 828; GFX6-NEXT: ; return to shader part epilog 829; 830; GFX8-LABEL: s_ashr_v2i16: 831; GFX8: ; %bb.0: 832; GFX8-NEXT: s_sext_i32_i16 s2, s0 833; GFX8-NEXT: s_bfe_i32 s0, s0, 0x100010 834; GFX8-NEXT: s_sext_i32_i16 s3, s1 835; GFX8-NEXT: s_bfe_i32 s1, s1, 0x100010 836; GFX8-NEXT: s_ashr_i32 s2, s2, s3 837; GFX8-NEXT: s_ashr_i32 s0, s0, s1 838; GFX8-NEXT: s_lshl_b32 s0, s0, 16 839; GFX8-NEXT: s_and_b32 s1, s2, 0xffff 840; GFX8-NEXT: s_or_b32 s0, s0, s1 841; GFX8-NEXT: ; return to shader part epilog 842; 843; GFX9-LABEL: s_ashr_v2i16: 844; GFX9: ; %bb.0: 845; GFX9-NEXT: s_sext_i32_i16 s2, s0 846; GFX9-NEXT: s_ashr_i32 s0, s0, 16 847; GFX9-NEXT: s_sext_i32_i16 s3, s1 848; GFX9-NEXT: s_ashr_i32 s1, s1, 16 849; GFX9-NEXT: s_ashr_i32 s2, s2, s3 850; GFX9-NEXT: s_ashr_i32 s0, s0, s1 851; GFX9-NEXT: s_pack_ll_b32_b16 s0, s2, s0 852; GFX9-NEXT: ; return to shader part epilog 853; 854; GFX10PLUS-LABEL: s_ashr_v2i16: 855; GFX10PLUS: ; %bb.0: 856; GFX10PLUS-NEXT: s_sext_i32_i16 s2, s0 857; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 16 858; GFX10PLUS-NEXT: s_sext_i32_i16 s3, s1 859; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 16 860; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s3 861; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1 862; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s2, s0 863; GFX10PLUS-NEXT: ; return to shader part epilog 864 %result = ashr <2 x i16> %value, %amount 865 %cast = bitcast <2 x i16> %result to i32 866 ret i32 %cast 867} 868 869define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 870; GFX6-LABEL: ashr_v2i16_sv: 871; GFX6: ; %bb.0: 872; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 873; GFX6-NEXT: s_sext_i32_i16 s0, s0 874; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0 875; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 876; GFX6-NEXT: s_sext_i32_i16 s0, s1 877; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1 878; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 879; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 880; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 881; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 882; GFX6-NEXT: ; return to shader part epilog 883; 884; GFX8-LABEL: ashr_v2i16_sv: 885; GFX8: ; %bb.0: 886; GFX8-NEXT: s_lshr_b32 s1, s0, 16 887; GFX8-NEXT: v_mov_b32_e32 v2, s1 888; GFX8-NEXT: v_ashrrev_i16_e64 v1, v0, s0 889; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 890; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 891; GFX8-NEXT: ; return to shader part epilog 892; 893; GFX9-LABEL: ashr_v2i16_sv: 894; GFX9: ; %bb.0: 895; GFX9-NEXT: v_pk_ashrrev_i16 v0, v0, s0 896; GFX9-NEXT: ; return to shader part epilog 897; 898; GFX10PLUS-LABEL: ashr_v2i16_sv: 899; GFX10PLUS: ; %bb.0: 900; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v0, s0 901; GFX10PLUS-NEXT: ; return to shader part epilog 902 %result = ashr <2 x i16> %value, %amount 903 %cast = bitcast <2 x i16> %result to float 904 ret float %cast 905} 906 907define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 908; GFX6-LABEL: ashr_v2i16_vs: 909; GFX6: ; %bb.0: 910; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 911; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 912; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0 913; GFX6-NEXT: s_and_b32 s0, s1, 0xffff 914; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 915; GFX6-NEXT: v_ashrrev_i32_e32 v1, s0, v1 916; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 917; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 918; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 919; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 920; GFX6-NEXT: ; return to shader part epilog 921; 922; GFX8-LABEL: ashr_v2i16_vs: 923; GFX8: ; %bb.0: 924; GFX8-NEXT: s_lshr_b32 s1, s0, 16 925; GFX8-NEXT: v_mov_b32_e32 v2, s1 926; GFX8-NEXT: v_ashrrev_i16_e32 v1, s0, v0 927; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 928; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 929; GFX8-NEXT: ; return to shader part epilog 930; 931; GFX9-LABEL: ashr_v2i16_vs: 932; GFX9: ; %bb.0: 933; GFX9-NEXT: v_pk_ashrrev_i16 v0, s0, v0 934; GFX9-NEXT: ; return to shader part epilog 935; 936; GFX10PLUS-LABEL: ashr_v2i16_vs: 937; GFX10PLUS: ; %bb.0: 938; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, s0, v0 939; GFX10PLUS-NEXT: ; return to shader part epilog 940 %result = ashr <2 x i16> %value, %amount 941 %cast = bitcast <2 x i16> %result to float 942 ret float %cast 943} 944 945; FIXME 946; define <3 x i16> @v_ashr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 947; %result = ashr <3 x i16> %value, %amount 948; ret <3 x i16> %result 949; } 950 951; define amdgpu_ps <3 x i16> @s_ashr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 952; %result = ashr <3 x i16> %value, %amount 953; ret <3 x i16> %result 954; } 955 956define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 957; GFX6-LABEL: v_ashr_v4i16: 958; GFX6: ; %bb.0: 959; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 960; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 961; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 962; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0 963; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5 964; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 965; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v1 966; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6 967; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 968; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v2 969; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7 970; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 971; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 972; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v3 973; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 974; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 975; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 976; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2 977; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3 978; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 979; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 980; GFX6-NEXT: s_setpc_b64 s[30:31] 981; 982; GFX8-LABEL: v_ashr_v4i16: 983; GFX8: ; %bb.0: 984; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 985; GFX8-NEXT: v_ashrrev_i16_e32 v4, v2, v0 986; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 987; GFX8-NEXT: v_ashrrev_i16_e32 v2, v3, v1 988; GFX8-NEXT: v_ashrrev_i16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 989; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 990; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 991; GFX8-NEXT: s_setpc_b64 s[30:31] 992; 993; GFX9-LABEL: v_ashr_v4i16: 994; GFX9: ; %bb.0: 995; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 996; GFX9-NEXT: v_pk_ashrrev_i16 v0, v2, v0 997; GFX9-NEXT: v_pk_ashrrev_i16 v1, v3, v1 998; GFX9-NEXT: s_setpc_b64 s[30:31] 999; 1000; GFX10PLUS-LABEL: v_ashr_v4i16: 1001; GFX10PLUS: ; %bb.0: 1002; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1003; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1004; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v2, v0 1005; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, v3, v1 1006; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1007 %result = ashr <4 x i16> %value, %amount 1008 %cast = bitcast <4 x i16> %result to <2 x float> 1009 ret <2 x float> %cast 1010} 1011 1012define amdgpu_ps <2 x i32> @s_ashr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 1013; GFX6-LABEL: s_ashr_v4i16: 1014; GFX6: ; %bb.0: 1015; GFX6-NEXT: s_sext_i32_i16 s1, s1 1016; GFX6-NEXT: s_sext_i32_i16 s0, s0 1017; GFX6-NEXT: s_ashr_i32 s1, s1, s5 1018; GFX6-NEXT: s_ashr_i32 s0, s0, s4 1019; GFX6-NEXT: s_sext_i32_i16 s2, s2 1020; GFX6-NEXT: s_sext_i32_i16 s3, s3 1021; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 1022; GFX6-NEXT: s_ashr_i32 s2, s2, s6 1023; GFX6-NEXT: s_ashr_i32 s3, s3, s7 1024; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 1025; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1026; GFX6-NEXT: s_or_b32 s0, s0, s1 1027; GFX6-NEXT: s_and_b32 s1, s2, 0xffff 1028; GFX6-NEXT: s_and_b32 s2, s3, 0xffff 1029; GFX6-NEXT: s_lshl_b32 s2, s2, 16 1030; GFX6-NEXT: s_or_b32 s1, s1, s2 1031; GFX6-NEXT: ; return to shader part epilog 1032; 1033; GFX8-LABEL: s_ashr_v4i16: 1034; GFX8: ; %bb.0: 1035; GFX8-NEXT: s_sext_i32_i16 s4, s0 1036; GFX8-NEXT: s_bfe_i32 s0, s0, 0x100010 1037; GFX8-NEXT: s_sext_i32_i16 s5, s1 1038; GFX8-NEXT: s_bfe_i32 s1, s1, 0x100010 1039; GFX8-NEXT: s_sext_i32_i16 s6, s2 1040; GFX8-NEXT: s_bfe_i32 s2, s2, 0x100010 1041; GFX8-NEXT: s_sext_i32_i16 s7, s3 1042; GFX8-NEXT: s_bfe_i32 s3, s3, 0x100010 1043; GFX8-NEXT: s_ashr_i32 s4, s4, s6 1044; GFX8-NEXT: s_ashr_i32 s0, s0, s2 1045; GFX8-NEXT: s_ashr_i32 s2, s5, s7 1046; GFX8-NEXT: s_ashr_i32 s1, s1, s3 1047; GFX8-NEXT: s_lshl_b32 s0, s0, 16 1048; GFX8-NEXT: s_and_b32 s3, s4, 0xffff 1049; GFX8-NEXT: s_lshl_b32 s1, s1, 16 1050; GFX8-NEXT: s_and_b32 s2, s2, 0xffff 1051; GFX8-NEXT: s_or_b32 s0, s0, s3 1052; GFX8-NEXT: s_or_b32 s1, s1, s2 1053; GFX8-NEXT: ; return to shader part epilog 1054; 1055; GFX9-LABEL: s_ashr_v4i16: 1056; GFX9: ; %bb.0: 1057; GFX9-NEXT: s_sext_i32_i16 s4, s0 1058; GFX9-NEXT: s_ashr_i32 s0, s0, 16 1059; GFX9-NEXT: s_sext_i32_i16 s5, s2 1060; GFX9-NEXT: s_ashr_i32 s2, s2, 16 1061; GFX9-NEXT: s_ashr_i32 s4, s4, s5 1062; GFX9-NEXT: s_ashr_i32 s0, s0, s2 1063; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s0 1064; GFX9-NEXT: s_sext_i32_i16 s2, s1 1065; GFX9-NEXT: s_ashr_i32 s1, s1, 16 1066; GFX9-NEXT: s_sext_i32_i16 s4, s3 1067; GFX9-NEXT: s_ashr_i32 s3, s3, 16 1068; GFX9-NEXT: s_ashr_i32 s2, s2, s4 1069; GFX9-NEXT: s_ashr_i32 s1, s1, s3 1070; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1 1071; GFX9-NEXT: ; return to shader part epilog 1072; 1073; GFX10PLUS-LABEL: s_ashr_v4i16: 1074; GFX10PLUS: ; %bb.0: 1075; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s0 1076; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 16 1077; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s2 1078; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 16 1079; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s5 1080; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s2 1081; GFX10PLUS-NEXT: s_sext_i32_i16 s2, s1 1082; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 16 1083; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s3 1084; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 16 1085; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s5 1086; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s3 1087; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s4, s0 1088; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s2, s1 1089; GFX10PLUS-NEXT: ; return to shader part epilog 1090 %result = ashr <4 x i16> %value, %amount 1091 %cast = bitcast <4 x i16> %result to <2 x i32> 1092 ret <2 x i32> %cast 1093} 1094 1095; FIXME 1096; define <5 x i16> @v_ashr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1097; %result = ashr <5 x i16> %value, %amount 1098; ret <5 x i16> %result 1099; } 1100 1101; define amdgpu_ps <5 x i16> @s_ashr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1102; %result = ashr <5 x i16> %value, %amount 1103; ret <5 x i16> %result 1104; } 1105 1106; define <3 x float> @v_ashr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1107; %result = ashr <6 x i16> %value, %amount 1108; %cast = bitcast <6 x i16> %result to <3 x float> 1109; ret <3 x float> %cast 1110; } 1111 1112; define amdgpu_ps <3 x i32> @s_ashr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1113; %result = ashr <6 x i16> %value, %amount 1114; %cast = bitcast <6 x i16> %result to <3 x i32> 1115; ret <3 x i32> %cast 1116; } 1117 1118define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1119; GFX6-LABEL: v_ashr_v8i16: 1120; GFX6: ; %bb.0: 1121; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1122; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v8 1123; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 1124; GFX6-NEXT: v_ashrrev_i32_e32 v0, v8, v0 1125; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v9 1126; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 1127; GFX6-NEXT: v_ashrrev_i32_e32 v1, v8, v1 1128; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v10 1129; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 1130; GFX6-NEXT: v_ashrrev_i32_e32 v2, v8, v2 1131; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v11 1132; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 1133; GFX6-NEXT: v_ashrrev_i32_e32 v3, v8, v3 1134; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v12 1135; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 1136; GFX6-NEXT: v_ashrrev_i32_e32 v4, v8, v4 1137; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v13 1138; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 1139; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 1140; GFX6-NEXT: v_ashrrev_i32_e32 v5, v8, v5 1141; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v14 1142; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 1143; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 1144; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1145; GFX6-NEXT: v_ashrrev_i32_e32 v6, v8, v6 1146; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v15 1147; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 1148; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1149; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2 1150; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3 1151; GFX6-NEXT: v_ashrrev_i32_e32 v7, v8, v7 1152; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 1153; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5 1154; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 1155; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4 1156; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 1157; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7 1158; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 1159; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v6 1160; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4 1161; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 1162; GFX6-NEXT: s_setpc_b64 s[30:31] 1163; 1164; GFX8-LABEL: v_ashr_v8i16: 1165; GFX8: ; %bb.0: 1166; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1167; GFX8-NEXT: v_ashrrev_i16_e32 v8, v4, v0 1168; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1169; GFX8-NEXT: v_ashrrev_i16_e32 v4, v5, v1 1170; GFX8-NEXT: v_ashrrev_i16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1171; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1172; GFX8-NEXT: v_ashrrev_i16_e32 v4, v6, v2 1173; GFX8-NEXT: v_ashrrev_i16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1174; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1175; GFX8-NEXT: v_ashrrev_i16_e32 v4, v7, v3 1176; GFX8-NEXT: v_ashrrev_i16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1177; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1178; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1179; GFX8-NEXT: s_setpc_b64 s[30:31] 1180; 1181; GFX9-LABEL: v_ashr_v8i16: 1182; GFX9: ; %bb.0: 1183; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1184; GFX9-NEXT: v_pk_ashrrev_i16 v0, v4, v0 1185; GFX9-NEXT: v_pk_ashrrev_i16 v1, v5, v1 1186; GFX9-NEXT: v_pk_ashrrev_i16 v2, v6, v2 1187; GFX9-NEXT: v_pk_ashrrev_i16 v3, v7, v3 1188; GFX9-NEXT: s_setpc_b64 s[30:31] 1189; 1190; GFX10PLUS-LABEL: v_ashr_v8i16: 1191; GFX10PLUS: ; %bb.0: 1192; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1193; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1194; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v4, v0 1195; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, v5, v1 1196; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v2, v6, v2 1197; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v3, v7, v3 1198; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1199 %result = ashr <8 x i16> %value, %amount 1200 %cast = bitcast <8 x i16> %result to <4 x float> 1201 ret <4 x float> %cast 1202} 1203 1204define amdgpu_ps <4 x i32> @s_ashr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1205; GFX6-LABEL: s_ashr_v8i16: 1206; GFX6: ; %bb.0: 1207; GFX6-NEXT: s_sext_i32_i16 s1, s1 1208; GFX6-NEXT: s_sext_i32_i16 s0, s0 1209; GFX6-NEXT: s_ashr_i32 s1, s1, s9 1210; GFX6-NEXT: s_ashr_i32 s0, s0, s8 1211; GFX6-NEXT: s_sext_i32_i16 s2, s2 1212; GFX6-NEXT: s_sext_i32_i16 s3, s3 1213; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 1214; GFX6-NEXT: s_ashr_i32 s2, s2, s10 1215; GFX6-NEXT: s_ashr_i32 s3, s3, s11 1216; GFX6-NEXT: s_sext_i32_i16 s5, s5 1217; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 1218; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1219; GFX6-NEXT: s_sext_i32_i16 s4, s4 1220; GFX6-NEXT: s_ashr_i32 s5, s5, s13 1221; GFX6-NEXT: s_sext_i32_i16 s7, s7 1222; GFX6-NEXT: s_or_b32 s0, s0, s1 1223; GFX6-NEXT: s_and_b32 s1, s2, 0xffff 1224; GFX6-NEXT: s_and_b32 s2, s3, 0xffff 1225; GFX6-NEXT: s_ashr_i32 s4, s4, s12 1226; GFX6-NEXT: s_sext_i32_i16 s6, s6 1227; GFX6-NEXT: s_ashr_i32 s7, s7, s15 1228; GFX6-NEXT: s_lshl_b32 s2, s2, 16 1229; GFX6-NEXT: s_and_b32 s3, s5, 0xffff 1230; GFX6-NEXT: s_ashr_i32 s6, s6, s14 1231; GFX6-NEXT: s_or_b32 s1, s1, s2 1232; GFX6-NEXT: s_and_b32 s2, s4, 0xffff 1233; GFX6-NEXT: s_lshl_b32 s3, s3, 16 1234; GFX6-NEXT: s_and_b32 s4, s7, 0xffff 1235; GFX6-NEXT: s_or_b32 s2, s2, s3 1236; GFX6-NEXT: s_and_b32 s3, s6, 0xffff 1237; GFX6-NEXT: s_lshl_b32 s4, s4, 16 1238; GFX6-NEXT: s_or_b32 s3, s3, s4 1239; GFX6-NEXT: ; return to shader part epilog 1240; 1241; GFX8-LABEL: s_ashr_v8i16: 1242; GFX8: ; %bb.0: 1243; GFX8-NEXT: s_sext_i32_i16 s8, s0 1244; GFX8-NEXT: s_bfe_i32 s0, s0, 0x100010 1245; GFX8-NEXT: s_sext_i32_i16 s9, s1 1246; GFX8-NEXT: s_bfe_i32 s1, s1, 0x100010 1247; GFX8-NEXT: s_sext_i32_i16 s12, s4 1248; GFX8-NEXT: s_bfe_i32 s4, s4, 0x100010 1249; GFX8-NEXT: s_sext_i32_i16 s13, s5 1250; GFX8-NEXT: s_bfe_i32 s5, s5, 0x100010 1251; GFX8-NEXT: s_sext_i32_i16 s10, s2 1252; GFX8-NEXT: s_bfe_i32 s2, s2, 0x100010 1253; GFX8-NEXT: s_sext_i32_i16 s14, s6 1254; GFX8-NEXT: s_bfe_i32 s6, s6, 0x100010 1255; GFX8-NEXT: s_ashr_i32 s0, s0, s4 1256; GFX8-NEXT: s_ashr_i32 s4, s9, s13 1257; GFX8-NEXT: s_ashr_i32 s1, s1, s5 1258; GFX8-NEXT: s_sext_i32_i16 s11, s3 1259; GFX8-NEXT: s_bfe_i32 s3, s3, 0x100010 1260; GFX8-NEXT: s_sext_i32_i16 s15, s7 1261; GFX8-NEXT: s_bfe_i32 s7, s7, 0x100010 1262; GFX8-NEXT: s_ashr_i32 s5, s10, s14 1263; GFX8-NEXT: s_ashr_i32 s2, s2, s6 1264; GFX8-NEXT: s_lshl_b32 s1, s1, 16 1265; GFX8-NEXT: s_and_b32 s4, s4, 0xffff 1266; GFX8-NEXT: s_ashr_i32 s8, s8, s12 1267; GFX8-NEXT: s_ashr_i32 s6, s11, s15 1268; GFX8-NEXT: s_ashr_i32 s3, s3, s7 1269; GFX8-NEXT: s_or_b32 s1, s1, s4 1270; GFX8-NEXT: s_lshl_b32 s2, s2, 16 1271; GFX8-NEXT: s_and_b32 s4, s5, 0xffff 1272; GFX8-NEXT: s_lshl_b32 s0, s0, 16 1273; GFX8-NEXT: s_and_b32 s7, s8, 0xffff 1274; GFX8-NEXT: s_or_b32 s2, s2, s4 1275; GFX8-NEXT: s_lshl_b32 s3, s3, 16 1276; GFX8-NEXT: s_and_b32 s4, s6, 0xffff 1277; GFX8-NEXT: s_or_b32 s0, s0, s7 1278; GFX8-NEXT: s_or_b32 s3, s3, s4 1279; GFX8-NEXT: ; return to shader part epilog 1280; 1281; GFX9-LABEL: s_ashr_v8i16: 1282; GFX9: ; %bb.0: 1283; GFX9-NEXT: s_sext_i32_i16 s8, s0 1284; GFX9-NEXT: s_ashr_i32 s0, s0, 16 1285; GFX9-NEXT: s_sext_i32_i16 s9, s4 1286; GFX9-NEXT: s_ashr_i32 s4, s4, 16 1287; GFX9-NEXT: s_ashr_i32 s8, s8, s9 1288; GFX9-NEXT: s_ashr_i32 s0, s0, s4 1289; GFX9-NEXT: s_pack_ll_b32_b16 s0, s8, s0 1290; GFX9-NEXT: s_sext_i32_i16 s4, s1 1291; GFX9-NEXT: s_ashr_i32 s1, s1, 16 1292; GFX9-NEXT: s_sext_i32_i16 s8, s5 1293; GFX9-NEXT: s_ashr_i32 s5, s5, 16 1294; GFX9-NEXT: s_ashr_i32 s4, s4, s8 1295; GFX9-NEXT: s_ashr_i32 s1, s1, s5 1296; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s1 1297; GFX9-NEXT: s_sext_i32_i16 s4, s2 1298; GFX9-NEXT: s_ashr_i32 s2, s2, 16 1299; GFX9-NEXT: s_sext_i32_i16 s5, s6 1300; GFX9-NEXT: s_ashr_i32 s6, s6, 16 1301; GFX9-NEXT: s_ashr_i32 s4, s4, s5 1302; GFX9-NEXT: s_ashr_i32 s2, s2, s6 1303; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2 1304; GFX9-NEXT: s_sext_i32_i16 s4, s3 1305; GFX9-NEXT: s_ashr_i32 s3, s3, 16 1306; GFX9-NEXT: s_sext_i32_i16 s5, s7 1307; GFX9-NEXT: s_ashr_i32 s6, s7, 16 1308; GFX9-NEXT: s_ashr_i32 s4, s4, s5 1309; GFX9-NEXT: s_ashr_i32 s3, s3, s6 1310; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 1311; GFX9-NEXT: ; return to shader part epilog 1312; 1313; GFX10PLUS-LABEL: s_ashr_v8i16: 1314; GFX10PLUS: ; %bb.0: 1315; GFX10PLUS-NEXT: s_sext_i32_i16 s8, s0 1316; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 16 1317; GFX10PLUS-NEXT: s_sext_i32_i16 s9, s4 1318; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, 16 1319; GFX10PLUS-NEXT: s_ashr_i32 s8, s8, s9 1320; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4 1321; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s1 1322; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 16 1323; GFX10PLUS-NEXT: s_sext_i32_i16 s9, s5 1324; GFX10PLUS-NEXT: s_ashr_i32 s5, s5, 16 1325; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s9 1326; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5 1327; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s6 1328; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s4, s1 1329; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s2 1330; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 16 1331; GFX10PLUS-NEXT: s_ashr_i32 s6, s6, 16 1332; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s5 1333; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s6 1334; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s3 1335; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 16 1336; GFX10PLUS-NEXT: s_sext_i32_i16 s6, s7 1337; GFX10PLUS-NEXT: s_ashr_i32 s7, s7, 16 1338; GFX10PLUS-NEXT: s_ashr_i32 s5, s5, s6 1339; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s7 1340; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s8, s0 1341; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s4, s2 1342; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s5, s3 1343; GFX10PLUS-NEXT: ; return to shader part epilog 1344 %result = ashr <8 x i16> %value, %amount 1345 %cast = bitcast <8 x i16> %result to <4 x i32> 1346 ret <4 x i32> %cast 1347} 1348 1349define i64 @v_ashr_i64(i64 %value, i64 %amount) { 1350; GFX6-LABEL: v_ashr_i64: 1351; GFX6: ; %bb.0: 1352; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1353; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2 1354; GFX6-NEXT: s_setpc_b64 s[30:31] 1355; 1356; GFX8-LABEL: v_ashr_i64: 1357; GFX8: ; %bb.0: 1358; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1359; GFX8-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1360; GFX8-NEXT: s_setpc_b64 s[30:31] 1361; 1362; GFX9-LABEL: v_ashr_i64: 1363; GFX9: ; %bb.0: 1364; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1365; GFX9-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1366; GFX9-NEXT: s_setpc_b64 s[30:31] 1367; 1368; GFX10PLUS-LABEL: v_ashr_i64: 1369; GFX10PLUS: ; %bb.0: 1370; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1371; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1372; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1373; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1374 %result = ashr i64 %value, %amount 1375 ret i64 %result 1376} 1377 1378define i64 @v_ashr_i64_63(i64 %value) { 1379; GCN-LABEL: v_ashr_i64_63: 1380; GCN: ; %bb.0: 1381; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1382; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v1 1383; GCN-NEXT: v_mov_b32_e32 v1, v0 1384; GCN-NEXT: s_setpc_b64 s[30:31] 1385; 1386; GFX10PLUS-LABEL: v_ashr_i64_63: 1387; GFX10PLUS: ; %bb.0: 1388; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1389; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1390; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v1 1391; GFX10PLUS-NEXT: v_mov_b32_e32 v1, v0 1392; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1393 %result = ashr i64 %value, 63 1394 ret i64 %result 1395} 1396 1397define i64 @v_ashr_i64_33(i64 %value) { 1398; GCN-LABEL: v_ashr_i64_33: 1399; GCN: ; %bb.0: 1400; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1401; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1402; GCN-NEXT: v_ashrrev_i32_e32 v0, 1, v1 1403; GCN-NEXT: v_mov_b32_e32 v1, v2 1404; GCN-NEXT: s_setpc_b64 s[30:31] 1405; 1406; GFX10PLUS-LABEL: v_ashr_i64_33: 1407; GFX10PLUS: ; %bb.0: 1408; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1409; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1410; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 1, v1 1411; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v1 1412; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1413 %result = ashr i64 %value, 33 1414 ret i64 %result 1415} 1416 1417define i64 @v_ashr_i64_32(i64 %value) { 1418; GCN-LABEL: v_ashr_i64_32: 1419; GCN: ; %bb.0: 1420; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1421; GCN-NEXT: v_mov_b32_e32 v0, v1 1422; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1423; GCN-NEXT: s_setpc_b64 s[30:31] 1424; 1425; GFX10PLUS-LABEL: v_ashr_i64_32: 1426; GFX10PLUS: ; %bb.0: 1427; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1428; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1429; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v1 1430; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1431; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1432 %result = ashr i64 %value, 32 1433 ret i64 %result 1434} 1435 1436define i64 @v_ashr_i64_31(i64 %value) { 1437; GFX6-LABEL: v_ashr_i64_31: 1438; GFX6: ; %bb.0: 1439; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1440; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 31 1441; GFX6-NEXT: s_setpc_b64 s[30:31] 1442; 1443; GFX8-LABEL: v_ashr_i64_31: 1444; GFX8: ; %bb.0: 1445; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1446; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1447; GFX8-NEXT: s_setpc_b64 s[30:31] 1448; 1449; GFX9-LABEL: v_ashr_i64_31: 1450; GFX9: ; %bb.0: 1451; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1452; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1453; GFX9-NEXT: s_setpc_b64 s[30:31] 1454; 1455; GFX10PLUS-LABEL: v_ashr_i64_31: 1456; GFX10PLUS: ; %bb.0: 1457; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1458; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1459; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1460; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1461 %result = ashr i64 %value, 31 1462 ret i64 %result 1463} 1464 1465define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value, i64 inreg %amount) { 1466; GCN-LABEL: s_ashr_i64: 1467; GCN: ; %bb.0: 1468; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], s2 1469; GCN-NEXT: ; return to shader part epilog 1470; 1471; GFX10PLUS-LABEL: s_ashr_i64: 1472; GFX10PLUS: ; %bb.0: 1473; GFX10PLUS-NEXT: s_ashr_i64 s[0:1], s[0:1], s2 1474; GFX10PLUS-NEXT: ; return to shader part epilog 1475 %result = ashr i64 %value, %amount 1476 ret i64 %result 1477} 1478 1479define amdgpu_ps i64 @s_ashr_i64_63(i64 inreg %value) { 1480; GCN-LABEL: s_ashr_i64_63: 1481; GCN: ; %bb.0: 1482; GCN-NEXT: s_ashr_i32 s0, s1, 31 1483; GCN-NEXT: s_mov_b32 s1, s0 1484; GCN-NEXT: ; return to shader part epilog 1485; 1486; GFX10PLUS-LABEL: s_ashr_i64_63: 1487; GFX10PLUS: ; %bb.0: 1488; GFX10PLUS-NEXT: s_ashr_i32 s0, s1, 31 1489; GFX10PLUS-NEXT: s_mov_b32 s1, s0 1490; GFX10PLUS-NEXT: ; return to shader part epilog 1491 %result = ashr i64 %value, 63 1492 ret i64 %result 1493} 1494 1495define amdgpu_ps i64 @s_ashr_i64_33(i64 inreg %value) { 1496; GCN-LABEL: s_ashr_i64_33: 1497; GCN: ; %bb.0: 1498; GCN-NEXT: s_ashr_i32 s2, s1, 31 1499; GCN-NEXT: s_ashr_i32 s0, s1, 1 1500; GCN-NEXT: s_mov_b32 s1, s2 1501; GCN-NEXT: ; return to shader part epilog 1502; 1503; GFX10PLUS-LABEL: s_ashr_i64_33: 1504; GFX10PLUS: ; %bb.0: 1505; GFX10PLUS-NEXT: s_ashr_i32 s0, s1, 1 1506; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 31 1507; GFX10PLUS-NEXT: ; return to shader part epilog 1508 %result = ashr i64 %value, 33 1509 ret i64 %result 1510} 1511 1512define amdgpu_ps i64 @s_ashr_i64_32(i64 inreg %value) { 1513; GCN-LABEL: s_ashr_i64_32: 1514; GCN: ; %bb.0: 1515; GCN-NEXT: s_mov_b32 s0, s1 1516; GCN-NEXT: s_ashr_i32 s1, s1, 31 1517; GCN-NEXT: ; return to shader part epilog 1518; 1519; GFX10PLUS-LABEL: s_ashr_i64_32: 1520; GFX10PLUS: ; %bb.0: 1521; GFX10PLUS-NEXT: s_mov_b32 s0, s1 1522; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 31 1523; GFX10PLUS-NEXT: ; return to shader part epilog 1524 %result = ashr i64 %value, 32 1525 ret i64 %result 1526} 1527 1528define amdgpu_ps i64 @s_ashr_i64_31(i64 inreg %value) { 1529; GCN-LABEL: s_ashr_i64_31: 1530; GCN: ; %bb.0: 1531; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 31 1532; GCN-NEXT: ; return to shader part epilog 1533; 1534; GFX10PLUS-LABEL: s_ashr_i64_31: 1535; GFX10PLUS: ; %bb.0: 1536; GFX10PLUS-NEXT: s_ashr_i64 s[0:1], s[0:1], 31 1537; GFX10PLUS-NEXT: ; return to shader part epilog 1538 %result = ashr i64 %value, 31 1539 ret i64 %result 1540} 1541 1542define amdgpu_ps <2 x float> @ashr_i64_sv(i64 inreg %value, i64 %amount) { 1543; GFX6-LABEL: ashr_i64_sv: 1544; GFX6: ; %bb.0: 1545; GFX6-NEXT: v_ashr_i64 v[0:1], s[0:1], v0 1546; GFX6-NEXT: ; return to shader part epilog 1547; 1548; GFX8-LABEL: ashr_i64_sv: 1549; GFX8: ; %bb.0: 1550; GFX8-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1551; GFX8-NEXT: ; return to shader part epilog 1552; 1553; GFX9-LABEL: ashr_i64_sv: 1554; GFX9: ; %bb.0: 1555; GFX9-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1556; GFX9-NEXT: ; return to shader part epilog 1557; 1558; GFX10PLUS-LABEL: ashr_i64_sv: 1559; GFX10PLUS: ; %bb.0: 1560; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1561; GFX10PLUS-NEXT: ; return to shader part epilog 1562 %result = ashr i64 %value, %amount 1563 %cast = bitcast i64 %result to <2 x float> 1564 ret <2 x float> %cast 1565} 1566 1567define amdgpu_ps <2 x float> @ashr_i64_vs(i64 %value, i64 inreg %amount) { 1568; GFX6-LABEL: ashr_i64_vs: 1569; GFX6: ; %bb.0: 1570; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], s0 1571; GFX6-NEXT: ; return to shader part epilog 1572; 1573; GFX8-LABEL: ashr_i64_vs: 1574; GFX8: ; %bb.0: 1575; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1576; GFX8-NEXT: ; return to shader part epilog 1577; 1578; GFX9-LABEL: ashr_i64_vs: 1579; GFX9: ; %bb.0: 1580; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1581; GFX9-NEXT: ; return to shader part epilog 1582; 1583; GFX10PLUS-LABEL: ashr_i64_vs: 1584; GFX10PLUS: ; %bb.0: 1585; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1586; GFX10PLUS-NEXT: ; return to shader part epilog 1587 %result = ashr i64 %value, %amount 1588 %cast = bitcast i64 %result to <2 x float> 1589 ret <2 x float> %cast 1590} 1591 1592define <2 x i64> @v_ashr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1593; GFX6-LABEL: v_ashr_v2i64: 1594; GFX6: ; %bb.0: 1595; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1596; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v4 1597; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], v6 1598; GFX6-NEXT: s_setpc_b64 s[30:31] 1599; 1600; GFX8-LABEL: v_ashr_v2i64: 1601; GFX8: ; %bb.0: 1602; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1603; GFX8-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1604; GFX8-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] 1605; GFX8-NEXT: s_setpc_b64 s[30:31] 1606; 1607; GFX9-LABEL: v_ashr_v2i64: 1608; GFX9: ; %bb.0: 1609; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1610; GFX9-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1611; GFX9-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] 1612; GFX9-NEXT: s_setpc_b64 s[30:31] 1613; 1614; GFX10PLUS-LABEL: v_ashr_v2i64: 1615; GFX10PLUS: ; %bb.0: 1616; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1617; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1618; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1619; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] 1620; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1621 %result = ashr <2 x i64> %value, %amount 1622 ret <2 x i64> %result 1623} 1624 1625define <2 x i64> @v_ashr_v2i64_31(<2 x i64> %value) { 1626; GFX6-LABEL: v_ashr_v2i64_31: 1627; GFX6: ; %bb.0: 1628; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1629; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 31 1630; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], 31 1631; GFX6-NEXT: s_setpc_b64 s[30:31] 1632; 1633; GFX8-LABEL: v_ashr_v2i64_31: 1634; GFX8: ; %bb.0: 1635; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1636; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1637; GFX8-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3] 1638; GFX8-NEXT: s_setpc_b64 s[30:31] 1639; 1640; GFX9-LABEL: v_ashr_v2i64_31: 1641; GFX9: ; %bb.0: 1642; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1643; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1644; GFX9-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3] 1645; GFX9-NEXT: s_setpc_b64 s[30:31] 1646; 1647; GFX10PLUS-LABEL: v_ashr_v2i64_31: 1648; GFX10PLUS: ; %bb.0: 1649; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1650; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1651; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1652; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3] 1653; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1654 %result = ashr <2 x i64> %value, <i64 31, i64 31> 1655 ret <2 x i64> %result 1656} 1657 1658define amdgpu_ps <2 x i64> @s_ashr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1659; GCN-LABEL: s_ashr_v2i64: 1660; GCN: ; %bb.0: 1661; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], s4 1662; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], s6 1663; GCN-NEXT: ; return to shader part epilog 1664; 1665; GFX10PLUS-LABEL: s_ashr_v2i64: 1666; GFX10PLUS: ; %bb.0: 1667; GFX10PLUS-NEXT: s_ashr_i64 s[0:1], s[0:1], s4 1668; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], s6 1669; GFX10PLUS-NEXT: ; return to shader part epilog 1670 %result = ashr <2 x i64> %value, %amount 1671 ret <2 x i64> %result 1672} 1673 1674define i65 @v_ashr_i65(i65 %value, i65 %amount) { 1675; GFX6-LABEL: v_ashr_i65: 1676; GFX6: ; %bb.0: 1677; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1678; GFX6-NEXT: v_bfe_i32 v4, v2, 0, 1 1679; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4 1680; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v3 1681; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v3 1682; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v8 1683; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 64, v3 1684; GFX6-NEXT: v_ashr_i64 v[10:11], v[4:5], v3 1685; GFX6-NEXT: v_or_b32_e32 v6, v6, v8 1686; GFX6-NEXT: v_ashrrev_i32_e32 v8, 31, v5 1687; GFX6-NEXT: v_ashr_i64 v[4:5], v[4:5], v2 1688; GFX6-NEXT: v_or_b32_e32 v7, v7, v9 1689; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1690; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1691; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1692; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1693; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1694; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1695; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc 1696; GFX6-NEXT: s_setpc_b64 s[30:31] 1697; 1698; GFX8-LABEL: v_ashr_i65: 1699; GFX8: ; %bb.0: 1700; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1701; GFX8-NEXT: v_bfe_i32 v4, v2, 0, 1 1702; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4 1703; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v3 1704; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1705; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1706; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 1707; GFX8-NEXT: v_ashrrev_i64 v[10:11], v3, v[4:5] 1708; GFX8-NEXT: v_or_b32_e32 v6, v6, v8 1709; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v5 1710; GFX8-NEXT: v_ashrrev_i64 v[4:5], v2, v[4:5] 1711; GFX8-NEXT: v_or_b32_e32 v7, v7, v9 1712; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1713; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1714; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1715; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1716; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1717; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1718; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc 1719; GFX8-NEXT: s_setpc_b64 s[30:31] 1720; 1721; GFX9-LABEL: v_ashr_i65: 1722; GFX9: ; %bb.0: 1723; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1724; GFX9-NEXT: v_bfe_i32 v4, v2, 0, 1 1725; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v4 1726; GFX9-NEXT: v_sub_u32_e32 v8, 64, v3 1727; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1728; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5] 1729; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3 1730; GFX9-NEXT: v_ashrrev_i64 v[10:11], v3, v[4:5] 1731; GFX9-NEXT: v_or_b32_e32 v6, v6, v8 1732; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v5 1733; GFX9-NEXT: v_ashrrev_i64 v[4:5], v2, v[4:5] 1734; GFX9-NEXT: v_or_b32_e32 v7, v7, v9 1735; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 1736; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc 1737; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc 1738; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3 1739; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] 1740; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] 1741; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc 1742; GFX9-NEXT: s_setpc_b64 s[30:31] 1743; 1744; GFX10-LABEL: v_ashr_i65: 1745; GFX10: ; %bb.0: 1746; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1747; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1748; GFX10-NEXT: v_bfe_i32 v4, v2, 0, 1 1749; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 1750; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 1751; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1752; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 1753; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v4 1754; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3 1755; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] 1756; GFX10-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5] 1757; GFX10-NEXT: v_or_b32_e32 v2, v6, v8 1758; GFX10-NEXT: v_or_b32_e32 v8, v7, v9 1759; GFX10-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5] 1760; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5 1761; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo 1762; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v8, vcc_lo 1763; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4 1764; GFX10-NEXT: v_cndmask_b32_e64 v1, v4, v1, s4 1765; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo 1766; GFX10-NEXT: s_setpc_b64 s[30:31] 1767; 1768; GFX11-LABEL: v_ashr_i65: 1769; GFX11: ; %bb.0: 1770; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1771; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1772; GFX11-NEXT: v_bfe_i32 v4, v2, 0, 1 1773; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v3 1774; GFX11-NEXT: v_subrev_nc_u32_e32 v10, 64, v3 1775; GFX11-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1] 1776; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3 1777; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v4 1778; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v3 1779; GFX11-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5] 1780; GFX11-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5] 1781; GFX11-NEXT: v_or_b32_e32 v2, v6, v8 1782; GFX11-NEXT: v_or_b32_e32 v8, v7, v9 1783; GFX11-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5] 1784; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v5 1785; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo 1786; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v8, vcc_lo 1787; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s0 1788; GFX11-NEXT: v_cndmask_b32_e64 v1, v4, v1, s0 1789; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v6, vcc_lo 1790; GFX11-NEXT: s_setpc_b64 s[30:31] 1791 %result = ashr i65 %value, %amount 1792 ret i65 %result 1793} 1794 1795define i65 @v_ashr_i65_33(i65 %value) { 1796; GFX6-LABEL: v_ashr_i65_33: 1797; GFX6: ; %bb.0: 1798; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1799; GFX6-NEXT: v_mov_b32_e32 v3, v1 1800; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 1 1801; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1802; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 31 1803; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3 1804; GFX6-NEXT: v_or_b32_e32 v0, v3, v0 1805; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v2 1806; GFX6-NEXT: s_setpc_b64 s[30:31] 1807; 1808; GFX8-LABEL: v_ashr_i65_33: 1809; GFX8: ; %bb.0: 1810; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1811; GFX8-NEXT: v_mov_b32_e32 v3, v1 1812; GFX8-NEXT: v_bfe_i32 v1, v2, 0, 1 1813; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1814; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] 1815; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v3 1816; GFX8-NEXT: v_or_b32_e32 v0, v3, v0 1817; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v2 1818; GFX8-NEXT: s_setpc_b64 s[30:31] 1819; 1820; GFX9-LABEL: v_ashr_i65_33: 1821; GFX9: ; %bb.0: 1822; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1823; GFX9-NEXT: v_mov_b32_e32 v3, v1 1824; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 1 1825; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1826; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] 1827; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3 1828; GFX9-NEXT: v_or_b32_e32 v0, v3, v0 1829; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2 1830; GFX9-NEXT: s_setpc_b64 s[30:31] 1831; 1832; GFX10PLUS-LABEL: v_ashr_i65_33: 1833; GFX10PLUS: ; %bb.0: 1834; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1835; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 1836; GFX10PLUS-NEXT: v_mov_b32_e32 v3, v1 1837; GFX10PLUS-NEXT: v_bfe_i32 v1, v2, 0, 1 1838; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 1, v3 1839; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1840; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2] 1841; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2 1842; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0 1843; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] 1844 %result = ashr i65 %value, 33 1845 ret i65 %result 1846} 1847 1848define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) { 1849; GCN-LABEL: s_ashr_i65: 1850; GCN: ; %bb.0: 1851; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000 1852; GCN-NEXT: s_sub_i32 s10, s3, 64 1853; GCN-NEXT: s_sub_i32 s8, 64, s3 1854; GCN-NEXT: s_cmp_lt_u32 s3, 64 1855; GCN-NEXT: s_cselect_b32 s11, 1, 0 1856; GCN-NEXT: s_cmp_eq_u32 s3, 0 1857; GCN-NEXT: s_cselect_b32 s12, 1, 0 1858; GCN-NEXT: s_ashr_i64 s[6:7], s[4:5], s3 1859; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 1860; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 1861; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] 1862; GCN-NEXT: s_ashr_i32 s8, s5, 31 1863; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], s10 1864; GCN-NEXT: s_cmp_lg_u32 s11, 0 1865; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] 1866; GCN-NEXT: s_cmp_lg_u32 s12, 0 1867; GCN-NEXT: s_mov_b32 s9, s8 1868; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] 1869; GCN-NEXT: s_cmp_lg_u32 s11, 0 1870; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], s[8:9] 1871; GCN-NEXT: ; return to shader part epilog 1872; 1873; GFX10PLUS-LABEL: s_ashr_i65: 1874; GFX10PLUS: ; %bb.0: 1875; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000 1876; GFX10PLUS-NEXT: s_sub_i32 s12, s3, 64 1877; GFX10PLUS-NEXT: s_sub_i32 s8, 64, s3 1878; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64 1879; GFX10PLUS-NEXT: s_cselect_b32 s13, 1, 0 1880; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0 1881; GFX10PLUS-NEXT: s_cselect_b32 s14, 1, 0 1882; GFX10PLUS-NEXT: s_ashr_i64 s[6:7], s[4:5], s3 1883; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 1884; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 1885; GFX10PLUS-NEXT: s_ashr_i32 s10, s5, 31 1886; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] 1887; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[4:5], s12 1888; GFX10PLUS-NEXT: s_cmp_lg_u32 s13, 0 1889; GFX10PLUS-NEXT: s_mov_b32 s11, s10 1890; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] 1891; GFX10PLUS-NEXT: s_cmp_lg_u32 s14, 0 1892; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] 1893; GFX10PLUS-NEXT: s_cmp_lg_u32 s13, 0 1894; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[6:7], s[10:11] 1895; GFX10PLUS-NEXT: ; return to shader part epilog 1896 %result = ashr i65 %value, %amount 1897 ret i65 %result 1898} 1899 1900define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) { 1901; GCN-LABEL: s_ashr_i65_33: 1902; GCN: ; %bb.0: 1903; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000 1904; GCN-NEXT: s_lshr_b32 s0, s1, 1 1905; GCN-NEXT: s_mov_b32 s1, 0 1906; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1907; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1908; GCN-NEXT: s_ashr_i32 s2, s3, 1 1909; GCN-NEXT: ; return to shader part epilog 1910; 1911; GFX10PLUS-LABEL: s_ashr_i65_33: 1912; GFX10PLUS: ; %bb.0: 1913; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000 1914; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1 1915; GFX10PLUS-NEXT: s_mov_b32 s1, 0 1916; GFX10PLUS-NEXT: s_lshl_b64 s[4:5], s[2:3], 31 1917; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1 1918; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] 1919; GFX10PLUS-NEXT: ; return to shader part epilog 1920 %result = ashr i65 %value, 33 1921 ret i65 %result 1922} 1923 1924; FIXME: Argument lowering asserts 1925; define <2 x i65> @v_ashr_v2i65(<2 x i65> %value, <2 x i65> %amount) { 1926; %result = ashr <2 x i65> %value, %amount 1927; ret <2 x i65> %result 1928; } 1929 1930; define amdgpu_ps <2 x i65> @s_ashr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) { 1931; %result = ashr <2 x i65> %value, %amount 1932; ret <2 x i65> %result 1933; } 1934