1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s 6 7define i8 @v_ashr_i8(i8 %value, i8 %amount) { 8; GFX6-LABEL: v_ashr_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 12; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 13; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_ashr_i8: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 20; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_1 21; GFX8-NEXT: s_setpc_b64 s[30:31] 22; 23; GFX9-LABEL: v_ashr_i8: 24; GFX9: ; %bb.0: 25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 26; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 27; GFX9-NEXT: s_setpc_b64 s[30:31] 28; 29; GFX10-LABEL: v_ashr_i8: 30; GFX10: ; %bb.0: 31; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 32; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 33; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1 34; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8 35; GFX10-NEXT: v_ashrrev_i16 v0, v1, v0 36; GFX10-NEXT: s_setpc_b64 s[30:31] 37 %result = ashr i8 %value, %amount 38 ret i8 %result 39} 40 41define i8 @v_ashr_i8_7(i8 %value) { 42; GFX6-LABEL: v_ashr_i8_7: 43; GFX6: ; %bb.0: 44; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 45; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 46; GFX6-NEXT: v_ashrrev_i32_e32 v0, 7, v0 47; GFX6-NEXT: s_setpc_b64 s[30:31] 48; 49; GFX8-LABEL: v_ashr_i8_7: 50; GFX8: ; %bb.0: 51; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 52; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 53; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v0 54; GFX8-NEXT: s_setpc_b64 s[30:31] 55; 56; GFX9-LABEL: v_ashr_i8_7: 57; GFX9: ; %bb.0: 58; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 59; GFX9-NEXT: v_mov_b32_e32 v1, 7 60; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 61; GFX9-NEXT: s_setpc_b64 s[30:31] 62; 63; GFX10-LABEL: v_ashr_i8_7: 64; GFX10: ; %bb.0: 65; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 66; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 67; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8 68; GFX10-NEXT: v_ashrrev_i16 v0, 7, v0 69; GFX10-NEXT: s_setpc_b64 s[30:31] 70 %result = ashr i8 %value, 7 71 ret i8 %result 72} 73 74define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) { 75; GFX6-LABEL: s_ashr_i8: 76; GFX6: ; %bb.0: 77; GFX6-NEXT: s_and_b32 s1, s1, 0xff 78; GFX6-NEXT: s_sext_i32_i8 s0, s0 79; GFX6-NEXT: s_ashr_i32 s0, s0, s1 80; GFX6-NEXT: ; return to shader part epilog 81; 82; GFX8-LABEL: s_ashr_i8: 83; GFX8: ; %bb.0: 84; GFX8-NEXT: s_sext_i32_i8 s0, s0 85; GFX8-NEXT: s_sext_i32_i8 s1, s1 86; GFX8-NEXT: s_ashr_i32 s0, s0, s1 87; GFX8-NEXT: ; return to shader part epilog 88; 89; GFX9-LABEL: s_ashr_i8: 90; GFX9: ; %bb.0: 91; GFX9-NEXT: s_sext_i32_i8 s0, s0 92; GFX9-NEXT: s_sext_i32_i8 s1, s1 93; GFX9-NEXT: s_ashr_i32 s0, s0, s1 94; GFX9-NEXT: ; return to shader part epilog 95; 96; GFX10-LABEL: s_ashr_i8: 97; GFX10: ; %bb.0: 98; GFX10-NEXT: s_sext_i32_i8 s0, s0 99; GFX10-NEXT: s_sext_i32_i8 s1, s1 100; GFX10-NEXT: s_ashr_i32 s0, s0, s1 101; GFX10-NEXT: ; return to shader part epilog 102 %result = ashr i8 %value, %amount 103 ret i8 %result 104} 105 106define amdgpu_ps i8 @s_ashr_i8_7(i8 inreg %value) { 107; GCN-LABEL: s_ashr_i8_7: 108; GCN: ; %bb.0: 109; GCN-NEXT: s_sext_i32_i8 s0, s0 110; GCN-NEXT: s_ashr_i32 s0, s0, 7 111; GCN-NEXT: ; return to shader part epilog 112; 113; GFX10-LABEL: s_ashr_i8_7: 114; GFX10: ; %bb.0: 115; GFX10-NEXT: s_sext_i32_i8 s0, s0 116; GFX10-NEXT: s_ashr_i32 s0, s0, 7 117; GFX10-NEXT: ; return to shader part epilog 118 %result = ashr i8 %value, 7 119 ret i8 %result 120} 121 122 123define i24 @v_ashr_i24(i24 %value, i24 %amount) { 124; GCN-LABEL: v_ashr_i24: 125; GCN: ; %bb.0: 126; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 127; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1 128; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 129; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0 130; GCN-NEXT: s_setpc_b64 s[30:31] 131; 132; GFX10-LABEL: v_ashr_i24: 133; GFX10: ; %bb.0: 134; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 135; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 136; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff, v1 137; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 24 138; GFX10-NEXT: v_ashrrev_i32_e32 v0, v1, v0 139; GFX10-NEXT: s_setpc_b64 s[30:31] 140 %result = ashr i24 %value, %amount 141 ret i24 %result 142} 143 144define i24 @v_ashr_i24_7(i24 %value) { 145; GCN-LABEL: v_ashr_i24_7: 146; GCN: ; %bb.0: 147; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 148; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 149; GCN-NEXT: v_ashrrev_i32_e32 v0, 7, v0 150; GCN-NEXT: s_setpc_b64 s[30:31] 151; 152; GFX10-LABEL: v_ashr_i24_7: 153; GFX10: ; %bb.0: 154; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 155; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 156; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 24 157; GFX10-NEXT: v_ashrrev_i32_e32 v0, 7, v0 158; GFX10-NEXT: s_setpc_b64 s[30:31] 159 %result = ashr i24 %value, 7 160 ret i24 %result 161} 162 163define amdgpu_ps i24 @s_ashr_i24(i24 inreg %value, i24 inreg %amount) { 164; GCN-LABEL: s_ashr_i24: 165; GCN: ; %bb.0: 166; GCN-NEXT: s_and_b32 s1, s1, 0xffffff 167; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000 168; GCN-NEXT: s_ashr_i32 s0, s0, s1 169; GCN-NEXT: ; return to shader part epilog 170; 171; GFX10-LABEL: s_ashr_i24: 172; GFX10: ; %bb.0: 173; GFX10-NEXT: s_and_b32 s1, s1, 0xffffff 174; GFX10-NEXT: s_bfe_i32 s0, s0, 0x180000 175; GFX10-NEXT: s_ashr_i32 s0, s0, s1 176; GFX10-NEXT: ; return to shader part epilog 177 %result = ashr i24 %value, %amount 178 ret i24 %result 179} 180 181define amdgpu_ps i24 @s_ashr_i24_7(i24 inreg %value) { 182; GCN-LABEL: s_ashr_i24_7: 183; GCN: ; %bb.0: 184; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000 185; GCN-NEXT: s_ashr_i32 s0, s0, 7 186; GCN-NEXT: ; return to shader part epilog 187; 188; GFX10-LABEL: s_ashr_i24_7: 189; GFX10: ; %bb.0: 190; GFX10-NEXT: s_bfe_i32 s0, s0, 0x180000 191; GFX10-NEXT: s_ashr_i32 s0, s0, 7 192; GFX10-NEXT: ; return to shader part epilog 193 %result = ashr i24 %value, 7 194 ret i24 %result 195} 196 197define i32 @v_ashr_i32(i32 %value, i32 %amount) { 198; GCN-LABEL: v_ashr_i32: 199; GCN: ; %bb.0: 200; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 201; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0 202; GCN-NEXT: s_setpc_b64 s[30:31] 203; 204; GFX10-LABEL: v_ashr_i32: 205; GFX10: ; %bb.0: 206; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 207; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 208; GFX10-NEXT: v_ashrrev_i32_e32 v0, v1, v0 209; GFX10-NEXT: s_setpc_b64 s[30:31] 210 %result = ashr i32 %value, %amount 211 ret i32 %result 212} 213 214define i32 @v_ashr_i32_31(i32 %value) { 215; GCN-LABEL: v_ashr_i32_31: 216; GCN: ; %bb.0: 217; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 218; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0 219; GCN-NEXT: s_setpc_b64 s[30:31] 220; 221; GFX10-LABEL: v_ashr_i32_31: 222; GFX10: ; %bb.0: 223; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 224; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 225; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v0 226; GFX10-NEXT: s_setpc_b64 s[30:31] 227 %result = ashr i32 %value, 31 228 ret i32 %result 229} 230 231define amdgpu_ps i32 @s_ashr_i32(i32 inreg %value, i32 inreg %amount) { 232; GCN-LABEL: s_ashr_i32: 233; GCN: ; %bb.0: 234; GCN-NEXT: s_ashr_i32 s0, s0, s1 235; GCN-NEXT: ; return to shader part epilog 236; 237; GFX10-LABEL: s_ashr_i32: 238; GFX10: ; %bb.0: 239; GFX10-NEXT: s_ashr_i32 s0, s0, s1 240; GFX10-NEXT: ; return to shader part epilog 241 %result = ashr i32 %value, %amount 242 ret i32 %result 243} 244 245define amdgpu_ps i32 @s_ashr_i32_31(i32 inreg %value) { 246; GCN-LABEL: s_ashr_i32_31: 247; GCN: ; %bb.0: 248; GCN-NEXT: s_ashr_i32 s0, s0, 31 249; GCN-NEXT: ; return to shader part epilog 250; 251; GFX10-LABEL: s_ashr_i32_31: 252; GFX10: ; %bb.0: 253; GFX10-NEXT: s_ashr_i32 s0, s0, 31 254; GFX10-NEXT: ; return to shader part epilog 255 %result = ashr i32 %value, 31 256 ret i32 %result 257} 258 259define amdgpu_ps float @ashr_i32_sv(i32 inreg %value, i32 %amount) { 260; GFX6-LABEL: ashr_i32_sv: 261; GFX6: ; %bb.0: 262; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0 263; GFX6-NEXT: ; return to shader part epilog 264; 265; GFX8-LABEL: ashr_i32_sv: 266; GFX8: ; %bb.0: 267; GFX8-NEXT: v_ashrrev_i32_e64 v0, v0, s0 268; GFX8-NEXT: ; return to shader part epilog 269; 270; GFX9-LABEL: ashr_i32_sv: 271; GFX9: ; %bb.0: 272; GFX9-NEXT: v_ashrrev_i32_e64 v0, v0, s0 273; GFX9-NEXT: ; return to shader part epilog 274; 275; GFX10-LABEL: ashr_i32_sv: 276; GFX10: ; %bb.0: 277; GFX10-NEXT: v_ashrrev_i32_e64 v0, v0, s0 278; GFX10-NEXT: ; return to shader part epilog 279 %result = ashr i32 %value, %amount 280 %cast = bitcast i32 %result to float 281 ret float %cast 282} 283 284define amdgpu_ps float @ashr_i32_vs(i32 %value, i32 inreg %amount) { 285; GCN-LABEL: ashr_i32_vs: 286; GCN: ; %bb.0: 287; GCN-NEXT: v_ashrrev_i32_e32 v0, s0, v0 288; GCN-NEXT: ; return to shader part epilog 289; 290; GFX10-LABEL: ashr_i32_vs: 291; GFX10: ; %bb.0: 292; GFX10-NEXT: v_ashrrev_i32_e32 v0, s0, v0 293; GFX10-NEXT: ; return to shader part epilog 294 %result = ashr i32 %value, %amount 295 %cast = bitcast i32 %result to float 296 ret float %cast 297} 298 299define <2 x i32> @v_ashr_v2i32(<2 x i32> %value, <2 x i32> %amount) { 300; GCN-LABEL: v_ashr_v2i32: 301; GCN: ; %bb.0: 302; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 303; GCN-NEXT: v_ashrrev_i32_e32 v0, v2, v0 304; GCN-NEXT: v_ashrrev_i32_e32 v1, v3, v1 305; GCN-NEXT: s_setpc_b64 s[30:31] 306; 307; GFX10-LABEL: v_ashr_v2i32: 308; GFX10: ; %bb.0: 309; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 310; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 311; GFX10-NEXT: v_ashrrev_i32_e32 v0, v2, v0 312; GFX10-NEXT: v_ashrrev_i32_e32 v1, v3, v1 313; GFX10-NEXT: s_setpc_b64 s[30:31] 314 %result = ashr <2 x i32> %value, %amount 315 ret <2 x i32> %result 316} 317 318define <2 x i32> @v_ashr_v2i32_31(<2 x i32> %value) { 319; GCN-LABEL: v_ashr_v2i32_31: 320; GCN: ; %bb.0: 321; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 322; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0 323; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v1 324; GCN-NEXT: s_setpc_b64 s[30:31] 325; 326; GFX10-LABEL: v_ashr_v2i32_31: 327; GFX10: ; %bb.0: 328; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 329; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 330; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v0 331; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v1 332; GFX10-NEXT: s_setpc_b64 s[30:31] 333 %result = ashr <2 x i32> %value, <i32 31, i32 31> 334 ret <2 x i32> %result 335} 336 337define amdgpu_ps <2 x i32> @s_ashr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) { 338; GCN-LABEL: s_ashr_v2i32: 339; GCN: ; %bb.0: 340; GCN-NEXT: s_ashr_i32 s0, s0, s2 341; GCN-NEXT: s_ashr_i32 s1, s1, s3 342; GCN-NEXT: ; return to shader part epilog 343; 344; GFX10-LABEL: s_ashr_v2i32: 345; GFX10: ; %bb.0: 346; GFX10-NEXT: s_ashr_i32 s0, s0, s2 347; GFX10-NEXT: s_ashr_i32 s1, s1, s3 348; GFX10-NEXT: ; return to shader part epilog 349 %result = ashr <2 x i32> %value, %amount 350 ret <2 x i32> %result 351} 352 353define <3 x i32> @v_ashr_v3i32(<3 x i32> %value, <3 x i32> %amount) { 354; GCN-LABEL: v_ashr_v3i32: 355; GCN: ; %bb.0: 356; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 357; GCN-NEXT: v_ashrrev_i32_e32 v0, v3, v0 358; GCN-NEXT: v_ashrrev_i32_e32 v1, v4, v1 359; GCN-NEXT: v_ashrrev_i32_e32 v2, v5, v2 360; GCN-NEXT: s_setpc_b64 s[30:31] 361; 362; GFX10-LABEL: v_ashr_v3i32: 363; GFX10: ; %bb.0: 364; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 365; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 366; GFX10-NEXT: v_ashrrev_i32_e32 v0, v3, v0 367; GFX10-NEXT: v_ashrrev_i32_e32 v1, v4, v1 368; GFX10-NEXT: v_ashrrev_i32_e32 v2, v5, v2 369; GFX10-NEXT: s_setpc_b64 s[30:31] 370 %result = ashr <3 x i32> %value, %amount 371 ret <3 x i32> %result 372} 373 374define amdgpu_ps <3 x i32> @s_ashr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) { 375; GCN-LABEL: s_ashr_v3i32: 376; GCN: ; %bb.0: 377; GCN-NEXT: s_ashr_i32 s0, s0, s3 378; GCN-NEXT: s_ashr_i32 s1, s1, s4 379; GCN-NEXT: s_ashr_i32 s2, s2, s5 380; GCN-NEXT: ; return to shader part epilog 381; 382; GFX10-LABEL: s_ashr_v3i32: 383; GFX10: ; %bb.0: 384; GFX10-NEXT: s_ashr_i32 s0, s0, s3 385; GFX10-NEXT: s_ashr_i32 s1, s1, s4 386; GFX10-NEXT: s_ashr_i32 s2, s2, s5 387; GFX10-NEXT: ; return to shader part epilog 388 %result = ashr <3 x i32> %value, %amount 389 ret <3 x i32> %result 390} 391 392define <4 x i32> @v_ashr_v4i32(<4 x i32> %value, <4 x i32> %amount) { 393; GCN-LABEL: v_ashr_v4i32: 394; GCN: ; %bb.0: 395; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 396; GCN-NEXT: v_ashrrev_i32_e32 v0, v4, v0 397; GCN-NEXT: v_ashrrev_i32_e32 v1, v5, v1 398; GCN-NEXT: v_ashrrev_i32_e32 v2, v6, v2 399; GCN-NEXT: v_ashrrev_i32_e32 v3, v7, v3 400; GCN-NEXT: s_setpc_b64 s[30:31] 401; 402; GFX10-LABEL: v_ashr_v4i32: 403; GFX10: ; %bb.0: 404; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 405; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 406; GFX10-NEXT: v_ashrrev_i32_e32 v0, v4, v0 407; GFX10-NEXT: v_ashrrev_i32_e32 v1, v5, v1 408; GFX10-NEXT: v_ashrrev_i32_e32 v2, v6, v2 409; GFX10-NEXT: v_ashrrev_i32_e32 v3, v7, v3 410; GFX10-NEXT: s_setpc_b64 s[30:31] 411 %result = ashr <4 x i32> %value, %amount 412 ret <4 x i32> %result 413} 414 415define amdgpu_ps <4 x i32> @s_ashr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) { 416; GCN-LABEL: s_ashr_v4i32: 417; GCN: ; %bb.0: 418; GCN-NEXT: s_ashr_i32 s0, s0, s4 419; GCN-NEXT: s_ashr_i32 s1, s1, s5 420; GCN-NEXT: s_ashr_i32 s2, s2, s6 421; GCN-NEXT: s_ashr_i32 s3, s3, s7 422; GCN-NEXT: ; return to shader part epilog 423; 424; GFX10-LABEL: s_ashr_v4i32: 425; GFX10: ; %bb.0: 426; GFX10-NEXT: s_ashr_i32 s0, s0, s4 427; GFX10-NEXT: s_ashr_i32 s1, s1, s5 428; GFX10-NEXT: s_ashr_i32 s2, s2, s6 429; GFX10-NEXT: s_ashr_i32 s3, s3, s7 430; GFX10-NEXT: ; return to shader part epilog 431 %result = ashr <4 x i32> %value, %amount 432 ret <4 x i32> %result 433} 434 435define <5 x i32> @v_ashr_v5i32(<5 x i32> %value, <5 x i32> %amount) { 436; GCN-LABEL: v_ashr_v5i32: 437; GCN: ; %bb.0: 438; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 439; GCN-NEXT: v_ashrrev_i32_e32 v0, v5, v0 440; GCN-NEXT: v_ashrrev_i32_e32 v1, v6, v1 441; GCN-NEXT: v_ashrrev_i32_e32 v2, v7, v2 442; GCN-NEXT: v_ashrrev_i32_e32 v3, v8, v3 443; GCN-NEXT: v_ashrrev_i32_e32 v4, v9, v4 444; GCN-NEXT: s_setpc_b64 s[30:31] 445; 446; GFX10-LABEL: v_ashr_v5i32: 447; GFX10: ; %bb.0: 448; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 449; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 450; GFX10-NEXT: v_ashrrev_i32_e32 v0, v5, v0 451; GFX10-NEXT: v_ashrrev_i32_e32 v1, v6, v1 452; GFX10-NEXT: v_ashrrev_i32_e32 v2, v7, v2 453; GFX10-NEXT: v_ashrrev_i32_e32 v3, v8, v3 454; GFX10-NEXT: v_ashrrev_i32_e32 v4, v9, v4 455; GFX10-NEXT: s_setpc_b64 s[30:31] 456 %result = ashr <5 x i32> %value, %amount 457 ret <5 x i32> %result 458} 459 460define amdgpu_ps <5 x i32> @s_ashr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) { 461; GCN-LABEL: s_ashr_v5i32: 462; GCN: ; %bb.0: 463; GCN-NEXT: s_ashr_i32 s0, s0, s5 464; GCN-NEXT: s_ashr_i32 s1, s1, s6 465; GCN-NEXT: s_ashr_i32 s2, s2, s7 466; GCN-NEXT: s_ashr_i32 s3, s3, s8 467; GCN-NEXT: s_ashr_i32 s4, s4, s9 468; GCN-NEXT: ; return to shader part epilog 469; 470; GFX10-LABEL: s_ashr_v5i32: 471; GFX10: ; %bb.0: 472; GFX10-NEXT: s_ashr_i32 s0, s0, s5 473; GFX10-NEXT: s_ashr_i32 s1, s1, s6 474; GFX10-NEXT: s_ashr_i32 s2, s2, s7 475; GFX10-NEXT: s_ashr_i32 s3, s3, s8 476; GFX10-NEXT: s_ashr_i32 s4, s4, s9 477; GFX10-NEXT: ; return to shader part epilog 478 %result = ashr <5 x i32> %value, %amount 479 ret <5 x i32> %result 480} 481 482define <16 x i32> @v_ashr_v16i32(<16 x i32> %value, <16 x i32> %amount) { 483; GCN-LABEL: v_ashr_v16i32: 484; GCN: ; %bb.0: 485; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 486; GCN-NEXT: v_ashrrev_i32_e32 v0, v16, v0 487; GCN-NEXT: v_ashrrev_i32_e32 v1, v17, v1 488; GCN-NEXT: v_ashrrev_i32_e32 v2, v18, v2 489; GCN-NEXT: v_ashrrev_i32_e32 v3, v19, v3 490; GCN-NEXT: v_ashrrev_i32_e32 v4, v20, v4 491; GCN-NEXT: v_ashrrev_i32_e32 v5, v21, v5 492; GCN-NEXT: v_ashrrev_i32_e32 v6, v22, v6 493; GCN-NEXT: v_ashrrev_i32_e32 v7, v23, v7 494; GCN-NEXT: v_ashrrev_i32_e32 v8, v24, v8 495; GCN-NEXT: v_ashrrev_i32_e32 v9, v25, v9 496; GCN-NEXT: v_ashrrev_i32_e32 v10, v26, v10 497; GCN-NEXT: v_ashrrev_i32_e32 v11, v27, v11 498; GCN-NEXT: v_ashrrev_i32_e32 v12, v28, v12 499; GCN-NEXT: v_ashrrev_i32_e32 v13, v29, v13 500; GCN-NEXT: v_ashrrev_i32_e32 v14, v30, v14 501; GCN-NEXT: v_ashrrev_i32_e32 v15, v31, v15 502; GCN-NEXT: s_setpc_b64 s[30:31] 503; 504; GFX10-LABEL: v_ashr_v16i32: 505; GFX10: ; %bb.0: 506; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 507; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 508; GFX10-NEXT: v_ashrrev_i32_e32 v0, v16, v0 509; GFX10-NEXT: v_ashrrev_i32_e32 v1, v17, v1 510; GFX10-NEXT: v_ashrrev_i32_e32 v2, v18, v2 511; GFX10-NEXT: v_ashrrev_i32_e32 v3, v19, v3 512; GFX10-NEXT: v_ashrrev_i32_e32 v4, v20, v4 513; GFX10-NEXT: v_ashrrev_i32_e32 v5, v21, v5 514; GFX10-NEXT: v_ashrrev_i32_e32 v6, v22, v6 515; GFX10-NEXT: v_ashrrev_i32_e32 v7, v23, v7 516; GFX10-NEXT: v_ashrrev_i32_e32 v8, v24, v8 517; GFX10-NEXT: v_ashrrev_i32_e32 v9, v25, v9 518; GFX10-NEXT: v_ashrrev_i32_e32 v10, v26, v10 519; GFX10-NEXT: v_ashrrev_i32_e32 v11, v27, v11 520; GFX10-NEXT: v_ashrrev_i32_e32 v12, v28, v12 521; GFX10-NEXT: v_ashrrev_i32_e32 v13, v29, v13 522; GFX10-NEXT: v_ashrrev_i32_e32 v14, v30, v14 523; GFX10-NEXT: v_ashrrev_i32_e32 v15, v31, v15 524; GFX10-NEXT: s_setpc_b64 s[30:31] 525 %result = ashr <16 x i32> %value, %amount 526 ret <16 x i32> %result 527} 528 529define amdgpu_ps <16 x i32> @s_ashr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) { 530; GCN-LABEL: s_ashr_v16i32: 531; GCN: ; %bb.0: 532; GCN-NEXT: s_ashr_i32 s0, s0, s16 533; GCN-NEXT: s_ashr_i32 s1, s1, s17 534; GCN-NEXT: s_ashr_i32 s2, s2, s18 535; GCN-NEXT: s_ashr_i32 s3, s3, s19 536; GCN-NEXT: s_ashr_i32 s4, s4, s20 537; GCN-NEXT: s_ashr_i32 s5, s5, s21 538; GCN-NEXT: s_ashr_i32 s6, s6, s22 539; GCN-NEXT: s_ashr_i32 s7, s7, s23 540; GCN-NEXT: s_ashr_i32 s8, s8, s24 541; GCN-NEXT: s_ashr_i32 s9, s9, s25 542; GCN-NEXT: s_ashr_i32 s10, s10, s26 543; GCN-NEXT: s_ashr_i32 s11, s11, s27 544; GCN-NEXT: s_ashr_i32 s12, s12, s28 545; GCN-NEXT: s_ashr_i32 s13, s13, s29 546; GCN-NEXT: s_ashr_i32 s14, s14, s30 547; GCN-NEXT: s_ashr_i32 s15, s15, s31 548; GCN-NEXT: ; return to shader part epilog 549; 550; GFX10-LABEL: s_ashr_v16i32: 551; GFX10: ; %bb.0: 552; GFX10-NEXT: s_ashr_i32 s0, s0, s16 553; GFX10-NEXT: s_ashr_i32 s1, s1, s17 554; GFX10-NEXT: s_ashr_i32 s2, s2, s18 555; GFX10-NEXT: s_ashr_i32 s3, s3, s19 556; GFX10-NEXT: s_ashr_i32 s4, s4, s20 557; GFX10-NEXT: s_ashr_i32 s5, s5, s21 558; GFX10-NEXT: s_ashr_i32 s6, s6, s22 559; GFX10-NEXT: s_ashr_i32 s7, s7, s23 560; GFX10-NEXT: s_ashr_i32 s8, s8, s24 561; GFX10-NEXT: s_ashr_i32 s9, s9, s25 562; GFX10-NEXT: s_ashr_i32 s10, s10, s26 563; GFX10-NEXT: s_ashr_i32 s11, s11, s27 564; GFX10-NEXT: s_ashr_i32 s12, s12, s28 565; GFX10-NEXT: s_ashr_i32 s13, s13, s29 566; GFX10-NEXT: s_ashr_i32 s14, s14, s30 567; GFX10-NEXT: s_ashr_i32 s15, s15, s31 568; GFX10-NEXT: ; return to shader part epilog 569 %result = ashr <16 x i32> %value, %amount 570 ret <16 x i32> %result 571} 572 573define i16 @v_ashr_i16(i16 %value, i16 %amount) { 574; GFX6-LABEL: v_ashr_i16: 575; GFX6: ; %bb.0: 576; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 577; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 578; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 579; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0 580; GFX6-NEXT: s_setpc_b64 s[30:31] 581; 582; GFX8-LABEL: v_ashr_i16: 583; GFX8: ; %bb.0: 584; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 585; GFX8-NEXT: v_ashrrev_i16_e32 v0, v1, v0 586; GFX8-NEXT: s_setpc_b64 s[30:31] 587; 588; GFX9-LABEL: v_ashr_i16: 589; GFX9: ; %bb.0: 590; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 591; GFX9-NEXT: v_ashrrev_i16_e32 v0, v1, v0 592; GFX9-NEXT: s_setpc_b64 s[30:31] 593; 594; GFX10-LABEL: v_ashr_i16: 595; GFX10: ; %bb.0: 596; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 597; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 598; GFX10-NEXT: v_ashrrev_i16 v0, v1, v0 599; GFX10-NEXT: s_setpc_b64 s[30:31] 600 %result = ashr i16 %value, %amount 601 ret i16 %result 602} 603 604define i16 @v_ashr_i16_31(i16 %value) { 605; GCN-LABEL: v_ashr_i16_31: 606; GCN: ; %bb.0: 607; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 608; GCN-NEXT: s_setpc_b64 s[30:31] 609; 610; GFX10-LABEL: v_ashr_i16_31: 611; GFX10: ; %bb.0: 612; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 613; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 614; GFX10-NEXT: s_setpc_b64 s[30:31] 615 %result = ashr i16 %value, 31 616 ret i16 %result 617} 618 619define amdgpu_ps i16 @s_ashr_i16(i16 inreg %value, i16 inreg %amount) { 620; GFX6-LABEL: s_ashr_i16: 621; GFX6: ; %bb.0: 622; GFX6-NEXT: s_and_b32 s1, s1, 0xffff 623; GFX6-NEXT: s_sext_i32_i16 s0, s0 624; GFX6-NEXT: s_ashr_i32 s0, s0, s1 625; GFX6-NEXT: ; return to shader part epilog 626; 627; GFX8-LABEL: s_ashr_i16: 628; GFX8: ; %bb.0: 629; GFX8-NEXT: s_sext_i32_i16 s0, s0 630; GFX8-NEXT: s_sext_i32_i16 s1, s1 631; GFX8-NEXT: s_ashr_i32 s0, s0, s1 632; GFX8-NEXT: ; return to shader part epilog 633; 634; GFX9-LABEL: s_ashr_i16: 635; GFX9: ; %bb.0: 636; GFX9-NEXT: s_sext_i32_i16 s0, s0 637; GFX9-NEXT: s_sext_i32_i16 s1, s1 638; GFX9-NEXT: s_ashr_i32 s0, s0, s1 639; GFX9-NEXT: ; return to shader part epilog 640; 641; GFX10-LABEL: s_ashr_i16: 642; GFX10: ; %bb.0: 643; GFX10-NEXT: s_sext_i32_i16 s0, s0 644; GFX10-NEXT: s_sext_i32_i16 s1, s1 645; GFX10-NEXT: s_ashr_i32 s0, s0, s1 646; GFX10-NEXT: ; return to shader part epilog 647 %result = ashr i16 %value, %amount 648 ret i16 %result 649} 650 651define amdgpu_ps i16 @s_ashr_i16_15(i16 inreg %value) { 652; GCN-LABEL: s_ashr_i16_15: 653; GCN: ; %bb.0: 654; GCN-NEXT: s_sext_i32_i16 s0, s0 655; GCN-NEXT: s_ashr_i32 s0, s0, 15 656; GCN-NEXT: ; return to shader part epilog 657; 658; GFX10-LABEL: s_ashr_i16_15: 659; GFX10: ; %bb.0: 660; GFX10-NEXT: s_sext_i32_i16 s0, s0 661; GFX10-NEXT: s_ashr_i32 s0, s0, 15 662; GFX10-NEXT: ; return to shader part epilog 663 %result = ashr i16 %value, 15 664 ret i16 %result 665} 666 667define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) { 668; GFX6-LABEL: ashr_i16_sv: 669; GFX6: ; %bb.0: 670; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 671; GFX6-NEXT: s_sext_i32_i16 s0, s0 672; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0 673; GFX6-NEXT: ; return to shader part epilog 674; 675; GFX8-LABEL: ashr_i16_sv: 676; GFX8: ; %bb.0: 677; GFX8-NEXT: v_ashrrev_i16_e64 v0, v0, s0 678; GFX8-NEXT: ; return to shader part epilog 679; 680; GFX9-LABEL: ashr_i16_sv: 681; GFX9: ; %bb.0: 682; GFX9-NEXT: v_ashrrev_i16_e64 v0, v0, s0 683; GFX9-NEXT: ; return to shader part epilog 684; 685; GFX10-LABEL: ashr_i16_sv: 686; GFX10: ; %bb.0: 687; GFX10-NEXT: v_ashrrev_i16 v0, v0, s0 688; GFX10-NEXT: ; return to shader part epilog 689 %result = ashr i16 %value, %amount 690 %cast = bitcast i16 %result to half 691 ret half %cast 692} 693 694define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) { 695; GFX6-LABEL: ashr_i16_vs: 696; GFX6: ; %bb.0: 697; GFX6-NEXT: s_and_b32 s0, s0, 0xffff 698; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 699; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0 700; GFX6-NEXT: ; return to shader part epilog 701; 702; GFX8-LABEL: ashr_i16_vs: 703; GFX8: ; %bb.0: 704; GFX8-NEXT: v_ashrrev_i16_e32 v0, s0, v0 705; GFX8-NEXT: ; return to shader part epilog 706; 707; GFX9-LABEL: ashr_i16_vs: 708; GFX9: ; %bb.0: 709; GFX9-NEXT: v_ashrrev_i16_e32 v0, s0, v0 710; GFX9-NEXT: ; return to shader part epilog 711; 712; GFX10-LABEL: ashr_i16_vs: 713; GFX10: ; %bb.0: 714; GFX10-NEXT: v_ashrrev_i16 v0, s0, v0 715; GFX10-NEXT: ; return to shader part epilog 716 %result = ashr i16 %value, %amount 717 %cast = bitcast i16 %result to half 718 ret half %cast 719} 720 721define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) { 722; GFX6-LABEL: v_ashr_v2i16: 723; GFX6: ; %bb.0: 724; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 725; GFX6-NEXT: s_mov_b32 s4, 0xffff 726; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0 727; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1 728; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 729; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 730; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0 731; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 16 732; GFX6-NEXT: v_ashrrev_i32_e32 v1, v3, v1 733; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 734; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 735; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 736; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 737; GFX6-NEXT: s_setpc_b64 s[30:31] 738; 739; GFX8-LABEL: v_ashr_v2i16: 740; GFX8: ; %bb.0: 741; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 742; GFX8-NEXT: v_ashrrev_i16_e32 v2, v1, v0 743; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 744; GFX8-NEXT: v_or_b32_e32 v0, v2, v0 745; GFX8-NEXT: s_setpc_b64 s[30:31] 746; 747; GFX9-LABEL: v_ashr_v2i16: 748; GFX9: ; %bb.0: 749; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 750; GFX9-NEXT: v_pk_ashrrev_i16 v0, v1, v0 751; GFX9-NEXT: s_setpc_b64 s[30:31] 752; 753; GFX10-LABEL: v_ashr_v2i16: 754; GFX10: ; %bb.0: 755; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 756; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 757; GFX10-NEXT: v_pk_ashrrev_i16 v0, v1, v0 758; GFX10-NEXT: s_setpc_b64 s[30:31] 759 %result = ashr <2 x i16> %value, %amount 760 ret <2 x i16> %result 761} 762 763define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) { 764; GFX6-LABEL: v_ashr_v2i16_15: 765; GFX6: ; %bb.0: 766; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 767; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 768; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 769; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 770; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v1 771; GFX6-NEXT: s_mov_b32 s4, 0xffff 772; GFX6-NEXT: v_ashrrev_i32_e32 v0, 15, v0 773; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 774; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 775; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 776; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 777; GFX6-NEXT: s_setpc_b64 s[30:31] 778; 779; GFX8-LABEL: v_ashr_v2i16_15: 780; GFX8: ; %bb.0: 781; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 782; GFX8-NEXT: v_mov_b32_e32 v2, 15 783; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v0 784; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 785; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 786; GFX8-NEXT: s_setpc_b64 s[30:31] 787; 788; GFX9-LABEL: v_ashr_v2i16_15: 789; GFX9: ; %bb.0: 790; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 791; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1] 792; GFX9-NEXT: s_setpc_b64 s[30:31] 793; 794; GFX10-LABEL: v_ashr_v2i16_15: 795; GFX10: ; %bb.0: 796; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 797; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 798; GFX10-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1] 799; GFX10-NEXT: s_setpc_b64 s[30:31] 800 %result = ashr <2 x i16> %value, <i16 15, i16 15> 801 ret <2 x i16> %result 802} 803 804define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) { 805; GFX6-LABEL: s_ashr_v2i16: 806; GFX6: ; %bb.0: 807; GFX6-NEXT: s_mov_b32 s4, 0xffff 808; GFX6-NEXT: s_lshr_b32 s2, s0, 16 809; GFX6-NEXT: s_lshr_b32 s3, s1, 16 810; GFX6-NEXT: s_and_b32 s1, s1, s4 811; GFX6-NEXT: s_sext_i32_i16 s0, s0 812; GFX6-NEXT: s_ashr_i32 s0, s0, s1 813; GFX6-NEXT: s_sext_i32_i16 s1, s2 814; GFX6-NEXT: s_ashr_i32 s1, s1, s3 815; GFX6-NEXT: s_and_b32 s1, s1, s4 816; GFX6-NEXT: s_and_b32 s0, s0, s4 817; GFX6-NEXT: s_lshl_b32 s1, s1, 16 818; GFX6-NEXT: s_or_b32 s0, s0, s1 819; GFX6-NEXT: ; return to shader part epilog 820; 821; GFX8-LABEL: s_ashr_v2i16: 822; GFX8: ; %bb.0: 823; GFX8-NEXT: s_lshr_b32 s2, s0, 16 824; GFX8-NEXT: s_lshr_b32 s3, s1, 16 825; GFX8-NEXT: s_sext_i32_i16 s0, s0 826; GFX8-NEXT: s_sext_i32_i16 s1, s1 827; GFX8-NEXT: s_sext_i32_i16 s2, s2 828; GFX8-NEXT: s_sext_i32_i16 s3, s3 829; GFX8-NEXT: s_ashr_i32 s0, s0, s1 830; GFX8-NEXT: s_ashr_i32 s1, s2, s3 831; GFX8-NEXT: s_lshl_b32 s1, s1, 16 832; GFX8-NEXT: s_and_b32 s0, s0, 0xffff 833; GFX8-NEXT: s_or_b32 s0, s1, s0 834; GFX8-NEXT: ; return to shader part epilog 835; 836; GFX9-LABEL: s_ashr_v2i16: 837; GFX9: ; %bb.0: 838; GFX9-NEXT: s_sext_i32_i16 s2, s0 839; GFX9-NEXT: s_sext_i32_i16 s3, s1 840; GFX9-NEXT: s_ashr_i32 s0, s0, 16 841; GFX9-NEXT: s_ashr_i32 s1, s1, 16 842; GFX9-NEXT: s_ashr_i32 s2, s2, s3 843; GFX9-NEXT: s_ashr_i32 s0, s0, s1 844; GFX9-NEXT: s_pack_ll_b32_b16 s0, s2, s0 845; GFX9-NEXT: ; return to shader part epilog 846; 847; GFX10-LABEL: s_ashr_v2i16: 848; GFX10: ; %bb.0: 849; GFX10-NEXT: s_sext_i32_i16 s2, s0 850; GFX10-NEXT: s_sext_i32_i16 s3, s1 851; GFX10-NEXT: s_ashr_i32 s0, s0, 16 852; GFX10-NEXT: s_ashr_i32 s1, s1, 16 853; GFX10-NEXT: s_ashr_i32 s2, s2, s3 854; GFX10-NEXT: s_ashr_i32 s0, s0, s1 855; GFX10-NEXT: s_pack_ll_b32_b16 s0, s2, s0 856; GFX10-NEXT: ; return to shader part epilog 857 %result = ashr <2 x i16> %value, %amount 858 %cast = bitcast <2 x i16> %result to i32 859 ret i32 %cast 860} 861 862define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { 863; GFX6-LABEL: ashr_v2i16_sv: 864; GFX6: ; %bb.0: 865; GFX6-NEXT: s_mov_b32 s2, 0xffff 866; GFX6-NEXT: s_lshr_b32 s1, s0, 16 867; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 868; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 869; GFX6-NEXT: s_sext_i32_i16 s0, s0 870; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0 871; GFX6-NEXT: s_sext_i32_i16 s0, s1 872; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1 873; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 874; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 875; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 876; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 877; GFX6-NEXT: ; return to shader part epilog 878; 879; GFX8-LABEL: ashr_v2i16_sv: 880; GFX8: ; %bb.0: 881; GFX8-NEXT: s_lshr_b32 s1, s0, 16 882; GFX8-NEXT: v_mov_b32_e32 v2, s1 883; GFX8-NEXT: v_ashrrev_i16_e64 v1, v0, s0 884; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 885; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 886; GFX8-NEXT: ; return to shader part epilog 887; 888; GFX9-LABEL: ashr_v2i16_sv: 889; GFX9: ; %bb.0: 890; GFX9-NEXT: v_pk_ashrrev_i16 v0, v0, s0 891; GFX9-NEXT: ; return to shader part epilog 892; 893; GFX10-LABEL: ashr_v2i16_sv: 894; GFX10: ; %bb.0: 895; GFX10-NEXT: v_pk_ashrrev_i16 v0, v0, s0 896; GFX10-NEXT: ; return to shader part epilog 897 %result = ashr <2 x i16> %value, %amount 898 %cast = bitcast <2 x i16> %result to float 899 ret float %cast 900} 901 902define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) { 903; GFX6-LABEL: ashr_v2i16_vs: 904; GFX6: ; %bb.0: 905; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 906; GFX6-NEXT: s_lshr_b32 s1, s0, 16 907; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 908; GFX6-NEXT: s_mov_b32 s2, 0xffff 909; GFX6-NEXT: v_ashrrev_i32_e32 v1, s1, v1 910; GFX6-NEXT: s_and_b32 s0, s0, s2 911; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 912; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0 913; GFX6-NEXT: v_and_b32_e32 v1, s2, v1 914; GFX6-NEXT: v_and_b32_e32 v0, s2, v0 915; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 916; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 917; GFX6-NEXT: ; return to shader part epilog 918; 919; GFX8-LABEL: ashr_v2i16_vs: 920; GFX8: ; %bb.0: 921; GFX8-NEXT: s_lshr_b32 s1, s0, 16 922; GFX8-NEXT: v_mov_b32_e32 v2, s1 923; GFX8-NEXT: v_ashrrev_i16_e32 v1, s0, v0 924; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 925; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 926; GFX8-NEXT: ; return to shader part epilog 927; 928; GFX9-LABEL: ashr_v2i16_vs: 929; GFX9: ; %bb.0: 930; GFX9-NEXT: v_pk_ashrrev_i16 v0, s0, v0 931; GFX9-NEXT: ; return to shader part epilog 932; 933; GFX10-LABEL: ashr_v2i16_vs: 934; GFX10: ; %bb.0: 935; GFX10-NEXT: v_pk_ashrrev_i16 v0, s0, v0 936; GFX10-NEXT: ; return to shader part epilog 937 %result = ashr <2 x i16> %value, %amount 938 %cast = bitcast <2 x i16> %result to float 939 ret float %cast 940} 941 942; FIXME 943; define <3 x i16> @v_ashr_v3i16(<3 x i16> %value, <3 x i16> %amount) { 944; %result = ashr <3 x i16> %value, %amount 945; ret <3 x i16> %result 946; } 947 948; define amdgpu_ps <3 x i16> @s_ashr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) { 949; %result = ashr <3 x i16> %value, %amount 950; ret <3 x i16> %result 951; } 952 953define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) { 954; GFX6-LABEL: v_ashr_v4i16: 955; GFX6: ; %bb.0: 956; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 957; GFX6-NEXT: s_mov_b32 s4, 0xffff 958; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 959; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 960; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0 961; GFX6-NEXT: v_and_b32_e32 v4, s4, v5 962; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 963; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v1 964; GFX6-NEXT: v_and_b32_e32 v4, s4, v6 965; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 966; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 967; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v2 968; GFX6-NEXT: v_and_b32_e32 v4, s4, v7 969; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 970; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v3 971; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 972; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 973; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 974; GFX6-NEXT: v_and_b32_e32 v1, s4, v2 975; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 976; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 977; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 978; GFX6-NEXT: s_setpc_b64 s[30:31] 979; 980; GFX8-LABEL: v_ashr_v4i16: 981; GFX8: ; %bb.0: 982; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 983; GFX8-NEXT: v_ashrrev_i16_e32 v4, v2, v0 984; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 985; GFX8-NEXT: v_ashrrev_i16_e32 v2, v3, v1 986; GFX8-NEXT: v_ashrrev_i16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 987; GFX8-NEXT: v_or_b32_e32 v0, v4, v0 988; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 989; GFX8-NEXT: s_setpc_b64 s[30:31] 990; 991; GFX9-LABEL: v_ashr_v4i16: 992; GFX9: ; %bb.0: 993; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 994; GFX9-NEXT: v_pk_ashrrev_i16 v0, v2, v0 995; GFX9-NEXT: v_pk_ashrrev_i16 v1, v3, v1 996; GFX9-NEXT: s_setpc_b64 s[30:31] 997; 998; GFX10-LABEL: v_ashr_v4i16: 999; GFX10: ; %bb.0: 1000; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1001; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1002; GFX10-NEXT: v_pk_ashrrev_i16 v0, v2, v0 1003; GFX10-NEXT: v_pk_ashrrev_i16 v1, v3, v1 1004; GFX10-NEXT: s_setpc_b64 s[30:31] 1005 %result = ashr <4 x i16> %value, %amount 1006 %cast = bitcast <4 x i16> %result to <2 x float> 1007 ret <2 x float> %cast 1008} 1009 1010define amdgpu_ps <2 x i32> @s_ashr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) { 1011; GFX6-LABEL: s_ashr_v4i16: 1012; GFX6: ; %bb.0: 1013; GFX6-NEXT: s_mov_b32 s8, 0xffff 1014; GFX6-NEXT: s_and_b32 s4, s4, s8 1015; GFX6-NEXT: s_sext_i32_i16 s0, s0 1016; GFX6-NEXT: s_ashr_i32 s0, s0, s4 1017; GFX6-NEXT: s_and_b32 s4, s5, s8 1018; GFX6-NEXT: s_sext_i32_i16 s1, s1 1019; GFX6-NEXT: s_ashr_i32 s1, s1, s4 1020; GFX6-NEXT: s_and_b32 s4, s6, s8 1021; GFX6-NEXT: s_sext_i32_i16 s2, s2 1022; GFX6-NEXT: s_and_b32 s1, s1, s8 1023; GFX6-NEXT: s_ashr_i32 s2, s2, s4 1024; GFX6-NEXT: s_and_b32 s4, s7, s8 1025; GFX6-NEXT: s_sext_i32_i16 s3, s3 1026; GFX6-NEXT: s_ashr_i32 s3, s3, s4 1027; GFX6-NEXT: s_and_b32 s0, s0, s8 1028; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1029; GFX6-NEXT: s_or_b32 s0, s0, s1 1030; GFX6-NEXT: s_and_b32 s1, s2, s8 1031; GFX6-NEXT: s_and_b32 s2, s3, s8 1032; GFX6-NEXT: s_lshl_b32 s2, s2, 16 1033; GFX6-NEXT: s_or_b32 s1, s1, s2 1034; GFX6-NEXT: ; return to shader part epilog 1035; 1036; GFX8-LABEL: s_ashr_v4i16: 1037; GFX8: ; %bb.0: 1038; GFX8-NEXT: s_lshr_b32 s4, s0, 16 1039; GFX8-NEXT: s_lshr_b32 s6, s2, 16 1040; GFX8-NEXT: s_lshr_b32 s5, s1, 16 1041; GFX8-NEXT: s_lshr_b32 s7, s3, 16 1042; GFX8-NEXT: s_sext_i32_i16 s0, s0 1043; GFX8-NEXT: s_sext_i32_i16 s2, s2 1044; GFX8-NEXT: s_sext_i32_i16 s4, s4 1045; GFX8-NEXT: s_sext_i32_i16 s6, s6 1046; GFX8-NEXT: s_ashr_i32 s0, s0, s2 1047; GFX8-NEXT: s_ashr_i32 s2, s4, s6 1048; GFX8-NEXT: s_mov_b32 s4, 0xffff 1049; GFX8-NEXT: s_sext_i32_i16 s1, s1 1050; GFX8-NEXT: s_sext_i32_i16 s3, s3 1051; GFX8-NEXT: s_sext_i32_i16 s5, s5 1052; GFX8-NEXT: s_sext_i32_i16 s7, s7 1053; GFX8-NEXT: s_ashr_i32 s1, s1, s3 1054; GFX8-NEXT: s_ashr_i32 s3, s5, s7 1055; GFX8-NEXT: s_lshl_b32 s2, s2, 16 1056; GFX8-NEXT: s_and_b32 s0, s0, s4 1057; GFX8-NEXT: s_or_b32 s0, s2, s0 1058; GFX8-NEXT: s_lshl_b32 s2, s3, 16 1059; GFX8-NEXT: s_and_b32 s1, s1, s4 1060; GFX8-NEXT: s_or_b32 s1, s2, s1 1061; GFX8-NEXT: ; return to shader part epilog 1062; 1063; GFX9-LABEL: s_ashr_v4i16: 1064; GFX9: ; %bb.0: 1065; GFX9-NEXT: s_sext_i32_i16 s4, s0 1066; GFX9-NEXT: s_sext_i32_i16 s5, s2 1067; GFX9-NEXT: s_ashr_i32 s0, s0, 16 1068; GFX9-NEXT: s_ashr_i32 s2, s2, 16 1069; GFX9-NEXT: s_ashr_i32 s0, s0, s2 1070; GFX9-NEXT: s_ashr_i32 s4, s4, s5 1071; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s0 1072; GFX9-NEXT: s_sext_i32_i16 s2, s1 1073; GFX9-NEXT: s_sext_i32_i16 s4, s3 1074; GFX9-NEXT: s_ashr_i32 s1, s1, 16 1075; GFX9-NEXT: s_ashr_i32 s3, s3, 16 1076; GFX9-NEXT: s_ashr_i32 s2, s2, s4 1077; GFX9-NEXT: s_ashr_i32 s1, s1, s3 1078; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1 1079; GFX9-NEXT: ; return to shader part epilog 1080; 1081; GFX10-LABEL: s_ashr_v4i16: 1082; GFX10: ; %bb.0: 1083; GFX10-NEXT: s_sext_i32_i16 s4, s0 1084; GFX10-NEXT: s_sext_i32_i16 s5, s2 1085; GFX10-NEXT: s_ashr_i32 s0, s0, 16 1086; GFX10-NEXT: s_ashr_i32 s2, s2, 16 1087; GFX10-NEXT: s_ashr_i32 s4, s4, s5 1088; GFX10-NEXT: s_ashr_i32 s0, s0, s2 1089; GFX10-NEXT: s_sext_i32_i16 s2, s1 1090; GFX10-NEXT: s_sext_i32_i16 s5, s3 1091; GFX10-NEXT: s_ashr_i32 s1, s1, 16 1092; GFX10-NEXT: s_ashr_i32 s3, s3, 16 1093; GFX10-NEXT: s_ashr_i32 s2, s2, s5 1094; GFX10-NEXT: s_ashr_i32 s1, s1, s3 1095; GFX10-NEXT: s_pack_ll_b32_b16 s0, s4, s0 1096; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1 1097; GFX10-NEXT: ; return to shader part epilog 1098 %result = ashr <4 x i16> %value, %amount 1099 %cast = bitcast <4 x i16> %result to <2 x i32> 1100 ret <2 x i32> %cast 1101} 1102 1103; FIXME 1104; define <5 x i16> @v_ashr_v5i16(<5 x i16> %value, <5 x i16> %amount) { 1105; %result = ashr <5 x i16> %value, %amount 1106; ret <5 x i16> %result 1107; } 1108 1109; define amdgpu_ps <5 x i16> @s_ashr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) { 1110; %result = ashr <5 x i16> %value, %amount 1111; ret <5 x i16> %result 1112; } 1113 1114; define <3 x float> @v_ashr_v6i16(<6 x i16> %value, <6 x i16> %amount) { 1115; %result = ashr <6 x i16> %value, %amount 1116; %cast = bitcast <6 x i16> %result to <3 x float> 1117; ret <3 x float> %cast 1118; } 1119 1120; define amdgpu_ps <3 x i32> @s_ashr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) { 1121; %result = ashr <6 x i16> %value, %amount 1122; %cast = bitcast <6 x i16> %result to <3 x i32> 1123; ret <3 x i32> %cast 1124; } 1125 1126define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) { 1127; GFX6-LABEL: v_ashr_v8i16: 1128; GFX6: ; %bb.0: 1129; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1130; GFX6-NEXT: s_mov_b32 s4, 0xffff 1131; GFX6-NEXT: v_and_b32_e32 v8, s4, v8 1132; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 1133; GFX6-NEXT: v_ashrrev_i32_e32 v0, v8, v0 1134; GFX6-NEXT: v_and_b32_e32 v8, s4, v9 1135; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 1136; GFX6-NEXT: v_ashrrev_i32_e32 v1, v8, v1 1137; GFX6-NEXT: v_and_b32_e32 v8, s4, v10 1138; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 1139; GFX6-NEXT: v_ashrrev_i32_e32 v2, v8, v2 1140; GFX6-NEXT: v_and_b32_e32 v8, s4, v11 1141; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 1142; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff 1143; GFX6-NEXT: v_ashrrev_i32_e32 v3, v8, v3 1144; GFX6-NEXT: v_and_b32_e32 v8, s4, v12 1145; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 1146; GFX6-NEXT: v_and_b32_e32 v1, v1, v16 1147; GFX6-NEXT: v_ashrrev_i32_e32 v4, v8, v4 1148; GFX6-NEXT: v_and_b32_e32 v8, s4, v13 1149; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 1150; GFX6-NEXT: v_ashrrev_i32_e32 v5, v8, v5 1151; GFX6-NEXT: v_and_b32_e32 v8, s4, v14 1152; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 1153; GFX6-NEXT: v_and_b32_e32 v0, v0, v16 1154; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1155; GFX6-NEXT: v_ashrrev_i32_e32 v6, v8, v6 1156; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 1157; GFX6-NEXT: v_and_b32_e32 v1, v2, v16 1158; GFX6-NEXT: v_and_b32_e32 v2, v3, v16 1159; GFX6-NEXT: v_and_b32_e32 v8, v15, v16 1160; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 1161; GFX6-NEXT: v_and_b32_e32 v3, v5, v16 1162; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 1163; GFX6-NEXT: v_ashrrev_i32_e32 v7, v8, v7 1164; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 1165; GFX6-NEXT: v_and_b32_e32 v2, v4, v16 1166; GFX6-NEXT: v_and_b32_e32 v4, v7, v16 1167; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 1168; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 1169; GFX6-NEXT: v_and_b32_e32 v3, v6, v16 1170; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4 1171; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 1172; GFX6-NEXT: s_setpc_b64 s[30:31] 1173; 1174; GFX8-LABEL: v_ashr_v8i16: 1175; GFX8: ; %bb.0: 1176; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1177; GFX8-NEXT: v_ashrrev_i16_e32 v8, v4, v0 1178; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1179; GFX8-NEXT: v_ashrrev_i16_e32 v4, v5, v1 1180; GFX8-NEXT: v_ashrrev_i16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1181; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 1182; GFX8-NEXT: v_ashrrev_i16_e32 v4, v6, v2 1183; GFX8-NEXT: v_ashrrev_i16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1184; GFX8-NEXT: v_or_b32_e32 v2, v4, v2 1185; GFX8-NEXT: v_ashrrev_i16_e32 v4, v7, v3 1186; GFX8-NEXT: v_ashrrev_i16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 1187; GFX8-NEXT: v_or_b32_e32 v0, v8, v0 1188; GFX8-NEXT: v_or_b32_e32 v3, v4, v3 1189; GFX8-NEXT: s_setpc_b64 s[30:31] 1190; 1191; GFX9-LABEL: v_ashr_v8i16: 1192; GFX9: ; %bb.0: 1193; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1194; GFX9-NEXT: v_pk_ashrrev_i16 v0, v4, v0 1195; GFX9-NEXT: v_pk_ashrrev_i16 v1, v5, v1 1196; GFX9-NEXT: v_pk_ashrrev_i16 v2, v6, v2 1197; GFX9-NEXT: v_pk_ashrrev_i16 v3, v7, v3 1198; GFX9-NEXT: s_setpc_b64 s[30:31] 1199; 1200; GFX10-LABEL: v_ashr_v8i16: 1201; GFX10: ; %bb.0: 1202; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1203; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1204; GFX10-NEXT: v_pk_ashrrev_i16 v0, v4, v0 1205; GFX10-NEXT: v_pk_ashrrev_i16 v1, v5, v1 1206; GFX10-NEXT: v_pk_ashrrev_i16 v2, v6, v2 1207; GFX10-NEXT: v_pk_ashrrev_i16 v3, v7, v3 1208; GFX10-NEXT: s_setpc_b64 s[30:31] 1209 %result = ashr <8 x i16> %value, %amount 1210 %cast = bitcast <8 x i16> %result to <4 x float> 1211 ret <4 x float> %cast 1212} 1213 1214define amdgpu_ps <4 x i32> @s_ashr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) { 1215; GFX6-LABEL: s_ashr_v8i16: 1216; GFX6: ; %bb.0: 1217; GFX6-NEXT: s_mov_b32 s16, 0xffff 1218; GFX6-NEXT: s_and_b32 s8, s8, s16 1219; GFX6-NEXT: s_sext_i32_i16 s0, s0 1220; GFX6-NEXT: s_ashr_i32 s0, s0, s8 1221; GFX6-NEXT: s_and_b32 s8, s9, s16 1222; GFX6-NEXT: s_sext_i32_i16 s1, s1 1223; GFX6-NEXT: s_ashr_i32 s1, s1, s8 1224; GFX6-NEXT: s_and_b32 s8, s10, s16 1225; GFX6-NEXT: s_sext_i32_i16 s2, s2 1226; GFX6-NEXT: s_ashr_i32 s2, s2, s8 1227; GFX6-NEXT: s_and_b32 s8, s11, s16 1228; GFX6-NEXT: s_sext_i32_i16 s3, s3 1229; GFX6-NEXT: s_ashr_i32 s3, s3, s8 1230; GFX6-NEXT: s_and_b32 s8, s12, s16 1231; GFX6-NEXT: s_sext_i32_i16 s4, s4 1232; GFX6-NEXT: s_and_b32 s1, s1, s16 1233; GFX6-NEXT: s_ashr_i32 s4, s4, s8 1234; GFX6-NEXT: s_and_b32 s8, s13, s16 1235; GFX6-NEXT: s_sext_i32_i16 s5, s5 1236; GFX6-NEXT: s_ashr_i32 s5, s5, s8 1237; GFX6-NEXT: s_and_b32 s8, s14, s16 1238; GFX6-NEXT: s_sext_i32_i16 s6, s6 1239; GFX6-NEXT: s_and_b32 s0, s0, s16 1240; GFX6-NEXT: s_lshl_b32 s1, s1, 16 1241; GFX6-NEXT: s_ashr_i32 s6, s6, s8 1242; GFX6-NEXT: s_or_b32 s0, s0, s1 1243; GFX6-NEXT: s_and_b32 s1, s2, s16 1244; GFX6-NEXT: s_and_b32 s2, s3, s16 1245; GFX6-NEXT: s_and_b32 s8, s15, s16 1246; GFX6-NEXT: s_sext_i32_i16 s7, s7 1247; GFX6-NEXT: s_and_b32 s3, s5, s16 1248; GFX6-NEXT: s_lshl_b32 s2, s2, 16 1249; GFX6-NEXT: s_ashr_i32 s7, s7, s8 1250; GFX6-NEXT: s_or_b32 s1, s1, s2 1251; GFX6-NEXT: s_and_b32 s2, s4, s16 1252; GFX6-NEXT: s_and_b32 s4, s7, s16 1253; GFX6-NEXT: s_lshl_b32 s3, s3, 16 1254; GFX6-NEXT: s_or_b32 s2, s2, s3 1255; GFX6-NEXT: s_and_b32 s3, s6, s16 1256; GFX6-NEXT: s_lshl_b32 s4, s4, 16 1257; GFX6-NEXT: s_or_b32 s3, s3, s4 1258; GFX6-NEXT: ; return to shader part epilog 1259; 1260; GFX8-LABEL: s_ashr_v8i16: 1261; GFX8: ; %bb.0: 1262; GFX8-NEXT: s_lshr_b32 s8, s0, 16 1263; GFX8-NEXT: s_lshr_b32 s12, s4, 16 1264; GFX8-NEXT: s_lshr_b32 s9, s1, 16 1265; GFX8-NEXT: s_lshr_b32 s13, s5, 16 1266; GFX8-NEXT: s_sext_i32_i16 s0, s0 1267; GFX8-NEXT: s_sext_i32_i16 s4, s4 1268; GFX8-NEXT: s_sext_i32_i16 s8, s8 1269; GFX8-NEXT: s_sext_i32_i16 s12, s12 1270; GFX8-NEXT: s_lshr_b32 s10, s2, 16 1271; GFX8-NEXT: s_lshr_b32 s14, s6, 16 1272; GFX8-NEXT: s_ashr_i32 s0, s0, s4 1273; GFX8-NEXT: s_ashr_i32 s4, s8, s12 1274; GFX8-NEXT: s_mov_b32 s8, 0xffff 1275; GFX8-NEXT: s_sext_i32_i16 s1, s1 1276; GFX8-NEXT: s_sext_i32_i16 s5, s5 1277; GFX8-NEXT: s_sext_i32_i16 s9, s9 1278; GFX8-NEXT: s_sext_i32_i16 s13, s13 1279; GFX8-NEXT: s_lshr_b32 s11, s3, 16 1280; GFX8-NEXT: s_lshr_b32 s15, s7, 16 1281; GFX8-NEXT: s_ashr_i32 s1, s1, s5 1282; GFX8-NEXT: s_sext_i32_i16 s2, s2 1283; GFX8-NEXT: s_sext_i32_i16 s6, s6 1284; GFX8-NEXT: s_sext_i32_i16 s10, s10 1285; GFX8-NEXT: s_sext_i32_i16 s14, s14 1286; GFX8-NEXT: s_ashr_i32 s5, s9, s13 1287; GFX8-NEXT: s_lshl_b32 s4, s4, 16 1288; GFX8-NEXT: s_and_b32 s0, s0, s8 1289; GFX8-NEXT: s_ashr_i32 s2, s2, s6 1290; GFX8-NEXT: s_or_b32 s0, s4, s0 1291; GFX8-NEXT: s_sext_i32_i16 s3, s3 1292; GFX8-NEXT: s_sext_i32_i16 s7, s7 1293; GFX8-NEXT: s_sext_i32_i16 s11, s11 1294; GFX8-NEXT: s_sext_i32_i16 s15, s15 1295; GFX8-NEXT: s_ashr_i32 s6, s10, s14 1296; GFX8-NEXT: s_lshl_b32 s4, s5, 16 1297; GFX8-NEXT: s_and_b32 s1, s1, s8 1298; GFX8-NEXT: s_ashr_i32 s3, s3, s7 1299; GFX8-NEXT: s_or_b32 s1, s4, s1 1300; GFX8-NEXT: s_ashr_i32 s7, s11, s15 1301; GFX8-NEXT: s_lshl_b32 s4, s6, 16 1302; GFX8-NEXT: s_and_b32 s2, s2, s8 1303; GFX8-NEXT: s_or_b32 s2, s4, s2 1304; GFX8-NEXT: s_lshl_b32 s4, s7, 16 1305; GFX8-NEXT: s_and_b32 s3, s3, s8 1306; GFX8-NEXT: s_or_b32 s3, s4, s3 1307; GFX8-NEXT: ; return to shader part epilog 1308; 1309; GFX9-LABEL: s_ashr_v8i16: 1310; GFX9: ; %bb.0: 1311; GFX9-NEXT: s_sext_i32_i16 s8, s0 1312; GFX9-NEXT: s_sext_i32_i16 s9, s4 1313; GFX9-NEXT: s_ashr_i32 s0, s0, 16 1314; GFX9-NEXT: s_ashr_i32 s4, s4, 16 1315; GFX9-NEXT: s_ashr_i32 s0, s0, s4 1316; GFX9-NEXT: s_ashr_i32 s8, s8, s9 1317; GFX9-NEXT: s_pack_ll_b32_b16 s0, s8, s0 1318; GFX9-NEXT: s_sext_i32_i16 s4, s1 1319; GFX9-NEXT: s_sext_i32_i16 s8, s5 1320; GFX9-NEXT: s_ashr_i32 s1, s1, 16 1321; GFX9-NEXT: s_ashr_i32 s5, s5, 16 1322; GFX9-NEXT: s_ashr_i32 s1, s1, s5 1323; GFX9-NEXT: s_ashr_i32 s4, s4, s8 1324; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s1 1325; GFX9-NEXT: s_sext_i32_i16 s4, s2 1326; GFX9-NEXT: s_sext_i32_i16 s5, s6 1327; GFX9-NEXT: s_ashr_i32 s2, s2, 16 1328; GFX9-NEXT: s_ashr_i32 s6, s6, 16 1329; GFX9-NEXT: s_ashr_i32 s4, s4, s5 1330; GFX9-NEXT: s_ashr_i32 s2, s2, s6 1331; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2 1332; GFX9-NEXT: s_sext_i32_i16 s4, s3 1333; GFX9-NEXT: s_sext_i32_i16 s5, s7 1334; GFX9-NEXT: s_ashr_i32 s3, s3, 16 1335; GFX9-NEXT: s_ashr_i32 s6, s7, 16 1336; GFX9-NEXT: s_ashr_i32 s4, s4, s5 1337; GFX9-NEXT: s_ashr_i32 s3, s3, s6 1338; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 1339; GFX9-NEXT: ; return to shader part epilog 1340; 1341; GFX10-LABEL: s_ashr_v8i16: 1342; GFX10: ; %bb.0: 1343; GFX10-NEXT: s_sext_i32_i16 s8, s0 1344; GFX10-NEXT: s_sext_i32_i16 s9, s4 1345; GFX10-NEXT: s_ashr_i32 s0, s0, 16 1346; GFX10-NEXT: s_ashr_i32 s4, s4, 16 1347; GFX10-NEXT: s_ashr_i32 s8, s8, s9 1348; GFX10-NEXT: s_ashr_i32 s0, s0, s4 1349; GFX10-NEXT: s_sext_i32_i16 s4, s1 1350; GFX10-NEXT: s_sext_i32_i16 s9, s5 1351; GFX10-NEXT: s_ashr_i32 s1, s1, 16 1352; GFX10-NEXT: s_ashr_i32 s5, s5, 16 1353; GFX10-NEXT: s_ashr_i32 s4, s4, s9 1354; GFX10-NEXT: s_ashr_i32 s1, s1, s5 1355; GFX10-NEXT: s_sext_i32_i16 s5, s6 1356; GFX10-NEXT: s_pack_ll_b32_b16 s1, s4, s1 1357; GFX10-NEXT: s_sext_i32_i16 s4, s2 1358; GFX10-NEXT: s_ashr_i32 s2, s2, 16 1359; GFX10-NEXT: s_ashr_i32 s6, s6, 16 1360; GFX10-NEXT: s_ashr_i32 s4, s4, s5 1361; GFX10-NEXT: s_ashr_i32 s2, s2, s6 1362; GFX10-NEXT: s_sext_i32_i16 s5, s3 1363; GFX10-NEXT: s_sext_i32_i16 s6, s7 1364; GFX10-NEXT: s_ashr_i32 s3, s3, 16 1365; GFX10-NEXT: s_ashr_i32 s7, s7, 16 1366; GFX10-NEXT: s_ashr_i32 s5, s5, s6 1367; GFX10-NEXT: s_ashr_i32 s3, s3, s7 1368; GFX10-NEXT: s_pack_ll_b32_b16 s0, s8, s0 1369; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s2 1370; GFX10-NEXT: s_pack_ll_b32_b16 s3, s5, s3 1371; GFX10-NEXT: ; return to shader part epilog 1372 %result = ashr <8 x i16> %value, %amount 1373 %cast = bitcast <8 x i16> %result to <4 x i32> 1374 ret <4 x i32> %cast 1375} 1376 1377define i64 @v_ashr_i64(i64 %value, i64 %amount) { 1378; GFX6-LABEL: v_ashr_i64: 1379; GFX6: ; %bb.0: 1380; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1381; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v2 1382; GFX6-NEXT: s_setpc_b64 s[30:31] 1383; 1384; GFX8-LABEL: v_ashr_i64: 1385; GFX8: ; %bb.0: 1386; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1387; GFX8-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1388; GFX8-NEXT: s_setpc_b64 s[30:31] 1389; 1390; GFX9-LABEL: v_ashr_i64: 1391; GFX9: ; %bb.0: 1392; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1393; GFX9-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1394; GFX9-NEXT: s_setpc_b64 s[30:31] 1395; 1396; GFX10-LABEL: v_ashr_i64: 1397; GFX10: ; %bb.0: 1398; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1399; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1400; GFX10-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1] 1401; GFX10-NEXT: s_setpc_b64 s[30:31] 1402 %result = ashr i64 %value, %amount 1403 ret i64 %result 1404} 1405 1406define i64 @v_ashr_i64_63(i64 %value) { 1407; GCN-LABEL: v_ashr_i64_63: 1408; GCN: ; %bb.0: 1409; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1410; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v1 1411; GCN-NEXT: v_mov_b32_e32 v1, v0 1412; GCN-NEXT: s_setpc_b64 s[30:31] 1413; 1414; GFX10-LABEL: v_ashr_i64_63: 1415; GFX10: ; %bb.0: 1416; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1417; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1418; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v1 1419; GFX10-NEXT: v_mov_b32_e32 v1, v0 1420; GFX10-NEXT: s_setpc_b64 s[30:31] 1421 %result = ashr i64 %value, 63 1422 ret i64 %result 1423} 1424 1425define i64 @v_ashr_i64_33(i64 %value) { 1426; GCN-LABEL: v_ashr_i64_33: 1427; GCN: ; %bb.0: 1428; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1429; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 1430; GCN-NEXT: v_ashrrev_i32_e32 v0, 1, v1 1431; GCN-NEXT: v_mov_b32_e32 v1, v2 1432; GCN-NEXT: s_setpc_b64 s[30:31] 1433; 1434; GFX10-LABEL: v_ashr_i64_33: 1435; GFX10: ; %bb.0: 1436; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1437; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1438; GFX10-NEXT: v_ashrrev_i32_e32 v0, 1, v1 1439; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v1 1440; GFX10-NEXT: s_setpc_b64 s[30:31] 1441 %result = ashr i64 %value, 33 1442 ret i64 %result 1443} 1444 1445define i64 @v_ashr_i64_32(i64 %value) { 1446; GCN-LABEL: v_ashr_i64_32: 1447; GCN: ; %bb.0: 1448; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1449; GCN-NEXT: v_mov_b32_e32 v0, v1 1450; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1451; GCN-NEXT: s_setpc_b64 s[30:31] 1452; 1453; GFX10-LABEL: v_ashr_i64_32: 1454; GFX10: ; %bb.0: 1455; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1456; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1457; GFX10-NEXT: v_mov_b32_e32 v0, v1 1458; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0 1459; GFX10-NEXT: s_setpc_b64 s[30:31] 1460 %result = ashr i64 %value, 32 1461 ret i64 %result 1462} 1463 1464define i64 @v_ashr_i64_31(i64 %value) { 1465; GFX6-LABEL: v_ashr_i64_31: 1466; GFX6: ; %bb.0: 1467; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1468; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 31 1469; GFX6-NEXT: s_setpc_b64 s[30:31] 1470; 1471; GFX8-LABEL: v_ashr_i64_31: 1472; GFX8: ; %bb.0: 1473; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1474; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1475; GFX8-NEXT: s_setpc_b64 s[30:31] 1476; 1477; GFX9-LABEL: v_ashr_i64_31: 1478; GFX9: ; %bb.0: 1479; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1480; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1481; GFX9-NEXT: s_setpc_b64 s[30:31] 1482; 1483; GFX10-LABEL: v_ashr_i64_31: 1484; GFX10: ; %bb.0: 1485; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1486; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1487; GFX10-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1488; GFX10-NEXT: s_setpc_b64 s[30:31] 1489 %result = ashr i64 %value, 31 1490 ret i64 %result 1491} 1492 1493define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value, i64 inreg %amount) { 1494; GCN-LABEL: s_ashr_i64: 1495; GCN: ; %bb.0: 1496; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], s2 1497; GCN-NEXT: ; return to shader part epilog 1498; 1499; GFX10-LABEL: s_ashr_i64: 1500; GFX10: ; %bb.0: 1501; GFX10-NEXT: s_ashr_i64 s[0:1], s[0:1], s2 1502; GFX10-NEXT: ; return to shader part epilog 1503 %result = ashr i64 %value, %amount 1504 ret i64 %result 1505} 1506 1507define amdgpu_ps i64 @s_ashr_i64_63(i64 inreg %value) { 1508; GCN-LABEL: s_ashr_i64_63: 1509; GCN: ; %bb.0: 1510; GCN-NEXT: s_ashr_i32 s0, s1, 31 1511; GCN-NEXT: s_mov_b32 s1, s0 1512; GCN-NEXT: ; return to shader part epilog 1513; 1514; GFX10-LABEL: s_ashr_i64_63: 1515; GFX10: ; %bb.0: 1516; GFX10-NEXT: s_ashr_i32 s0, s1, 31 1517; GFX10-NEXT: s_mov_b32 s1, s0 1518; GFX10-NEXT: ; return to shader part epilog 1519 %result = ashr i64 %value, 63 1520 ret i64 %result 1521} 1522 1523define amdgpu_ps i64 @s_ashr_i64_33(i64 inreg %value) { 1524; GCN-LABEL: s_ashr_i64_33: 1525; GCN: ; %bb.0: 1526; GCN-NEXT: s_ashr_i32 s2, s1, 31 1527; GCN-NEXT: s_ashr_i32 s0, s1, 1 1528; GCN-NEXT: s_mov_b32 s1, s2 1529; GCN-NEXT: ; return to shader part epilog 1530; 1531; GFX10-LABEL: s_ashr_i64_33: 1532; GFX10: ; %bb.0: 1533; GFX10-NEXT: s_ashr_i32 s0, s1, 1 1534; GFX10-NEXT: s_ashr_i32 s1, s1, 31 1535; GFX10-NEXT: ; return to shader part epilog 1536 %result = ashr i64 %value, 33 1537 ret i64 %result 1538} 1539 1540define amdgpu_ps i64 @s_ashr_i64_32(i64 inreg %value) { 1541; GCN-LABEL: s_ashr_i64_32: 1542; GCN: ; %bb.0: 1543; GCN-NEXT: s_mov_b32 s0, s1 1544; GCN-NEXT: s_ashr_i32 s1, s1, 31 1545; GCN-NEXT: ; return to shader part epilog 1546; 1547; GFX10-LABEL: s_ashr_i64_32: 1548; GFX10: ; %bb.0: 1549; GFX10-NEXT: s_mov_b32 s0, s1 1550; GFX10-NEXT: s_ashr_i32 s1, s1, 31 1551; GFX10-NEXT: ; return to shader part epilog 1552 %result = ashr i64 %value, 32 1553 ret i64 %result 1554} 1555 1556define amdgpu_ps i64 @s_ashr_i64_31(i64 inreg %value) { 1557; GCN-LABEL: s_ashr_i64_31: 1558; GCN: ; %bb.0: 1559; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 31 1560; GCN-NEXT: ; return to shader part epilog 1561; 1562; GFX10-LABEL: s_ashr_i64_31: 1563; GFX10: ; %bb.0: 1564; GFX10-NEXT: s_ashr_i64 s[0:1], s[0:1], 31 1565; GFX10-NEXT: ; return to shader part epilog 1566 %result = ashr i64 %value, 31 1567 ret i64 %result 1568} 1569 1570define amdgpu_ps <2 x float> @ashr_i64_sv(i64 inreg %value, i64 %amount) { 1571; GFX6-LABEL: ashr_i64_sv: 1572; GFX6: ; %bb.0: 1573; GFX6-NEXT: v_ashr_i64 v[0:1], s[0:1], v0 1574; GFX6-NEXT: ; return to shader part epilog 1575; 1576; GFX8-LABEL: ashr_i64_sv: 1577; GFX8: ; %bb.0: 1578; GFX8-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1579; GFX8-NEXT: ; return to shader part epilog 1580; 1581; GFX9-LABEL: ashr_i64_sv: 1582; GFX9: ; %bb.0: 1583; GFX9-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1584; GFX9-NEXT: ; return to shader part epilog 1585; 1586; GFX10-LABEL: ashr_i64_sv: 1587; GFX10: ; %bb.0: 1588; GFX10-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1] 1589; GFX10-NEXT: ; return to shader part epilog 1590 %result = ashr i64 %value, %amount 1591 %cast = bitcast i64 %result to <2 x float> 1592 ret <2 x float> %cast 1593} 1594 1595define amdgpu_ps <2 x float> @ashr_i64_vs(i64 %value, i64 inreg %amount) { 1596; GFX6-LABEL: ashr_i64_vs: 1597; GFX6: ; %bb.0: 1598; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], s0 1599; GFX6-NEXT: ; return to shader part epilog 1600; 1601; GFX8-LABEL: ashr_i64_vs: 1602; GFX8: ; %bb.0: 1603; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1604; GFX8-NEXT: ; return to shader part epilog 1605; 1606; GFX9-LABEL: ashr_i64_vs: 1607; GFX9: ; %bb.0: 1608; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1609; GFX9-NEXT: ; return to shader part epilog 1610; 1611; GFX10-LABEL: ashr_i64_vs: 1612; GFX10: ; %bb.0: 1613; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1] 1614; GFX10-NEXT: ; return to shader part epilog 1615 %result = ashr i64 %value, %amount 1616 %cast = bitcast i64 %result to <2 x float> 1617 ret <2 x float> %cast 1618} 1619 1620define <2 x i64> @v_ashr_v2i64(<2 x i64> %value, <2 x i64> %amount) { 1621; GFX6-LABEL: v_ashr_v2i64: 1622; GFX6: ; %bb.0: 1623; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1624; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v4 1625; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], v6 1626; GFX6-NEXT: s_setpc_b64 s[30:31] 1627; 1628; GFX8-LABEL: v_ashr_v2i64: 1629; GFX8: ; %bb.0: 1630; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1631; GFX8-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1632; GFX8-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] 1633; GFX8-NEXT: s_setpc_b64 s[30:31] 1634; 1635; GFX9-LABEL: v_ashr_v2i64: 1636; GFX9: ; %bb.0: 1637; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1638; GFX9-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1639; GFX9-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] 1640; GFX9-NEXT: s_setpc_b64 s[30:31] 1641; 1642; GFX10-LABEL: v_ashr_v2i64: 1643; GFX10: ; %bb.0: 1644; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1645; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1646; GFX10-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1] 1647; GFX10-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3] 1648; GFX10-NEXT: s_setpc_b64 s[30:31] 1649 %result = ashr <2 x i64> %value, %amount 1650 ret <2 x i64> %result 1651} 1652 1653define <2 x i64> @v_ashr_v2i64_31(<2 x i64> %value) { 1654; GFX6-LABEL: v_ashr_v2i64_31: 1655; GFX6: ; %bb.0: 1656; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1657; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 31 1658; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], 31 1659; GFX6-NEXT: s_setpc_b64 s[30:31] 1660; 1661; GFX8-LABEL: v_ashr_v2i64_31: 1662; GFX8: ; %bb.0: 1663; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1664; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1665; GFX8-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3] 1666; GFX8-NEXT: s_setpc_b64 s[30:31] 1667; 1668; GFX9-LABEL: v_ashr_v2i64_31: 1669; GFX9: ; %bb.0: 1670; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1671; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1672; GFX9-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3] 1673; GFX9-NEXT: s_setpc_b64 s[30:31] 1674; 1675; GFX10-LABEL: v_ashr_v2i64_31: 1676; GFX10: ; %bb.0: 1677; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1678; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1679; GFX10-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1] 1680; GFX10-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3] 1681; GFX10-NEXT: s_setpc_b64 s[30:31] 1682 %result = ashr <2 x i64> %value, <i64 31, i64 31> 1683 ret <2 x i64> %result 1684} 1685 1686define amdgpu_ps <2 x i64> @s_ashr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) { 1687; GCN-LABEL: s_ashr_v2i64: 1688; GCN: ; %bb.0: 1689; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], s4 1690; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], s6 1691; GCN-NEXT: ; return to shader part epilog 1692; 1693; GFX10-LABEL: s_ashr_v2i64: 1694; GFX10: ; %bb.0: 1695; GFX10-NEXT: s_ashr_i64 s[0:1], s[0:1], s4 1696; GFX10-NEXT: s_ashr_i64 s[2:3], s[2:3], s6 1697; GFX10-NEXT: ; return to shader part epilog 1698 %result = ashr <2 x i64> %value, %amount 1699 ret <2 x i64> %result 1700} 1701