1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s
3
4define <16 x i32> @no_existing_zext(<16 x i8> %a, <16 x i32> %op) {
5; CHECK-LABEL: no_existing_zext:
6; CHECK:       ; %bb.0: ; %entry
7; CHECK-NEXT:    movi.16b v5, #10
8; CHECK-NEXT:    cmhi.16b v0, v0, v5
9; CHECK-NEXT:    sshll.8h v5, v0, #0
10; CHECK-NEXT:    sshll2.8h v0, v0, #0
11; CHECK-NEXT:    sshll.4s v6, v5, #0
12; CHECK-NEXT:    sshll.4s v7, v0, #0
13; CHECK-NEXT:    sshll2.4s v0, v0, #0
14; CHECK-NEXT:    sshll2.4s v5, v5, #0
15; CHECK-NEXT:    and.16b v4, v4, v0
16; CHECK-NEXT:    and.16b v5, v2, v5
17; CHECK-NEXT:    and.16b v2, v3, v7
18; CHECK-NEXT:    and.16b v0, v1, v6
19; CHECK-NEXT:    mov.16b v1, v5
20; CHECK-NEXT:    mov.16b v3, v4
21; CHECK-NEXT:    ret
22entry:
23  %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
24  %sel = select <16 x i1> %cmp, <16 x i32> %op, <16 x i32> zeroinitializer
25  ret <16 x i32> %sel
26}
27
28define <16 x i32> @second_compare_operand_not_splat(<16 x i8> %a, <16 x i8> %b) {
29; CHECK-LABEL: second_compare_operand_not_splat:
30; CHECK:       ; %bb.0: ; %entry
31; CHECK-NEXT:    ushll.8h v2, v0, #0
32; CHECK-NEXT:    ushll2.8h v3, v0, #0
33; CHECK-NEXT:    cmgt.16b v0, v0, v1
34; CHECK-NEXT:    ushll.4s v4, v2, #0
35; CHECK-NEXT:    ushll.4s v5, v3, #0
36; CHECK-NEXT:    ushll2.4s v1, v2, #0
37; CHECK-NEXT:    ushll2.4s v2, v3, #0
38; CHECK-NEXT:    sshll.8h v3, v0, #0
39; CHECK-NEXT:    sshll2.8h v0, v0, #0
40; CHECK-NEXT:    sshll.4s v6, v3, #0
41; CHECK-NEXT:    sshll.4s v7, v0, #0
42; CHECK-NEXT:    sshll2.4s v0, v0, #0
43; CHECK-NEXT:    sshll2.4s v16, v3, #0
44; CHECK-NEXT:    and.16b v3, v2, v0
45; CHECK-NEXT:    and.16b v1, v1, v16
46; CHECK-NEXT:    and.16b v2, v5, v7
47; CHECK-NEXT:    and.16b v0, v4, v6
48; CHECK-NEXT:    ret
49entry:
50  %ext = zext <16 x i8> %a to <16 x i32>
51  %cmp = icmp sgt <16 x i8> %a, %b
52  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
53  ret <16 x i32> %sel
54}
55
56define <16 x i32> @same_zext_used_in_cmp_signed_pred_and_select(<16 x i8> %a) {
57; CHECK-LABEL: same_zext_used_in_cmp_signed_pred_and_select:
58; CHECK:       ; %bb.0: ; %entry
59; CHECK-NEXT:    movi.16b v1, #10
60; CHECK-NEXT:    ushll.8h v2, v0, #0
61; CHECK-NEXT:    ushll2.8h v3, v0, #0
62; CHECK-NEXT:    ushll.4s v4, v2, #0
63; CHECK-NEXT:    cmgt.16b v0, v0, v1
64; CHECK-NEXT:    ushll.4s v5, v3, #0
65; CHECK-NEXT:    ushll2.4s v1, v3, #0
66; CHECK-NEXT:    sshll.8h v3, v0, #0
67; CHECK-NEXT:    sshll2.8h v0, v0, #0
68; CHECK-NEXT:    ushll2.4s v2, v2, #0
69; CHECK-NEXT:    sshll.4s v6, v3, #0
70; CHECK-NEXT:    sshll.4s v7, v0, #0
71; CHECK-NEXT:    sshll2.4s v0, v0, #0
72; CHECK-NEXT:    sshll2.4s v16, v3, #0
73; CHECK-NEXT:    and.16b v3, v1, v0
74; CHECK-NEXT:    and.16b v1, v2, v16
75; CHECK-NEXT:    and.16b v2, v5, v7
76; CHECK-NEXT:    and.16b v0, v4, v6
77; CHECK-NEXT:    ret
78entry:
79  %ext = zext <16 x i8> %a to <16 x i32>
80  %cmp = icmp sgt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
81  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
82  ret <16 x i32> %sel
83}
84
85define <8 x i64> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i64(<8 x i8> %a) {
86; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i64:
87; CHECK:       ; %bb.0:
88; CHECK-NEXT:    movi.8b v1, #10
89; CHECK-NEXT:    ushll.8h v2, v0, #0
90; CHECK-NEXT:    cmhi.8b v0, v0, v1
91; CHECK-NEXT:    ushll.4s v1, v2, #0
92; CHECK-NEXT:    sshll.8h v0, v0, #0
93; CHECK-NEXT:    ushll2.4s v2, v2, #0
94; CHECK-NEXT:    sshll.4s v3, v0, #0
95; CHECK-NEXT:    sshll2.4s v0, v0, #0
96; CHECK-NEXT:    ushll.2d v4, v1, #0
97; CHECK-NEXT:    ushll.2d v5, v2, #0
98; CHECK-NEXT:    ushll2.2d v1, v1, #0
99; CHECK-NEXT:    ushll2.2d v2, v2, #0
100; CHECK-NEXT:    sshll.2d v6, v3, #0
101; CHECK-NEXT:    sshll.2d v7, v0, #0
102; CHECK-NEXT:    sshll2.2d v0, v0, #0
103; CHECK-NEXT:    sshll2.2d v16, v3, #0
104; CHECK-NEXT:    and.16b v3, v2, v0
105; CHECK-NEXT:    and.16b v1, v1, v16
106; CHECK-NEXT:    and.16b v2, v5, v7
107; CHECK-NEXT:    and.16b v0, v4, v6
108; CHECK-NEXT:    ret
109  %ext = zext <8 x i8> %a to <8 x i64>
110  %cmp = icmp ugt <8 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
111  %sel = select <8 x i1> %cmp, <8 x i64> %ext, <8 x i64> zeroinitializer
112  ret <8 x i64> %sel
113}
114
115
116define <16 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v16i32(<16 x i8> %a) {
117; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v16i32:
118; CHECK:       ; %bb.0:
119; CHECK-NEXT:    movi.16b v1, #10
120; CHECK-NEXT:    ushll.8h v2, v0, #0
121; CHECK-NEXT:    ushll2.8h v3, v0, #0
122; CHECK-NEXT:    ushll.4s v4, v2, #0
123; CHECK-NEXT:    cmhi.16b v0, v0, v1
124; CHECK-NEXT:    ushll.4s v5, v3, #0
125; CHECK-NEXT:    ushll2.4s v1, v3, #0
126; CHECK-NEXT:    sshll.8h v3, v0, #0
127; CHECK-NEXT:    sshll2.8h v0, v0, #0
128; CHECK-NEXT:    ushll2.4s v2, v2, #0
129; CHECK-NEXT:    sshll.4s v6, v3, #0
130; CHECK-NEXT:    sshll.4s v7, v0, #0
131; CHECK-NEXT:    sshll2.4s v0, v0, #0
132; CHECK-NEXT:    sshll2.4s v16, v3, #0
133; CHECK-NEXT:    and.16b v3, v1, v0
134; CHECK-NEXT:    and.16b v1, v2, v16
135; CHECK-NEXT:    and.16b v2, v5, v7
136; CHECK-NEXT:    and.16b v0, v4, v6
137; CHECK-NEXT:    ret
138  %ext = zext <16 x i8> %a to <16 x i32>
139  %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
140  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
141  ret <16 x i32> %sel
142}
143
144define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32(<8 x i8> %a) {
145; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32:
146; CHECK:       ; %bb.0:
147; CHECK-NEXT:    movi.8b v1, #10
148; CHECK-NEXT:    ushll.8h v2, v0, #0
149; CHECK-NEXT:    ushll.4s v3, v2, #0
150; CHECK-NEXT:    cmhi.8b v0, v0, v1
151; CHECK-NEXT:    ushll2.4s v1, v2, #0
152; CHECK-NEXT:    sshll.8h v0, v0, #0
153; CHECK-NEXT:    sshll2.4s v2, v0, #0
154; CHECK-NEXT:    sshll.4s v0, v0, #0
155; CHECK-NEXT:    and.16b v1, v1, v2
156; CHECK-NEXT:    and.16b v0, v3, v0
157; CHECK-NEXT:    ret
158  %ext = zext <8 x i8> %a to <8 x i32>
159  %cmp = icmp ugt <8 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
160  %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
161  ret <8 x i32> %sel
162}
163
164define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2(<8 x i16> %a) {
165; check-label: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:
166; check:       ; %bb.0:
167; check-next:    movi.4s v1, #10
168; check-next:    ushll2.4s v2, v0, #0
169; check-next:    ushll.4s v0, v0, #0
170; check-next:    cmhi.4s v3, v2, v1
171; check-next:    cmhi.4s v4, v0, v1
172; check-next:    and.16b v1, v2, v3
173; check-next:    and.16b v0, v0, v4
174; check-next:    ret
175; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:
176; CHECK:       ; %bb.0:
177; CHECK-NEXT:    movi.8h v1, #10
178; CHECK-NEXT:    ushll.4s v2, v0, #0
179; CHECK-NEXT:    cmhi.8h v1, v0, v1
180; CHECK-NEXT:    ushll2.4s v0, v0, #0
181; CHECK-NEXT:    sshll2.4s v3, v1, #0
182; CHECK-NEXT:    sshll.4s v4, v1, #0
183; CHECK-NEXT:    and.16b v1, v0, v3
184; CHECK-NEXT:    and.16b v0, v2, v4
185; CHECK-NEXT:    ret
186  %ext = zext <8 x i16> %a to <8 x i32>
187  %cmp = icmp ugt <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
188  %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
189  ret <8 x i32> %sel
190}
191
192define <7 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v7i32(<7 x i16> %a) {
193; check-label: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:
194; check:       ; %bb.0:
195; check-next:    movi.4s v1, #10
196; check-next:    ushll2.4s v2, v0, #0
197; check-next:    ushll.4s v0, v0, #0
198; check-next:    cmhi.4s v3, v2, v1
199; check-next:    cmhi.4s v4, v0, v1
200; check-next:    and.16b v1, v2, v3
201; check-next:    and.16b v0, v0, v4
202; check-next:    ret
203; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v7i32:
204; CHECK:       ; %bb.0:
205; CHECK-NEXT:    movi.8h v1, #10
206; CHECK-NEXT:    ushll2.4s v2, v0, #0
207; CHECK-NEXT:    cmhi.8h v1, v0, v1
208; CHECK-NEXT:    ushll.4s v0, v0, #0
209; CHECK-NEXT:    sshll.4s v3, v1, #0
210; CHECK-NEXT:    sshll2.4s v1, v1, #0
211; CHECK-NEXT:    and.16b v0, v0, v3
212; CHECK-NEXT:    and.16b v1, v2, v1
213; CHECK-NEXT:    mov.s w1, v0[1]
214; CHECK-NEXT:    mov.s w2, v0[2]
215; CHECK-NEXT:    mov.s w3, v0[3]
216; CHECK-NEXT:    mov.s w5, v1[1]
217; CHECK-NEXT:    mov.s w6, v1[2]
218; CHECK-NEXT:    fmov w0, s0
219; CHECK-NEXT:    fmov w4, s1
220; CHECK-NEXT:    ret
221  %ext = zext <7 x i16> %a to <7 x i32>
222  %cmp = icmp ugt <7 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
223  %sel = select <7 x i1> %cmp, <7 x i32> %ext, <7 x i32> zeroinitializer
224  ret <7 x i32> %sel
225}
226
227define <4 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v4i32(<4 x i16> %a) {
228; check-label: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:
229; check:       ; %bb.0:
230; check-next:    movi.4s v1, #10
231; check-next:    ushll2.4s v2, v0, #0
232; check-next:    ushll.4s v0, v0, #0
233; check-next:    cmhi.4s v3, v2, v1
234; check-next:    cmhi.4s v4, v0, v1
235; check-next:    and.16b v1, v2, v3
236; check-next:    and.16b v0, v0, v4
237; check-next:    ret
238; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v4i32:
239; CHECK:       ; %bb.0:
240; CHECK-NEXT:    movi.4h v1, #10
241; CHECK-NEXT:    ushll.4s v2, v0, #0
242; CHECK-NEXT:    cmhi.4h v0, v0, v1
243; CHECK-NEXT:    sshll.4s v0, v0, #0
244; CHECK-NEXT:    and.16b v0, v2, v0
245; CHECK-NEXT:    ret
246  %ext = zext <4 x i16> %a to <4 x i32>
247  %cmp = icmp ugt <4 x i16> %a, <i16 10, i16 10, i16 10, i16 10>
248  %sel = select <4 x i1> %cmp, <4 x i32> %ext, <4 x i32> zeroinitializer
249  ret <4 x i32> %sel
250}
251
252define <2 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v2i32(<2 x i16> %a) {
253; check-label: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:
254; check:       ; %bb.0:
255; check-next:    movi.4s v1, #10
256; check-next:    ushll2.4s v2, v0, #0
257; check-next:    ushll.4s v0, v0, #0
258; check-next:    cmhi.4s v3, v2, v1
259; check-next:    cmhi.4s v4, v0, v1
260; check-next:    and.16b v1, v2, v3
261; check-next:    and.16b v0, v0, v4
262; check-next:    ret
263; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v2i32:
264; CHECK:       ; %bb.0:
265; CHECK-NEXT:    movi d1, #0x00ffff0000ffff
266; CHECK-NEXT:    movi.2s v2, #10
267; CHECK-NEXT:    and.8b v0, v0, v1
268; CHECK-NEXT:    cmhi.2s v1, v0, v2
269; CHECK-NEXT:    and.8b v0, v0, v1
270; CHECK-NEXT:    ret
271  %ext = zext <2 x i16> %a to <2 x i32>
272  %cmp = icmp ugt <2 x i16> %a, <i16 10, i16 10>
273  %sel = select <2 x i1> %cmp, <2 x i32> %ext, <2 x i32> zeroinitializer
274  ret <2 x i32> %sel
275}
276
277;
278; A variation of @same_zext_used_in_cmp_unsigned_pred_and_select, with with
279; multiple users of the compare.
280define <16 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_other_use(<16 x i8> %a, <16 x i64> %v, <16 x i64>* %ptr) {
281; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_other_use:
282; CHECK:       ; %bb.0: ; %entry
283; CHECK-NEXT:    mov.16b v16, v2
284; CHECK-NEXT:    movi.16b v2, #10
285; CHECK-NEXT:    ushll.8h v18, v0, #0
286; CHECK-NEXT:    ushll2.8h v20, v0, #0
287; CHECK-NEXT:    mov.16b v17, v1
288; CHECK-NEXT:    ldr q1, [sp]
289; CHECK-NEXT:    cmhi.16b v0, v0, v2
290; CHECK-NEXT:    ushll.4s v19, v18, #0
291; CHECK-NEXT:    sshll2.8h v21, v0, #0
292; CHECK-NEXT:    sshll.8h v0, v0, #0
293; CHECK-NEXT:    sshll2.4s v22, v21, #0
294; CHECK-NEXT:    sshll.4s v21, v21, #0
295; CHECK-NEXT:    sshll2.2d v23, v22, #0
296; CHECK-NEXT:    sshll.2d v24, v22, #0
297; CHECK-NEXT:    sshll2.4s v25, v0, #0
298; CHECK-NEXT:    sshll2.2d v26, v21, #0
299; CHECK-NEXT:    sshll.2d v28, v21, #0
300; CHECK-NEXT:    sshll2.2d v27, v25, #0
301; CHECK-NEXT:    sshll.4s v0, v0, #0
302; CHECK-NEXT:    and.16b v1, v1, v23
303; CHECK-NEXT:    and.16b v7, v7, v24
304; CHECK-NEXT:    sshll.2d v29, v25, #0
305; CHECK-NEXT:    stp q7, q1, [x0, #96]
306; CHECK-NEXT:    and.16b v1, v6, v26
307; CHECK-NEXT:    and.16b v5, v5, v28
308; CHECK-NEXT:    ushll.4s v2, v20, #0
309; CHECK-NEXT:    stp q5, q1, [x0, #64]
310; CHECK-NEXT:    ushll2.4s v18, v18, #0
311; CHECK-NEXT:    ushll2.4s v20, v20, #0
312; CHECK-NEXT:    and.16b v1, v4, v27
313; CHECK-NEXT:    sshll2.2d v4, v0, #0
314; CHECK-NEXT:    sshll.2d v5, v0, #0
315; CHECK-NEXT:    and.16b v3, v3, v29
316; CHECK-NEXT:    stp q3, q1, [x0, #32]
317; CHECK-NEXT:    and.16b v3, v20, v22
318; CHECK-NEXT:    and.16b v1, v18, v25
319; CHECK-NEXT:    and.16b v2, v2, v21
320; CHECK-NEXT:    and.16b v0, v19, v0
321; CHECK-NEXT:    and.16b v4, v16, v4
322; CHECK-NEXT:    and.16b v5, v17, v5
323; CHECK-NEXT:    stp q5, q4, [x0]
324; CHECK-NEXT:    ret
325entry:
326  %ext = zext <16 x i8> %a to <16 x i32>
327  %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
328  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
329  %sel.2 = select <16 x i1> %cmp, <16 x i64> %v, <16 x i64> zeroinitializer
330  store <16 x i64> %sel.2, <16 x i64>* %ptr
331  ret <16 x i32> %sel
332}
333
334define <16 x i32> @same_sext_used_in_cmp_signed_pred_and_select_v16i32(<16 x i8> %a) {
335; CHECK-LABEL: same_sext_used_in_cmp_signed_pred_and_select_v16i32:
336; CHECK:       ; %bb.0: ; %entry
337; CHECK-NEXT:    movi.16b v1, #10
338; CHECK-NEXT:    sshll.8h v3, v0, #0
339; CHECK-NEXT:    sshll2.8h v2, v0, #0
340; CHECK-NEXT:    cmgt.16b v0, v0, v1
341; CHECK-NEXT:    ext.16b v1, v3, v3, #8
342; CHECK-NEXT:    sshll.8h v5, v0, #0
343; CHECK-NEXT:    sshll2.8h v0, v0, #0
344; CHECK-NEXT:    ext.16b v4, v2, v2, #8
345; CHECK-NEXT:    ext.16b v6, v5, v5, #8
346; CHECK-NEXT:    ext.16b v7, v0, v0, #8
347; CHECK-NEXT:    and.8b v0, v2, v0
348; CHECK-NEXT:    sshll.4s v2, v0, #0
349; CHECK-NEXT:    and.8b v0, v3, v5
350; CHECK-NEXT:    and.8b v1, v1, v6
351; CHECK-NEXT:    and.8b v3, v4, v7
352; CHECK-NEXT:    sshll.4s v0, v0, #0
353; CHECK-NEXT:    sshll.4s v1, v1, #0
354; CHECK-NEXT:    sshll.4s v3, v3, #0
355; CHECK-NEXT:    ret
356entry:
357  %ext = sext <16 x i8> %a to <16 x i32>
358  %cmp = icmp sgt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
359  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
360  ret <16 x i32> %sel
361}
362
363define <8 x i32> @same_sext_used_in_cmp_signed_pred_and_select_v8i32(<8 x i16> %a) {
364; CHECK-LABEL: same_sext_used_in_cmp_signed_pred_and_select_v8i32:
365; CHECK:       ; %bb.0: ; %entry
366; CHECK-NEXT:    movi.8h v1, #10
367; CHECK-NEXT:    ext.16b v2, v0, v0, #8
368; CHECK-NEXT:    cmgt.8h v1, v0, v1
369; CHECK-NEXT:    ext.16b v3, v1, v1, #8
370; CHECK-NEXT:    and.8b v0, v0, v1
371; CHECK-NEXT:    sshll.4s v0, v0, #0
372; CHECK-NEXT:    and.8b v1, v2, v3
373; CHECK-NEXT:    sshll.4s v1, v1, #0
374; CHECK-NEXT:    ret
375entry:
376  %ext = sext <8 x i16> %a to <8 x i32>
377  %cmp = icmp sgt <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
378  %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
379  ret <8 x i32> %sel
380}
381
382
383
384define <16 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select(<16 x i8> %a) {
385; CHECK-LABEL: same_sext_used_in_cmp_unsigned_pred_and_select:
386; CHECK:       ; %bb.0: ; %entry
387; CHECK-NEXT:    movi.16b v1, #10
388; CHECK-NEXT:    sshll.8h v3, v0, #0
389; CHECK-NEXT:    sshll2.8h v2, v0, #0
390; CHECK-NEXT:    cmhi.16b v0, v0, v1
391; CHECK-NEXT:    ext.16b v1, v3, v3, #8
392; CHECK-NEXT:    sshll.8h v5, v0, #0
393; CHECK-NEXT:    sshll2.8h v0, v0, #0
394; CHECK-NEXT:    ext.16b v4, v2, v2, #8
395; CHECK-NEXT:    ext.16b v6, v5, v5, #8
396; CHECK-NEXT:    ext.16b v7, v0, v0, #8
397; CHECK-NEXT:    and.8b v0, v2, v0
398; CHECK-NEXT:    sshll.4s v2, v0, #0
399; CHECK-NEXT:    and.8b v0, v3, v5
400; CHECK-NEXT:    and.8b v1, v1, v6
401; CHECK-NEXT:    and.8b v3, v4, v7
402; CHECK-NEXT:    sshll.4s v0, v0, #0
403; CHECK-NEXT:    sshll.4s v1, v1, #0
404; CHECK-NEXT:    sshll.4s v3, v3, #0
405; CHECK-NEXT:    ret
406entry:
407  %ext = sext <16 x i8> %a to <16 x i32>
408  %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
409  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
410  ret <16 x i32> %sel
411}
412
413define <16 x i32> @same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred(<16 x i8> %a) {
414; CHECK-LABEL: same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred:
415; CHECK:       ; %bb.0: ; %entry
416; CHECK-NEXT:    movi.2d v1, #0xffffffffffffffff
417; CHECK-NEXT:    ushll.8h v2, v0, #0
418; CHECK-NEXT:    ushll2.8h v3, v0, #0
419; CHECK-NEXT:    ushll.4s v4, v2, #0
420; CHECK-NEXT:    cmgt.16b v0, v0, v1
421; CHECK-NEXT:    ushll.4s v5, v3, #0
422; CHECK-NEXT:    ushll2.4s v1, v3, #0
423; CHECK-NEXT:    sshll.8h v3, v0, #0
424; CHECK-NEXT:    sshll2.8h v0, v0, #0
425; CHECK-NEXT:    ushll2.4s v2, v2, #0
426; CHECK-NEXT:    sshll.4s v6, v3, #0
427; CHECK-NEXT:    sshll.4s v7, v0, #0
428; CHECK-NEXT:    sshll2.4s v0, v0, #0
429; CHECK-NEXT:    sshll2.4s v16, v3, #0
430; CHECK-NEXT:    and.16b v3, v1, v0
431; CHECK-NEXT:    and.16b v1, v2, v16
432; CHECK-NEXT:    and.16b v2, v5, v7
433; CHECK-NEXT:    and.16b v0, v4, v6
434; CHECK-NEXT:    ret
435entry:
436  %ext = zext <16 x i8> %a to <16 x i32>
437  %cmp = icmp sgt <16 x i8> %a,  <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
438  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
439  ret <16 x i32> %sel
440}
441
442define void @extension_in_loop_v16i8_to_v16i32(i8* %src, i32* %dst) {
443; CHECK-LABEL: extension_in_loop_v16i8_to_v16i32:
444; CHECK:       ; %bb.0: ; %entry
445; CHECK-NEXT:    movi.2d v0, #0xffffffffffffffff
446; CHECK-NEXT:    mov x8, xzr
447; CHECK-NEXT:  LBB15_1: ; %loop
448; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
449; CHECK-NEXT:    ldr q1, [x0, x8]
450; CHECK-NEXT:    add x8, x8, #16
451; CHECK-NEXT:    cmp x8, #128
452; CHECK-NEXT:    cmgt.16b v2, v1, v0
453; CHECK-NEXT:    ushll2.8h v3, v1, #0
454; CHECK-NEXT:    sshll2.8h v4, v2, #0
455; CHECK-NEXT:    ushll2.4s v5, v3, #0
456; CHECK-NEXT:    ushll.4s v3, v3, #0
457; CHECK-NEXT:    sshll2.4s v6, v4, #0
458; CHECK-NEXT:    sshll.4s v4, v4, #0
459; CHECK-NEXT:    ushll.8h v1, v1, #0
460; CHECK-NEXT:    sshll.8h v2, v2, #0
461; CHECK-NEXT:    and.16b v5, v5, v6
462; CHECK-NEXT:    and.16b v3, v3, v4
463; CHECK-NEXT:    stp q3, q5, [x1, #32]
464; CHECK-NEXT:    sshll2.4s v4, v2, #0
465; CHECK-NEXT:    sshll.4s v2, v2, #0
466; CHECK-NEXT:    ushll2.4s v3, v1, #0
467; CHECK-NEXT:    ushll.4s v1, v1, #0
468; CHECK-NEXT:    and.16b v3, v3, v4
469; CHECK-NEXT:    and.16b v1, v1, v2
470; CHECK-NEXT:    stp q1, q3, [x1], #64
471; CHECK-NEXT:    b.ne LBB15_1
472; CHECK-NEXT:  ; %bb.2: ; %exit
473; CHECK-NEXT:    ret
474entry:
475  br label %loop
476
477loop:
478  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
479  %src.gep = getelementptr i8, i8* %src, i64 %iv
480  %src.gep.cast = bitcast i8* %src.gep to <16 x i8>*
481  %load = load <16 x i8>, <16 x i8>* %src.gep.cast
482  %cmp = icmp sgt <16 x i8> %load,  <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
483  %ext = zext <16 x i8> %load to <16 x i32>
484  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
485  %dst.gep = getelementptr i32, i32* %dst, i64 %iv
486  %dst.gep.cast = bitcast i32* %dst.gep to <16 x i32>*
487  store <16 x i32> %sel, <16 x i32>* %dst.gep.cast
488  %iv.next = add nuw i64 %iv, 16
489  %ec = icmp eq i64 %iv.next, 128
490  br i1 %ec, label %exit, label %loop
491
492exit:
493  ret void
494}
495
496define void @extension_in_loop_as_shuffle_v16i8_to_v16i32(i8* %src, i32* %dst) {
497; CHECK-LABEL: extension_in_loop_as_shuffle_v16i8_to_v16i32:
498; CHECK:       ; %bb.0: ; %entry
499; CHECK-NEXT:  Lloh0:
500; CHECK-NEXT:    adrp x9, lCPI16_0@PAGE
501; CHECK-NEXT:  Lloh1:
502; CHECK-NEXT:    adrp x10, lCPI16_1@PAGE
503; CHECK-NEXT:  Lloh2:
504; CHECK-NEXT:    adrp x11, lCPI16_2@PAGE
505; CHECK-NEXT:  Lloh3:
506; CHECK-NEXT:    adrp x12, lCPI16_3@PAGE
507; CHECK-NEXT:    movi.2d v2, #0xffffffffffffffff
508; CHECK-NEXT:    mov x8, xzr
509; CHECK-NEXT:  Lloh4:
510; CHECK-NEXT:    ldr q0, [x9, lCPI16_0@PAGEOFF]
511; CHECK-NEXT:  Lloh5:
512; CHECK-NEXT:    ldr q1, [x10, lCPI16_1@PAGEOFF]
513; CHECK-NEXT:  Lloh6:
514; CHECK-NEXT:    ldr q3, [x11, lCPI16_2@PAGEOFF]
515; CHECK-NEXT:  Lloh7:
516; CHECK-NEXT:    ldr q4, [x12, lCPI16_3@PAGEOFF]
517; CHECK-NEXT:  LBB16_1: ; %loop
518; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
519; CHECK-NEXT:    ldr q5, [x0, x8]
520; CHECK-NEXT:    add x8, x8, #16
521; CHECK-NEXT:    cmp x8, #128
522; CHECK-NEXT:    cmgt.16b v6, v5, v2
523; CHECK-NEXT:    tbl.16b v7, { v5 }, v0
524; CHECK-NEXT:    tbl.16b v16, { v5 }, v1
525; CHECK-NEXT:    sshll2.8h v18, v6, #0
526; CHECK-NEXT:    tbl.16b v17, { v5 }, v3
527; CHECK-NEXT:    sshll2.4s v19, v18, #0
528; CHECK-NEXT:    sshll.4s v18, v18, #0
529; CHECK-NEXT:    tbl.16b v5, { v5 }, v4
530; CHECK-NEXT:    sshll.8h v6, v6, #0
531; CHECK-NEXT:    and.16b v7, v7, v19
532; CHECK-NEXT:    and.16b v16, v16, v18
533; CHECK-NEXT:    stp q16, q7, [x1, #32]
534; CHECK-NEXT:    sshll2.4s v7, v6, #0
535; CHECK-NEXT:    sshll.4s v6, v6, #0
536; CHECK-NEXT:    and.16b v7, v17, v7
537; CHECK-NEXT:    and.16b v5, v5, v6
538; CHECK-NEXT:    stp q5, q7, [x1], #64
539; CHECK-NEXT:    b.ne LBB16_1
540; CHECK-NEXT:  ; %bb.2: ; %exit
541; CHECK-NEXT:    ret
542; CHECK-NEXT:    .loh AdrpLdr Lloh3, Lloh7
543; CHECK-NEXT:    .loh AdrpLdr Lloh2, Lloh6
544; CHECK-NEXT:    .loh AdrpLdr Lloh1, Lloh5
545; CHECK-NEXT:    .loh AdrpLdr Lloh0, Lloh4
546entry:
547  br label %loop
548
549loop:
550  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
551  %src.gep = getelementptr i8, i8* %src, i64 %iv
552  %src.gep.cast = bitcast i8* %src.gep to <16 x i8>*
553  %load = load <16 x i8>, <16 x i8>* %src.gep.cast
554  %cmp = icmp sgt <16 x i8> %load,  <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
555  %ext.shuf = shufflevector <16 x i8> %load, <16 x i8> zeroinitializer, <64 x i32> <i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 1, i32 16, i32 16, i32 16, i32 2, i32 16, i32 16, i32 16, i32 3, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 5, i32 16, i32 16, i32 16, i32 6, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 9, i32 16, i32 16, i32 16, i32 10, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 12, i32 16, i32 16, i32 16, i32 13, i32 16, i32 16, i32 16, i32 14, i32 16, i32 16, i32 16, i32 15>
556  %ext = bitcast <64 x i8> %ext.shuf to <16 x i32>
557  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
558  %dst.gep = getelementptr i32, i32* %dst, i64 %iv
559  %dst.gep.cast = bitcast i32* %dst.gep to <16 x i32>*
560  store <16 x i32> %sel, <16 x i32>* %dst.gep.cast
561  %iv.next = add nuw i64 %iv, 16
562  %ec = icmp eq i64 %iv.next, 128
563  br i1 %ec, label %exit, label %loop
564
565exit:
566  ret void
567}
568
569define void @shuffle_in_loop_is_no_extend_v16i8_to_v16i32(i8* %src, i32* %dst) {
570; CHECK-LABEL: shuffle_in_loop_is_no_extend_v16i8_to_v16i32:
571; CHECK:       ; %bb.0: ; %entry
572; CHECK-NEXT:  Lloh8:
573; CHECK-NEXT:    adrp x9, lCPI17_0@PAGE
574; CHECK-NEXT:  Lloh9:
575; CHECK-NEXT:    adrp x10, lCPI17_1@PAGE
576; CHECK-NEXT:  Lloh10:
577; CHECK-NEXT:    adrp x11, lCPI17_2@PAGE
578; CHECK-NEXT:  Lloh11:
579; CHECK-NEXT:    adrp x12, lCPI17_3@PAGE
580; CHECK-NEXT:    movi.2d v2, #0xffffffffffffffff
581; CHECK-NEXT:    mov x8, xzr
582; CHECK-NEXT:  Lloh12:
583; CHECK-NEXT:    ldr q0, [x9, lCPI17_0@PAGEOFF]
584; CHECK-NEXT:  Lloh13:
585; CHECK-NEXT:    ldr q1, [x10, lCPI17_1@PAGEOFF]
586; CHECK-NEXT:  Lloh14:
587; CHECK-NEXT:    ldr q3, [x11, lCPI17_2@PAGEOFF]
588; CHECK-NEXT:  Lloh15:
589; CHECK-NEXT:    ldr q4, [x12, lCPI17_3@PAGEOFF]
590; CHECK-NEXT:  LBB17_1: ; %loop
591; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
592; CHECK-NEXT:    ldr q5, [x0, x8]
593; CHECK-NEXT:    add x8, x8, #16
594; CHECK-NEXT:    cmp x8, #128
595; CHECK-NEXT:    cmgt.16b v6, v5, v2
596; CHECK-NEXT:    tbl.16b v7, { v5 }, v0
597; CHECK-NEXT:    tbl.16b v16, { v5 }, v1
598; CHECK-NEXT:    sshll2.8h v18, v6, #0
599; CHECK-NEXT:    tbl.16b v17, { v5 }, v3
600; CHECK-NEXT:    sshll2.4s v19, v18, #0
601; CHECK-NEXT:    sshll.4s v18, v18, #0
602; CHECK-NEXT:    tbl.16b v5, { v5 }, v4
603; CHECK-NEXT:    sshll.8h v6, v6, #0
604; CHECK-NEXT:    and.16b v7, v7, v19
605; CHECK-NEXT:    and.16b v16, v16, v18
606; CHECK-NEXT:    stp q16, q7, [x1, #32]
607; CHECK-NEXT:    sshll2.4s v7, v6, #0
608; CHECK-NEXT:    sshll.4s v6, v6, #0
609; CHECK-NEXT:    and.16b v7, v17, v7
610; CHECK-NEXT:    and.16b v5, v5, v6
611; CHECK-NEXT:    stp q5, q7, [x1], #64
612; CHECK-NEXT:    b.ne LBB17_1
613; CHECK-NEXT:  ; %bb.2: ; %exit
614; CHECK-NEXT:    ret
615; CHECK-NEXT:    .loh AdrpLdr Lloh11, Lloh15
616; CHECK-NEXT:    .loh AdrpLdr Lloh10, Lloh14
617; CHECK-NEXT:    .loh AdrpLdr Lloh9, Lloh13
618; CHECK-NEXT:    .loh AdrpLdr Lloh8, Lloh12
619entry:
620  br label %loop
621
622loop:
623  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
624  %src.gep = getelementptr i8, i8* %src, i64 %iv
625  %src.gep.cast = bitcast i8* %src.gep to <16 x i8>*
626  %load = load <16 x i8>, <16 x i8>* %src.gep.cast
627  %cmp = icmp sgt <16 x i8> %load,  <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
628  %ext.shuf = shufflevector <16 x i8> %load, <16 x i8> zeroinitializer, <64 x i32> <i32 1, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 1, i32 16, i32 16, i32 16, i32 2, i32 16, i32 16, i32 16, i32 3, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 5, i32 16, i32 16, i32 16, i32 6, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 9, i32 16, i32 16, i32 16, i32 10, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 12, i32 16, i32 16, i32 16, i32 13, i32 16, i32 16, i32 16, i32 14, i32 16, i32 16, i32 16, i32 15>
629  %ext = bitcast <64 x i8> %ext.shuf to <16 x i32>
630  %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
631  %dst.gep = getelementptr i32, i32* %dst, i64 %iv
632  %dst.gep.cast = bitcast i32* %dst.gep to <16 x i32>*
633  store <16 x i32> %sel, <16 x i32>* %dst.gep.cast
634  %iv.next = add nuw i64 %iv, 16
635  %ec = icmp eq i64 %iv.next, 128
636  br i1 %ec, label %exit, label %loop
637
638exit:
639  ret void
640}
641