1; REQUIRES: arm-registered-target
2; REQUIRES: asserts
3; RUN: llc -o /dev/null %s -debug-only=legalize-types 2>&1 | FileCheck %s
4
5; This test check that when v4f64 gets broken down to two v2f64 it maintains
6; the "nnan" flags.
7
8; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
9; CHECK-NEXT: Analyzing result type: v4f64
10; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
11
12; CHECK: Legalizing node: [[VTWOA:t.*]]: v2f64 = BUILD_VECTOR
13; CHECK: Legally typed node: [[VTWOA]]: v2f64 = BUILD_VECTOR
14; CHECK: Legalizing node: [[VTWOB:t.*]]: v2f64 = BUILD_VECTOR
15; CHECK: Legally typed node: [[VTWOB]]: v2f64 = BUILD_VECTOR
16; CHECK: Legalizing node: t30: v2f64 = fmaxnum nnan reassoc [[VTWOB]], [[VTWOA]]
17
18target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
19target triple = "aarch64--linux-gnu"
20
21
22; Function Attrs: norecurse nounwind
23define fastcc double @test(double %a0, double %a1, double %a2, double %a3) unnamed_addr #1 {
24entry:
25 %0 = insertelement <4 x double> undef, double %a0, i32 0
26 %1 = insertelement <4 x double> %0, double %a1, i32 1
27 %2 = insertelement <4 x double> %1, double %a2, i32 2
28 %3 = insertelement <4 x double> %2, double %a3, i32 3
29 %4 = call nnan reassoc double @llvm.vector.reduce.fmax.v4f64(<4 x double> %3)
30 ret double %4
31}
32
33declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
34