1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK
3
4; LEGAL INTEGER TYPES
5
6define <vscale x 2 x i64> @stepvector_nxv2i64() {
7; CHECK-LABEL: stepvector_nxv2i64:
8; CHECK:       // %bb.0: // %entry
9; CHECK-NEXT:    index z0.d, #0, #1
10; CHECK-NEXT:    ret
11entry:
12  %0 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
13  ret <vscale x 2 x i64> %0
14}
15
16define <vscale x 4 x i32> @stepvector_nxv4i32() {
17; CHECK-LABEL: stepvector_nxv4i32:
18; CHECK:       // %bb.0: // %entry
19; CHECK-NEXT:    index z0.s, #0, #1
20; CHECK-NEXT:    ret
21entry:
22  %0 = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
23  ret <vscale x 4 x i32> %0
24}
25
26define <vscale x 8 x i16> @stepvector_nxv8i16() {
27; CHECK-LABEL: stepvector_nxv8i16:
28; CHECK:       // %bb.0: // %entry
29; CHECK-NEXT:    index z0.h, #0, #1
30; CHECK-NEXT:    ret
31entry:
32  %0 = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
33  ret <vscale x 8 x i16> %0
34}
35
36define <vscale x 16 x i8> @stepvector_nxv16i8() {
37; CHECK-LABEL: stepvector_nxv16i8:
38; CHECK:       // %bb.0: // %entry
39; CHECK-NEXT:    index z0.b, #0, #1
40; CHECK-NEXT:    ret
41entry:
42  %0 = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
43  ret <vscale x 16 x i8> %0
44}
45
46; ILLEGAL INTEGER TYPES
47
48define <vscale x 4 x i64> @stepvector_nxv4i64() {
49; CHECK-LABEL: stepvector_nxv4i64:
50; CHECK:       // %bb.0: // %entry
51; CHECK-NEXT:    cntd x8
52; CHECK-NEXT:    mov z1.d, x8
53; CHECK-NEXT:    index z0.d, #0, #1
54; CHECK-NEXT:    add z1.d, z0.d, z1.d
55; CHECK-NEXT:    ret
56entry:
57  %0 = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
58  ret <vscale x 4 x i64> %0
59}
60
61define <vscale x 16 x i32> @stepvector_nxv16i32() {
62; CHECK-LABEL: stepvector_nxv16i32:
63; CHECK:       // %bb.0: // %entry
64; CHECK-NEXT:    cntw x9
65; CHECK-NEXT:    cnth x8
66; CHECK-NEXT:    index z0.s, #0, #1
67; CHECK-NEXT:    mov z1.s, w9
68; CHECK-NEXT:    mov z3.s, w8
69; CHECK-NEXT:    add z1.s, z0.s, z1.s
70; CHECK-NEXT:    add z2.s, z0.s, z3.s
71; CHECK-NEXT:    add z3.s, z1.s, z3.s
72; CHECK-NEXT:    ret
73entry:
74  %0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
75  ret <vscale x 16 x i32> %0
76}
77
78define <vscale x 2 x i32> @stepvector_nxv2i32() {
79; CHECK-LABEL: stepvector_nxv2i32:
80; CHECK:       // %bb.0: // %entry
81; CHECK-NEXT:    index z0.d, #0, #1
82; CHECK-NEXT:    ret
83entry:
84  %0 = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
85  ret <vscale x 2 x i32> %0
86}
87
88define <vscale x 4 x i16> @stepvector_nxv4i16() {
89; CHECK-LABEL: stepvector_nxv4i16:
90; CHECK:       // %bb.0: // %entry
91; CHECK-NEXT:    index z0.s, #0, #1
92; CHECK-NEXT:    ret
93entry:
94  %0 = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
95  ret <vscale x 4 x i16> %0
96}
97
98define <vscale x 8 x i8> @stepvector_nxv8i8() {
99; CHECK-LABEL: stepvector_nxv8i8:
100; CHECK:       // %bb.0: // %entry
101; CHECK-NEXT:    index z0.h, #0, #1
102; CHECK-NEXT:    ret
103entry:
104  %0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
105  ret <vscale x 8 x i8> %0
106}
107
108declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
109declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
110declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
111declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
112
113declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
114declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
115declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
116declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
117declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
118