1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4define void @store_promote_4i8(<vscale x 4 x i8> %data, <vscale x 4 x i8>* %a) {
5; CHECK-LABEL: store_promote_4i8:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    ptrue p0.s
8; CHECK-NEXT:    st1b { z0.s }, p0, [x0]
9; CHECK-NEXT:    ret
10  store <vscale x 4 x i8> %data, <vscale x 4 x i8>* %a
11  ret void
12}
13
14define void @store_split_i16(<vscale x 16 x i16> %data, <vscale x 16 x i16>* %a) {
15; CHECK-LABEL: store_split_i16:
16; CHECK:       // %bb.0:
17; CHECK-NEXT:    ptrue p0.h
18; CHECK-NEXT:    st1h { z1.h }, p0, [x0, #1, mul vl]
19; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
20; CHECK-NEXT:    ret
21  store <vscale x 16 x i16> %data, <vscale x 16 x i16>* %a
22  ret void
23}
24
25define void @store_split_16i32(<vscale x 16 x i32> %data, <vscale x 16 x i32>* %a) {
26; CHECK-LABEL: store_split_16i32:
27; CHECK:       // %bb.0:
28; CHECK-NEXT:    ptrue p0.s
29; CHECK-NEXT:    st1w { z3.s }, p0, [x0, #3, mul vl]
30; CHECK-NEXT:    st1w { z2.s }, p0, [x0, #2, mul vl]
31; CHECK-NEXT:    st1w { z1.s }, p0, [x0, #1, mul vl]
32; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
33; CHECK-NEXT:    ret
34  store <vscale x 16 x i32> %data, <vscale x 16 x i32>* %a
35  ret void
36}
37
38define void @store_split_16i64(<vscale x 16 x i64> %data, <vscale x 16 x i64>* %a) {
39; CHECK-LABEL: store_split_16i64:
40; CHECK:       // %bb.0:
41; CHECK-NEXT:    ptrue p0.d
42; CHECK-NEXT:    st1d { z7.d }, p0, [x0, #7, mul vl]
43; CHECK-NEXT:    st1d { z6.d }, p0, [x0, #6, mul vl]
44; CHECK-NEXT:    st1d { z5.d }, p0, [x0, #5, mul vl]
45; CHECK-NEXT:    st1d { z4.d }, p0, [x0, #4, mul vl]
46; CHECK-NEXT:    st1d { z3.d }, p0, [x0, #3, mul vl]
47; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #2, mul vl]
48; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
49; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
50; CHECK-NEXT:    ret
51  store <vscale x 16 x i64> %data, <vscale x 16 x i64>* %a
52  ret void
53}
54