1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4; LOAD
5
6define <vscale x 4 x i16> @load_promote_4i8(<vscale x 4 x i16>* %a) {
7; CHECK-LABEL: load_promote_4i8:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    ptrue p0.s
10; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
11; CHECK-NEXT:    ret
12  %load = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
13  ret <vscale x 4 x i16> %load
14}
15
16define <vscale x 16 x i16> @load_split_i16(<vscale x 16 x i16>* %a) {
17; CHECK-LABEL: load_split_i16:
18; CHECK:       // %bb.0:
19; CHECK-NEXT:    ptrue p0.h
20; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
21; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x0, #1, mul vl]
22; CHECK-NEXT:    ret
23  %load = load <vscale x 16 x i16>, <vscale x 16 x i16>* %a
24  ret <vscale x 16 x i16> %load
25}
26
27define <vscale x 32 x i16> @load_split_32i16(<vscale x 32 x i16>* %a) {
28; CHECK-LABEL: load_split_32i16:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    ptrue p0.h
31; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
32; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x0, #1, mul vl]
33; CHECK-NEXT:    ld1h { z2.h }, p0/z, [x0, #2, mul vl]
34; CHECK-NEXT:    ld1h { z3.h }, p0/z, [x0, #3, mul vl]
35; CHECK-NEXT:    ret
36  %load = load <vscale x 32 x i16>, <vscale x 32 x i16>* %a
37  ret <vscale x 32 x i16> %load
38}
39
40define <vscale x 16 x i64> @load_split_16i64(<vscale x 16 x i64>* %a) {
41; CHECK-LABEL: load_split_16i64:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    ptrue p0.d
44; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
45; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0, #1, mul vl]
46; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x0, #2, mul vl]
47; CHECK-NEXT:    ld1d { z3.d }, p0/z, [x0, #3, mul vl]
48; CHECK-NEXT:    ld1d { z4.d }, p0/z, [x0, #4, mul vl]
49; CHECK-NEXT:    ld1d { z5.d }, p0/z, [x0, #5, mul vl]
50; CHECK-NEXT:    ld1d { z6.d }, p0/z, [x0, #6, mul vl]
51; CHECK-NEXT:    ld1d { z7.d }, p0/z, [x0, #7, mul vl]
52; CHECK-NEXT:    ret
53  %load = load <vscale x 16 x i64>, <vscale x 16 x i64>* %a
54  ret <vscale x 16 x i64> %load
55}
56