1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK
3
4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
5; CHECK-LABEL: insert_v2i64_nxv2i64:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
8; CHECK-NEXT:    addvl sp, sp, #-1
9; CHECK-NEXT:    ptrue p0.d
10; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
11; CHECK-NEXT:    str q1, [sp]
12; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
13; CHECK-NEXT:    addvl sp, sp, #1
14; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
15; CHECK-NEXT:    ret
16  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)
17  ret <vscale x 2 x i64> %retval
18}
19
20define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
21; CHECK-LABEL: insert_v2i64_nxv2i64_idx2:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
24; CHECK-NEXT:    addvl sp, sp, #-1
25; CHECK-NEXT:    cntd x9
26; CHECK-NEXT:    sub x9, x9, #2 // =2
27; CHECK-NEXT:    mov w8, #2
28; CHECK-NEXT:    cmp x9, #2 // =2
29; CHECK-NEXT:    csel x8, x9, x8, lo
30; CHECK-NEXT:    ptrue p0.d
31; CHECK-NEXT:    lsl x8, x8, #3
32; CHECK-NEXT:    mov x9, sp
33; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
34; CHECK-NEXT:    str q1, [x9, x8]
35; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
36; CHECK-NEXT:    addvl sp, sp, #1
37; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
38; CHECK-NEXT:    ret
39  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
40  ret <vscale x 2 x i64> %retval
41}
42
43define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
44; CHECK-LABEL: insert_v4i32_nxv4i32:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
47; CHECK-NEXT:    addvl sp, sp, #-1
48; CHECK-NEXT:    ptrue p0.s
49; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
50; CHECK-NEXT:    str q1, [sp]
51; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
52; CHECK-NEXT:    addvl sp, sp, #1
53; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
54; CHECK-NEXT:    ret
55  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
56  ret <vscale x 4 x i32> %retval
57}
58
59define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
60; CHECK-LABEL: insert_v4i32_nxv4i32_idx4:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
63; CHECK-NEXT:    addvl sp, sp, #-1
64; CHECK-NEXT:    cntw x9
65; CHECK-NEXT:    sub x9, x9, #4 // =4
66; CHECK-NEXT:    mov w8, #4
67; CHECK-NEXT:    cmp x9, #4 // =4
68; CHECK-NEXT:    csel x8, x9, x8, lo
69; CHECK-NEXT:    ptrue p0.s
70; CHECK-NEXT:    lsl x8, x8, #2
71; CHECK-NEXT:    mov x9, sp
72; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
73; CHECK-NEXT:    str q1, [x9, x8]
74; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
75; CHECK-NEXT:    addvl sp, sp, #1
76; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
77; CHECK-NEXT:    ret
78  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4)
79  ret <vscale x 4 x i32> %retval
80}
81
82define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
83; CHECK-LABEL: insert_v8i16_nxv8i16:
84; CHECK:       // %bb.0:
85; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
86; CHECK-NEXT:    addvl sp, sp, #-1
87; CHECK-NEXT:    ptrue p0.h
88; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
89; CHECK-NEXT:    str q1, [sp]
90; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
91; CHECK-NEXT:    addvl sp, sp, #1
92; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
93; CHECK-NEXT:    ret
94  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)
95  ret <vscale x 8 x i16> %retval
96}
97
98define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
99; CHECK-LABEL: insert_v8i16_nxv8i16_idx8:
100; CHECK:       // %bb.0:
101; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
102; CHECK-NEXT:    addvl sp, sp, #-1
103; CHECK-NEXT:    cnth x9
104; CHECK-NEXT:    sub x9, x9, #8 // =8
105; CHECK-NEXT:    mov w8, #8
106; CHECK-NEXT:    cmp x9, #8 // =8
107; CHECK-NEXT:    csel x8, x9, x8, lo
108; CHECK-NEXT:    ptrue p0.h
109; CHECK-NEXT:    lsl x8, x8, #1
110; CHECK-NEXT:    mov x9, sp
111; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
112; CHECK-NEXT:    str q1, [x9, x8]
113; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
114; CHECK-NEXT:    addvl sp, sp, #1
115; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
116; CHECK-NEXT:    ret
117  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8)
118  ret <vscale x 8 x i16> %retval
119}
120
121define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
122; CHECK-LABEL: insert_v16i8_nxv16i8:
123; CHECK:       // %bb.0:
124; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
125; CHECK-NEXT:    addvl sp, sp, #-1
126; CHECK-NEXT:    ptrue p0.b
127; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
128; CHECK-NEXT:    str q1, [sp]
129; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
130; CHECK-NEXT:    addvl sp, sp, #1
131; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
132; CHECK-NEXT:    ret
133  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)
134  ret <vscale x 16 x i8> %retval
135}
136
137define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
138; CHECK-LABEL: insert_v16i8_nxv16i8_idx16:
139; CHECK:       // %bb.0:
140; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
141; CHECK-NEXT:    addvl sp, sp, #-1
142; CHECK-NEXT:    rdvl x9, #1
143; CHECK-NEXT:    sub x9, x9, #16 // =16
144; CHECK-NEXT:    mov w8, #16
145; CHECK-NEXT:    cmp x9, #16 // =16
146; CHECK-NEXT:    ptrue p0.b
147; CHECK-NEXT:    csel x8, x9, x8, lo
148; CHECK-NEXT:    mov x9, sp
149; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
150; CHECK-NEXT:    str q1, [x9, x8]
151; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
152; CHECK-NEXT:    addvl sp, sp, #1
153; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
154; CHECK-NEXT:    ret
155  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16)
156  ret <vscale x 16 x i8> %retval
157}
158
159
160; Insert subvectors into illegal vectors
161
162define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) {
163; CHECK-LABEL: insert_nxv8i64_nxv16i64:
164; CHECK:       // %bb.0:
165; CHECK-NEXT:    ptrue p0.d
166; CHECK-NEXT:    st1d { z7.d }, p0, [x0, #7, mul vl]
167; CHECK-NEXT:    st1d { z6.d }, p0, [x0, #6, mul vl]
168; CHECK-NEXT:    st1d { z5.d }, p0, [x0, #5, mul vl]
169; CHECK-NEXT:    st1d { z4.d }, p0, [x0, #4, mul vl]
170; CHECK-NEXT:    st1d { z3.d }, p0, [x0, #3, mul vl]
171; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #2, mul vl]
172; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
173; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
174; CHECK-NEXT:    ret
175  %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
176  %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)
177  store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
178  ret void
179}
180
181define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
182; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:
183; CHECK:       // %bb.0:
184; CHECK-NEXT:    ptrue p0.d
185; CHECK-NEXT:    st1d { z3.d }, p0, [x0, #3, mul vl]
186; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #2, mul vl]
187; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
188; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
189; CHECK-NEXT:    ret
190  %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
191  store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
192  ret void
193}
194
195define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
196; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:
197; CHECK:       // %bb.0:
198; CHECK-NEXT:    ptrue p0.d
199; CHECK-NEXT:    st1d { z3.d }, p0, [x0, #7, mul vl]
200; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #6, mul vl]
201; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #5, mul vl]
202; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #4, mul vl]
203; CHECK-NEXT:    ret
204  %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8)
205  store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
206  ret void
207}
208
209define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) {
210; CHECK-LABEL: insert_v2i64_nxv16i64:
211; CHECK:       // %bb.0:
212; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
213; CHECK-NEXT:    addvl sp, sp, #-4
214; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
215; CHECK-NEXT:    .cfi_offset w29, -16
216; CHECK-NEXT:    ptrue p0.d
217; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
218; CHECK-NEXT:    mov x8, sp
219; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
220; CHECK-NEXT:    str q1, [sp, #32]
221; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, #1, mul vl]
222; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x8, #2, mul vl]
223; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x8, #3, mul vl]
224; CHECK-NEXT:    ld1d { z3.d }, p0/z, [sp]
225; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #3, mul vl]
226; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #2, mul vl]
227; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #1, mul vl]
228; CHECK-NEXT:    st1d { z3.d }, p0, [x0]
229; CHECK-NEXT:    addvl sp, sp, #4
230; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
231; CHECK-NEXT:    ret
232  %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
233  %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
234  store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
235  ret void
236}
237
238define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
239; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:
240; CHECK:       // %bb.0:
241; CHECK-NEXT:    ldr q0, [x0]
242; CHECK-NEXT:    ptrue p0.d
243; CHECK-NEXT:    st1d { z0.d }, p0, [x1]
244; CHECK-NEXT:    ret
245  %sv = load <2 x i64>, <2 x i64>* %psv
246  %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0)
247  store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
248  ret void
249}
250
251define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
252; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
253; CHECK:       // %bb.0:
254; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
255; CHECK-NEXT:    addvl sp, sp, #-2
256; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
257; CHECK-NEXT:    .cfi_offset w29, -16
258; CHECK-NEXT:    ldr q0, [x0]
259; CHECK-NEXT:    ptrue p0.d
260; CHECK-NEXT:    mov x8, sp
261; CHECK-NEXT:    str q0, [sp, #16]
262; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, #1, mul vl]
263; CHECK-NEXT:    ld1d { z1.d }, p0/z, [sp]
264; CHECK-NEXT:    st1d { z0.d }, p0, [x1, #1, mul vl]
265; CHECK-NEXT:    st1d { z1.d }, p0, [x1]
266; CHECK-NEXT:    addvl sp, sp, #2
267; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
268; CHECK-NEXT:    ret
269  %sv = load <2 x i64>, <2 x i64>* %psv
270  %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
271  store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
272  ret void
273}
274
275
276; Insert subvectors that need widening
277
278define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind {
279; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef:
280; CHECK:       // %bb.0: // %entry
281; CHECK-NEXT:    mov z0.s, #1 // =0x1
282; CHECK-NEXT:    ret
283entry:
284  %0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
285  %subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
286  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0)
287  ret <vscale x 4 x i32> %retval
288}
289
290define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind {
291; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef:
292; CHECK:       // %bb.0: // %entry
293; CHECK-NEXT:    mov z0.h, #1 // =0x1
294; CHECK-NEXT:    ret
295entry:
296  %0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
297  %subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
298  %retval = call <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0)
299  ret <vscale x 6 x i16> %retval
300}
301
302; Fixed length clamping
303
304define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 {
305; CHECK-LABEL: insert_fixed_v2i64_nxv2i64:
306; CHECK:       // %bb.0:
307; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
308; CHECK-NEXT:    addvl sp, sp, #-1
309; CHECK-NEXT:    cntd x9
310; CHECK-NEXT:    sub x9, x9, #2 // =2
311; CHECK-NEXT:    mov w8, #2
312; CHECK-NEXT:    cmp x9, #2 // =2
313; CHECK-NEXT:    csel x8, x9, x8, lo
314; CHECK-NEXT:    ptrue p0.d
315; CHECK-NEXT:    lsl x8, x8, #3
316; CHECK-NEXT:    mov x9, sp
317; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
318; CHECK-NEXT:    str q1, [x9, x8]
319; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
320; CHECK-NEXT:    addvl sp, sp, #1
321; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
322; CHECK-NEXT:    ret
323  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2)
324  ret <vscale x 2 x i64> %retval
325}
326
327define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 {
328; CHECK-LABEL: insert_fixed_v4i64_nxv2i64:
329; CHECK:       // %bb.0:
330; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
331; CHECK-NEXT:    addvl sp, sp, #-1
332; CHECK-NEXT:    ptrue p0.d, vl4
333; CHECK-NEXT:    cntd x8
334; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0]
335; CHECK-NEXT:    subs x8, x8, #4 // =4
336; CHECK-NEXT:    csel x8, xzr, x8, lo
337; CHECK-NEXT:    mov w9, #4
338; CHECK-NEXT:    cmp x8, #4 // =4
339; CHECK-NEXT:    ptrue p1.d
340; CHECK-NEXT:    csel x8, x8, x9, lo
341; CHECK-NEXT:    mov x9, sp
342; CHECK-NEXT:    st1d { z0.d }, p1, [sp]
343; CHECK-NEXT:    st1d { z1.d }, p0, [x9, x8, lsl #3]
344; CHECK-NEXT:    ld1d { z0.d }, p1/z, [sp]
345; CHECK-NEXT:    addvl sp, sp, #1
346; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
347; CHECK-NEXT:    ret
348  %subvec = load <4 x i64>, <4 x i64>* %ptr
349  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4)
350  ret <vscale x 2 x i64> %retval
351}
352
353attributes #0 = { vscale_range(2,2) }
354
355declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
356declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
357declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
358declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
359
360declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64>, <4 x i64>, i64)
361
362declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
363declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
364declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64)
365declare <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64)
366