1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+bf16 < %s | FileCheck %s --check-prefixes=CHECK 3 4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { 5; CHECK-LABEL: insert_v2i64_nxv2i64: 6; CHECK: // %bb.0: 7; CHECK-NEXT: ptrue p0.d, vl2 8; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 9; CHECK-NEXT: mov z0.d, p0/m, z1.d 10; CHECK-NEXT: ret 11 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0) 12 ret <vscale x 2 x i64> %retval 13} 14 15define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { 16; CHECK-LABEL: insert_v2i64_nxv2i64_idx2: 17; CHECK: // %bb.0: 18; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 19; CHECK-NEXT: addvl sp, sp, #-1 20; CHECK-NEXT: cntd x8 21; CHECK-NEXT: mov w9, #2 22; CHECK-NEXT: sub x8, x8, #2 23; CHECK-NEXT: ptrue p0.d 24; CHECK-NEXT: cmp x8, #2 25; CHECK-NEXT: st1d { z0.d }, p0, [sp] 26; CHECK-NEXT: csel x8, x8, x9, lo 27; CHECK-NEXT: mov x9, sp 28; CHECK-NEXT: lsl x8, x8, #3 29; CHECK-NEXT: str q1, [x9, x8] 30; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 31; CHECK-NEXT: addvl sp, sp, #1 32; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 33; CHECK-NEXT: ret 34 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) 35 ret <vscale x 2 x i64> %retval 36} 37 38define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { 39; CHECK-LABEL: insert_v4i32_nxv4i32: 40; CHECK: // %bb.0: 41; CHECK-NEXT: ptrue p0.s, vl4 42; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 43; CHECK-NEXT: mov z0.s, p0/m, z1.s 44; CHECK-NEXT: ret 45 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0) 46 ret <vscale x 4 x i32> %retval 47} 48 49define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { 50; CHECK-LABEL: insert_v4i32_nxv4i32_idx4: 51; CHECK: // %bb.0: 52; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 53; CHECK-NEXT: addvl sp, sp, #-1 54; CHECK-NEXT: cntw x8 55; CHECK-NEXT: mov w9, #4 56; CHECK-NEXT: sub x8, x8, #4 57; CHECK-NEXT: ptrue p0.s 58; CHECK-NEXT: cmp x8, #4 59; CHECK-NEXT: st1w { z0.s }, p0, [sp] 60; CHECK-NEXT: csel x8, x8, x9, lo 61; CHECK-NEXT: mov x9, sp 62; CHECK-NEXT: lsl x8, x8, #2 63; CHECK-NEXT: str q1, [x9, x8] 64; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] 65; CHECK-NEXT: addvl sp, sp, #1 66; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 67; CHECK-NEXT: ret 68 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4) 69 ret <vscale x 4 x i32> %retval 70} 71 72define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { 73; CHECK-LABEL: insert_v8i16_nxv8i16: 74; CHECK: // %bb.0: 75; CHECK-NEXT: ptrue p0.h, vl8 76; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 77; CHECK-NEXT: mov z0.h, p0/m, z1.h 78; CHECK-NEXT: ret 79 %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0) 80 ret <vscale x 8 x i16> %retval 81} 82 83define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { 84; CHECK-LABEL: insert_v8i16_nxv8i16_idx8: 85; CHECK: // %bb.0: 86; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 87; CHECK-NEXT: addvl sp, sp, #-1 88; CHECK-NEXT: cnth x8 89; CHECK-NEXT: mov w9, #8 90; CHECK-NEXT: sub x8, x8, #8 91; CHECK-NEXT: ptrue p0.h 92; CHECK-NEXT: cmp x8, #8 93; CHECK-NEXT: st1h { z0.h }, p0, [sp] 94; CHECK-NEXT: csel x8, x8, x9, lo 95; CHECK-NEXT: mov x9, sp 96; CHECK-NEXT: lsl x8, x8, #1 97; CHECK-NEXT: str q1, [x9, x8] 98; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] 99; CHECK-NEXT: addvl sp, sp, #1 100; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 101; CHECK-NEXT: ret 102 %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8) 103 ret <vscale x 8 x i16> %retval 104} 105 106define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { 107; CHECK-LABEL: insert_v16i8_nxv16i8: 108; CHECK: // %bb.0: 109; CHECK-NEXT: ptrue p0.b, vl16 110; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 111; CHECK-NEXT: mov z0.b, p0/m, z1.b 112; CHECK-NEXT: ret 113 %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0) 114 ret <vscale x 16 x i8> %retval 115} 116 117define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { 118; CHECK-LABEL: insert_v16i8_nxv16i8_idx16: 119; CHECK: // %bb.0: 120; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 121; CHECK-NEXT: addvl sp, sp, #-1 122; CHECK-NEXT: mov x8, #-16 123; CHECK-NEXT: mov w9, #16 124; CHECK-NEXT: ptrue p0.b 125; CHECK-NEXT: st1b { z0.b }, p0, [sp] 126; CHECK-NEXT: addvl x8, x8, #1 127; CHECK-NEXT: cmp x8, #16 128; CHECK-NEXT: csel x8, x8, x9, lo 129; CHECK-NEXT: mov x9, sp 130; CHECK-NEXT: str q1, [x9, x8] 131; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] 132; CHECK-NEXT: addvl sp, sp, #1 133; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 134; CHECK-NEXT: ret 135 %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16) 136 ret <vscale x 16 x i8> %retval 137} 138 139 140; Insert subvectors into illegal vectors 141 142define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) { 143; CHECK-LABEL: insert_nxv8i64_nxv16i64: 144; CHECK: // %bb.0: 145; CHECK-NEXT: ptrue p0.d 146; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] 147; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] 148; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] 149; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] 150; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 151; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 152; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 153; CHECK-NEXT: st1d { z0.d }, p0, [x0] 154; CHECK-NEXT: ret 155 %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) 156 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8) 157 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 158 ret void 159} 160 161define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { 162; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo: 163; CHECK: // %bb.0: 164; CHECK-NEXT: ptrue p0.d 165; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 166; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 167; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 168; CHECK-NEXT: st1d { z0.d }, p0, [x0] 169; CHECK-NEXT: ret 170 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) 171 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 172 ret void 173} 174 175define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { 176; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi: 177; CHECK: // %bb.0: 178; CHECK-NEXT: ptrue p0.d 179; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl] 180; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl] 181; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl] 182; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl] 183; CHECK-NEXT: ret 184 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8) 185 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 186 ret void 187} 188 189define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) uwtable { 190; CHECK-LABEL: insert_v2i64_nxv16i64: 191; CHECK: // %bb.0: 192; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 193; CHECK-NEXT: .cfi_def_cfa_offset 16 194; CHECK-NEXT: .cfi_offset w29, -16 195; CHECK-NEXT: addvl sp, sp, #-4 196; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG 197; CHECK-NEXT: ptrue p0.d 198; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 199; CHECK-NEXT: st1d { z0.d }, p0, [sp] 200; CHECK-NEXT: str q1, [sp, #32] 201; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 202; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp, #1, mul vl] 203; CHECK-NEXT: ld1d { z2.d }, p0/z, [sp, #2, mul vl] 204; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp, #3, mul vl] 205; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 206; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 207; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 208; CHECK-NEXT: st1d { z0.d }, p0, [x0] 209; CHECK-NEXT: addvl sp, sp, #4 210; CHECK-NEXT: .cfi_def_cfa wsp, 16 211; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 212; CHECK-NEXT: .cfi_def_cfa_offset 0 213; CHECK-NEXT: .cfi_restore w29 214; CHECK-NEXT: ret 215 %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) 216 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) 217 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 218 ret void 219} 220 221define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { 222; CHECK-LABEL: insert_v2i64_nxv16i64_lo0: 223; CHECK: // %bb.0: 224; CHECK-NEXT: ldr q0, [x0] 225; CHECK-NEXT: ptrue p0.d 226; CHECK-NEXT: st1d { z0.d }, p0, [x1] 227; CHECK-NEXT: ret 228 %sv = load <2 x i64>, <2 x i64>* %psv 229 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0) 230 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 231 ret void 232} 233 234define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) uwtable { 235; CHECK-LABEL: insert_v2i64_nxv16i64_lo2: 236; CHECK: // %bb.0: 237; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 238; CHECK-NEXT: .cfi_def_cfa_offset 16 239; CHECK-NEXT: .cfi_offset w29, -16 240; CHECK-NEXT: addvl sp, sp, #-2 241; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG 242; CHECK-NEXT: ldr q0, [x0] 243; CHECK-NEXT: ptrue p0.d 244; CHECK-NEXT: str q0, [sp, #16] 245; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 246; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp, #1, mul vl] 247; CHECK-NEXT: st1d { z1.d }, p0, [x1, #1, mul vl] 248; CHECK-NEXT: st1d { z0.d }, p0, [x1] 249; CHECK-NEXT: addvl sp, sp, #2 250; CHECK-NEXT: .cfi_def_cfa wsp, 16 251; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 252; CHECK-NEXT: .cfi_def_cfa_offset 0 253; CHECK-NEXT: .cfi_restore w29 254; CHECK-NEXT: ret 255 %sv = load <2 x i64>, <2 x i64>* %psv 256 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2) 257 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 258 ret void 259} 260 261 262; Insert subvectors that need widening 263 264define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind { 265; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef: 266; CHECK: // %bb.0: // %entry 267; CHECK-NEXT: mov z0.s, #1 // =0x1 268; CHECK-NEXT: ret 269entry: 270 %0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0 271 %subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 272 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0) 273 ret <vscale x 4 x i32> %retval 274} 275 276define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind { 277; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef: 278; CHECK: // %bb.0: // %entry 279; CHECK-NEXT: mov z0.h, #1 // =0x1 280; CHECK-NEXT: ret 281entry: 282 %0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0 283 %subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 284 %retval = call <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0) 285 ret <vscale x 6 x i16> %retval 286} 287 288; This tests promotion of the input operand to INSERT_SUBVECTOR. 289define <vscale x 8 x i16> @insert_nxv8i16_nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in) nounwind { 290; CHECK-LABEL: insert_nxv8i16_nxv2i16: 291; CHECK: // %bb.0: 292; CHECK-NEXT: uunpklo z2.s, z0.h 293; CHECK-NEXT: uunpkhi z0.s, z0.h 294; CHECK-NEXT: uunpklo z2.d, z2.s 295; CHECK-NEXT: uzp1 z1.s, z2.s, z1.s 296; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h 297; CHECK-NEXT: ret 298 %r = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in, i64 2) 299 ret <vscale x 8 x i16> %r 300} 301 302define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_0(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind { 303; CHECK-LABEL: insert_nxv4f16_nxv2f16_0: 304; CHECK: // %bb.0: 305; CHECK-NEXT: uunpkhi z0.d, z0.s 306; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s 307; CHECK-NEXT: ret 308 %v0 = call <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 0) 309 ret <vscale x 4 x half> %v0 310} 311 312define <vscale x 4 x half> @insert_nxv4f16_nxv2f16_2(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1) nounwind { 313; CHECK-LABEL: insert_nxv4f16_nxv2f16_2: 314; CHECK: // %bb.0: 315; CHECK-NEXT: uunpklo z0.d, z0.s 316; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 317; CHECK-NEXT: ret 318 %v0 = call <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> %sv0, <vscale x 2 x half> %sv1, i64 2) 319 ret <vscale x 4 x half> %v0 320} 321 322; Test that the index is scaled by vscale if the subvector is scalable. 323define <vscale x 8 x half> @insert_nxv8f16_nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in) nounwind { 324; CHECK-LABEL: insert_nxv8f16_nxv2f16: 325; CHECK: // %bb.0: 326; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 327; CHECK-NEXT: addvl sp, sp, #-1 328; CHECK-NEXT: ptrue p0.h 329; CHECK-NEXT: ptrue p1.d 330; CHECK-NEXT: st1h { z0.h }, p0, [sp] 331; CHECK-NEXT: st1h { z1.d }, p1, [sp, #1, mul vl] 332; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] 333; CHECK-NEXT: addvl sp, sp, #1 334; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 335; CHECK-NEXT: ret 336 %r = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in, i64 2) 337 ret <vscale x 8 x half> %r 338} 339 340define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_0(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind { 341; CHECK-LABEL: insert_nxv8f16_nxv4f16_0: 342; CHECK: // %bb.0: 343; CHECK-NEXT: uunpkhi z0.s, z0.h 344; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h 345; CHECK-NEXT: ret 346 %v0 = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 0) 347 ret <vscale x 8 x half> %v0 348} 349 350define <vscale x 8 x half> @insert_nxv8f16_nxv4f16_4(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1) nounwind { 351; CHECK-LABEL: insert_nxv8f16_nxv4f16_4: 352; CHECK: // %bb.0: 353; CHECK-NEXT: uunpklo z0.s, z0.h 354; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h 355; CHECK-NEXT: ret 356 %v0 = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %sv0, <vscale x 4 x half> %sv1, i64 4) 357 ret <vscale x 8 x half> %v0 358} 359 360; Fixed length clamping 361 362define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 { 363; CHECK-LABEL: insert_fixed_v2i64_nxv2i64: 364; CHECK: // %bb.0: 365; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 366; CHECK-NEXT: addvl sp, sp, #-1 367; CHECK-NEXT: cntd x8 368; CHECK-NEXT: mov w9, #2 369; CHECK-NEXT: sub x8, x8, #2 370; CHECK-NEXT: ptrue p0.d 371; CHECK-NEXT: cmp x8, #2 372; CHECK-NEXT: st1d { z0.d }, p0, [sp] 373; CHECK-NEXT: csel x8, x8, x9, lo 374; CHECK-NEXT: mov x9, sp 375; CHECK-NEXT: lsl x8, x8, #3 376; CHECK-NEXT: str q1, [x9, x8] 377; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 378; CHECK-NEXT: addvl sp, sp, #1 379; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 380; CHECK-NEXT: ret 381 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) 382 ret <vscale x 2 x i64> %retval 383} 384 385define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 { 386; CHECK-LABEL: insert_fixed_v4i64_nxv2i64: 387; CHECK: // %bb.0: 388; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 389; CHECK-NEXT: addvl sp, sp, #-1 390; CHECK-NEXT: cntd x8 391; CHECK-NEXT: ptrue p0.d 392; CHECK-NEXT: subs x8, x8, #4 393; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0] 394; CHECK-NEXT: csel x8, xzr, x8, lo 395; CHECK-NEXT: mov w9, #4 396; CHECK-NEXT: cmp x8, #4 397; CHECK-NEXT: st1d { z0.d }, p0, [sp] 398; CHECK-NEXT: csel x8, x8, x9, lo 399; CHECK-NEXT: mov x9, sp 400; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3] 401; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 402; CHECK-NEXT: addvl sp, sp, #1 403; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 404; CHECK-NEXT: ret 405 %subvec = load <4 x i64>, <4 x i64>* %ptr 406 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4) 407 ret <vscale x 2 x i64> %retval 408} 409 410;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 411;; Upacked types that need result widening 412;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 413 414define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) { 415; CHECK-LABEL: insert_nxv3i32_nxv2i32: 416; CHECK: // %bb.0: 417; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s 418; CHECK-NEXT: ret 419 %v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> undef, <vscale x 2 x i32> %sv0, i64 0) 420 ret <vscale x 3 x i32> %v0 421} 422 423;; Check that the Subvector is not widen so it does not crash. 424define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32_2(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1) { 425; CHECK-LABEL: insert_nxv3i32_nxv2i32_2: 426; CHECK: // %bb.0: 427; CHECK-NEXT: uunpkhi z0.d, z0.s 428; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s 429; CHECK-NEXT: ret 430 %v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1, i64 0) 431 ret <vscale x 3 x i32> %v0 432} 433 434define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0) nounwind { 435; CHECK-LABEL: insert_nxv3f32_nxv2f32: 436; CHECK: // %bb.0: 437; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s 438; CHECK-NEXT: ret 439 %v0 = call <vscale x 3 x float> @llvm.experimental.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float> undef, <vscale x 2 x float> %sv0, i64 0) 440 ret <vscale x 3 x float> %v0 441} 442 443define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_0(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind { 444; CHECK-LABEL: insert_nxv4f32_nxv2f32_0: 445; CHECK: // %bb.0: 446; CHECK-NEXT: uunpkhi z0.d, z0.s 447; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s 448; CHECK-NEXT: ret 449 %v0 = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 0) 450 ret <vscale x 4 x float> %v0 451} 452 453define <vscale x 4 x float> @insert_nxv4f32_nxv2f32_2(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1) nounwind { 454; CHECK-LABEL: insert_nxv4f32_nxv2f32_2: 455; CHECK: // %bb.0: 456; CHECK-NEXT: uunpklo z0.d, z0.s 457; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 458; CHECK-NEXT: ret 459 %v0 = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %sv0, <vscale x 2 x float> %sv1, i64 2) 460 ret <vscale x 4 x float> %v0 461} 462 463define <vscale x 6 x i32> @insert_nxv6i32_nxv2i32(<vscale x 2 x i32> %sv0, <vscale x 2 x i32> %sv1) nounwind { 464; CHECK-LABEL: insert_nxv6i32_nxv2i32: 465; CHECK: // %bb.0: 466; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 467; CHECK-NEXT: addvl sp, sp, #-2 468; CHECK-NEXT: ptrue p0.s 469; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 470; CHECK-NEXT: st1w { z0.s }, p0, [sp] 471; CHECK-NEXT: ld1w { z1.s }, p0/z, [sp, #1, mul vl] 472; CHECK-NEXT: addvl sp, sp, #2 473; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 474; CHECK-NEXT: ret 475 %v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> undef, <vscale x 2 x i32> %sv0, i64 0) 476 %v1 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> %v0, <vscale x 2 x i32> %sv1, i64 2) 477 ret <vscale x 6 x i32> %v1 478} 479 480;; This only works because the input vector is undef and index is zero 481define <vscale x 6 x i32> @insert_nxv6i32_nxv3i32(<vscale x 3 x i32> %sv0) { 482; CHECK-LABEL: insert_nxv6i32_nxv3i32: 483; CHECK: // %bb.0: 484; CHECK-NEXT: ret 485 %v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32> undef, <vscale x 3 x i32> %sv0, i64 0) 486 ret <vscale x 6 x i32> %v0 487} 488 489define <vscale x 12 x i32> @insert_nxv12i32_nxv4i32(<vscale x 4 x i32> %sv0, <vscale x 4 x i32> %sv1, <vscale x 4 x i32> %sv2) { 490; CHECK-LABEL: insert_nxv12i32_nxv4i32: 491; CHECK: // %bb.0: 492; CHECK-NEXT: ret 493 %v0 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> undef, <vscale x 4 x i32> %sv0, i64 0) 494 %v1 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v0, <vscale x 4 x i32> %sv1, i64 4) 495 %v2 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v1, <vscale x 4 x i32> %sv2, i64 8) 496 ret <vscale x 12 x i32> %v2 497} 498 499define <vscale x 2 x bfloat> @insert_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { 500; CHECK-LABEL: insert_nxv2bf16_nxv2bf16: 501; CHECK: // %bb.0: 502; CHECK-NEXT: mov z0.d, z1.d 503; CHECK-NEXT: ret 504 %v0 = call <vscale x 2 x bfloat> @llvm.experimental.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0) 505 ret <vscale x 2 x bfloat> %v0 506} 507 508define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { 509; CHECK-LABEL: insert_nxv4bf16_nxv4bf16: 510; CHECK: // %bb.0: 511; CHECK-NEXT: mov z0.d, z1.d 512; CHECK-NEXT: ret 513 %v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0) 514 ret <vscale x 4 x bfloat> %v0 515} 516 517define <vscale x 4 x bfloat> @insert_nxv4bf16_v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1) nounwind { 518; CHECK-LABEL: insert_nxv4bf16_v4bf16: 519; CHECK: // %bb.0: 520; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 521; CHECK-NEXT: addvl sp, sp, #-1 522; CHECK-NEXT: ptrue p0.s 523; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl] 524; CHECK-NEXT: addpl x8, sp, #4 525; CHECK-NEXT: str d1, [x8] 526; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl] 527; CHECK-NEXT: addvl sp, sp, #1 528; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 529; CHECK-NEXT: ret 530 %v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1, i64 0) 531 ret <vscale x 4 x bfloat> %v0 532} 533 534define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1) nounwind { 535; CHECK-LABEL: insert_nxv8bf16_nxv8bf16: 536; CHECK: // %bb.0: 537; CHECK-NEXT: mov z0.d, z1.d 538; CHECK-NEXT: ret 539 %v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1, i64 0) 540 ret <vscale x 8 x bfloat> %v0 541} 542 543define <vscale x 8 x bfloat> @insert_nxv8bf16_v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1) nounwind { 544; CHECK-LABEL: insert_nxv8bf16_v8bf16: 545; CHECK: // %bb.0: 546; CHECK-NEXT: ptrue p0.h, vl8 547; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 548; CHECK-NEXT: mov z0.h, p0/m, z1.h 549; CHECK-NEXT: ret 550 %v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1, i64 0) 551 ret <vscale x 8 x bfloat> %v0 552} 553 554define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_0(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { 555; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_0: 556; CHECK: // %bb.0: 557; CHECK-NEXT: uunpkhi z0.s, z0.h 558; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h 559; CHECK-NEXT: ret 560 %v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0) 561 ret <vscale x 8 x bfloat> %v0 562} 563 564define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv4bf16_4(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { 565; CHECK-LABEL: insert_nxv8bf16_nxv4bf16_4: 566; CHECK: // %bb.0: 567; CHECK-NEXT: uunpklo z0.s, z0.h 568; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h 569; CHECK-NEXT: ret 570 %v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 4) 571 ret <vscale x 8 x bfloat> %v0 572} 573 574define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_0(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { 575; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_0: 576; CHECK: // %bb.0: 577; CHECK-NEXT: uunpkhi z0.d, z0.s 578; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s 579; CHECK-NEXT: ret 580 %v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0) 581 ret <vscale x 4 x bfloat> %v0 582} 583 584define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv2bf16_2(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { 585; CHECK-LABEL: insert_nxv4bf16_nxv2bf16_2: 586; CHECK: // %bb.0: 587; CHECK-NEXT: uunpklo z0.d, z0.s 588; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 589; CHECK-NEXT: ret 590 %v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 2) 591 ret <vscale x 4 x bfloat> %v0 592} 593 594; Test predicate inserts of half size. 595define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_0(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) { 596; CHECK-LABEL: insert_nxv16i1_nxv8i1_0: 597; CHECK: // %bb.0: 598; CHECK-NEXT: punpkhi p0.h, p0.b 599; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b 600; CHECK-NEXT: ret 601 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 0) 602 ret <vscale x 16 x i1> %v0 603} 604 605define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_8(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) { 606; CHECK-LABEL: insert_nxv16i1_nxv8i1_8: 607; CHECK: // %bb.0: 608; CHECK-NEXT: punpklo p0.h, p0.b 609; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 610; CHECK-NEXT: ret 611 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 8) 612 ret <vscale x 16 x i1> %v0 613} 614 615; Test predicate inserts of less than half the size. 616define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_0(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) { 617; CHECK-LABEL: insert_nxv16i1_nxv4i1_0: 618; CHECK: // %bb.0: 619; CHECK-NEXT: punpklo p2.h, p0.b 620; CHECK-NEXT: punpkhi p0.h, p0.b 621; CHECK-NEXT: punpkhi p2.h, p2.b 622; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h 623; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b 624; CHECK-NEXT: ret 625 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 0) 626 ret <vscale x 16 x i1> %v0 627} 628 629define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_12(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) { 630; CHECK-LABEL: insert_nxv16i1_nxv4i1_12: 631; CHECK: // %bb.0: 632; CHECK-NEXT: punpkhi p2.h, p0.b 633; CHECK-NEXT: punpklo p0.h, p0.b 634; CHECK-NEXT: punpklo p2.h, p2.b 635; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h 636; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 637; CHECK-NEXT: ret 638 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 12) 639 ret <vscale x 16 x i1> %v0 640} 641 642; Test predicate insert into undef/zero 643define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_zero(<vscale x 4 x i1> %sv) { 644; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_zero: 645; CHECK: // %bb.0: 646; CHECK-NEXT: pfalse p1.b 647; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h 648; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 649; CHECK-NEXT: ret 650 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %sv, i64 0) 651 ret <vscale x 16 x i1> %v0 652} 653 654define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_poison(<vscale x 4 x i1> %sv) { 655; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_poison: 656; CHECK: // %bb.0: 657; CHECK-NEXT: uzp1 p0.h, p0.h, p0.h 658; CHECK-NEXT: uzp1 p0.b, p0.b, p0.b 659; CHECK-NEXT: ret 660 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %sv, i64 0) 661 ret <vscale x 16 x i1> %v0 662} 663 664; Test constant predicate insert into undef 665define <vscale x 2 x i1> @insert_nxv2i1_v8i1_const_true_into_undef() vscale_range(4,8) { 666; CHECK-LABEL: insert_nxv2i1_v8i1_const_true_into_undef: 667; CHECK: // %bb.0: 668; CHECK-NEXT: ptrue p0.d 669; CHECK-NEXT: ret 670 %v0 = call <vscale x 2 x i1> @llvm.experimental.vector.insert.nxv2i1.v8i1 (<vscale x 2 x i1> undef, <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 671 ret <vscale x 2 x i1> %v0 672} 673 674define <vscale x 4 x i1> @insert_nxv4i1_v16i1_const_true_into_undef() vscale_range(4,8) { 675; CHECK-LABEL: insert_nxv4i1_v16i1_const_true_into_undef: 676; CHECK: // %bb.0: 677; CHECK-NEXT: ptrue p0.s 678; CHECK-NEXT: ret 679 %v0 = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv4i1.v16i1 (<vscale x 4 x i1> undef, <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 680 ret <vscale x 4 x i1> %v0 681} 682 683define <vscale x 8 x i1> @insert_nxv8i1_v32i1_const_true_into_undef() vscale_range(4,8) { 684; CHECK-LABEL: insert_nxv8i1_v32i1_const_true_into_undef: 685; CHECK: // %bb.0: 686; CHECK-NEXT: ptrue p0.h 687; CHECK-NEXT: ret 688 %v0 = call <vscale x 8 x i1> @llvm.experimental.vector.insert.nxv8i1.v32i1 (<vscale x 8 x i1> undef, <32 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 689 ret <vscale x 8 x i1> %v0 690} 691 692define <vscale x 16 x i1> @insert_nxv16i1_v64i1_const_true_into_undef() vscale_range(4,8) { 693; CHECK-LABEL: insert_nxv16i1_v64i1_const_true_into_undef: 694; CHECK: // %bb.0: 695; CHECK-NEXT: ptrue p0.b 696; CHECK-NEXT: ret 697 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.v64i1 (<vscale x 16 x i1> undef, <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 698 ret <vscale x 16 x i1> %v0 699} 700 701attributes #0 = { vscale_range(2,2) } 702 703declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64) 704 705declare <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64) 706declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16>, <vscale x 2 x i16>, i64) 707declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64) 708 709declare <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32>, <vscale x 2 x i32>, i64) 710declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64) 711declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64) 712declare <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32>, <vscale x 4 x i32>, i64) 713declare <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32>, <vscale x 2 x i32>, i64) 714declare <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32>, <vscale x 3 x i32>, i64) 715 716declare <vscale x 2 x bfloat> @llvm.experimental.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) 717declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64) 718declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) 719declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat>, <4 x bfloat>, i64) 720declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) 721declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64) 722declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat>, <8 x bfloat>, i64) 723 724declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64) 725declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64>, <4 x i64>, i64) 726declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64) 727declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64) 728 729declare <vscale x 4 x half> @llvm.experimental.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64) 730declare <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64) 731declare <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64) 732 733declare <vscale x 3 x float> @llvm.experimental.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float>, <vscale x 2 x float>, i64) 734declare <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64) 735 736declare <vscale x 2 x i1> @llvm.experimental.vector.insert.nxv2i1.v8i1(<vscale x 2 x i1>, <8 x i1>, i64) 737declare <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv4i1.v16i1(<vscale x 4 x i1>, <16 x i1>, i64) 738declare <vscale x 8 x i1> @llvm.experimental.vector.insert.nxv8i1.v32i1(<vscale x 8 x i1>, <32 x i1>, i64) 739declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64) 740declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1>, <vscale x 8 x i1>, i64) 741declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.v64i1(<vscale x 16 x i1>, <64 x i1>, i64) 742