1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK
3
4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
5; CHECK-LABEL: insert_v2i64_nxv2i64:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
8; CHECK-NEXT:    addvl sp, sp, #-1
9; CHECK-NEXT:    ptrue p0.d
10; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
11; CHECK-NEXT:    str q1, [sp]
12; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
13; CHECK-NEXT:    addvl sp, sp, #1
14; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
15; CHECK-NEXT:    ret
16  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)
17  ret <vscale x 2 x i64> %retval
18}
19
20define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx1(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
21; CHECK-LABEL: insert_v2i64_nxv2i64_idx1:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
24; CHECK-NEXT:    addvl sp, sp, #-1
25; CHECK-NEXT:    ptrue p0.d
26; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
27; CHECK-NEXT:    stur q1, [sp, #8]
28; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
29; CHECK-NEXT:    addvl sp, sp, #1
30; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
31; CHECK-NEXT:    ret
32  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 1)
33  ret <vscale x 2 x i64> %retval
34}
35
36define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
37; CHECK-LABEL: insert_v4i32_nxv4i32:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
40; CHECK-NEXT:    addvl sp, sp, #-1
41; CHECK-NEXT:    ptrue p0.s
42; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
43; CHECK-NEXT:    str q1, [sp]
44; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
45; CHECK-NEXT:    addvl sp, sp, #1
46; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
47; CHECK-NEXT:    ret
48  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
49  ret <vscale x 4 x i32> %retval
50}
51
52define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx1(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
53; CHECK-LABEL: insert_v4i32_nxv4i32_idx1:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
56; CHECK-NEXT:    addvl sp, sp, #-1
57; CHECK-NEXT:    ptrue p0.s
58; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
59; CHECK-NEXT:    stur q1, [sp, #4]
60; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
61; CHECK-NEXT:    addvl sp, sp, #1
62; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
63; CHECK-NEXT:    ret
64  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 1)
65  ret <vscale x 4 x i32> %retval
66}
67
68define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
69; CHECK-LABEL: insert_v8i16_nxv8i16:
70; CHECK:       // %bb.0:
71; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
72; CHECK-NEXT:    addvl sp, sp, #-1
73; CHECK-NEXT:    ptrue p0.h
74; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
75; CHECK-NEXT:    str q1, [sp]
76; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
77; CHECK-NEXT:    addvl sp, sp, #1
78; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
79; CHECK-NEXT:    ret
80  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)
81  ret <vscale x 8 x i16> %retval
82}
83
84define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx1(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
85; CHECK-LABEL: insert_v8i16_nxv8i16_idx1:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
88; CHECK-NEXT:    addvl sp, sp, #-1
89; CHECK-NEXT:    ptrue p0.h
90; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
91; CHECK-NEXT:    stur q1, [sp, #2]
92; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
93; CHECK-NEXT:    addvl sp, sp, #1
94; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
95; CHECK-NEXT:    ret
96  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 1)
97  ret <vscale x 8 x i16> %retval
98}
99
100define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
101; CHECK-LABEL: insert_v16i8_nxv16i8:
102; CHECK:       // %bb.0:
103; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
104; CHECK-NEXT:    addvl sp, sp, #-1
105; CHECK-NEXT:    ptrue p0.b
106; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
107; CHECK-NEXT:    str q1, [sp]
108; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
109; CHECK-NEXT:    addvl sp, sp, #1
110; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
111; CHECK-NEXT:    ret
112  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)
113  ret <vscale x 16 x i8> %retval
114}
115
116define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
117; CHECK-LABEL: insert_v16i8_nxv16i8_idx1:
118; CHECK:       // %bb.0:
119; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
120; CHECK-NEXT:    addvl sp, sp, #-1
121; CHECK-NEXT:    ptrue p0.b
122; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
123; CHECK-NEXT:    stur q1, [sp, #1]
124; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
125; CHECK-NEXT:    addvl sp, sp, #1
126; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
127; CHECK-NEXT:    ret
128  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 1)
129  ret <vscale x 16 x i8> %retval
130}
131
132declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
133declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
134declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
135declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
136