1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK 3 4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { 5; CHECK-LABEL: insert_v2i64_nxv2i64: 6; CHECK: // %bb.0: 7; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 8; CHECK-NEXT: addvl sp, sp, #-1 9; CHECK-NEXT: ptrue p0.d 10; CHECK-NEXT: st1d { z0.d }, p0, [sp] 11; CHECK-NEXT: str q1, [sp] 12; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 13; CHECK-NEXT: addvl sp, sp, #1 14; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 15; CHECK-NEXT: ret 16 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0) 17 ret <vscale x 2 x i64> %retval 18} 19 20define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx1(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { 21; CHECK-LABEL: insert_v2i64_nxv2i64_idx1: 22; CHECK: // %bb.0: 23; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 24; CHECK-NEXT: addvl sp, sp, #-1 25; CHECK-NEXT: ptrue p0.d 26; CHECK-NEXT: st1d { z0.d }, p0, [sp] 27; CHECK-NEXT: stur q1, [sp, #8] 28; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 29; CHECK-NEXT: addvl sp, sp, #1 30; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 31; CHECK-NEXT: ret 32 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 1) 33 ret <vscale x 2 x i64> %retval 34} 35 36define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { 37; CHECK-LABEL: insert_v4i32_nxv4i32: 38; CHECK: // %bb.0: 39; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 40; CHECK-NEXT: addvl sp, sp, #-1 41; CHECK-NEXT: ptrue p0.s 42; CHECK-NEXT: st1w { z0.s }, p0, [sp] 43; CHECK-NEXT: str q1, [sp] 44; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] 45; CHECK-NEXT: addvl sp, sp, #1 46; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 47; CHECK-NEXT: ret 48 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0) 49 ret <vscale x 4 x i32> %retval 50} 51 52define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx1(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { 53; CHECK-LABEL: insert_v4i32_nxv4i32_idx1: 54; CHECK: // %bb.0: 55; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 56; CHECK-NEXT: addvl sp, sp, #-1 57; CHECK-NEXT: ptrue p0.s 58; CHECK-NEXT: st1w { z0.s }, p0, [sp] 59; CHECK-NEXT: stur q1, [sp, #4] 60; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] 61; CHECK-NEXT: addvl sp, sp, #1 62; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 63; CHECK-NEXT: ret 64 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 1) 65 ret <vscale x 4 x i32> %retval 66} 67 68define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { 69; CHECK-LABEL: insert_v8i16_nxv8i16: 70; CHECK: // %bb.0: 71; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 72; CHECK-NEXT: addvl sp, sp, #-1 73; CHECK-NEXT: ptrue p0.h 74; CHECK-NEXT: st1h { z0.h }, p0, [sp] 75; CHECK-NEXT: str q1, [sp] 76; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] 77; CHECK-NEXT: addvl sp, sp, #1 78; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 79; CHECK-NEXT: ret 80 %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0) 81 ret <vscale x 8 x i16> %retval 82} 83 84define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx1(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { 85; CHECK-LABEL: insert_v8i16_nxv8i16_idx1: 86; CHECK: // %bb.0: 87; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 88; CHECK-NEXT: addvl sp, sp, #-1 89; CHECK-NEXT: ptrue p0.h 90; CHECK-NEXT: st1h { z0.h }, p0, [sp] 91; CHECK-NEXT: stur q1, [sp, #2] 92; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] 93; CHECK-NEXT: addvl sp, sp, #1 94; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 95; CHECK-NEXT: ret 96 %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 1) 97 ret <vscale x 8 x i16> %retval 98} 99 100define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { 101; CHECK-LABEL: insert_v16i8_nxv16i8: 102; CHECK: // %bb.0: 103; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 104; CHECK-NEXT: addvl sp, sp, #-1 105; CHECK-NEXT: ptrue p0.b 106; CHECK-NEXT: st1b { z0.b }, p0, [sp] 107; CHECK-NEXT: str q1, [sp] 108; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] 109; CHECK-NEXT: addvl sp, sp, #1 110; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 111; CHECK-NEXT: ret 112 %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0) 113 ret <vscale x 16 x i8> %retval 114} 115 116define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { 117; CHECK-LABEL: insert_v16i8_nxv16i8_idx1: 118; CHECK: // %bb.0: 119; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 120; CHECK-NEXT: addvl sp, sp, #-1 121; CHECK-NEXT: ptrue p0.b 122; CHECK-NEXT: st1b { z0.b }, p0, [sp] 123; CHECK-NEXT: stur q1, [sp, #1] 124; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] 125; CHECK-NEXT: addvl sp, sp, #1 126; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 127; CHECK-NEXT: ret 128 %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 1) 129 ret <vscale x 16 x i8> %retval 130} 131 132 133; Insert subvectors into illegal vectors 134 135define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) { 136; CHECK-LABEL: insert_nxv8i64_nxv16i64: 137; CHECK: // %bb.0: 138; CHECK-NEXT: ptrue p0.d 139; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] 140; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] 141; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] 142; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] 143; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 144; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 145; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 146; CHECK-NEXT: st1d { z0.d }, p0, [x0] 147; CHECK-NEXT: ret 148 %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) 149 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8) 150 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 151 ret void 152} 153 154define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { 155; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo: 156; CHECK: // %bb.0: 157; CHECK-NEXT: ptrue p0.d 158; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 159; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 160; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 161; CHECK-NEXT: st1d { z0.d }, p0, [x0] 162; CHECK-NEXT: ret 163 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) 164 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 165 ret void 166} 167 168define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { 169; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi: 170; CHECK: // %bb.0: 171; CHECK-NEXT: ptrue p0.d 172; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl] 173; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl] 174; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl] 175; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl] 176; CHECK-NEXT: ret 177 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8) 178 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 179 ret void 180} 181 182define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) { 183; CHECK-LABEL: insert_v2i64_nxv16i64: 184; CHECK: // %bb.0: 185; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 186; CHECK-NEXT: addvl sp, sp, #-4 187; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG 188; CHECK-NEXT: .cfi_offset w29, -16 189; CHECK-NEXT: ptrue p0.d 190; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 191; CHECK-NEXT: mov x8, sp 192; CHECK-NEXT: st1d { z0.d }, p0, [sp] 193; CHECK-NEXT: str q1, [sp, #32] 194; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl] 195; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8, #2, mul vl] 196; CHECK-NEXT: ld1d { z2.d }, p0/z, [x8, #3, mul vl] 197; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp] 198; CHECK-NEXT: st1d { z2.d }, p0, [x0, #3, mul vl] 199; CHECK-NEXT: st1d { z1.d }, p0, [x0, #2, mul vl] 200; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl] 201; CHECK-NEXT: st1d { z3.d }, p0, [x0] 202; CHECK-NEXT: addvl sp, sp, #4 203; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 204; CHECK-NEXT: ret 205 %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) 206 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) 207 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 208 ret void 209} 210 211define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { 212; CHECK-LABEL: insert_v2i64_nxv16i64_lo0: 213; CHECK: // %bb.0: 214; CHECK-NEXT: ldr q0, [x0] 215; CHECK-NEXT: ptrue p0.d 216; CHECK-NEXT: st1d { z0.d }, p0, [x1] 217; CHECK-NEXT: ret 218 %sv = load <2 x i64>, <2 x i64>* %psv 219 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0) 220 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 221 ret void 222} 223 224define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { 225; CHECK-LABEL: insert_v2i64_nxv16i64_lo2: 226; CHECK: // %bb.0: 227; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 228; CHECK-NEXT: addvl sp, sp, #-2 229; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG 230; CHECK-NEXT: .cfi_offset w29, -16 231; CHECK-NEXT: ldr q0, [x0] 232; CHECK-NEXT: ptrue p0.d 233; CHECK-NEXT: mov x8, sp 234; CHECK-NEXT: str q0, [sp, #16] 235; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl] 236; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp] 237; CHECK-NEXT: st1d { z0.d }, p0, [x1, #1, mul vl] 238; CHECK-NEXT: st1d { z1.d }, p0, [x1] 239; CHECK-NEXT: addvl sp, sp, #2 240; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 241; CHECK-NEXT: ret 242 %sv = load <2 x i64>, <2 x i64>* %psv 243 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2) 244 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 245 ret void 246} 247 248 249declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64) 250declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64) 251declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64) 252declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64) 253 254declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64) 255declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64) 256