1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+bf16 < %s | FileCheck %s --check-prefixes=CHECK 3 4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { 5; CHECK-LABEL: insert_v2i64_nxv2i64: 6; CHECK: // %bb.0: 7; CHECK-NEXT: ptrue p0.d, vl2 8; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 9; CHECK-NEXT: mov z0.d, p0/m, z1.d 10; CHECK-NEXT: ret 11 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0) 12 ret <vscale x 2 x i64> %retval 13} 14 15define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind { 16; CHECK-LABEL: insert_v2i64_nxv2i64_idx2: 17; CHECK: // %bb.0: 18; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 19; CHECK-NEXT: addvl sp, sp, #-1 20; CHECK-NEXT: cntd x8 21; CHECK-NEXT: mov w9, #2 22; CHECK-NEXT: sub x8, x8, #2 23; CHECK-NEXT: ptrue p0.d 24; CHECK-NEXT: cmp x8, #2 25; CHECK-NEXT: st1d { z0.d }, p0, [sp] 26; CHECK-NEXT: csel x8, x8, x9, lo 27; CHECK-NEXT: mov x9, sp 28; CHECK-NEXT: lsl x8, x8, #3 29; CHECK-NEXT: str q1, [x9, x8] 30; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 31; CHECK-NEXT: addvl sp, sp, #1 32; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 33; CHECK-NEXT: ret 34 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) 35 ret <vscale x 2 x i64> %retval 36} 37 38define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { 39; CHECK-LABEL: insert_v4i32_nxv4i32: 40; CHECK: // %bb.0: 41; CHECK-NEXT: ptrue p0.s, vl4 42; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 43; CHECK-NEXT: mov z0.s, p0/m, z1.s 44; CHECK-NEXT: ret 45 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0) 46 ret <vscale x 4 x i32> %retval 47} 48 49define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind { 50; CHECK-LABEL: insert_v4i32_nxv4i32_idx4: 51; CHECK: // %bb.0: 52; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 53; CHECK-NEXT: addvl sp, sp, #-1 54; CHECK-NEXT: cntw x8 55; CHECK-NEXT: mov w9, #4 56; CHECK-NEXT: sub x8, x8, #4 57; CHECK-NEXT: ptrue p0.s 58; CHECK-NEXT: cmp x8, #4 59; CHECK-NEXT: st1w { z0.s }, p0, [sp] 60; CHECK-NEXT: csel x8, x8, x9, lo 61; CHECK-NEXT: mov x9, sp 62; CHECK-NEXT: lsl x8, x8, #2 63; CHECK-NEXT: str q1, [x9, x8] 64; CHECK-NEXT: ld1w { z0.s }, p0/z, [sp] 65; CHECK-NEXT: addvl sp, sp, #1 66; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 67; CHECK-NEXT: ret 68 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 4) 69 ret <vscale x 4 x i32> %retval 70} 71 72define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { 73; CHECK-LABEL: insert_v8i16_nxv8i16: 74; CHECK: // %bb.0: 75; CHECK-NEXT: ptrue p0.h, vl8 76; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 77; CHECK-NEXT: mov z0.h, p0/m, z1.h 78; CHECK-NEXT: ret 79 %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0) 80 ret <vscale x 8 x i16> %retval 81} 82 83define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind { 84; CHECK-LABEL: insert_v8i16_nxv8i16_idx8: 85; CHECK: // %bb.0: 86; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 87; CHECK-NEXT: addvl sp, sp, #-1 88; CHECK-NEXT: cnth x8 89; CHECK-NEXT: mov w9, #8 90; CHECK-NEXT: sub x8, x8, #8 91; CHECK-NEXT: ptrue p0.h 92; CHECK-NEXT: cmp x8, #8 93; CHECK-NEXT: st1h { z0.h }, p0, [sp] 94; CHECK-NEXT: csel x8, x8, x9, lo 95; CHECK-NEXT: mov x9, sp 96; CHECK-NEXT: lsl x8, x8, #1 97; CHECK-NEXT: str q1, [x9, x8] 98; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] 99; CHECK-NEXT: addvl sp, sp, #1 100; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 101; CHECK-NEXT: ret 102 %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 8) 103 ret <vscale x 8 x i16> %retval 104} 105 106define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { 107; CHECK-LABEL: insert_v16i8_nxv16i8: 108; CHECK: // %bb.0: 109; CHECK-NEXT: ptrue p0.b, vl16 110; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 111; CHECK-NEXT: mov z0.b, p0/m, z1.b 112; CHECK-NEXT: ret 113 %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0) 114 ret <vscale x 16 x i8> %retval 115} 116 117define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind { 118; CHECK-LABEL: insert_v16i8_nxv16i8_idx16: 119; CHECK: // %bb.0: 120; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 121; CHECK-NEXT: addvl sp, sp, #-1 122; CHECK-NEXT: mov x8, #-16 123; CHECK-NEXT: mov w9, #16 124; CHECK-NEXT: ptrue p0.b 125; CHECK-NEXT: st1b { z0.b }, p0, [sp] 126; CHECK-NEXT: addvl x8, x8, #1 127; CHECK-NEXT: cmp x8, #16 128; CHECK-NEXT: csel x8, x8, x9, lo 129; CHECK-NEXT: mov x9, sp 130; CHECK-NEXT: str q1, [x9, x8] 131; CHECK-NEXT: ld1b { z0.b }, p0/z, [sp] 132; CHECK-NEXT: addvl sp, sp, #1 133; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 134; CHECK-NEXT: ret 135 %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 16) 136 ret <vscale x 16 x i8> %retval 137} 138 139 140; Insert subvectors into illegal vectors 141 142define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) { 143; CHECK-LABEL: insert_nxv8i64_nxv16i64: 144; CHECK: // %bb.0: 145; CHECK-NEXT: ptrue p0.d 146; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] 147; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] 148; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] 149; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] 150; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 151; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 152; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 153; CHECK-NEXT: st1d { z0.d }, p0, [x0] 154; CHECK-NEXT: ret 155 %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) 156 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8) 157 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 158 ret void 159} 160 161define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { 162; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo: 163; CHECK: // %bb.0: 164; CHECK-NEXT: ptrue p0.d 165; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 166; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 167; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 168; CHECK-NEXT: st1d { z0.d }, p0, [x0] 169; CHECK-NEXT: ret 170 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0) 171 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 172 ret void 173} 174 175define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) { 176; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi: 177; CHECK: // %bb.0: 178; CHECK-NEXT: ptrue p0.d 179; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl] 180; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl] 181; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl] 182; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl] 183; CHECK-NEXT: ret 184 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8) 185 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 186 ret void 187} 188 189define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) { 190; CHECK-LABEL: insert_v2i64_nxv16i64: 191; CHECK: // %bb.0: 192; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 193; CHECK-NEXT: .cfi_def_cfa_offset 16 194; CHECK-NEXT: .cfi_offset w29, -16 195; CHECK-NEXT: addvl sp, sp, #-4 196; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG 197; CHECK-NEXT: ptrue p0.d 198; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 199; CHECK-NEXT: st1d { z0.d }, p0, [sp] 200; CHECK-NEXT: str q1, [sp, #32] 201; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 202; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp, #1, mul vl] 203; CHECK-NEXT: ld1d { z2.d }, p0/z, [sp, #2, mul vl] 204; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp, #3, mul vl] 205; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 206; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 207; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 208; CHECK-NEXT: st1d { z0.d }, p0, [x0] 209; CHECK-NEXT: addvl sp, sp, #4 210; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 211; CHECK-NEXT: ret 212 %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) 213 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) 214 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 215 ret void 216} 217 218define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { 219; CHECK-LABEL: insert_v2i64_nxv16i64_lo0: 220; CHECK: // %bb.0: 221; CHECK-NEXT: ldr q0, [x0] 222; CHECK-NEXT: ptrue p0.d 223; CHECK-NEXT: st1d { z0.d }, p0, [x1] 224; CHECK-NEXT: ret 225 %sv = load <2 x i64>, <2 x i64>* %psv 226 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0) 227 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 228 ret void 229} 230 231define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) { 232; CHECK-LABEL: insert_v2i64_nxv16i64_lo2: 233; CHECK: // %bb.0: 234; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 235; CHECK-NEXT: .cfi_def_cfa_offset 16 236; CHECK-NEXT: .cfi_offset w29, -16 237; CHECK-NEXT: addvl sp, sp, #-2 238; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG 239; CHECK-NEXT: ldr q0, [x0] 240; CHECK-NEXT: ptrue p0.d 241; CHECK-NEXT: str q0, [sp, #16] 242; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 243; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp, #1, mul vl] 244; CHECK-NEXT: st1d { z1.d }, p0, [x1, #1, mul vl] 245; CHECK-NEXT: st1d { z0.d }, p0, [x1] 246; CHECK-NEXT: addvl sp, sp, #2 247; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 248; CHECK-NEXT: ret 249 %sv = load <2 x i64>, <2 x i64>* %psv 250 %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2) 251 store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out 252 ret void 253} 254 255 256; Insert subvectors that need widening 257 258define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind { 259; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef: 260; CHECK: // %bb.0: // %entry 261; CHECK-NEXT: mov z0.s, #1 // =0x1 262; CHECK-NEXT: ret 263entry: 264 %0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0 265 %subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 266 %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0) 267 ret <vscale x 4 x i32> %retval 268} 269 270define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind { 271; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef: 272; CHECK: // %bb.0: // %entry 273; CHECK-NEXT: mov z0.h, #1 // =0x1 274; CHECK-NEXT: ret 275entry: 276 %0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0 277 %subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 278 %retval = call <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0) 279 ret <vscale x 6 x i16> %retval 280} 281 282; This tests promotion of the input operand to INSERT_SUBVECTOR. 283define <vscale x 8 x i16> @insert_nxv8i16_nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in) nounwind { 284; CHECK-LABEL: insert_nxv8i16_nxv2i16: 285; CHECK: // %bb.0: 286; CHECK-NEXT: uunpklo z2.s, z0.h 287; CHECK-NEXT: uunpkhi z0.s, z0.h 288; CHECK-NEXT: uunpklo z2.d, z2.s 289; CHECK-NEXT: uzp1 z1.s, z2.s, z1.s 290; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h 291; CHECK-NEXT: ret 292 %r = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16> %vec, <vscale x 2 x i16> %in, i64 2) 293 ret <vscale x 8 x i16> %r 294} 295 296; Test that the index is scaled by vscale if the subvector is scalable. 297define <vscale x 8 x half> @insert_nxv8f16_nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in) nounwind { 298; CHECK-LABEL: insert_nxv8f16_nxv2f16: 299; CHECK: // %bb.0: 300; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 301; CHECK-NEXT: addvl sp, sp, #-1 302; CHECK-NEXT: ptrue p0.h 303; CHECK-NEXT: ptrue p1.d 304; CHECK-NEXT: st1h { z0.h }, p0, [sp] 305; CHECK-NEXT: st1h { z1.d }, p1, [sp, #1, mul vl] 306; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp] 307; CHECK-NEXT: addvl sp, sp, #1 308; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 309; CHECK-NEXT: ret 310 %r = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in, i64 2) 311 ret <vscale x 8 x half> %r 312} 313 314; Fixed length clamping 315 316define <vscale x 2 x i64> @insert_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind #0 { 317; CHECK-LABEL: insert_fixed_v2i64_nxv2i64: 318; CHECK: // %bb.0: 319; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 320; CHECK-NEXT: addvl sp, sp, #-1 321; CHECK-NEXT: cntd x8 322; CHECK-NEXT: mov w9, #2 323; CHECK-NEXT: sub x8, x8, #2 324; CHECK-NEXT: ptrue p0.d 325; CHECK-NEXT: cmp x8, #2 326; CHECK-NEXT: st1d { z0.d }, p0, [sp] 327; CHECK-NEXT: csel x8, x8, x9, lo 328; CHECK-NEXT: mov x9, sp 329; CHECK-NEXT: lsl x8, x8, #3 330; CHECK-NEXT: str q1, [x9, x8] 331; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 332; CHECK-NEXT: addvl sp, sp, #1 333; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 334; CHECK-NEXT: ret 335 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 2) 336 ret <vscale x 2 x i64> %retval 337} 338 339define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <4 x i64>* %ptr) nounwind #0 { 340; CHECK-LABEL: insert_fixed_v4i64_nxv2i64: 341; CHECK: // %bb.0: 342; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 343; CHECK-NEXT: addvl sp, sp, #-1 344; CHECK-NEXT: cntd x8 345; CHECK-NEXT: ptrue p0.d 346; CHECK-NEXT: subs x8, x8, #4 347; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0] 348; CHECK-NEXT: csel x8, xzr, x8, lo 349; CHECK-NEXT: mov w9, #4 350; CHECK-NEXT: cmp x8, #4 351; CHECK-NEXT: st1d { z0.d }, p0, [sp] 352; CHECK-NEXT: csel x8, x8, x9, lo 353; CHECK-NEXT: mov x9, sp 354; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3] 355; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp] 356; CHECK-NEXT: addvl sp, sp, #1 357; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 358; CHECK-NEXT: ret 359 %subvec = load <4 x i64>, <4 x i64>* %ptr 360 %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64> %vec, <4 x i64> %subvec, i64 4) 361 ret <vscale x 2 x i64> %retval 362} 363 364attributes #0 = { vscale_range(2,2) } 365 366declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64) 367declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64) 368declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64) 369declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64) 370 371declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v4i64(<vscale x 2 x i64>, <4 x i64>, i64) 372 373declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64) 374declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64) 375declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64) 376declare <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64) 377 378declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv2i16(<vscale x 8 x i16>, <vscale x 2 x i16>, i64) 379 380declare <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64) 381 382;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 383;; Upacked types that need result widening 384;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 385 386define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) { 387; CHECK-LABEL: insert_nxv3i32_nxv2i32: 388; CHECK: // %bb.0: 389; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s 390; CHECK-NEXT: ret 391 %v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> undef, <vscale x 2 x i32> %sv0, i64 0) 392 ret <vscale x 3 x i32> %v0 393} 394 395;; Check that the Subvector is not widen so it does not crash. 396define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32_2(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1) { 397; CHECK-LABEL: insert_nxv3i32_nxv2i32_2: 398; CHECK: // %bb.0: 399; CHECK-NEXT: uunpkhi z0.d, z0.s 400; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s 401; CHECK-NEXT: ret 402 %v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1, i64 0) 403 ret <vscale x 3 x i32> %v0 404} 405 406define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0) nounwind { 407; CHECK-LABEL: insert_nxv3f32_nxv2f32: 408; CHECK: // %bb.0: 409; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s 410; CHECK-NEXT: ret 411 %v0 = call <vscale x 3 x float> @llvm.experimental.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float> undef, <vscale x 2 x float> %sv0, i64 0) 412 ret <vscale x 3 x float> %v0 413} 414 415define <vscale x 6 x i32> @insert_nxv6i32_nxv2i32(<vscale x 2 x i32> %sv0, <vscale x 2 x i32> %sv1) nounwind { 416; CHECK-LABEL: insert_nxv6i32_nxv2i32: 417; CHECK: // %bb.0: 418; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 419; CHECK-NEXT: addvl sp, sp, #-2 420; CHECK-NEXT: ptrue p0.s 421; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 422; CHECK-NEXT: st1w { z0.s }, p0, [sp] 423; CHECK-NEXT: ld1w { z1.s }, p0/z, [sp, #1, mul vl] 424; CHECK-NEXT: addvl sp, sp, #2 425; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 426; CHECK-NEXT: ret 427 %v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> undef, <vscale x 2 x i32> %sv0, i64 0) 428 %v1 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> %v0, <vscale x 2 x i32> %sv1, i64 2) 429 ret <vscale x 6 x i32> %v1 430} 431 432;; This only works because the input vector is undef and index is zero 433define <vscale x 6 x i32> @insert_nxv6i32_nxv3i32(<vscale x 3 x i32> %sv0) { 434; CHECK-LABEL: insert_nxv6i32_nxv3i32: 435; CHECK: // %bb.0: 436; CHECK-NEXT: ret 437 %v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32> undef, <vscale x 3 x i32> %sv0, i64 0) 438 ret <vscale x 6 x i32> %v0 439} 440 441define <vscale x 12 x i32> @insert_nxv12i32_nxv4i32(<vscale x 4 x i32> %sv0, <vscale x 4 x i32> %sv1, <vscale x 4 x i32> %sv2) { 442; CHECK-LABEL: insert_nxv12i32_nxv4i32: 443; CHECK: // %bb.0: 444; CHECK-NEXT: ret 445 %v0 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> undef, <vscale x 4 x i32> %sv0, i64 0) 446 %v1 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v0, <vscale x 4 x i32> %sv1, i64 4) 447 %v2 = call <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32> %v1, <vscale x 4 x i32> %sv2, i64 8) 448 ret <vscale x 12 x i32> %v2 449} 450 451define <vscale x 2 x bfloat> @insert_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1) nounwind { 452; CHECK-LABEL: insert_nxv2bf16_nxv2bf16: 453; CHECK: // %bb.0: 454; CHECK-NEXT: mov z0.d, z1.d 455; CHECK-NEXT: ret 456 %v0 = call <vscale x 2 x bfloat> @llvm.experimental.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat> %sv0, <vscale x 2 x bfloat> %sv1, i64 0) 457 ret <vscale x 2 x bfloat> %v0 458} 459 460define <vscale x 4 x bfloat> @insert_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1) nounwind { 461; CHECK-LABEL: insert_nxv4bf16_nxv4bf16: 462; CHECK: // %bb.0: 463; CHECK-NEXT: mov z0.d, z1.d 464; CHECK-NEXT: ret 465 %v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat> %sv0, <vscale x 4 x bfloat> %sv1, i64 0) 466 ret <vscale x 4 x bfloat> %v0 467} 468 469define <vscale x 4 x bfloat> @insert_nxv4bf16_v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1) nounwind { 470; CHECK-LABEL: insert_nxv4bf16_v4bf16: 471; CHECK: // %bb.0: 472; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 473; CHECK-NEXT: addvl sp, sp, #-1 474; CHECK-NEXT: ptrue p0.s 475; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl] 476; CHECK-NEXT: addpl x8, sp, #4 477; CHECK-NEXT: str d1, [x8] 478; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl] 479; CHECK-NEXT: addvl sp, sp, #1 480; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 481; CHECK-NEXT: ret 482 %v0 = call <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat> %sv0, <4 x bfloat> %v1, i64 0) 483 ret <vscale x 4 x bfloat> %v0 484} 485 486define <vscale x 8 x bfloat> @insert_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1) nounwind { 487; CHECK-LABEL: insert_nxv8bf16_nxv8bf16: 488; CHECK: // %bb.0: 489; CHECK-NEXT: mov z0.d, z1.d 490; CHECK-NEXT: ret 491 %v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %sv0, <vscale x 8 x bfloat> %sv1, i64 0) 492 ret <vscale x 8 x bfloat> %v0 493} 494 495define <vscale x 8 x bfloat> @insert_nxv8bf16_v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1) nounwind { 496; CHECK-LABEL: insert_nxv8bf16_v8bf16: 497; CHECK: // %bb.0: 498; CHECK-NEXT: ptrue p0.h, vl8 499; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 500; CHECK-NEXT: mov z0.h, p0/m, z1.h 501; CHECK-NEXT: ret 502 %v0 = call <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat> %sv0, <8 x bfloat> %v1, i64 0) 503 ret <vscale x 8 x bfloat> %v0 504} 505 506; Test predicate inserts of half size. 507define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_0(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) { 508; CHECK-LABEL: insert_nxv16i1_nxv8i1_0: 509; CHECK: // %bb.0: 510; CHECK-NEXT: punpkhi p0.h, p0.b 511; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b 512; CHECK-NEXT: ret 513 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 0) 514 ret <vscale x 16 x i1> %v0 515} 516 517define <vscale x 16 x i1> @insert_nxv16i1_nxv8i1_8(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv) { 518; CHECK-LABEL: insert_nxv16i1_nxv8i1_8: 519; CHECK: // %bb.0: 520; CHECK-NEXT: punpklo p0.h, p0.b 521; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 522; CHECK-NEXT: ret 523 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1> %vec, <vscale x 8 x i1> %sv, i64 8) 524 ret <vscale x 16 x i1> %v0 525} 526 527; Test predicate inserts of less than half the size. 528define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_0(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) { 529; CHECK-LABEL: insert_nxv16i1_nxv4i1_0: 530; CHECK: // %bb.0: 531; CHECK-NEXT: punpklo p2.h, p0.b 532; CHECK-NEXT: punpkhi p0.h, p0.b 533; CHECK-NEXT: punpkhi p2.h, p2.b 534; CHECK-NEXT: uzp1 p1.h, p1.h, p2.h 535; CHECK-NEXT: uzp1 p0.b, p1.b, p0.b 536; CHECK-NEXT: ret 537 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 0) 538 ret <vscale x 16 x i1> %v0 539} 540 541define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_12(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv) { 542; CHECK-LABEL: insert_nxv16i1_nxv4i1_12: 543; CHECK: // %bb.0: 544; CHECK-NEXT: punpkhi p2.h, p0.b 545; CHECK-NEXT: punpklo p0.h, p0.b 546; CHECK-NEXT: punpklo p2.h, p2.b 547; CHECK-NEXT: uzp1 p1.h, p2.h, p1.h 548; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 549; CHECK-NEXT: ret 550 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %sv, i64 12) 551 ret <vscale x 16 x i1> %v0 552} 553 554; Test predicate insert into undef/zero 555define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_zero(<vscale x 4 x i1> %sv) { 556; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_zero: 557; CHECK: // %bb.0: 558; CHECK-NEXT: pfalse p1.b 559; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h 560; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 561; CHECK-NEXT: ret 562 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %sv, i64 0) 563 ret <vscale x 16 x i1> %v0 564} 565 566define <vscale x 16 x i1> @insert_nxv16i1_nxv4i1_into_poison(<vscale x 4 x i1> %sv) { 567; CHECK-LABEL: insert_nxv16i1_nxv4i1_into_poison: 568; CHECK: // %bb.0: 569; CHECK-NEXT: uzp1 p0.h, p0.h, p0.h 570; CHECK-NEXT: uzp1 p0.b, p0.b, p0.b 571; CHECK-NEXT: ret 572 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %sv, i64 0) 573 ret <vscale x 16 x i1> %v0 574} 575 576; Test constant predicate insert into undef 577define <vscale x 2 x i1> @insert_nxv2i1_v8i1_const_true_into_undef() vscale_range(4,8) { 578; CHECK-LABEL: insert_nxv2i1_v8i1_const_true_into_undef: 579; CHECK: // %bb.0: 580; CHECK-NEXT: ptrue p0.d 581; CHECK-NEXT: ret 582 %v0 = call <vscale x 2 x i1> @llvm.experimental.vector.insert.nxv2i1.v8i1 (<vscale x 2 x i1> undef, <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 583 ret <vscale x 2 x i1> %v0 584} 585 586define <vscale x 4 x i1> @insert_nxv4i1_v16i1_const_true_into_undef() vscale_range(4,8) { 587; CHECK-LABEL: insert_nxv4i1_v16i1_const_true_into_undef: 588; CHECK: // %bb.0: 589; CHECK-NEXT: ptrue p0.s 590; CHECK-NEXT: ret 591 %v0 = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv4i1.v16i1 (<vscale x 4 x i1> undef, <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 592 ret <vscale x 4 x i1> %v0 593} 594 595define <vscale x 8 x i1> @insert_nxv8i1_v32i1_const_true_into_undef() vscale_range(4,8) { 596; CHECK-LABEL: insert_nxv8i1_v32i1_const_true_into_undef: 597; CHECK: // %bb.0: 598; CHECK-NEXT: ptrue p0.h 599; CHECK-NEXT: ret 600 %v0 = call <vscale x 8 x i1> @llvm.experimental.vector.insert.nxv8i1.v32i1 (<vscale x 8 x i1> undef, <32 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 601 ret <vscale x 8 x i1> %v0 602} 603 604define <vscale x 16 x i1> @insert_nxv16i1_v64i1_const_true_into_undef() vscale_range(4,8) { 605; CHECK-LABEL: insert_nxv16i1_v64i1_const_true_into_undef: 606; CHECK: // %bb.0: 607; CHECK-NEXT: ptrue p0.b 608; CHECK-NEXT: ret 609 %v0 = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.v64i1 (<vscale x 16 x i1> undef, <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, i64 0) 610 ret <vscale x 16 x i1> %v0 611} 612 613declare <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32>, <vscale x 2 x i32>, i64) 614declare <vscale x 3 x float> @llvm.experimental.vector.insert.nxv3f32.nxv2f32(<vscale x 3 x float>, <vscale x 2 x float>, i64) 615declare <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32>, <vscale x 2 x i32>, i64) 616declare <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv3i32(<vscale x 6 x i32>, <vscale x 3 x i32>, i64) 617declare <vscale x 12 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv12i32(<vscale x 12 x i32>, <vscale x 4 x i32>, i64) 618declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) 619declare <vscale x 8 x bfloat> @llvm.experimental.vector.insert.nxv8bf16.v8bf16(<vscale x 8 x bfloat>, <8 x bfloat>, i64) 620declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) 621declare <vscale x 4 x bfloat> @llvm.experimental.vector.insert.nxv4bf16.v4bf16(<vscale x 4 x bfloat>, <4 x bfloat>, i64) 622declare <vscale x 2 x bfloat> @llvm.experimental.vector.insert.nxv2bf16.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) 623 624declare <vscale x 2 x i1> @llvm.experimental.vector.insert.nxv2i1.v8i1(<vscale x 2 x i1>, <8 x i1>, i64) 625declare <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv4i1.v16i1(<vscale x 4 x i1>, <16 x i1>, i64) 626declare <vscale x 8 x i1> @llvm.experimental.vector.insert.nxv8i1.v32i1(<vscale x 8 x i1>, <32 x i1>, i64) 627declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64) 628declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nx16i1.nxv8i1(<vscale x 16 x i1>, <vscale x 8 x i1>, i64) 629declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.v64i1(<vscale x 16 x i1>, <64 x i1>, i64) 630