1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK
3
4define <vscale x 2 x i64> @insert_v2i64_nxv2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
5; CHECK-LABEL: insert_v2i64_nxv2i64:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
8; CHECK-NEXT:    addvl sp, sp, #-1
9; CHECK-NEXT:    cntd x8
10; CHECK-NEXT:    sub x8, x8, #1 // =1
11; CHECK-NEXT:    cmp x8, #0 // =0
12; CHECK-NEXT:    csel x8, x8, xzr, lo
13; CHECK-NEXT:    ptrue p0.d
14; CHECK-NEXT:    lsl x8, x8, #3
15; CHECK-NEXT:    mov x9, sp
16; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
17; CHECK-NEXT:    str q1, [x9, x8]
18; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
19; CHECK-NEXT:    addvl sp, sp, #1
20; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
21; CHECK-NEXT:    ret
22  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 0)
23  ret <vscale x 2 x i64> %retval
24}
25
26define <vscale x 2 x i64> @insert_v2i64_nxv2i64_idx1(<vscale x 2 x i64> %vec, <2 x i64> %subvec) nounwind {
27; CHECK-LABEL: insert_v2i64_nxv2i64_idx1:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
30; CHECK-NEXT:    addvl sp, sp, #-1
31; CHECK-NEXT:    cntd x8
32; CHECK-NEXT:    sub x8, x8, #1 // =1
33; CHECK-NEXT:    cmp x8, #1 // =1
34; CHECK-NEXT:    csinc x8, x8, xzr, lo
35; CHECK-NEXT:    ptrue p0.d
36; CHECK-NEXT:    lsl x8, x8, #3
37; CHECK-NEXT:    mov x9, sp
38; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
39; CHECK-NEXT:    str q1, [x9, x8]
40; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
41; CHECK-NEXT:    addvl sp, sp, #1
42; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
43; CHECK-NEXT:    ret
44  %retval = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64> %vec, <2 x i64> %subvec, i64 1)
45  ret <vscale x 2 x i64> %retval
46}
47
48define <vscale x 4 x i32> @insert_v4i32_nxv4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
49; CHECK-LABEL: insert_v4i32_nxv4i32:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
52; CHECK-NEXT:    addvl sp, sp, #-1
53; CHECK-NEXT:    cntw x8
54; CHECK-NEXT:    sub x8, x8, #1 // =1
55; CHECK-NEXT:    cmp x8, #0 // =0
56; CHECK-NEXT:    csel x8, x8, xzr, lo
57; CHECK-NEXT:    ptrue p0.s
58; CHECK-NEXT:    lsl x8, x8, #2
59; CHECK-NEXT:    mov x9, sp
60; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
61; CHECK-NEXT:    str q1, [x9, x8]
62; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
63; CHECK-NEXT:    addvl sp, sp, #1
64; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
65; CHECK-NEXT:    ret
66  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 0)
67  ret <vscale x 4 x i32> %retval
68}
69
70define <vscale x 4 x i32> @insert_v4i32_nxv4i32_idx1(<vscale x 4 x i32> %vec, <4 x i32> %subvec) nounwind {
71; CHECK-LABEL: insert_v4i32_nxv4i32_idx1:
72; CHECK:       // %bb.0:
73; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
74; CHECK-NEXT:    addvl sp, sp, #-1
75; CHECK-NEXT:    cntw x8
76; CHECK-NEXT:    sub x8, x8, #1 // =1
77; CHECK-NEXT:    cmp x8, #1 // =1
78; CHECK-NEXT:    csinc x8, x8, xzr, lo
79; CHECK-NEXT:    ptrue p0.s
80; CHECK-NEXT:    lsl x8, x8, #2
81; CHECK-NEXT:    mov x9, sp
82; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
83; CHECK-NEXT:    str q1, [x9, x8]
84; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
85; CHECK-NEXT:    addvl sp, sp, #1
86; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
87; CHECK-NEXT:    ret
88  %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %vec, <4 x i32> %subvec, i64 1)
89  ret <vscale x 4 x i32> %retval
90}
91
92define <vscale x 8 x i16> @insert_v8i16_nxv8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
93; CHECK-LABEL: insert_v8i16_nxv8i16:
94; CHECK:       // %bb.0:
95; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
96; CHECK-NEXT:    addvl sp, sp, #-1
97; CHECK-NEXT:    cnth x8
98; CHECK-NEXT:    sub x8, x8, #1 // =1
99; CHECK-NEXT:    cmp x8, #0 // =0
100; CHECK-NEXT:    csel x8, x8, xzr, lo
101; CHECK-NEXT:    ptrue p0.h
102; CHECK-NEXT:    lsl x8, x8, #1
103; CHECK-NEXT:    mov x9, sp
104; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
105; CHECK-NEXT:    str q1, [x9, x8]
106; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
107; CHECK-NEXT:    addvl sp, sp, #1
108; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
109; CHECK-NEXT:    ret
110  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 0)
111  ret <vscale x 8 x i16> %retval
112}
113
114define <vscale x 8 x i16> @insert_v8i16_nxv8i16_idx1(<vscale x 8 x i16> %vec, <8 x i16> %subvec) nounwind {
115; CHECK-LABEL: insert_v8i16_nxv8i16_idx1:
116; CHECK:       // %bb.0:
117; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
118; CHECK-NEXT:    addvl sp, sp, #-1
119; CHECK-NEXT:    cnth x8
120; CHECK-NEXT:    sub x8, x8, #1 // =1
121; CHECK-NEXT:    cmp x8, #1 // =1
122; CHECK-NEXT:    csinc x8, x8, xzr, lo
123; CHECK-NEXT:    ptrue p0.h
124; CHECK-NEXT:    lsl x8, x8, #1
125; CHECK-NEXT:    mov x9, sp
126; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
127; CHECK-NEXT:    str q1, [x9, x8]
128; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
129; CHECK-NEXT:    addvl sp, sp, #1
130; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
131; CHECK-NEXT:    ret
132  %retval = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16> %vec, <8 x i16> %subvec, i64 1)
133  ret <vscale x 8 x i16> %retval
134}
135
136define <vscale x 16 x i8> @insert_v16i8_nxv16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
137; CHECK-LABEL: insert_v16i8_nxv16i8:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
140; CHECK-NEXT:    addvl sp, sp, #-1
141; CHECK-NEXT:    rdvl x8, #1
142; CHECK-NEXT:    sub x8, x8, #1 // =1
143; CHECK-NEXT:    cmp x8, #0 // =0
144; CHECK-NEXT:    ptrue p0.b
145; CHECK-NEXT:    csel x8, x8, xzr, lo
146; CHECK-NEXT:    mov x9, sp
147; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
148; CHECK-NEXT:    str q1, [x9, x8]
149; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
150; CHECK-NEXT:    addvl sp, sp, #1
151; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
152; CHECK-NEXT:    ret
153  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 0)
154  ret <vscale x 16 x i8> %retval
155}
156
157define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec, <16 x i8> %subvec) nounwind {
158; CHECK-LABEL: insert_v16i8_nxv16i8_idx1:
159; CHECK:       // %bb.0:
160; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
161; CHECK-NEXT:    addvl sp, sp, #-1
162; CHECK-NEXT:    rdvl x8, #1
163; CHECK-NEXT:    sub x8, x8, #1 // =1
164; CHECK-NEXT:    cmp x8, #1 // =1
165; CHECK-NEXT:    ptrue p0.b
166; CHECK-NEXT:    csinc x8, x8, xzr, lo
167; CHECK-NEXT:    mov x9, sp
168; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
169; CHECK-NEXT:    str q1, [x9, x8]
170; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
171; CHECK-NEXT:    addvl sp, sp, #1
172; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
173; CHECK-NEXT:    ret
174  %retval = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> %vec, <16 x i8> %subvec, i64 1)
175  ret <vscale x 16 x i8> %retval
176}
177
178declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
179declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
180declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
181declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
182