1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -aarch64-sve-vector-bits-min=256  < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
3; RUN: llc -aarch64-sve-vector-bits-min=512  < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
4; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
5
6target triple = "aarch64-unknown-linux-gnu"
7
8;
9; insertelement
10;
11
12; Don't use SVE for 64-bit vectors.
13define <4 x half> @insertelement_v4f16(<4 x half> %op1) vscale_range(2,0) #0 {
14; CHECK-LABEL: insertelement_v4f16:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    fmov h1, #5.00000000
17; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
18; CHECK-NEXT:    mov v0.h[3], v1.h[0]
19; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
20; CHECK-NEXT:    ret
21    %r = insertelement <4 x half> %op1, half 5.0, i64 3
22    ret <4 x half> %r
23}
24
25; Don't use SVE for 128-bit vectors.
26define <8 x half> @insertelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 {
27; CHECK-LABEL: insertelement_v8f16:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    fmov h1, #5.00000000
30; CHECK-NEXT:    mov v0.h[7], v1.h[0]
31; CHECK-NEXT:    ret
32    %r = insertelement <8 x half> %op1, half 5.0, i64 7
33    ret <8 x half> %r
34}
35
36define <16 x half> @insertelement_v16f16(<16 x half>* %a) vscale_range(2,0) #0 {
37; CHECK-LABEL: insertelement_v16f16:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    mov w9, #15
40; CHECK-NEXT:    ptrue p0.h, vl16
41; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
42; CHECK-NEXT:    fmov h2, #5.00000000
43; CHECK-NEXT:    index z3.h, #0, #1
44; CHECK-NEXT:    ptrue p1.h
45; CHECK-NEXT:    mov z1.h, w9
46; CHECK-NEXT:    cmpeq p1.h, p1/z, z3.h, z1.h
47; CHECK-NEXT:    mov z0.h, p1/m, h2
48; CHECK-NEXT:    st1h { z0.h }, p0, [x8]
49; CHECK-NEXT:    ret
50    %op1 = load <16 x half>, <16 x half>* %a
51    %r = insertelement <16 x half> %op1, half 5.0, i64 15
52    ret <16 x half> %r
53}
54
55define <32 x half> @insertelement_v32f16(<32 x half>* %a) #0 {
56; VBITS_GE_256-LABEL: insertelement_v32f16:
57; VBITS_GE_256:       // %bb.0:
58; VBITS_GE_256-NEXT:    mov x9, #16
59; VBITS_GE_256-NEXT:    mov w10, #15
60; VBITS_GE_256-NEXT:    ptrue p0.h, vl16
61; VBITS_GE_256-NEXT:    fmov h3, #5.00000000
62; VBITS_GE_256-NEXT:    index z4.h, #0, #1
63; VBITS_GE_256-NEXT:    ptrue p1.h
64; VBITS_GE_256-NEXT:    ld1h { z0.h }, p0/z, [x0, x9, lsl #1]
65; VBITS_GE_256-NEXT:    ld1h { z1.h }, p0/z, [x0]
66; VBITS_GE_256-NEXT:    mov z2.h, w10
67; VBITS_GE_256-NEXT:    cmpeq p1.h, p1/z, z4.h, z2.h
68; VBITS_GE_256-NEXT:    mov z0.h, p1/m, h3
69; VBITS_GE_256-NEXT:    st1h { z0.h }, p0, [x8, x9, lsl #1]
70; VBITS_GE_256-NEXT:    st1h { z1.h }, p0, [x8]
71; VBITS_GE_256-NEXT:    ret
72;
73; VBITS_GE_512-LABEL: insertelement_v32f16:
74; VBITS_GE_512:       // %bb.0:
75; VBITS_GE_512-NEXT:    mov w9, #31
76; VBITS_GE_512-NEXT:    ptrue p0.h, vl32
77; VBITS_GE_512-NEXT:    ld1h { z0.h }, p0/z, [x0]
78; VBITS_GE_512-NEXT:    fmov h2, #5.00000000
79; VBITS_GE_512-NEXT:    index z3.h, #0, #1
80; VBITS_GE_512-NEXT:    ptrue p1.h
81; VBITS_GE_512-NEXT:    mov z1.h, w9
82; VBITS_GE_512-NEXT:    cmpeq p1.h, p1/z, z3.h, z1.h
83; VBITS_GE_512-NEXT:    mov z0.h, p1/m, h2
84; VBITS_GE_512-NEXT:    st1h { z0.h }, p0, [x8]
85; VBITS_GE_512-NEXT:    ret
86    %op1 = load <32 x half>, <32 x half>* %a
87    %r = insertelement <32 x half> %op1, half 5.0, i64 31
88    ret <32 x half> %r
89}
90
91define <64 x half> @insertelement_v64f16(<64 x half>* %a) vscale_range(8,0) #0 {
92; CHECK-LABEL: insertelement_v64f16:
93; CHECK:       // %bb.0:
94; CHECK-NEXT:    mov w9, #63
95; CHECK-NEXT:    ptrue p0.h, vl64
96; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
97; CHECK-NEXT:    fmov h2, #5.00000000
98; CHECK-NEXT:    index z3.h, #0, #1
99; CHECK-NEXT:    ptrue p1.h
100; CHECK-NEXT:    mov z1.h, w9
101; CHECK-NEXT:    cmpeq p1.h, p1/z, z3.h, z1.h
102; CHECK-NEXT:    mov z0.h, p1/m, h2
103; CHECK-NEXT:    st1h { z0.h }, p0, [x8]
104; CHECK-NEXT:    ret
105    %op1 = load <64 x half>, <64 x half>* %a
106    %r = insertelement <64 x half> %op1, half 5.0, i64 63
107    ret <64 x half> %r
108}
109
110define <128 x half> @insertelement_v128f16(<128 x half>* %a) vscale_range(16,0) #0 {
111; CHECK-LABEL: insertelement_v128f16:
112; CHECK:       // %bb.0:
113; CHECK-NEXT:    mov w9, #127
114; CHECK-NEXT:    ptrue p0.h, vl128
115; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
116; CHECK-NEXT:    fmov h2, #5.00000000
117; CHECK-NEXT:    index z3.h, #0, #1
118; CHECK-NEXT:    ptrue p1.h
119; CHECK-NEXT:    mov z1.h, w9
120; CHECK-NEXT:    cmpeq p1.h, p1/z, z3.h, z1.h
121; CHECK-NEXT:    mov z0.h, p1/m, h2
122; CHECK-NEXT:    st1h { z0.h }, p0, [x8]
123; CHECK-NEXT:    ret
124    %op1 = load <128 x half>, <128 x half>* %a
125    %r = insertelement <128 x half> %op1, half 5.0, i64 127
126    ret <128 x half> %r
127}
128
129; Don't use SVE for 64-bit vectors.
130define <2 x float> @insertelement_v2f32(<2 x float> %op1) vscale_range(2,0) #0 {
131; CHECK-LABEL: insertelement_v2f32:
132; CHECK:       // %bb.0:
133; CHECK-NEXT:    fmov s1, #5.00000000
134; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
135; CHECK-NEXT:    mov v0.s[1], v1.s[0]
136; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
137; CHECK-NEXT:    ret
138    %r = insertelement <2 x float> %op1, float 5.0, i64 1
139    ret <2 x float> %r
140}
141
142; Don't use SVE for 128-bit vectors.
143define <4 x float> @insertelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 {
144; CHECK-LABEL: insertelement_v4f32:
145; CHECK:       // %bb.0:
146; CHECK-NEXT:    fmov s1, #5.00000000
147; CHECK-NEXT:    mov v0.s[3], v1.s[0]
148; CHECK-NEXT:    ret
149    %r = insertelement <4 x float> %op1, float 5.0, i64 3
150    ret <4 x float> %r
151}
152
153define <8 x float> @insertelement_v8f32(<8 x float>* %a) vscale_range(2,0) #0 {
154; CHECK-LABEL: insertelement_v8f32:
155; CHECK:       // %bb.0:
156; CHECK-NEXT:    mov w9, #7
157; CHECK-NEXT:    ptrue p0.s, vl8
158; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
159; CHECK-NEXT:    fmov s2, #5.00000000
160; CHECK-NEXT:    index z3.s, #0, #1
161; CHECK-NEXT:    ptrue p1.s
162; CHECK-NEXT:    mov z1.s, w9
163; CHECK-NEXT:    cmpeq p1.s, p1/z, z3.s, z1.s
164; CHECK-NEXT:    mov z0.s, p1/m, s2
165; CHECK-NEXT:    st1w { z0.s }, p0, [x8]
166; CHECK-NEXT:    ret
167    %op1 = load <8 x float>, <8 x float>* %a
168    %r = insertelement <8 x float> %op1, float 5.0, i64 7
169    ret <8 x float> %r
170}
171
172define <16 x float> @insertelement_v16f32(<16 x float>* %a) #0 {
173; VBITS_GE_256-LABEL: insertelement_v16f32:
174; VBITS_GE_256:       // %bb.0:
175; VBITS_GE_256-NEXT:    mov x9, #8
176; VBITS_GE_256-NEXT:    mov w10, #7
177; VBITS_GE_256-NEXT:    ptrue p0.s, vl8
178; VBITS_GE_256-NEXT:    fmov s3, #5.00000000
179; VBITS_GE_256-NEXT:    index z4.s, #0, #1
180; VBITS_GE_256-NEXT:    ptrue p1.s
181; VBITS_GE_256-NEXT:    ld1w { z0.s }, p0/z, [x0, x9, lsl #2]
182; VBITS_GE_256-NEXT:    ld1w { z1.s }, p0/z, [x0]
183; VBITS_GE_256-NEXT:    mov z2.s, w10
184; VBITS_GE_256-NEXT:    cmpeq p1.s, p1/z, z4.s, z2.s
185; VBITS_GE_256-NEXT:    mov z0.s, p1/m, s3
186; VBITS_GE_256-NEXT:    st1w { z0.s }, p0, [x8, x9, lsl #2]
187; VBITS_GE_256-NEXT:    st1w { z1.s }, p0, [x8]
188; VBITS_GE_256-NEXT:    ret
189;
190; VBITS_GE_512-LABEL: insertelement_v16f32:
191; VBITS_GE_512:       // %bb.0:
192; VBITS_GE_512-NEXT:    mov w9, #15
193; VBITS_GE_512-NEXT:    ptrue p0.s, vl16
194; VBITS_GE_512-NEXT:    ld1w { z0.s }, p0/z, [x0]
195; VBITS_GE_512-NEXT:    fmov s2, #5.00000000
196; VBITS_GE_512-NEXT:    index z3.s, #0, #1
197; VBITS_GE_512-NEXT:    ptrue p1.s
198; VBITS_GE_512-NEXT:    mov z1.s, w9
199; VBITS_GE_512-NEXT:    cmpeq p1.s, p1/z, z3.s, z1.s
200; VBITS_GE_512-NEXT:    mov z0.s, p1/m, s2
201; VBITS_GE_512-NEXT:    st1w { z0.s }, p0, [x8]
202; VBITS_GE_512-NEXT:    ret
203    %op1 = load <16 x float>, <16 x float>* %a
204    %r = insertelement <16 x float> %op1, float 5.0, i64 15
205    ret <16 x float> %r
206}
207
208define <32 x float> @insertelement_v32f32(<32 x float>* %a) vscale_range(8,0) #0 {
209; CHECK-LABEL: insertelement_v32f32:
210; CHECK:       // %bb.0:
211; CHECK-NEXT:    mov w9, #31
212; CHECK-NEXT:    ptrue p0.s, vl32
213; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
214; CHECK-NEXT:    fmov s2, #5.00000000
215; CHECK-NEXT:    index z3.s, #0, #1
216; CHECK-NEXT:    ptrue p1.s
217; CHECK-NEXT:    mov z1.s, w9
218; CHECK-NEXT:    cmpeq p1.s, p1/z, z3.s, z1.s
219; CHECK-NEXT:    mov z0.s, p1/m, s2
220; CHECK-NEXT:    st1w { z0.s }, p0, [x8]
221; CHECK-NEXT:    ret
222    %op1 = load <32 x float>, <32 x float>* %a
223    %r = insertelement <32 x float> %op1, float 5.0, i64 31
224    ret <32 x float> %r
225}
226
227define <64 x float> @insertelement_v64f32(<64 x float>* %a) vscale_range(16,0) #0 {
228; CHECK-LABEL: insertelement_v64f32:
229; CHECK:       // %bb.0:
230; CHECK-NEXT:    mov w9, #63
231; CHECK-NEXT:    ptrue p0.s, vl64
232; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
233; CHECK-NEXT:    fmov s2, #5.00000000
234; CHECK-NEXT:    index z3.s, #0, #1
235; CHECK-NEXT:    ptrue p1.s
236; CHECK-NEXT:    mov z1.s, w9
237; CHECK-NEXT:    cmpeq p1.s, p1/z, z3.s, z1.s
238; CHECK-NEXT:    mov z0.s, p1/m, s2
239; CHECK-NEXT:    st1w { z0.s }, p0, [x8]
240; CHECK-NEXT:    ret
241    %op1 = load <64 x float>, <64 x float>* %a
242    %r = insertelement <64 x float> %op1, float 5.0, i64 63
243    ret <64 x float> %r
244}
245
246; Don't use SVE for 64-bit vectors.
247define <1 x double> @insertelement_v1f64(<1 x double> %op1) vscale_range(2,0) #0 {
248; CHECK-LABEL: insertelement_v1f64:
249; CHECK:       // %bb.0:
250; CHECK-NEXT:    mov x8, #4617315517961601024
251; CHECK-NEXT:    fmov d0, x8
252; CHECK-NEXT:    ret
253    %r = insertelement <1 x double> %op1, double 5.0, i64 0
254    ret <1 x double> %r
255}
256
257; Don't use SVE for 128-bit vectors.
258define <2 x double> @insertelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 {
259; CHECK-LABEL: insertelement_v2f64:
260; CHECK:       // %bb.0:
261; CHECK-NEXT:    fmov d1, #5.00000000
262; CHECK-NEXT:    mov v0.d[1], v1.d[0]
263; CHECK-NEXT:    ret
264    %r = insertelement <2 x double> %op1, double 5.0, i64 1
265    ret <2 x double> %r
266}
267
268define <4 x double> @insertelement_v4f64(<4 x double>* %a) vscale_range(2,0) #0 {
269; CHECK-LABEL: insertelement_v4f64:
270; CHECK:       // %bb.0:
271; CHECK-NEXT:    mov w9, #3
272; CHECK-NEXT:    ptrue p0.d, vl4
273; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
274; CHECK-NEXT:    fmov d2, #5.00000000
275; CHECK-NEXT:    index z3.d, #0, #1
276; CHECK-NEXT:    ptrue p1.d
277; CHECK-NEXT:    mov z1.d, x9
278; CHECK-NEXT:    cmpeq p1.d, p1/z, z3.d, z1.d
279; CHECK-NEXT:    mov z0.d, p1/m, d2
280; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
281; CHECK-NEXT:    ret
282    %op1 = load <4 x double>, <4 x double>* %a
283    %r = insertelement <4 x double> %op1, double 5.0, i64 3
284    ret <4 x double> %r
285}
286
287define <8 x double> @insertelement_v8f64(<8 x double>* %a) #0 {
288; VBITS_GE_256-LABEL: insertelement_v8f64:
289; VBITS_GE_256:       // %bb.0:
290; VBITS_GE_256-NEXT:    mov x9, #4
291; VBITS_GE_256-NEXT:    mov w10, #3
292; VBITS_GE_256-NEXT:    ptrue p0.d, vl4
293; VBITS_GE_256-NEXT:    fmov d3, #5.00000000
294; VBITS_GE_256-NEXT:    index z4.d, #0, #1
295; VBITS_GE_256-NEXT:    ptrue p1.d
296; VBITS_GE_256-NEXT:    ld1d { z0.d }, p0/z, [x0, x9, lsl #3]
297; VBITS_GE_256-NEXT:    ld1d { z1.d }, p0/z, [x0]
298; VBITS_GE_256-NEXT:    mov z2.d, x10
299; VBITS_GE_256-NEXT:    cmpeq p1.d, p1/z, z4.d, z2.d
300; VBITS_GE_256-NEXT:    mov z0.d, p1/m, d3
301; VBITS_GE_256-NEXT:    st1d { z0.d }, p0, [x8, x9, lsl #3]
302; VBITS_GE_256-NEXT:    st1d { z1.d }, p0, [x8]
303; VBITS_GE_256-NEXT:    ret
304;
305; VBITS_GE_512-LABEL: insertelement_v8f64:
306; VBITS_GE_512:       // %bb.0:
307; VBITS_GE_512-NEXT:    mov w9, #7
308; VBITS_GE_512-NEXT:    ptrue p0.d, vl8
309; VBITS_GE_512-NEXT:    ld1d { z0.d }, p0/z, [x0]
310; VBITS_GE_512-NEXT:    fmov d2, #5.00000000
311; VBITS_GE_512-NEXT:    index z3.d, #0, #1
312; VBITS_GE_512-NEXT:    ptrue p1.d
313; VBITS_GE_512-NEXT:    mov z1.d, x9
314; VBITS_GE_512-NEXT:    cmpeq p1.d, p1/z, z3.d, z1.d
315; VBITS_GE_512-NEXT:    mov z0.d, p1/m, d2
316; VBITS_GE_512-NEXT:    st1d { z0.d }, p0, [x8]
317; VBITS_GE_512-NEXT:    ret
318    %op1 = load <8 x double>, <8 x double>* %a
319    %r = insertelement <8 x double> %op1, double 5.0, i64 7
320    ret <8 x double> %r
321}
322
323define <16 x double> @insertelement_v16f64(<16 x double>* %a) vscale_range(8,0) #0 {
324; CHECK-LABEL: insertelement_v16f64:
325; CHECK:       // %bb.0:
326; CHECK-NEXT:    mov w9, #15
327; CHECK-NEXT:    ptrue p0.d, vl16
328; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
329; CHECK-NEXT:    fmov d2, #5.00000000
330; CHECK-NEXT:    index z3.d, #0, #1
331; CHECK-NEXT:    ptrue p1.d
332; CHECK-NEXT:    mov z1.d, x9
333; CHECK-NEXT:    cmpeq p1.d, p1/z, z3.d, z1.d
334; CHECK-NEXT:    mov z0.d, p1/m, d2
335; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
336; CHECK-NEXT:    ret
337    %op1 = load <16 x double>, <16 x double>* %a
338    %r = insertelement <16 x double> %op1, double 5.0, i64 15
339    ret <16 x double> %r
340}
341
342define <32 x double> @insertelement_v32f64(<32 x double>* %a) vscale_range(16,0) #0 {
343; CHECK-LABEL: insertelement_v32f64:
344; CHECK:       // %bb.0:
345; CHECK-NEXT:    mov w9, #31
346; CHECK-NEXT:    ptrue p0.d, vl32
347; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
348; CHECK-NEXT:    fmov d2, #5.00000000
349; CHECK-NEXT:    index z3.d, #0, #1
350; CHECK-NEXT:    ptrue p1.d
351; CHECK-NEXT:    mov z1.d, x9
352; CHECK-NEXT:    cmpeq p1.d, p1/z, z3.d, z1.d
353; CHECK-NEXT:    mov z0.d, p1/m, d2
354; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
355; CHECK-NEXT:    ret
356    %op1 = load <32 x double>, <32 x double>* %a
357    %r = insertelement <32 x double> %op1, double 5.0, i64 31
358    ret <32 x double> %r
359}
360
361attributes #0 = { "target-features"="+sve" }
362