1; Test all AArch64 subarches with scheduling models.
2; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a72 < %s | FileCheck %s
4; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a73 < %s | FileCheck %s
5; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cyclone    < %s | FileCheck %s
6; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m1  < %s | FileCheck %s
7; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m2  < %s | FileCheck %s
8; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo       < %s | FileCheck %s
9; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=vulcan     < %s | FileCheck %s
10
11; Make sure that inst-combine fuses the multiply add in the addressing mode of
12; the load.
13
14; CHECK-LABEL: fun:
15; CHECK-NOT: mul
16; CHECK:     madd
17; CHECK-NOT: mul
18
19%class.D = type { %class.basic_string.base, [4 x i8] }
20%class.basic_string.base = type <{ i64, i64, i32 }>
21@a = global %class.D* zeroinitializer, align 8
22declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1)
23define internal void @fun() section ".text.startup" {
24entry:
25  %tmp.i.i = alloca %class.D, align 8
26  %y = bitcast %class.D* %tmp.i.i to i8*
27  br label %loop
28loop:
29  %conv11.i.i = phi i64 [ 0, %entry ], [ %inc.i.i, %loop ]
30  %i = phi i64 [ undef, %entry ], [ %inc.i.i, %loop ]
31  %x = load %class.D*, %class.D** getelementptr inbounds (%class.D*, %class.D** @a, i64 0), align 8
32  %arrayidx.i.i.i = getelementptr inbounds %class.D, %class.D* %x, i64 %conv11.i.i
33  %d = bitcast %class.D* %arrayidx.i.i.i to i8*
34  call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %y, i8* %d, i64 24, i32 8, i1 false)
35  %inc.i.i = add i64 %i, 1
36  %cmp.i.i = icmp slt i64 %inc.i.i, 0
37  br i1 %cmp.i.i, label %loop, label %exit
38exit:
39  ret void
40}
41