1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s
3
4define <8 x i8> @load4_v4i8_add(float %tmp, <4 x i8> *%a, <4 x i8> *%b) {
5; CHECK-LABEL: load4_v4i8_add:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    ldp s0, s1, [x0]
8; CHECK-NEXT:    ld1 { v0.s }[1], [x1], #4
9; CHECK-NEXT:    ld1 { v1.s }[1], [x1]
10; CHECK-NEXT:    add v0.8b, v0.8b, v1.8b
11; CHECK-NEXT:    ret
12  %la = load <4 x i8>, <4 x i8> *%a
13  %lb = load <4 x i8>, <4 x i8> *%b
14  %c = getelementptr <4 x i8>, <4 x i8> *%a, i64 1
15  %d = getelementptr <4 x i8>, <4 x i8> *%b, i64 1
16  %lc = load <4 x i8>, <4 x i8> *%c
17  %ld = load <4 x i8>, <4 x i8> *%d
18  %s1 = shufflevector <4 x i8> %la, <4 x i8> %lb, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
19  %s2 = shufflevector <4 x i8> %lc, <4 x i8> %ld, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
20  %add = add <8 x i8> %s1, %s2
21  ret <8 x i8> %add
22}
23
24define <8 x i16> @load4_v4i8_zext_add(float %tmp, <4 x i8> *%a, <4 x i8> *%b) {
25; CHECK-LABEL: load4_v4i8_zext_add:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    ldp s0, s1, [x0]
28; CHECK-NEXT:    ld1 { v0.s }[1], [x1], #4
29; CHECK-NEXT:    ld1 { v1.s }[1], [x1]
30; CHECK-NEXT:    uaddl v0.8h, v0.8b, v1.8b
31; CHECK-NEXT:    ret
32  %la = load <4 x i8>, <4 x i8> *%a
33  %lb = load <4 x i8>, <4 x i8> *%b
34  %c = getelementptr <4 x i8>, <4 x i8> *%a, i64 1
35  %d = getelementptr <4 x i8>, <4 x i8> *%b, i64 1
36  %lc = load <4 x i8>, <4 x i8> *%c
37  %ld = load <4 x i8>, <4 x i8> *%d
38  %s1 = shufflevector <4 x i8> %la, <4 x i8> %lb, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
39  %s2 = shufflevector <4 x i8> %lc, <4 x i8> %ld, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
40  %z1 = zext <8 x i8> %s1 to <8 x i16>
41  %z2 = zext <8 x i8> %s2 to <8 x i16>
42  %add = add <8 x i16> %z1, %z2
43  ret <8 x i16> %add
44}
45
46define i32 @large(i8* nocapture noundef readonly %p1, i32 noundef %st1, i8* nocapture noundef readonly %p2, i32 noundef %st2) {
47; CHECK-LABEL: large:
48; CHECK:       // %bb.0: // %entry
49; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
50; CHECK-NEXT:    sxtw x8, w1
51; CHECK-NEXT:    // kill: def $w3 killed $w3 def $x3
52; CHECK-NEXT:    sxtw x11, w3
53; CHECK-NEXT:    add x9, x0, x8
54; CHECK-NEXT:    add x12, x2, x11
55; CHECK-NEXT:    add x10, x9, x8
56; CHECK-NEXT:    add x13, x12, x11
57; CHECK-NEXT:    add x8, x10, x8
58; CHECK-NEXT:    add x11, x13, x11
59; CHECK-NEXT:    ldp s1, s5, [x9]
60; CHECK-NEXT:    ldp s0, s4, [x8]
61; CHECK-NEXT:    ld1 { v0.s }[1], [x10], #4
62; CHECK-NEXT:    ld1 { v1.s }[1], [x0], #4
63; CHECK-NEXT:    ldp s2, s6, [x11]
64; CHECK-NEXT:    ldp s3, s7, [x12]
65; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
66; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
67; CHECK-NEXT:    ld1 { v2.s }[1], [x13], #4
68; CHECK-NEXT:    ld1 { v3.s }[1], [x2], #4
69; CHECK-NEXT:    ld1 { v4.s }[1], [x10]
70; CHECK-NEXT:    ld1 { v5.s }[1], [x0]
71; CHECK-NEXT:    ld1 { v6.s }[1], [x13]
72; CHECK-NEXT:    ld1 { v7.s }[1], [x2]
73; CHECK-NEXT:    ushll v2.8h, v2.8b, #0
74; CHECK-NEXT:    ushll v3.8h, v3.8b, #0
75; CHECK-NEXT:    usubl v16.4s, v0.4h, v2.4h
76; CHECK-NEXT:    usubl2 v0.4s, v0.8h, v2.8h
77; CHECK-NEXT:    usubl v2.4s, v1.4h, v3.4h
78; CHECK-NEXT:    usubl2 v1.4s, v1.8h, v3.8h
79; CHECK-NEXT:    ushll v3.8h, v4.8b, #0
80; CHECK-NEXT:    ushll v4.8h, v5.8b, #0
81; CHECK-NEXT:    ushll v5.8h, v6.8b, #0
82; CHECK-NEXT:    ushll v6.8h, v7.8b, #0
83; CHECK-NEXT:    usubl2 v7.4s, v3.8h, v5.8h
84; CHECK-NEXT:    usubl v3.4s, v3.4h, v5.4h
85; CHECK-NEXT:    usubl2 v5.4s, v4.8h, v6.8h
86; CHECK-NEXT:    usubl v4.4s, v4.4h, v6.4h
87; CHECK-NEXT:    shl v3.4s, v3.4s, #16
88; CHECK-NEXT:    shl v6.4s, v7.4s, #16
89; CHECK-NEXT:    shl v5.4s, v5.4s, #16
90; CHECK-NEXT:    shl v4.4s, v4.4s, #16
91; CHECK-NEXT:    add v0.4s, v6.4s, v0.4s
92; CHECK-NEXT:    add v3.4s, v3.4s, v16.4s
93; CHECK-NEXT:    add v1.4s, v5.4s, v1.4s
94; CHECK-NEXT:    add v2.4s, v4.4s, v2.4s
95; CHECK-NEXT:    rev64 v4.4s, v0.4s
96; CHECK-NEXT:    rev64 v5.4s, v3.4s
97; CHECK-NEXT:    rev64 v6.4s, v1.4s
98; CHECK-NEXT:    rev64 v7.4s, v2.4s
99; CHECK-NEXT:    add v16.4s, v0.4s, v4.4s
100; CHECK-NEXT:    add v17.4s, v3.4s, v5.4s
101; CHECK-NEXT:    add v18.4s, v1.4s, v6.4s
102; CHECK-NEXT:    add v19.4s, v2.4s, v7.4s
103; CHECK-NEXT:    sub v1.4s, v1.4s, v6.4s
104; CHECK-NEXT:    sub v2.4s, v2.4s, v7.4s
105; CHECK-NEXT:    sub v0.4s, v0.4s, v4.4s
106; CHECK-NEXT:    sub v3.4s, v3.4s, v5.4s
107; CHECK-NEXT:    trn2 v4.4s, v16.4s, v17.4s
108; CHECK-NEXT:    trn2 v5.4s, v19.4s, v18.4s
109; CHECK-NEXT:    zip1 v7.4s, v2.4s, v1.4s
110; CHECK-NEXT:    trn2 v20.4s, v17.4s, v16.4s
111; CHECK-NEXT:    zip1 v6.4s, v0.4s, v3.4s
112; CHECK-NEXT:    zip2 v18.4s, v19.4s, v18.4s
113; CHECK-NEXT:    ext v5.16b, v19.16b, v5.16b, #8
114; CHECK-NEXT:    ext v16.16b, v4.16b, v16.16b, #8
115; CHECK-NEXT:    ext v7.16b, v2.16b, v7.16b, #8
116; CHECK-NEXT:    ext v17.16b, v20.16b, v17.16b, #8
117; CHECK-NEXT:    zip2 v0.4s, v0.4s, v3.4s
118; CHECK-NEXT:    mov v2.s[3], v1.s[2]
119; CHECK-NEXT:    mov v4.d[1], v5.d[1]
120; CHECK-NEXT:    mov v6.d[1], v7.d[1]
121; CHECK-NEXT:    mov v17.d[1], v18.d[1]
122; CHECK-NEXT:    mov v20.d[1], v5.d[1]
123; CHECK-NEXT:    mov v0.d[1], v2.d[1]
124; CHECK-NEXT:    mov v16.d[1], v18.d[1]
125; CHECK-NEXT:    add v1.4s, v17.4s, v20.4s
126; CHECK-NEXT:    add v2.4s, v0.4s, v6.4s
127; CHECK-NEXT:    sub v3.4s, v4.4s, v16.4s
128; CHECK-NEXT:    sub v0.4s, v6.4s, v0.4s
129; CHECK-NEXT:    rev64 v4.4s, v1.4s
130; CHECK-NEXT:    rev64 v5.4s, v3.4s
131; CHECK-NEXT:    rev64 v6.4s, v0.4s
132; CHECK-NEXT:    rev64 v7.4s, v2.4s
133; CHECK-NEXT:    add v16.4s, v1.4s, v4.4s
134; CHECK-NEXT:    add v17.4s, v3.4s, v5.4s
135; CHECK-NEXT:    add v18.4s, v0.4s, v6.4s
136; CHECK-NEXT:    add v19.4s, v2.4s, v7.4s
137; CHECK-NEXT:    sub v2.4s, v2.4s, v7.4s
138; CHECK-NEXT:    sub v0.4s, v0.4s, v6.4s
139; CHECK-NEXT:    sub v3.4s, v3.4s, v5.4s
140; CHECK-NEXT:    sub v1.4s, v1.4s, v4.4s
141; CHECK-NEXT:    ext v4.16b, v2.16b, v19.16b, #12
142; CHECK-NEXT:    ext v5.16b, v0.16b, v18.16b, #12
143; CHECK-NEXT:    ext v7.16b, v3.16b, v17.16b, #12
144; CHECK-NEXT:    rev64 v16.4s, v16.4s
145; CHECK-NEXT:    ext v6.16b, v4.16b, v2.16b, #4
146; CHECK-NEXT:    ext v17.16b, v4.16b, v4.16b, #8
147; CHECK-NEXT:    ext v18.16b, v5.16b, v0.16b, #4
148; CHECK-NEXT:    ext v19.16b, v5.16b, v5.16b, #8
149; CHECK-NEXT:    ext v20.16b, v7.16b, v3.16b, #4
150; CHECK-NEXT:    ext v21.16b, v7.16b, v7.16b, #8
151; CHECK-NEXT:    rev64 v7.4s, v7.4s
152; CHECK-NEXT:    trn2 v1.4s, v16.4s, v1.4s
153; CHECK-NEXT:    rev64 v5.4s, v5.4s
154; CHECK-NEXT:    rev64 v4.4s, v4.4s
155; CHECK-NEXT:    ext v6.16b, v6.16b, v17.16b, #12
156; CHECK-NEXT:    ext v17.16b, v18.16b, v19.16b, #12
157; CHECK-NEXT:    ext v18.16b, v20.16b, v21.16b, #12
158; CHECK-NEXT:    ext v3.16b, v7.16b, v3.16b, #4
159; CHECK-NEXT:    ext v7.16b, v1.16b, v1.16b, #8
160; CHECK-NEXT:    ext v0.16b, v5.16b, v0.16b, #4
161; CHECK-NEXT:    ext v2.16b, v4.16b, v2.16b, #4
162; CHECK-NEXT:    add v4.4s, v18.4s, v3.4s
163; CHECK-NEXT:    add v5.4s, v1.4s, v7.4s
164; CHECK-NEXT:    add v16.4s, v17.4s, v0.4s
165; CHECK-NEXT:    add v19.4s, v6.4s, v2.4s
166; CHECK-NEXT:    sub v3.4s, v18.4s, v3.4s
167; CHECK-NEXT:    sub v1.4s, v1.4s, v7.4s
168; CHECK-NEXT:    sub v2.4s, v6.4s, v2.4s
169; CHECK-NEXT:    sub v0.4s, v17.4s, v0.4s
170; CHECK-NEXT:    mov v19.d[1], v2.d[1]
171; CHECK-NEXT:    mov v16.d[1], v0.d[1]
172; CHECK-NEXT:    mov v4.d[1], v3.d[1]
173; CHECK-NEXT:    mov v5.d[1], v1.d[1]
174; CHECK-NEXT:    movi v0.8h, #1
175; CHECK-NEXT:    movi v7.2d, #0x00ffff0000ffff
176; CHECK-NEXT:    ushr v1.4s, v4.4s, #15
177; CHECK-NEXT:    ushr v2.4s, v19.4s, #15
178; CHECK-NEXT:    ushr v3.4s, v5.4s, #15
179; CHECK-NEXT:    ushr v6.4s, v16.4s, #15
180; CHECK-NEXT:    and v2.16b, v2.16b, v0.16b
181; CHECK-NEXT:    and v6.16b, v6.16b, v0.16b
182; CHECK-NEXT:    and v3.16b, v3.16b, v0.16b
183; CHECK-NEXT:    and v0.16b, v1.16b, v0.16b
184; CHECK-NEXT:    mul v1.4s, v2.4s, v7.4s
185; CHECK-NEXT:    mul v2.4s, v6.4s, v7.4s
186; CHECK-NEXT:    mul v0.4s, v0.4s, v7.4s
187; CHECK-NEXT:    mul v3.4s, v3.4s, v7.4s
188; CHECK-NEXT:    add v6.4s, v1.4s, v19.4s
189; CHECK-NEXT:    add v7.4s, v2.4s, v16.4s
190; CHECK-NEXT:    add v4.4s, v0.4s, v4.4s
191; CHECK-NEXT:    add v5.4s, v3.4s, v5.4s
192; CHECK-NEXT:    eor v0.16b, v4.16b, v0.16b
193; CHECK-NEXT:    eor v3.16b, v5.16b, v3.16b
194; CHECK-NEXT:    eor v2.16b, v7.16b, v2.16b
195; CHECK-NEXT:    eor v1.16b, v6.16b, v1.16b
196; CHECK-NEXT:    add v1.4s, v1.4s, v2.4s
197; CHECK-NEXT:    add v0.4s, v3.4s, v0.4s
198; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
199; CHECK-NEXT:    addv s0, v0.4s
200; CHECK-NEXT:    fmov w8, s0
201; CHECK-NEXT:    lsr w9, w8, #16
202; CHECK-NEXT:    add w8, w9, w8, uxth
203; CHECK-NEXT:    lsr w0, w8, #1
204; CHECK-NEXT:    ret
205entry:
206  %idx.ext = sext i32 %st1 to i64
207  %idx.ext63 = sext i32 %st2 to i64
208  %arrayidx3 = getelementptr inbounds i8, i8* %p1, i64 4
209  %arrayidx5 = getelementptr inbounds i8, i8* %p2, i64 4
210  %0 = bitcast i8* %p1 to <4 x i8>*
211  %1 = load <4 x i8>, <4 x i8>* %0, align 1
212  %2 = bitcast i8* %p2 to <4 x i8>*
213  %3 = load <4 x i8>, <4 x i8>* %2, align 1
214  %4 = bitcast i8* %arrayidx3 to <4 x i8>*
215  %5 = load <4 x i8>, <4 x i8>* %4, align 1
216  %6 = bitcast i8* %arrayidx5 to <4 x i8>*
217  %7 = load <4 x i8>, <4 x i8>* %6, align 1
218  %add.ptr = getelementptr inbounds i8, i8* %p1, i64 %idx.ext
219  %add.ptr64 = getelementptr inbounds i8, i8* %p2, i64 %idx.ext63
220  %arrayidx3.1 = getelementptr inbounds i8, i8* %add.ptr, i64 4
221  %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
222  %8 = bitcast i8* %add.ptr to <4 x i8>*
223  %9 = load <4 x i8>, <4 x i8>* %8, align 1
224  %10 = bitcast i8* %add.ptr64 to <4 x i8>*
225  %11 = load <4 x i8>, <4 x i8>* %10, align 1
226  %12 = bitcast i8* %arrayidx3.1 to <4 x i8>*
227  %13 = load <4 x i8>, <4 x i8>* %12, align 1
228  %14 = bitcast i8* %arrayidx5.1 to <4 x i8>*
229  %15 = load <4 x i8>, <4 x i8>* %14, align 1
230  %add.ptr.1 = getelementptr inbounds i8, i8* %add.ptr, i64 %idx.ext
231  %add.ptr64.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 %idx.ext63
232  %arrayidx3.2 = getelementptr inbounds i8, i8* %add.ptr.1, i64 4
233  %arrayidx5.2 = getelementptr inbounds i8, i8* %add.ptr64.1, i64 4
234  %16 = bitcast i8* %add.ptr.1 to <4 x i8>*
235  %17 = load <4 x i8>, <4 x i8>* %16, align 1
236  %18 = bitcast i8* %add.ptr64.1 to <4 x i8>*
237  %19 = load <4 x i8>, <4 x i8>* %18, align 1
238  %20 = bitcast i8* %arrayidx3.2 to <4 x i8>*
239  %21 = load <4 x i8>, <4 x i8>* %20, align 1
240  %22 = bitcast i8* %arrayidx5.2 to <4 x i8>*
241  %23 = load <4 x i8>, <4 x i8>* %22, align 1
242  %add.ptr.2 = getelementptr inbounds i8, i8* %add.ptr.1, i64 %idx.ext
243  %add.ptr64.2 = getelementptr inbounds i8, i8* %add.ptr64.1, i64 %idx.ext63
244  %arrayidx3.3 = getelementptr inbounds i8, i8* %add.ptr.2, i64 4
245  %arrayidx5.3 = getelementptr inbounds i8, i8* %add.ptr64.2, i64 4
246  %24 = bitcast i8* %add.ptr.2 to <4 x i8>*
247  %25 = load <4 x i8>, <4 x i8>* %24, align 1
248  %26 = shufflevector <4 x i8> %25, <4 x i8> %17, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
249  %27 = shufflevector <4 x i8> %9, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
250  %28 = shufflevector <16 x i8> %26, <16 x i8> %27, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef>
251  %29 = shufflevector <4 x i8> %1, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
252  %30 = shufflevector <16 x i8> %28, <16 x i8> %29, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
253  %31 = zext <16 x i8> %30 to <16 x i32>
254  %32 = bitcast i8* %add.ptr64.2 to <4 x i8>*
255  %33 = load <4 x i8>, <4 x i8>* %32, align 1
256  %34 = shufflevector <4 x i8> %33, <4 x i8> %19, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
257  %35 = shufflevector <4 x i8> %11, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
258  %36 = shufflevector <16 x i8> %34, <16 x i8> %35, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef>
259  %37 = shufflevector <4 x i8> %3, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
260  %38 = shufflevector <16 x i8> %36, <16 x i8> %37, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
261  %39 = zext <16 x i8> %38 to <16 x i32>
262  %40 = sub nsw <16 x i32> %31, %39
263  %41 = bitcast i8* %arrayidx3.3 to <4 x i8>*
264  %42 = load <4 x i8>, <4 x i8>* %41, align 1
265  %43 = shufflevector <4 x i8> %42, <4 x i8> %21, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
266  %44 = shufflevector <4 x i8> %13, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
267  %45 = shufflevector <16 x i8> %43, <16 x i8> %44, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef>
268  %46 = shufflevector <4 x i8> %5, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
269  %47 = shufflevector <16 x i8> %45, <16 x i8> %46, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
270  %48 = zext <16 x i8> %47 to <16 x i32>
271  %49 = bitcast i8* %arrayidx5.3 to <4 x i8>*
272  %50 = load <4 x i8>, <4 x i8>* %49, align 1
273  %51 = shufflevector <4 x i8> %50, <4 x i8> %23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
274  %52 = shufflevector <4 x i8> %15, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
275  %53 = shufflevector <16 x i8> %51, <16 x i8> %52, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef>
276  %54 = shufflevector <4 x i8> %7, <4 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
277  %55 = shufflevector <16 x i8> %53, <16 x i8> %54, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
278  %56 = zext <16 x i8> %55 to <16 x i32>
279  %57 = sub nsw <16 x i32> %48, %56
280  %58 = shl nsw <16 x i32> %57, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
281  %59 = add nsw <16 x i32> %58, %40
282  %60 = shufflevector <16 x i32> %59, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
283  %61 = add nsw <16 x i32> %59, %60
284  %62 = sub nsw <16 x i32> %59, %60
285  %63 = shufflevector <16 x i32> %61, <16 x i32> %62, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 22, i32 18, i32 26, i32 30, i32 5, i32 1, i32 9, i32 13, i32 20, i32 16, i32 24, i32 28>
286  %64 = shufflevector <16 x i32> %61, <16 x i32> %62, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 20, i32 16, i32 24, i32 28, i32 7, i32 3, i32 11, i32 15, i32 22, i32 18, i32 26, i32 30>
287  %65 = add nsw <16 x i32> %63, %64
288  %66 = sub nsw <16 x i32> %63, %64
289  %67 = shufflevector <16 x i32> %65, <16 x i32> %66, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
290  %68 = shufflevector <16 x i32> %65, <16 x i32> %66, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 25, i32 24, i32 27, i32 26, i32 29, i32 28, i32 31, i32 30>
291  %69 = add nsw <16 x i32> %67, %68
292  %70 = sub nsw <16 x i32> %67, %68
293  %71 = shufflevector <16 x i32> %69, <16 x i32> %70, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 20, i32 5, i32 6, i32 23, i32 24, i32 9, i32 10, i32 27, i32 28, i32 13, i32 14, i32 31>
294  %72 = shufflevector <16 x i32> %69, <16 x i32> %70, <16 x i32> <i32 2, i32 19, i32 0, i32 17, i32 23, i32 6, i32 5, i32 20, i32 27, i32 10, i32 9, i32 24, i32 31, i32 14, i32 13, i32 28>
295  %73 = add nsw <16 x i32> %71, %72
296  %74 = sub nsw <16 x i32> %71, %72
297  %75 = shufflevector <16 x i32> %73, <16 x i32> %74, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 4, i32 5, i32 22, i32 23, i32 8, i32 9, i32 26, i32 27, i32 12, i32 13, i32 30, i32 31>
298  %76 = lshr <16 x i32> %75, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
299  %77 = and <16 x i32> %76, <i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537>
300  %78 = mul nuw <16 x i32> %77, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
301  %79 = add <16 x i32> %78, %75
302  %80 = xor <16 x i32> %79, %78
303  %81 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %80)
304  %conv118 = and i32 %81, 65535
305  %shr = lshr i32 %81, 16
306  %add119 = add nuw nsw i32 %conv118, %shr
307  %shr120 = lshr i32 %add119, 1
308  ret i32 %shr120
309}
310
311declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
312