1; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s
2
3; CHECK-LABEL: lsl_i8
4; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
5define zeroext i8 @lsl_i8(i8 %a) {
6  %1 = shl i8 %a, 4
7  ret i8 %1
8}
9
10; CHECK-LABEL: lsl_i16
11; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
12define zeroext i16 @lsl_i16(i16 %a) {
13  %1 = shl i16 %a, 8
14  ret i16 %1
15}
16
17; CHECK-LABEL: lsl_i32
18; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
19define zeroext i32 @lsl_i32(i32 %a) {
20  %1 = shl i32 %a, 16
21  ret i32 %1
22}
23
24; FIXME: This shouldn't use the variable shift version.
25; CHECK-LABEL: lsl_i64
26; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
27define i64 @lsl_i64(i64 %a) {
28  %1 = shl i64 %a, 32
29  ret i64 %1
30}
31
32; CHECK-LABEL: lsr_i8
33; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
34define zeroext i8 @lsr_i8(i8 %a) {
35  %1 = lshr i8 %a, 4
36  ret i8 %1
37}
38
39; CHECK-LABEL: lsr_i16
40; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
41define zeroext i16 @lsr_i16(i16 %a) {
42  %1 = lshr i16 %a, 8
43  ret i16 %1
44}
45
46; CHECK-LABEL: lsr_i32
47; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
48define zeroext i32 @lsr_i32(i32 %a) {
49  %1 = lshr i32 %a, 16
50  ret i32 %1
51}
52
53; FIXME: This shouldn't use the variable shift version.
54; CHECK-LABEL: lsr_i64
55; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
56define i64 @lsr_i64(i64 %a) {
57  %1 = lshr i64 %a, 32
58  ret i64 %1
59}
60
61; CHECK-LABEL: asr_i8
62; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
63define zeroext i8 @asr_i8(i8 %a) {
64  %1 = ashr i8 %a, 4
65  ret i8 %1
66}
67
68; CHECK-LABEL: asr_i16
69; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
70define zeroext i16 @asr_i16(i16 %a) {
71  %1 = ashr i16 %a, 8
72  ret i16 %1
73}
74
75; CHECK-LABEL: asr_i32
76; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
77define zeroext i32 @asr_i32(i32 %a) {
78  %1 = ashr i32 %a, 16
79  ret i32 %1
80}
81
82; FIXME: This shouldn't use the variable shift version.
83; CHECK-LABEL: asr_i64
84; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
85define i64 @asr_i64(i64 %a) {
86  %1 = ashr i64 %a, 32
87  ret i64 %1
88}
89
90; CHECK-LABEL: shift_test1
91; CHECK:       ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
92; CHECK-NEXT:  sbfx  {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
93define i32 @shift_test1(i8 %a) {
94  %1 = shl i8 %a, 4
95  %2 = ashr i8 %1, 4
96  %3 = sext i8 %2 to i32
97  ret i32 %3
98}
99
100