1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm64-apple-iphoneos -o - %s | FileCheck %s
3
4define i3 @sign_i3(i3 %a) {
5; CHECK-LABEL: sign_i3:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    sbfx w8, w0, #2, #1
8; CHECK-NEXT:    orr w0, w8, #0x1
9; CHECK-NEXT:    ret
10  %c = icmp sgt i3 %a, -1
11  %res = select i1 %c, i3 1, i3 -1
12  ret i3 %res
13}
14
15define i4 @sign_i4(i4 %a) {
16; CHECK-LABEL: sign_i4:
17; CHECK:       // %bb.0:
18; CHECK-NEXT:    sbfx w8, w0, #3, #1
19; CHECK-NEXT:    orr w0, w8, #0x1
20; CHECK-NEXT:    ret
21  %c = icmp sgt i4 %a, -1
22  %res = select i1 %c, i4 1, i4 -1
23  ret i4 %res
24}
25
26define i8 @sign_i8(i8 %a) {
27; CHECK-LABEL: sign_i8:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    sbfx w8, w0, #7, #1
30; CHECK-NEXT:    orr w0, w8, #0x1
31; CHECK-NEXT:    ret
32  %c = icmp sgt i8 %a, -1
33  %res = select i1 %c, i8 1, i8 -1
34  ret i8 %res
35}
36
37define i16 @sign_i16(i16 %a) {
38; CHECK-LABEL: sign_i16:
39; CHECK:       // %bb.0:
40; CHECK-NEXT:    sbfx w8, w0, #15, #1
41; CHECK-NEXT:    orr w0, w8, #0x1
42; CHECK-NEXT:    ret
43  %c = icmp sgt i16 %a, -1
44  %res = select i1 %c, i16 1, i16 -1
45  ret i16 %res
46}
47
48define i32 @sign_i32(i32 %a) {
49; CHECK-LABEL: sign_i32:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    asr w8, w0, #31
52; CHECK-NEXT:    orr w0, w8, #0x1
53; CHECK-NEXT:    ret
54  %c = icmp sgt i32 %a, -1
55  %res = select i1 %c, i32 1, i32 -1
56  ret i32 %res
57}
58
59define i64 @sign_i64(i64 %a) {
60; CHECK-LABEL: sign_i64:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    asr x8, x0, #63
63; CHECK-NEXT:    orr x0, x8, #0x1
64; CHECK-NEXT:    ret
65  %c = icmp sgt i64 %a, -1
66  %res = select i1 %c, i64 1, i64 -1
67  ret i64 %res
68}
69
70
71define i64 @not_sign_i64(i64 %a) {
72; CHECK-LABEL: not_sign_i64:
73; CHECK:       // %bb.0:
74; CHECK-NEXT:    cmp x0, #0 // =0
75; CHECK-NEXT:    mov w8, #1
76; CHECK-NEXT:    cneg x0, x8, le
77; CHECK-NEXT:    ret
78  %c = icmp sgt i64 %a, 0
79  %res = select i1 %c, i64 1, i64 -1
80  ret i64 %res
81}
82
83define i64 @not_sign_i64_2(i64 %a) {
84; CHECK-LABEL: not_sign_i64_2:
85; CHECK:       // %bb.0:
86; CHECK-NEXT:    asr x0, x0, #63
87; CHECK-NEXT:    ret
88  %c = icmp sgt i64 %a, -1
89  %res = select i1 %c, i64 0, i64 -1
90  ret i64 %res
91}
92
93define i64 @not_sign_i64_3(i64 %a) {
94; CHECK-LABEL: not_sign_i64_3:
95; CHECK:       // %bb.0:
96; CHECK-NEXT:    mvn x8, x0
97; CHECK-NEXT:    lsr x0, x8, #63
98; CHECK-NEXT:    ret
99  %c = icmp sgt i64 %a, -1
100  %res = select i1 %c, i64 1, i64 0
101  ret i64 %res
102}
103
104define i64 @not_sign_i64_4(i64 %a) {
105; CHECK-LABEL: not_sign_i64_4:
106; CHECK:       // %bb.0:
107; CHECK-NEXT:    mov x0, #-1
108; CHECK-NEXT:    ret
109  %c = icmp ugt i64 %a, -1
110  %res = select i1 %c, i64 1, i64 -1
111  ret i64 %res
112}
113
114define <7 x i8> @sign_7xi8(<7 x i8> %a) {
115; CHECK-LABEL: sign_7xi8:
116; CHECK:       // %bb.0:
117; CHECK-NEXT:    sshr v0.8b, v0.8b, #7
118; CHECK-NEXT:    movi v1.8b, #1
119; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
120; CHECK-NEXT:    ret
121  %c = icmp sgt <7 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
122  %res = select <7 x i1> %c, <7 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <7 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
123  ret <7 x i8> %res
124}
125
126define <8 x i8> @sign_8xi8(<8 x i8> %a) {
127; CHECK-LABEL: sign_8xi8:
128; CHECK:       // %bb.0:
129; CHECK-NEXT:    sshr v0.8b, v0.8b, #7
130; CHECK-NEXT:    movi v1.8b, #1
131; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
132; CHECK-NEXT:    ret
133  %c = icmp sgt <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
134  %res = select <8 x i1> %c, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
135  ret <8 x i8> %res
136}
137
138define <16 x i8> @sign_16xi8(<16 x i8> %a) {
139; CHECK-LABEL: sign_16xi8:
140; CHECK:       // %bb.0:
141; CHECK-NEXT:    sshr v0.16b, v0.16b, #7
142; CHECK-NEXT:    movi v1.16b, #1
143; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
144; CHECK-NEXT:    ret
145  %c = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
146  %res = select <16 x i1> %c, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
147  ret <16 x i8> %res
148}
149
150define <3 x i32> @sign_3xi32(<3 x i32> %a) {
151; CHECK-LABEL: sign_3xi32:
152; CHECK:       // %bb.0:
153; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
154; CHECK-NEXT:    orr v0.4s, #1
155; CHECK-NEXT:    ret
156  %c = icmp sgt <3 x i32> %a, <i32 -1, i32 -1, i32 -1>
157  %res = select <3 x i1> %c, <3 x i32> <i32 1, i32 1, i32 1>, <3 x i32> <i32 -1, i32 -1, i32 -1>
158  ret <3 x i32> %res
159}
160
161define <4 x i32> @sign_4xi32(<4 x i32> %a) {
162; CHECK-LABEL: sign_4xi32:
163; CHECK:       // %bb.0:
164; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
165; CHECK-NEXT:    orr v0.4s, #1
166; CHECK-NEXT:    ret
167  %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
168  %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
169  ret <4 x i32> %res
170}
171
172define <4 x i32> @sign_4xi32_multi_use(<4 x i32> %a) {
173; CHECK-LABEL: sign_4xi32_multi_use:
174; CHECK:       // %bb.0:
175; CHECK-NEXT:    sub sp, sp, #32 // =32
176; CHECK-NEXT:    str x30, [sp, #16] // 8-byte Folded Spill
177; CHECK-NEXT:    .cfi_def_cfa_offset 32
178; CHECK-NEXT:    .cfi_offset w30, -16
179; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
180; CHECK-NEXT:    sshr v2.4s, v0.4s, #31
181; CHECK-NEXT:    cmgt v0.4s, v0.4s, v1.4s
182; CHECK-NEXT:    orr v2.4s, #1
183; CHECK-NEXT:    xtn v0.4h, v0.4s
184; CHECK-NEXT:    str q2, [sp] // 16-byte Folded Spill
185; CHECK-NEXT:    bl use_4xi1
186; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
187; CHECK-NEXT:    ldr x30, [sp, #16] // 8-byte Folded Reload
188; CHECK-NEXT:    add sp, sp, #32 // =32
189; CHECK-NEXT:    ret
190  %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
191  %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
192  call void @use_4xi1(<4 x i1> %c)
193  ret <4 x i32> %res
194}
195
196; Second icmp operand breaks sign pattern.
197define <4 x i32> @not_sign_4xi32(<4 x i32> %a) {
198; CHECK-LABEL: not_sign_4xi32:
199; CHECK:       // %bb.0:
200; CHECK-NEXT:    adrp x8, .LCPI16_0
201; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
202; CHECK-NEXT:    cmgt v0.4s, v0.4s, v1.4s
203; CHECK-NEXT:    movi v1.4s, #1
204; CHECK-NEXT:    and v1.16b, v0.16b, v1.16b
205; CHECK-NEXT:    orn v0.16b, v1.16b, v0.16b
206; CHECK-NEXT:    ret
207  %c = icmp sgt <4 x i32> %a, <i32 1, i32 -1, i32 -1, i32 -1>
208  %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
209  ret <4 x i32> %res
210}
211
212; First select operand breaks sign pattern.
213define <4 x i32> @not_sign_4xi32_2(<4 x i32> %a) {
214; CHECK-LABEL: not_sign_4xi32_2:
215; CHECK:       // %bb.0:
216; CHECK-NEXT:    adrp x8, .LCPI17_0
217; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
218; CHECK-NEXT:    movi v2.2d, #0xffffffffffffffff
219; CHECK-NEXT:    cmgt v0.4s, v0.4s, v2.4s
220; CHECK-NEXT:    and v1.16b, v0.16b, v1.16b
221; CHECK-NEXT:    orn v0.16b, v1.16b, v0.16b
222; CHECK-NEXT:    ret
223  %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
224  %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 -1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
225  ret <4 x i32> %res
226}
227
228; Second select operand breaks sign pattern.
229define <4 x i32> @not_sign_4xi32_3(<4 x i32> %a) {
230; CHECK-LABEL: not_sign_4xi32_3:
231; CHECK:       // %bb.0:
232; CHECK-NEXT:    adrp x8, .LCPI18_0
233; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_0]
234; CHECK-NEXT:    movi v2.2d, #0xffffffffffffffff
235; CHECK-NEXT:    cmgt v0.4s, v0.4s, v2.4s
236; CHECK-NEXT:    movi v2.4s, #1
237; CHECK-NEXT:    bsl v0.16b, v2.16b, v1.16b
238; CHECK-NEXT:    ret
239  %c = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
240  %res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 1>
241  ret <4 x i32> %res
242}
243
244; i65 is not legal.
245define <4 x i65> @sign_4xi65(<4 x i65> %a) {
246; CHECK-LABEL: sign_4xi65:
247; CHECK:       // %bb.0:
248; CHECK-NEXT:    sbfx x8, x1, #0, #1
249; CHECK-NEXT:    sbfx x9, x7, #0, #1
250; CHECK-NEXT:    orr x6, x9, #0x1
251; CHECK-NEXT:    lsr x7, x9, #63
252; CHECK-NEXT:    orr x9, x8, #0x1
253; CHECK-NEXT:    lsr x1, x8, #63
254; CHECK-NEXT:    fmov d0, x9
255; CHECK-NEXT:    sbfx x10, x5, #0, #1
256; CHECK-NEXT:    sbfx x11, x3, #0, #1
257; CHECK-NEXT:    mov v0.d[1], x1
258; CHECK-NEXT:    orr x2, x11, #0x1
259; CHECK-NEXT:    lsr x3, x11, #63
260; CHECK-NEXT:    orr x4, x10, #0x1
261; CHECK-NEXT:    lsr x5, x10, #63
262; CHECK-NEXT:    fmov x0, d0
263; CHECK-NEXT:    ret
264  %c = icmp sgt <4 x i65> %a, <i65 -1, i65 -1, i65 -1, i65 -1>
265  %res = select <4 x i1> %c, <4 x i65> <i65 1, i65 1, i65 1, i65 1>, <4 x i65 > <i65 -1, i65 -1, i65 -1, i65 -1>
266  ret <4 x i65> %res
267}
268
269declare void @use_4xi1(<4 x i1>)
270