1; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-neon-syntax=apple -no-integrated-as -disable-post-ra | FileCheck %s 2 3; rdar://9167275 4 5define i32 @t1() nounwind ssp { 6entry: 7; CHECK-LABEL: t1: 8; CHECK: mov {{w[0-9]+}}, 7 9 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind 10 ret i32 %0 11} 12 13define i64 @t2() nounwind ssp { 14entry: 15; CHECK-LABEL: t2: 16; CHECK: mov {{x[0-9]+}}, 7 17 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind 18 ret i64 %0 19} 20 21define i64 @t3() nounwind ssp { 22entry: 23; CHECK-LABEL: t3: 24; CHECK: mov {{w[0-9]+}}, 7 25 %0 = tail call i64 asm "mov ${0:w}, 7", "=r"() nounwind 26 ret i64 %0 27} 28 29; rdar://9281206 30 31define void @t4(i64 %op) nounwind { 32entry: 33; CHECK-LABEL: t4: 34; CHECK: mov x0, {{x[0-9]+}}; svc #0 35 %0 = tail call i64 asm sideeffect "mov x0, $1; svc #0;", "=r,r,r,~{x0}"(i64 %op, i64 undef) nounwind 36 ret void 37} 38 39; rdar://9394290 40 41define float @t5(float %x) nounwind { 42entry: 43; CHECK-LABEL: t5: 44; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 45 %0 = tail call float asm "fadd ${0:s}, ${0:s}, ${0:s}", "=w,0"(float %x) nounwind 46 ret float %0 47} 48 49; rdar://9553599 50 51define zeroext i8 @t6(i8* %src) nounwind { 52entry: 53; CHECK-LABEL: t6: 54; CHECK: ldtrb {{w[0-9]+}}, [{{x[0-9]+}}] 55 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind 56 ret i8 %0 57} 58 59define void @t7(i8* %f, i32 %g) nounwind { 60entry: 61 %f.addr = alloca i8*, align 8 62 store i8* %f, i8** %f.addr, align 8 63 ; CHECK-LABEL: t7: 64 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}] 65 call void asm "str ${1:w}, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind 66 ret void 67} 68 69; rdar://10258229 70; ARM64TargetLowering::getRegForInlineAsmConstraint() should recognize 'v' 71; registers. 72define void @t8() nounwind ssp { 73entry: 74; CHECK-LABEL: t8: 75; CHECK: stp {{d[0-9]+}}, {{d[0-9]+}}, [sp, #-16] 76 tail call void asm sideeffect "nop", "~{v8}"() nounwind 77 ret void 78} 79 80define i32 @constraint_I(i32 %i, i32 %j) nounwind { 81entry: 82 ; CHECK-LABEL: constraint_I: 83 %0 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 16773120) nounwind 84 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, 16773120 85 %1 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 4096) nounwind 86 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, 4096 87 ret i32 %1 88} 89 90define i32 @constraint_J(i32 %i, i32 %j, i64 %k) nounwind { 91entry: 92 ; CHECK-LABEL: constraint_J: 93 %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind 94 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, -16773120 95 %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind 96 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, -1 97 %2 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i32 -1) nounwind 98 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, -1 99 %3 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i64 -1) nounwind 100 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, -1 101 ret i32 %1 102} 103 104define i32 @constraint_KL(i32 %i, i32 %j) nounwind { 105entry: 106 ; CHECK-LABEL: constraint_KL: 107 %0 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,K"(i32 %i, i32 255) nounwind 108 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, 255 109 %1 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,L"(i32 %i, i64 16711680) nounwind 110 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, 16711680 111 ret i32 %1 112} 113 114define i32 @constraint_MN(i32 %i, i32 %j) nounwind { 115entry: 116 ; CHECK-LABEL: constraint_MN: 117 %0 = tail call i32 asm sideeffect "movk ${0:w}, $1", "=r,M"(i32 65535) nounwind 118 ; CHECK: movk {{w[0-9]+}}, 65535 119 %1 = tail call i32 asm sideeffect "movz ${0:w}, $1", "=r,N"(i64 0) nounwind 120 ; CHECK: movz {{w[0-9]+}}, 0 121 ret i32 %1 122} 123 124define void @t9() nounwind { 125entry: 126 ; CHECK-LABEL: t9: 127 %data = alloca <2 x double>, align 16 128 %0 = load <2 x double>, <2 x double>* %data, align 16 129 call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind 130 ; CHECK: mov.2d v4, {{v[0-9]+}} 131 ret void 132} 133 134define void @t10() nounwind { 135entry: 136 ; CHECK-LABEL: t10: 137 %data = alloca <2 x float>, align 8 138 %a = alloca [2 x float], align 4 139 %arraydecay = getelementptr inbounds [2 x float], [2 x float]* %a, i32 0, i32 0 140 %0 = load <2 x float>, <2 x float>* %data, align 8 141 call void asm sideeffect "ldr ${1:z}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 142 ; CHECK: ldr {{z[0-9]+}}, [{{x[0-9]+}}] 143 call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 144 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}] 145 call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 146 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}] 147 call void asm sideeffect "ldr ${1:s}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 148 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}] 149 call void asm sideeffect "ldr ${1:h}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 150 ; CHECK: ldr {{h[0-9]+}}, [{{x[0-9]+}}] 151 call void asm sideeffect "ldr ${1:b}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind 152 ; CHECK: ldr {{b[0-9]+}}, [{{x[0-9]+}}] 153 ret void 154} 155 156define void @t11() nounwind { 157entry: 158 ; CHECK-LABEL: t11: 159 %a = alloca i32, align 4 160 %0 = load i32, i32* %a, align 4 161 call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind 162 ; CHECK: mov xzr, {{x[0-9]+}} 163 %1 = load i32, i32* %a, align 4 164 call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind 165 ; CHECK: mov wzr, {{w[0-9]+}} 166 ret void 167} 168 169define void @t12() nounwind { 170entry: 171 ; CHECK-LABEL: t12: 172 %data = alloca <4 x float>, align 16 173 %0 = load <4 x float>, <4 x float>* %data, align 16 174 call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind 175 ; CHECK: mov.2d v4, {{v([0-9])|(1[0-5])}} 176 ret void 177} 178 179define void @t13() nounwind { 180entry: 181 ; CHECK-LABEL: t13: 182 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 1311673391471656960) nounwind 183 ; CHECK: mov x4, 1311673391471656960 184 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 -4662) nounwind 185 ; CHECK: mov x4, -4662 186 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 4660) nounwind 187 ; CHECK: mov x4, 4660 188 call void asm sideeffect "mov x4, $0\0A", "N"(i64 -71777214294589696) nounwind 189 ; CHECK: mov x4, -71777214294589696 190 ret void 191} 192 193define void @t14() nounwind { 194entry: 195 ; CHECK-LABEL: t14: 196 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 305397760) nounwind 197 ; CHECK: mov w4, 305397760 198 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 -4662) nounwind 199 ; CHECK: mov w4, 4294962634 200 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 4660) nounwind 201 ; CHECK: mov w4, 4660 202 call void asm sideeffect "mov w4, $0\0A", "M"(i32 -16711936) nounwind 203 ; CHECK: mov w4, 4278255360 204 ret void 205} 206 207define void @t15() nounwind { 208entry: 209 %0 = tail call double asm sideeffect "fmov $0, d8", "=r"() nounwind 210 ; CHECK: fmov {{x[0-9]+}}, d8 211 ret void 212} 213 214; rdar://problem/14285178 215 216define void @test_zero_reg(i32* %addr) { 217; CHECK-LABEL: test_zero_reg: 218 219 tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind 220; CHECK: USE(xzr) 221 222 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0) 223; CHECK: USE(wzr) 224 225 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1) 226; CHECK: mov [[VAL1:w[0-9]+]], #1 227; CHECK: USE([[VAL1]]) 228 229 tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind 230; CHECK: USE(xzr), USE(xzr) 231 232 tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind 233; CHECK: USE(xzr), USE(wzr) 234 235 ret void 236} 237 238define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind { 239 ; CHECK-LABEL: test_vreg_64bit: 240 %1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind 241 ; CHECK: fadd v14.2s, v0.2s, v0.2s 242 ret <2 x float> %1 243} 244 245define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind { 246 ; CHECK-LABEL: test_vreg_128bit: 247 %1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind 248 ; CHECK: fadd v14.4s, v0.4s, v0.4s 249 ret <4 x float> %1 250} 251 252define void @test_constraint_w(i32 %a) { 253 ; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}} 254 ; CHECK: sqxtn h0, [[SREG]] 255 256 tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a) 257 ret void 258} 259 260define void @test_inline_modifier_a(i8* %ptr) nounwind { 261 ; CHECK-LABEL: test_inline_modifier_a: 262 tail call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "r"(i8* %ptr) 263 ; CHECK: prfm pldl1keep, [x0] 264 ret void 265} 266 267; PR33134 268define void @test_zero_address() { 269entry: 270; CHECK-LABEL: test_zero_address 271; CHECK: mov {{x[0-9]+}}, xzr 272; CHECK: ldr {{x[0-9]+}}, {{[x[0-9]+]}} 273 tail call i32 asm sideeffect "ldr $0, $1 \0A", "=r,*Q"(i32* null) 274 ret void 275} 276 277; No '#' in lane specifier 278define void @test_no_hash_in_lane_specifier() { 279; CHECK-LABEL: test_no_hash_in_lane_specifier 280; CHECK: fmla v2.4s, v0.4s, v1.s[1] 281; CHECK: ret 282 tail call void asm sideeffect "fmla v2.4s, v0.4s, v1.s[$0]", "I"(i32 1) #1 283 ret void 284} 285define void @test_vector_too_large_r_m(<9 x float>* nocapture readonly %0) { 286; CHECK-LABEL: test_vector_too_large_r_m 287; CHECK: ldr [[S:s[0-9]+]], [x0, #32] 288; CHECK-DAG: ldp [[Q0:q[0-9]+]], [[Q1:q[0-9]+]], [x0] 289; CHECK: str [[S]], [sp, #32] 290; CHECK-DAG stp [[Q0]], [[Q1]], [sp] 291; CHECK: ; InlineAsm Start 292; 293entry: 294 %m.addr = alloca <9 x float>, align 16 295 %m = load <9 x float>, <9 x float>* %0, align 16 296 store <9 x float> %m, <9 x float>* %m.addr, align 16 297 call void asm sideeffect "", "=*r|m,0,~{memory}"(<9 x float>* nonnull %m.addr, <9 x float> %m) 298 ret void 299} 300 301define void @test_o_output_constraint() { 302; CHECK-LABEL: test_o_output_constraint: 303; CHECK: sub sp, sp, #16 304; CHECK: add x[[REG:[0-9]+]], sp, #15 305; CHECK: mov [x[[REG]]], 7 306 %b = alloca i8, align 1 307 call void asm "mov $0, 7", "=*o"(i8* %b) 308 ret void 309} 310