1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
3
4name:            v4s32_fpr
5alignment:       2
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $q1, $s0
12
13    ; CHECK-LABEL: name: v4s32_fpr
14    ; CHECK: liveins: $q1, $s0
15    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
16    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
17    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
18    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
19    ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
20    ; CHECK: $q0 = COPY [[INSvi32lane]]
21    ; CHECK: RET_ReallyLR implicit $q0
22    %0:fpr(s32) = COPY $s0
23    %1:fpr(<4 x s32>) = COPY $q1
24    %3:gpr(s32) = G_CONSTANT i32 1
25    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
26    $q0 = COPY %2(<4 x s32>)
27    RET_ReallyLR implicit $q0
28
29...
30---
31name:            v4s32_gpr
32alignment:       2
33legalized:       true
34regBankSelected: true
35tracksRegLiveness: true
36body:             |
37  bb.0:
38    liveins: $q0, $w0
39
40    ; CHECK-LABEL: name: v4s32_gpr
41    ; CHECK: liveins: $q0, $w0
42    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
43    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
44    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
45    ; CHECK: $q0 = COPY [[INSvi32gpr]]
46    ; CHECK: RET_ReallyLR implicit $q0
47    %0:gpr(s32) = COPY $w0
48    %1:fpr(<4 x s32>) = COPY $q0
49    %3:gpr(s32) = G_CONSTANT i32 1
50    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
51    $q0 = COPY %2(<4 x s32>)
52    RET_ReallyLR implicit $q0
53
54...
55---
56name:            v2s64_fpr
57alignment:       2
58legalized:       true
59regBankSelected: true
60tracksRegLiveness: true
61body:             |
62  bb.0:
63    liveins: $d0, $q1
64
65    ; CHECK-LABEL: name: v2s64_fpr
66    ; CHECK: liveins: $d0, $q1
67    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
68    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
69    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
70    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
71    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
72    ; CHECK: $q0 = COPY [[INSvi64lane]]
73    ; CHECK: RET_ReallyLR implicit $q0
74    %0:fpr(s64) = COPY $d0
75    %1:fpr(<2 x s64>) = COPY $q1
76    %3:gpr(s32) = G_CONSTANT i32 1
77    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
78    $q0 = COPY %2(<2 x s64>)
79    RET_ReallyLR implicit $q0
80
81...
82---
83name:            v2s64_gpr
84alignment:       2
85legalized:       true
86regBankSelected: true
87tracksRegLiveness: true
88body:             |
89  bb.0:
90    liveins: $q0, $x0
91
92    ; CHECK-LABEL: name: v2s64_gpr
93    ; CHECK: liveins: $q0, $x0
94    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
95    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
96    ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
97    ; CHECK: $q0 = COPY [[INSvi64gpr]]
98    ; CHECK: RET_ReallyLR implicit $q0
99    %0:gpr(s64) = COPY $x0
100    %1:fpr(<2 x s64>) = COPY $q0
101    %3:gpr(s32) = G_CONSTANT i32 0
102    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
103    $q0 = COPY %2(<2 x s64>)
104    RET_ReallyLR implicit $q0
105
106...
107---
108name:            v2s32_fpr
109alignment:       2
110legalized:       true
111regBankSelected: true
112tracksRegLiveness: true
113body:             |
114  bb.0:
115    liveins: $d1, $s0
116
117    ; CHECK-LABEL: name: v2s32_fpr
118    ; CHECK: liveins: $d1, $s0
119    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
120    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
121    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
122    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
123    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
124    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
125    ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
126    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
127    ; CHECK: $d0 = COPY [[COPY2]]
128    ; CHECK: RET_ReallyLR implicit $d0
129    %0:fpr(s32) = COPY $s0
130    %1:fpr(<2 x s32>) = COPY $d1
131    %3:gpr(s32) = G_CONSTANT i32 1
132    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
133    $d0 = COPY %2(<2 x s32>)
134    RET_ReallyLR implicit $d0
135
136...
137---
138name:            v2s32_gpr
139alignment:       2
140legalized:       true
141regBankSelected: true
142tracksRegLiveness: true
143body:             |
144  bb.0:
145    liveins: $d0, $w0
146
147    ; CHECK-LABEL: name: v2s32_gpr
148    ; CHECK: liveins: $d0, $w0
149    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
150    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
151    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
152    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
153    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
154    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
155    ; CHECK: $d0 = COPY [[COPY2]]
156    ; CHECK: RET_ReallyLR implicit $d0
157    %0:gpr(s32) = COPY $w0
158    %1:fpr(<2 x s32>) = COPY $d0
159    %3:gpr(s32) = G_CONSTANT i32 1
160    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
161    $d0 = COPY %2(<2 x s32>)
162    RET_ReallyLR implicit $d0
163
164...
165